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Hal Drivers for L4
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stm32l4xx_hal_cortex.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_cortex.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of CORTEX HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_CORTEX_H 00040 #define __STM32L4xx_HAL_CORTEX_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @defgroup CORTEX CORTEX 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 00059 * @{ 00060 */ 00061 00062 #if (__MPU_PRESENT == 1) 00063 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 00064 * @{ 00065 */ 00066 typedef struct 00067 { 00068 uint8_t Enable; /*!< Specifies the status of the region. 00069 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 00070 uint8_t Number; /*!< Specifies the number of the region to protect. 00071 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 00072 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 00073 uint8_t Size; /*!< Specifies the size of the region to protect. 00074 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 00075 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 00076 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00077 uint8_t TypeExtField; /*!< Specifies the TEX field level. 00078 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 00079 uint8_t AccessPermission; /*!< Specifies the region access permission type. 00080 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 00081 uint8_t DisableExec; /*!< Specifies the instruction access status. 00082 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 00083 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 00084 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 00085 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 00086 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 00087 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 00088 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 00089 }MPU_Region_InitTypeDef; 00090 /** 00091 * @} 00092 */ 00093 #endif /* __MPU_PRESENT */ 00094 00095 /** 00096 * @} 00097 */ 00098 00099 /* Exported constants --------------------------------------------------------*/ 00100 00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 00102 * @{ 00103 */ 00104 00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 00106 * @{ 00107 */ 00108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 00109 4 bits for subpriority */ 00110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 00111 3 bits for subpriority */ 00112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 00113 2 bits for subpriority */ 00114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 00115 1 bit for subpriority */ 00116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 00117 0 bit for subpriority */ 00118 /** 00119 * @} 00120 */ 00121 00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 00123 * @{ 00124 */ 00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 00126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 00127 /** 00128 * @} 00129 */ 00130 00131 #if (__MPU_PRESENT == 1) 00132 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 00133 * @{ 00134 */ 00135 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 00136 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 00137 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 00138 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 00139 /** 00140 * @} 00141 */ 00142 00143 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 00144 * @{ 00145 */ 00146 #define MPU_REGION_ENABLE ((uint8_t)0x01) 00147 #define MPU_REGION_DISABLE ((uint8_t)0x00) 00148 /** 00149 * @} 00150 */ 00151 00152 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 00153 * @{ 00154 */ 00155 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 00156 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 00162 * @{ 00163 */ 00164 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 00165 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 00171 * @{ 00172 */ 00173 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 00174 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 00180 * @{ 00181 */ 00182 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 00183 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 00189 * @{ 00190 */ 00191 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 00192 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 00193 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 00199 * @{ 00200 */ 00201 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 00202 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 00203 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 00204 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 00205 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 00206 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 00207 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 00208 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 00209 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 00210 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 00211 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 00212 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 00213 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 00214 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 00215 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 00216 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 00217 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 00218 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 00219 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 00220 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 00221 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 00222 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 00223 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 00224 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 00225 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 00226 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 00227 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 00228 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 00229 /** 00230 * @} 00231 */ 00232 00233 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 00234 * @{ 00235 */ 00236 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 00237 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 00238 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 00239 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 00240 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 00241 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 00242 /** 00243 * @} 00244 */ 00245 00246 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 00247 * @{ 00248 */ 00249 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 00250 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 00251 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 00252 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 00253 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 00254 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 00255 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 00256 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 00257 /** 00258 * @} 00259 */ 00260 #endif /* __MPU_PRESENT */ 00261 00262 /** 00263 * @} 00264 */ 00265 00266 /* Exported macros -----------------------------------------------------------*/ 00267 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 00268 * @{ 00269 */ 00270 00271 /** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source 00272 * @{ 00273 */ 00274 00275 /** @brief Configure the SysTick clock source. 00276 * @param __CLKSRC__: specifies the SysTick clock source. 00277 * This parameter can be one of the following values: 00278 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. 00279 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 00280 * @retval None 00281 */ 00282 #define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ 00283 do { \ 00284 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ 00285 { \ 00286 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ 00287 } \ 00288 else \ 00289 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ 00290 } while(0) 00291 00292 /** 00293 * @} 00294 */ 00295 00296 /** 00297 * @} 00298 */ 00299 00300 /* Exported functions --------------------------------------------------------*/ 00301 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 00302 * @{ 00303 */ 00304 00305 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 00306 * @brief Initialization and Configuration functions 00307 * @{ 00308 */ 00309 /* Initialization and Configuration functions *****************************/ 00310 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 00311 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 00312 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 00313 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 00314 void HAL_NVIC_SystemReset(void); 00315 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 00316 00317 #if (__MPU_PRESENT == 1) 00318 /** 00319 * @brief Disable the MPU. 00320 * @retval None 00321 */ 00322 __STATIC_INLINE void HAL_MPU_Disable(void) 00323 { 00324 /* Disable fault exceptions */ 00325 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 00326 00327 /* Disable the MPU */ 00328 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 00329 } 00330 00331 /** 00332 * @brief Enable the MPU. 00333 * @param MPU_Control: Specifies the control mode of the MPU during hard fault, 00334 * NMI, FAULTMASK and privileged accessto the default memory 00335 * This parameter can be one of the following values: 00336 * @arg MPU_HFNMI_PRIVDEF_NONE 00337 * @arg MPU_HARDFAULT_NMI 00338 * @arg MPU_PRIVILEGED_DEFAULT 00339 * @arg MPU_HFNMI_PRIVDEF 00340 * @retval None 00341 */ 00342 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) 00343 { 00344 /* Enable the MPU */ 00345 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 00346 00347 /* Enable fault exceptions */ 00348 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 00349 } 00350 #endif /* __MPU_PRESENT */ 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 00356 * @brief Cortex control functions 00357 * @{ 00358 */ 00359 /* Peripheral Control functions ***********************************************/ 00360 uint32_t HAL_NVIC_GetPriorityGrouping(void); 00361 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 00362 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 00363 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 00364 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 00365 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 00366 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 00367 void HAL_SYSTICK_IRQHandler(void); 00368 void HAL_SYSTICK_Callback(void); 00369 00370 #if (__MPU_PRESENT == 1) 00371 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 00372 #endif /* __MPU_PRESENT */ 00373 /** 00374 * @} 00375 */ 00376 00377 /** 00378 * @} 00379 */ 00380 00381 /* Private types -------------------------------------------------------------*/ 00382 /* Private variables ---------------------------------------------------------*/ 00383 /* Private constants ---------------------------------------------------------*/ 00384 /* Private macros ------------------------------------------------------------*/ 00385 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 00386 * @{ 00387 */ 00388 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 00389 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 00390 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 00391 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 00392 ((GROUP) == NVIC_PRIORITYGROUP_4)) 00393 00394 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00395 00396 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00397 00398 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 00399 00400 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 00401 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 00402 00403 #if (__MPU_PRESENT == 1) 00404 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 00405 ((STATE) == MPU_REGION_DISABLE)) 00406 00407 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 00408 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 00409 00410 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 00411 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 00412 00413 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 00414 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 00415 00416 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 00417 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 00418 00419 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 00420 ((TYPE) == MPU_TEX_LEVEL1) || \ 00421 ((TYPE) == MPU_TEX_LEVEL2)) 00422 00423 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 00424 ((TYPE) == MPU_REGION_PRIV_RW) || \ 00425 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 00426 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 00427 ((TYPE) == MPU_REGION_PRIV_RO) || \ 00428 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 00429 00430 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00431 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00432 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00433 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00434 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00435 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00436 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00437 ((NUMBER) == MPU_REGION_NUMBER7)) 00438 00439 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 00440 ((SIZE) == MPU_REGION_SIZE_64B) || \ 00441 ((SIZE) == MPU_REGION_SIZE_128B) || \ 00442 ((SIZE) == MPU_REGION_SIZE_256B) || \ 00443 ((SIZE) == MPU_REGION_SIZE_512B) || \ 00444 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 00445 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 00446 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 00447 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 00448 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 00449 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 00450 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 00451 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 00452 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 00453 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 00454 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 00455 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 00456 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 00457 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 00458 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 00459 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 00460 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 00461 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 00462 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 00463 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 00464 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 00465 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 00466 ((SIZE) == MPU_REGION_SIZE_4GB)) 00467 00468 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 00469 #endif /* __MPU_PRESENT */ 00470 00471 /** 00472 * @} 00473 */ 00474 00475 /* Private functions ---------------------------------------------------------*/ 00476 00477 /** 00478 * @} 00479 */ 00480 00481 /** 00482 * @} 00483 */ 00484 00485 #ifdef __cplusplus 00486 } 00487 #endif 00488 00489 #endif /* __STM32L4xx_HAL_CORTEX_H */ 00490 00491 00492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00493
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