system_stm32l4xx.c

00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32l4xx.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    16-September-2015
00007   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
00008   *
00009   *   This file provides two functions and one global variable to be called from
00010   *   user application:
00011   *      - SystemInit(): This function is called at startup just after reset and
00012   *                      before branch to main program. This call is made inside
00013   *                      the "startup_stm32l4xx.s" file.
00014   *
00015   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00016   *                                  by the user application to setup the SysTick
00017   *                                  timer or configure other parameters.
00018   *
00019   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00020   *                                 be called whenever the core clock is changed
00021   *                                 during program execution.
00022   *
00023   *   After each device reset the MSI (4 MHz) is used as system clock source.
00024   *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
00025   *   configure the system clock before to branch to main program.
00026   *
00027   *   This file configures the system clock as follows:
00028   *=============================================================================
00029   *-----------------------------------------------------------------------------
00030   *        System Clock source                    | MSI
00031   *-----------------------------------------------------------------------------
00032   *        SYSCLK(Hz)                             | 4000000
00033   *-----------------------------------------------------------------------------
00034   *        HCLK(Hz)                               | 4000000
00035   *-----------------------------------------------------------------------------
00036   *        AHB Prescaler                          | 1
00037   *-----------------------------------------------------------------------------
00038   *        APB1 Prescaler                         | 1
00039   *-----------------------------------------------------------------------------
00040   *        APB2 Prescaler                         | 1
00041   *-----------------------------------------------------------------------------
00042   *        PLL_M                                  | 1
00043   *-----------------------------------------------------------------------------
00044   *        PLL_N                                  | 8
00045   *-----------------------------------------------------------------------------
00046   *        PLL_P                                  | 7
00047   *-----------------------------------------------------------------------------
00048   *        PLL_Q                                  | 2
00049   *-----------------------------------------------------------------------------
00050   *        PLL_R                                  | 2
00051   *-----------------------------------------------------------------------------
00052   *        PLLSAI1_P                              | NA
00053   *-----------------------------------------------------------------------------
00054   *        PLLSAI1_Q                              | NA
00055   *-----------------------------------------------------------------------------
00056   *        PLLSAI1_R                              | NA
00057   *-----------------------------------------------------------------------------
00058   *        PLLSAI2_P                              | NA
00059   *-----------------------------------------------------------------------------
00060   *        PLLSAI2_Q                              | NA
00061   *-----------------------------------------------------------------------------
00062   *        PLLSAI2_R                              | NA
00063   *-----------------------------------------------------------------------------
00064   *        Require 48MHz for USB OTG FS,          | Disabled
00065   *        SDIO and RNG clock                     |
00066   *-----------------------------------------------------------------------------
00067   *=============================================================================
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096   */
00097 
00098 /** @addtogroup CMSIS
00099   * @{
00100   */
00101 
00102 /** @addtogroup stm32l4xx_system
00103   * @{
00104   */
00105 
00106 /** @addtogroup STM32L4xx_System_Private_Includes
00107   * @{
00108   */
00109 
00110 #include "stm32l4xx.h"
00111 
00112 #if !defined  (HSE_VALUE)
00113   #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
00114 #endif /* HSE_VALUE */
00115 
00116 #if !defined  (MSI_VALUE)
00117   #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
00118 #endif /* MSI_VALUE */
00119 
00120 #if !defined  (HSI_VALUE)
00121   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
00122 #endif /* HSI_VALUE */
00123 
00124 /**
00125   * @}
00126   */
00127 
00128 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
00129   * @{
00130   */
00131 
00132 /**
00133   * @}
00134   */
00135 
00136 /** @addtogroup STM32L4xx_System_Private_Defines
00137   * @{
00138   */
00139 
00140 /************************* Miscellaneous Configuration ************************/
00141 /*!< Uncomment the following line if you need to relocate your vector Table in
00142      Internal SRAM. */
00143 /* #define VECT_TAB_SRAM */
00144 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
00145                                    This value must be a multiple of 0x200. */
00146 /******************************************************************************/
00147 /**
00148   * @}
00149   */
00150 
00151 /** @addtogroup STM32L4xx_System_Private_Macros
00152   * @{
00153   */
00154 
00155 /**
00156   * @}
00157   */
00158 
00159 /** @addtogroup STM32L4xx_System_Private_Variables
00160   * @{
00161   */
00162   /* This variable is updated in three ways:
00163       1) by calling CMSIS function SystemCoreClockUpdate()
00164       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
00165       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
00166          Note: If you use this function to configure the system clock; then there
00167                is no need to call the 2 first functions listed above, since SystemCoreClock
00168                variable is updated automatically.
00169   */
00170   uint32_t SystemCoreClock = 4000000;
00171 
00172   const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00173   const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
00174                                       4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
00175 /**
00176   * @}
00177   */
00178 
00179 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
00180   * @{
00181   */
00182 
00183 /**
00184   * @}
00185   */
00186 
00187 /** @addtogroup STM32L4xx_System_Private_Functions
00188   * @{
00189   */
00190 
00191 /**
00192   * @brief  Setup the microcontroller system.
00193   * @param  None
00194   * @retval None
00195   */
00196 
00197 void SystemInit(void)
00198 {
00199   /* FPU settings ------------------------------------------------------------*/
00200   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00201     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
00202   #endif
00203   /* Reset the RCC clock configuration to the default reset state ------------*/
00204   /* Set MSION bit */
00205   RCC->CR |= RCC_CR_MSION;
00206 
00207   /* Reset CFGR register */
00208   RCC->CFGR = 0x00000000;
00209 
00210   /* Reset HSEON, CSSON , HSION, and PLLON bits */
00211   RCC->CR &= (uint32_t)0xEAF6FFFF;
00212 
00213   /* Reset PLLCFGR register */
00214   RCC->PLLCFGR = 0x00000800;
00215 
00216   /* Reset HSEBYP bit */
00217   RCC->CR &= (uint32_t)0xFFFBFFFF;
00218 
00219   /* Disable all interrupts */
00220   RCC->CIER = 0x00000000;
00221 
00222   /* Configure the Vector Table location add offset address ------------------*/
00223 #ifdef VECT_TAB_SRAM
00224   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
00225 #else
00226   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
00227 #endif
00228 }
00229 
00230 /**
00231   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00232   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00233   *         be used by the user application to setup the SysTick timer or configure
00234   *         other parameters.
00235   *
00236   * @note   Each time the core clock (HCLK) changes, this function must be called
00237   *         to update SystemCoreClock variable value. Otherwise, any configuration
00238   *         based on this variable will be incorrect.
00239   *
00240   * @note   - The system frequency computed by this function is not the real
00241   *           frequency in the chip. It is calculated based on the predefined
00242   *           constant and the selected clock source:
00243   *
00244   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
00245   *
00246   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
00247   *
00248   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
00249   *
00250   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
00251   *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
00252   *
00253   *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
00254   *             4 MHz) but the real value may vary depending on the variations
00255   *             in voltage and temperature.
00256   *
00257   *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
00258   *              16 MHz) but the real value may vary depending on the variations
00259   *              in voltage and temperature.
00260   *
00261   *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
00262   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
00263   *              frequency of the crystal used. Otherwise, this function may
00264   *              have wrong result.
00265   *
00266   *         - The result of this function could be not correct when using fractional
00267   *           value for HSE crystal.
00268   *
00269   * @param  None
00270   * @retval None
00271   */
00272 void SystemCoreClockUpdate(void)
00273 {
00274   uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
00275 
00276   /* Get MSI Range frequency--------------------------------------------------*/
00277   if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
00278   { /* MSISRANGE from RCC_CSR applies */
00279     msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
00280   }
00281   else
00282   { /* MSIRANGE from RCC_CR applies */
00283     msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
00284   }
00285   /*MSI frequency range in HZ*/
00286   msirange = MSIRangeTable[msirange];
00287 
00288   /* Get SYSCLK source -------------------------------------------------------*/
00289   switch (RCC->CFGR & RCC_CFGR_SWS)
00290   {
00291     case 0x00:  /* MSI used as system clock source */
00292       SystemCoreClock = msirange;
00293       break;
00294 
00295     case 0x04:  /* HSI used as system clock source */
00296       SystemCoreClock = HSI_VALUE;
00297       break;
00298 
00299     case 0x08:  /* HSE used as system clock source */
00300       SystemCoreClock = HSE_VALUE;
00301       break;
00302 
00303     case 0x0C:  /* PLL used as system clock  source */
00304       /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
00305          SYSCLK = PLL_VCO / PLLR
00306          */
00307       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
00308       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
00309 
00310       switch (pllsource)
00311       {
00312         case 0x02:  /* HSI used as PLL clock source */
00313           pllvco = (HSI_VALUE / pllm);
00314           break;
00315 
00316         case 0x03:  /* HSE used as PLL clock source */
00317           pllvco = (HSE_VALUE / pllm);
00318           break;
00319 
00320         default:    /* MSI used as PLL clock source */
00321           pllvco = (msirange / pllm);
00322           break;
00323       }
00324       pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
00325       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
00326       SystemCoreClock = pllvco/pllr;
00327       break;
00328 
00329     default:
00330       SystemCoreClock = msirange;
00331       break;
00332   }
00333   /* Compute HCLK clock frequency --------------------------------------------*/
00334   /* Get HCLK prescaler */
00335   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00336   /* HCLK clock frequency */
00337   SystemCoreClock >>= tmp;
00338 }
00339 
00340 
00341 /**
00342   * @}
00343   */
00344 
00345 /**
00346   * @}
00347   */
00348 
00349 /**
00350   * @}
00351   */
00352 
00353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00354