Semtech
NAMote72 Utility Application – Serial Terminal Monitor control for NAMote72 (note: this application replaces the previous na_mote1 test code application)
Dependencies: SX127x lib_gps lib_mma8451q lib_mpl3115a2 lib_sx9500 mbed
Fork of
na_mote1
by 
wayne roberts
Embed:
(wiki syntax)
Show/hide line numbers
main.cpp
00001 #include "sx127x_lora.h" 00002 #include "sx127x_fsk.h" 00003 00004 #include "mma8451q.h" 00005 #include "mpl3115a2.h" 00006 #include "sx9500.h" 00007 #include "gps.h" 00008 #include <inttypes.h> 00009 00010 #define RADIO_RESET PC_2 //NorAm_Mote Reset_sx 00011 #define RADIO_MOSI PB_15 //NorAm_Mote SPI2 Mosi 00012 #define RADIO_MISO PB_14 //NorAm_Mote SPI2 Miso 00013 #define RADIO_SCLK PB_13 //NorAm_Mote SPI2 Clk 00014 #define RADIO_NSS PB_12 //NorAm_Mote SPI2 Nss 00015 00016 #define RADIO_DIO_0 PC_6 //NorAm_Mote DIO0 00017 #define RADIO_DIO_1 PC_10 //NorAm_Mote DIO1 00018 #define RADIO_DIO_2 PC_8 //NorAm_Mote DIO2 00019 #define RADIO_DIO_3 PB_4 //NorAm_Mote DIO3 00020 #define RADIO_DIO_4 PB_5 //NorAm_Mote DIO4 00021 #define RADIO_DIO_5 PB_6 //NorAm_Mote DIO5 00022 00023 #define RFSW1 PC_4 //NorAm_Mote RFSwitch_CNTR_1 00024 #define RFSW2 PC_13 //NorAm_Mote RFSwitch_CNTR_2 00025 00026 #define FSK_RSSI_OFFSET 5 00027 #define FSK_RSSI_SMOOTHING 2 00028 /* 00029 * 00030 */ 00031 Serial pc(USBTX, USBRX); 00032 #ifdef I2C_PIN_TEST 00033 DigitalInOut pb8(PB_8); 00034 DigitalInOut pb9(PB_9); 00035 #else 00036 I2C i2c(I2C_SDA, I2C_SCL); 00037 DigitalIn i2c_int_pin(RADIO_DIO_3); 00038 MMA8451Q mma8451q(i2c, i2c_int_pin); 00039 MPL3115A2 mpl3115a2(i2c, i2c_int_pin); 00040 SX9500 sx9500(i2c, PA_9, PA_10); 00041 #endif /* I2C_PIN_TeST */ 00042 00043 /* gps(tx, rx, en); */ 00044 GPS gps(PB_6, PB_7, PB_11); 00045 DigitalOut pd2(PD_2); 00046 00047 AnalogIn* ain_bat; 00048 #define AIN_VREF 3.3 // stm32 internal refernce 00049 #define AIN_VBAT_DIV 2 // resistor divider 00050 00051 typedef enum { 00052 MOTE_NONE = 0, 00053 MOTE_V2, 00054 MOTE_V3 00055 } mote_version_e; 00056 00057 mote_version_e mote_version = MOTE_NONE; 00058 DigitalOut pc_7(PC_7); 00059 00060 DigitalIn pc_1(PC_1); 00061 DigitalOut hdr_fem_csd(PC_0); 00062 00063 DigitalOut red_led(PB_1); 00064 DigitalOut led2(PC_3); // green 00065 DigitalOut yellow_led(PB_10); 00066 #define LED_ON 0 00067 #define LED_OFF 1 00068 00069 Timeout hop_timeout; 00070 00071 InterruptIn dio3(PC_8); 00072 bool clear_valid_header; 00073 00074 #ifdef FCC_TEST 00075 typedef enum { 00076 HOP_TYPE_NONE = 0, 00077 HOP_TYPE_64CH, 00078 HOP_TYPE_4CH 00079 } hop_type_e; 00080 hop_type_e hop_type; 00081 float hop_base_MHz = 902.3; 00082 float hop_step_MHz = 0.2; 00083 #endif /* #ifdef FCC_TEST */ 00084 00085 bool abort_key; 00086 bool per_en; 00087 uint32_t PacketRxSequencePrev; 00088 uint32_t PacketPerKoCnt; 00089 uint32_t PacketPerOkCnt; 00090 uint32_t PacketNormalCnt; 00091 Timeout per_timeout; 00092 float per_tx_delay = 0.1; 00093 int per_id; 00094 uint32_t PacketTxCnt; 00095 00096 uint8_t tx_cnt; 00097 char pcbuf[64]; 00098 bool rx_after_tx; 00099 00100 typedef enum { 00101 APP_NONE = 0, 00102 APP_CHAT 00103 } app_e; 00104 00105 app_e app = APP_NONE; 00106 00107 char service_en = 1; 00108 00109 #define FSK_LARGE_PKT_THRESHOLD 0x3f 00110 00111 /******************************************************************************/ 00112 00113 SPI spi(RADIO_MOSI, RADIO_MISO, RADIO_SCLK); 00114 // dio0, dio1, nss, spi, rst 00115 SX127x radio(RADIO_DIO_0, RADIO_DIO_1, RADIO_NSS, spi, RADIO_RESET); 00116 00117 SX127x_fsk fsk(radio); 00118 SX127x_lora lora(radio); 00119 00120 DigitalOut rfsw1(RFSW1); 00121 DigitalOut rfsw2(RFSW2); 00122 DigitalIn dio2(RADIO_DIO_2); 00123 00124 void rfsw_callback() 00125 { 00126 if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { // start of transmission 00127 if (radio.HF) { 00128 if (radio.RegPaConfig.bits.PaSelect) { // if PA_BOOST 00129 rfsw2 = 0; 00130 rfsw1 = 1; 00131 } else { // RFO to power amp 00132 rfsw2 = 1; 00133 rfsw1 = 0; 00134 } 00135 } else { 00136 // todo: sx1276 00137 } 00138 //hdr_fem_csd = 1; //debug 00139 } else if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_CAD) { // start of reception 00140 if (radio.HF) { 00141 rfsw2 = 1; 00142 rfsw1 = 1; 00143 } else { 00144 // todo: sx1276 00145 } 00146 //hdr_fem_csd = 0; //debug 00147 } else { // RF switch shutdown 00148 rfsw2 = 0; 00149 rfsw1 = 0; 00150 //hdr_fem_csd = 0; //debug 00151 } 00152 } 00153 00154 void printLoraIrqs_(bool clear) 00155 { 00156 //in radio class -- RegIrqFlags_t RegIrqFlags; 00157 00158 //already read RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); 00159 printf("\r\nIrqFlags:"); 00160 if (lora.RegIrqFlags.bits.CadDetected) 00161 printf("CadDetected "); 00162 if (lora.RegIrqFlags.bits.FhssChangeChannel) { 00163 //radio.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); 00164 printf("FhssChangeChannel:%d ", lora.RegHopChannel.bits.FhssPresentChannel); 00165 } 00166 if (lora.RegIrqFlags.bits.CadDone) 00167 printf("CadDone "); 00168 if (lora.RegIrqFlags.bits.TxDone) 00169 printf("TxDone "); 00170 if (lora.RegIrqFlags.bits.ValidHeader) 00171 printf("[42mValidHeader[0m "); 00172 if (lora.RegIrqFlags.bits.PayloadCrcError) 00173 printf("[41mPayloadCrcError[0m "); 00174 if (lora.RegIrqFlags.bits.RxDone) 00175 printf("[42mRxDone[0m "); 00176 if (lora.RegIrqFlags.bits.RxTimeout) 00177 printf("RxTimeout "); 00178 00179 printf("\r\n"); 00180 00181 if (clear) 00182 radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); 00183 00184 } 00185 00186 void lora_printCodingRate(bool from_rx) 00187 { 00188 uint8_t d = lora.getCodingRate(from_rx); 00189 printf("CodingRate:"); 00190 switch (d) { 00191 case 1: printf("4/5 "); break; 00192 case 2: printf("4/6 "); break; 00193 case 3: printf("4/7 "); break; 00194 case 4: printf("4/8 "); break; 00195 default: 00196 printf("%d ", d); 00197 break; 00198 } 00199 } 00200 00201 void lora_printHeaderMode() 00202 { 00203 if (lora.getHeaderMode()) 00204 printf("implicit "); 00205 else 00206 printf("explicit "); 00207 } 00208 00209 void lora_printBw() 00210 { 00211 uint8_t bw = lora.getBw(); 00212 00213 printf("Bw:"); 00214 if (radio.type == SX1276) { 00215 switch (bw) { 00216 case 0: printf("7.8KHz "); break; 00217 case 1: printf("10.4KHz "); break; 00218 case 2: printf("15.6KHz "); break; 00219 case 3: printf("20.8KHz "); break; 00220 case 4: printf("31.25KHz "); break; 00221 case 5: printf("41.7KHz "); break; 00222 case 6: printf("62.5KHz "); break; 00223 case 7: printf("125KHz "); break; 00224 case 8: printf("250KHz "); break; 00225 case 9: printf("500KHz "); break; 00226 default: printf("%x ", lora.RegModemConfig.sx1276bits.Bw); break; 00227 } 00228 } else if (radio.type == SX1272) { 00229 switch (bw) { 00230 case 0: printf("125KHz "); break; 00231 case 1: printf("250KHz "); break; 00232 case 2: printf("500KHz "); break; 00233 case 3: printf("11b "); break; 00234 } 00235 } 00236 } 00237 00238 void lora_printAllBw() 00239 { 00240 int i, s; 00241 00242 if (radio.type == SX1276) { 00243 s = lora.RegModemConfig.sx1276bits.Bw; 00244 for (i = 0; i < 10; i++ ) { 00245 lora.RegModemConfig.sx1276bits.Bw = i; 00246 printf("%d ", i); 00247 lora_printBw(); 00248 printf("\r\n"); 00249 } 00250 lora.RegModemConfig.sx1276bits.Bw = s; 00251 } else if (radio.type == SX1272) { 00252 s = lora.RegModemConfig.sx1272bits.Bw; 00253 for (i = 0; i < 3; i++ ) { 00254 lora.RegModemConfig.sx1272bits.Bw = i; 00255 printf("%d ", i); 00256 lora_printBw(); 00257 printf("\r\n"); 00258 } 00259 lora.RegModemConfig.sx1272bits.Bw = s; 00260 } 00261 } 00262 00263 void lora_printSf() 00264 { 00265 // spreading factor same between sx127[26] 00266 printf("sf:%d ", lora.getSf()); 00267 } 00268 00269 void lora_printRxPayloadCrcOn() 00270 { 00271 bool on = lora.getRxPayloadCrcOn(); 00272 //printf("RxPayloadCrcOn:%s ", on ? "on" : "off"); 00273 if (on) 00274 printf("RxPayloadCrcOn:1 = Tx CRC Enabled\r\n"); 00275 else 00276 printf("RxPayloadCrcOn:1 = no Tx CRC\r\n"); 00277 } 00278 00279 void lora_printTxContinuousMode() 00280 { 00281 printf("TxContinuousMode:%d ", lora.RegModemConfig2.sx1276bits.TxContinuousMode); // same for sx1272 and sx1276 00282 } 00283 00284 void lora_printAgcAutoOn() 00285 { 00286 printf("AgcAutoOn:%d", lora.getAgcAutoOn()); 00287 } 00288 00289 void lora_print_dio() 00290 { 00291 radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); 00292 printf("DIO5:"); 00293 switch (radio.RegDioMapping2.bits.Dio5Mapping) { 00294 case 0: printf("ModeReady"); break; 00295 case 1: printf("ClkOut"); break; 00296 case 2: printf("ClkOut"); break; 00297 } 00298 printf(" DIO4:"); 00299 switch (radio.RegDioMapping2.bits.Dio4Mapping) { 00300 case 0: printf("CadDetected"); break; 00301 case 1: printf("PllLock"); break; 00302 case 2: printf("PllLock"); break; 00303 } 00304 radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); 00305 printf(" DIO3:"); 00306 switch (radio.RegDioMapping1.bits.Dio3Mapping) { 00307 case 0: printf("CadDone"); break; 00308 case 1: printf("ValidHeader"); break; 00309 case 2: printf("PayloadCrcError"); break; 00310 } 00311 printf(" DIO2:"); 00312 switch (radio.RegDioMapping1.bits.Dio2Mapping) { 00313 case 0: 00314 case 1: 00315 case 2: 00316 printf("FhssChangeChannel"); 00317 break; 00318 } 00319 printf(" DIO1:"); 00320 switch (radio.RegDioMapping1.bits.Dio1Mapping) { 00321 case 0: printf("RxTimeout"); break; 00322 case 1: printf("FhssChangeChannel"); break; 00323 case 2: printf("CadDetected"); break; 00324 } 00325 printf(" DIO0:"); 00326 switch (radio.RegDioMapping1.bits.Dio0Mapping) { 00327 case 0: printf("RxDone"); break; 00328 case 1: printf("TxDone"); break; 00329 case 2: printf("CadDone"); break; 00330 } 00331 00332 printf("\r\n"); 00333 } 00334 00335 void fsk_print_dio() 00336 { 00337 radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); 00338 00339 printf("DIO5:"); 00340 switch (radio.RegDioMapping2.bits.Dio5Mapping) { 00341 case 0: printf("ClkOut"); break; 00342 case 1: printf("PllLock"); break; 00343 case 2: 00344 if (fsk.RegPktConfig2.bits.DataModePacket) 00345 printf("data"); 00346 else { 00347 if (radio.RegDioMapping2.bits.MapPreambleDetect) 00348 printf("preamble"); 00349 else 00350 printf("rssi"); 00351 } 00352 break; 00353 case 3: printf("ModeReady"); break; 00354 } 00355 00356 printf(" DIO4:"); 00357 switch (radio.RegDioMapping2.bits.Dio4Mapping) { 00358 case 0: printf("temp/eol"); break; 00359 case 1: printf("PllLock"); break; 00360 case 2: printf("TimeOut"); break; 00361 case 3: 00362 if (fsk.RegPktConfig2.bits.DataModePacket) { 00363 if (radio.RegDioMapping2.bits.MapPreambleDetect) 00364 printf("preamble"); 00365 else 00366 printf("rssi"); 00367 } else 00368 printf("ModeReady"); 00369 break; 00370 } 00371 00372 radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); 00373 00374 printf(" DIO3:"); 00375 switch (radio.RegDioMapping1.bits.Dio3Mapping) { 00376 case 0: printf("Timeout"); break; 00377 case 1: 00378 if (radio.RegDioMapping2.bits.MapPreambleDetect) 00379 printf("preamble"); 00380 else 00381 printf("rssi"); 00382 break; 00383 case 2: printf("?automode_status?"); break; 00384 case 3: printf("TempChange/LowBat"); break; 00385 } 00386 00387 printf(" DIO2:"); 00388 if (fsk.RegPktConfig2.bits.DataModePacket) { 00389 switch (radio.RegDioMapping1.bits.Dio2Mapping) { 00390 case 0: printf("FifoFull"); break; 00391 case 1: printf("RxReady"); break; 00392 case 2: printf("FifoFull/rx-timeout"); break; 00393 case 3: printf("FifoFull/rx-syncadrs"); break; 00394 } 00395 } else { 00396 printf("Data"); 00397 } 00398 00399 printf(" DIO1:"); 00400 if (fsk.RegPktConfig2.bits.DataModePacket) { 00401 switch (radio.RegDioMapping1.bits.Dio1Mapping) { 00402 case 0: printf("FifoThresh"); break; 00403 case 1: printf("FifoEmpty"); break; 00404 case 2: printf("FifoFull"); break; 00405 case 3: printf("[41m-3-[0m"); break; 00406 } 00407 } else { 00408 switch (radio.RegDioMapping1.bits.Dio1Mapping) { 00409 case 0: printf("Dclk"); break; 00410 case 1: 00411 if (radio.RegDioMapping2.bits.MapPreambleDetect) 00412 printf("preamble"); 00413 else 00414 printf("rssi"); 00415 break; 00416 case 2: printf("[41m-2-[0m"); break; 00417 case 3: printf("[41m-3-[0m"); break; 00418 } 00419 } 00420 00421 printf(" DIO0:"); 00422 if (fsk.RegPktConfig2.bits.DataModePacket) { 00423 switch (radio.RegDioMapping1.bits.Dio0Mapping) { 00424 case 0: printf("PayloadReady/PacketSent"); break; 00425 case 1: printf("CrcOk"); break; 00426 case 2: printf("[41m-2-[0m"); break; 00427 case 3: printf("TempChange/LowBat"); break; 00428 } 00429 } else { 00430 switch (radio.RegDioMapping1.bits.Dio0Mapping) { 00431 case 0: printf("SyncAdrs/TxReady"); break; 00432 case 1: 00433 if (radio.RegDioMapping2.bits.MapPreambleDetect) 00434 printf("preamble"); 00435 else 00436 printf("rssi"); 00437 break; 00438 case 2: printf("RxReady"); break; 00439 case 3: printf("[41m-3-[0m"); break; 00440 } 00441 } 00442 printf("\r\n"); 00443 } 00444 00445 void lora_print_status() 00446 { 00447 uint8_t d; 00448 00449 if (radio.type == SX1276) 00450 printf("\r\nSX1276 "); 00451 else if (radio.type == SX1272) 00452 printf("\r\nSX1272 "); 00453 00454 radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); 00455 if (!radio.RegOpMode.bits.LongRangeMode) { 00456 printf("FSK\r\n"); 00457 return; 00458 } 00459 00460 lora_print_dio(); 00461 printf("LoRa "); 00462 00463 // printing LoRa registers at 0x0d -> 0x3f 00464 00465 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 00466 lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); 00467 00468 lora_printCodingRate(false); // false: transmitted coding rate 00469 lora_printHeaderMode(); 00470 lora_printBw(); 00471 lora_printSf(); 00472 lora_printRxPayloadCrcOn(); 00473 // RegModemStat 00474 printf("ModemStat:0x%02x\r\n", radio.read_reg(REG_LR_MODEMSTAT)); 00475 00476 // fifo ptrs: 00477 lora.RegPayloadLength = radio.read_reg(REG_LR_PAYLOADLENGTH); 00478 lora.RegRxMaxPayloadLength = radio.read_reg(REG_LR_RX_MAX_PAYLOADLENGTH); 00479 printf("fifoptr=0x%02x txbase=0x%02x rxbase=0x%02x payloadLength=0x%02x maxlen=0x%02x", 00480 radio.read_reg(REG_LR_FIFOADDRPTR), 00481 radio.read_reg(REG_LR_FIFOTXBASEADDR), 00482 radio.read_reg(REG_LR_FIFORXBASEADDR), 00483 lora.RegPayloadLength, 00484 lora.RegRxMaxPayloadLength 00485 ); 00486 00487 lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); 00488 printLoraIrqs_(false); 00489 00490 lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); 00491 if (lora.RegHopPeriod != 0) { 00492 printf("\r\nHopPeriod:0x%02x\r\n", lora.RegHopPeriod); 00493 } 00494 00495 printf("SymbTimeout:0x%03x ", radio.read_u16(REG_LR_MODEMCONFIG2) & 0x3ff); 00496 00497 lora.RegPreamble = radio.read_u16(REG_LR_PREAMBLEMSB); 00498 printf("PreambleLength:%d ", lora.RegPreamble); 00499 00500 if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER_SINGLE) { 00501 d = radio.read_reg(REG_LR_RSSIVALUE); 00502 printf("rssi:%ddBm ", d-120); 00503 } 00504 00505 lora_printTxContinuousMode(); 00506 00507 printf("\r\n"); 00508 lora_printAgcAutoOn(); 00509 00510 printf("\r\nHeaderCount:%d PacketCount:%d, ", 00511 radio.read_u16(REG_LR_RXHEADERCNTVALUE_MSB), radio.read_u16(REG_LR_RXPACKETCNTVALUE_MSB)); 00512 00513 printf("Lora detection threshold:%02x\r\n", radio.read_reg(REG_LR_DETECTION_THRESHOLD)); 00514 lora.RegTest31.octet = radio.read_reg(REG_LR_TEST31); 00515 printf("detect_trig_same_peaks_nb:%d\r\n", lora.RegTest31.bits.detect_trig_same_peaks_nb); 00516 00517 printf("LowDataRateOptimize:"); 00518 if (radio.type == SX1272) { 00519 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 00520 printf("%d ", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); 00521 } else if (radio.type == SX1276) { 00522 lora.RegModemConfig3.octet = radio.read_reg(REG_LR_MODEMCONFIG3); 00523 printf("%d ", lora.RegModemConfig3.sx1276bits.LowDataRateOptimize); 00524 } 00525 00526 printf(" invert: rx=%d tx=%d\r\n", lora.RegTest33.bits.invert_i_q, !lora.RegTest33.bits.chirp_invert_tx); 00527 00528 #ifdef FCC_TEST 00529 switch (hop_type) { 00530 case HOP_TYPE_NONE: 00531 break; 00532 case HOP_TYPE_64CH: 00533 printf("hop 64ch\r\n"); 00534 break; 00535 case HOP_TYPE_4CH: 00536 printf("hop 4ch\r\n"); 00537 break; 00538 } 00539 #endif /* #ifdef FCC_TEST */ 00540 printf("\r\n"); 00541 } 00542 00543 uint16_t 00544 fsk_get_PayloadLength(void) 00545 { 00546 fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); 00547 00548 return fsk.RegPktConfig2.bits.PayloadLength; 00549 } 00550 00551 void fsk_printAddressFiltering() 00552 { 00553 uint8_t FSKRegNodeAdrs, FSKRegBroadcastAdrs; 00554 00555 printf(" AddressFiltering:"); 00556 switch (fsk.RegPktConfig1.bits.AddressFiltering) { 00557 case 0: printf("off"); break; 00558 case 1: // NodeAddress 00559 FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); 00560 printf("NodeAdrs:%02x\r\n", FSKRegNodeAdrs); 00561 break; 00562 case 2: // NodeAddress & BroadcastAddress 00563 FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); 00564 printf("NodeAdrs:%02x ", FSKRegNodeAdrs); 00565 FSKRegBroadcastAdrs = radio.read_reg(REG_FSK_BROADCASTADRS); 00566 printf("BroadcastAdrs:%02x\r\n", FSKRegBroadcastAdrs ); 00567 break; 00568 default: 00569 printf("%d", fsk.RegPktConfig1.bits.AddressFiltering); 00570 break; 00571 } 00572 } 00573 00574 void fsk_print_IrqFlags2() 00575 { 00576 RegIrqFlags2_t RegIrqFlags2; 00577 00578 printf("IrqFlags2: "); 00579 RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); 00580 if (RegIrqFlags2.bits.FifoFull) 00581 printf("FifoFull "); 00582 if (RegIrqFlags2.bits.FifoEmpty) 00583 printf("FifoEmpty "); 00584 if (RegIrqFlags2.bits.FifoLevel) 00585 printf("FifoLevel "); 00586 if (RegIrqFlags2.bits.FifoOverrun) 00587 printf("FifoOverrun "); 00588 if (RegIrqFlags2.bits.PacketSent) 00589 printf("PacketSent "); 00590 if (RegIrqFlags2.bits.PayloadReady) 00591 printf("PayloadReady "); 00592 if (RegIrqFlags2.bits.CrcOk) 00593 printf("CrcOk "); 00594 if (RegIrqFlags2.bits.LowBat) 00595 printf("LowBat "); 00596 printf("\r\n"); 00597 } 00598 00599 void 00600 fsk_print_status() 00601 { 00602 //uint16_t s; 00603 RegIrqFlags1_t RegIrqFlags1; 00604 00605 if (radio.RegOpMode.bits.LongRangeMode) { 00606 printf("LoRa\r\n"); 00607 return; 00608 } 00609 00610 if (radio.RegOpMode.bits.ModulationType == 0) { 00611 printf("FSK "); 00612 switch (radio.RegOpMode.bits.ModulationShaping) { 00613 case 1: printf("BT1.0 "); break; 00614 case 2: printf("BT0.5 "); break; 00615 case 3: printf("BT0.3 "); break; 00616 } 00617 } else if (radio.RegOpMode.bits.ModulationType == 1) { 00618 printf("OOK "); 00619 } 00620 00621 printf("%" PRIu32 "bps fdev:%" PRIu32 "Hz\r\n", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); 00622 00623 fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); 00624 00625 fsk_print_dio(); 00626 00627 printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); 00628 printf("afcbw:%" PRIu32 "Hz\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW)); 00629 00630 fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); 00631 printf("RssiOffset:%ddB smoothing:%dsamples\r\n", fsk.RegRssiConfig.bits.RssiOffset, 1 << (fsk.RegRssiConfig.bits.RssiSmoothing+1)); 00632 00633 00634 fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); 00635 00636 if (fsk.RegPktConfig2.bits.DataModePacket) { 00637 uint16_t len; 00638 /* packet mode */ 00639 len = fsk_get_PayloadLength(); 00640 printf("packet RegPayloadLength:0x%03x ", len); 00641 00642 if (fsk.RegPktConfig2.bits.BeaconOn) 00643 printf("BeaconOn "); 00644 00645 fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); 00646 printf("FifoThreshold:%d TxStartCondition:", fsk.RegFifoThreshold.bits.FifoThreshold); 00647 if (fsk.RegFifoThreshold.bits.TxStartCondition) 00648 printf("!FifoEmpty"); 00649 else 00650 printf("FifoLevel"); 00651 00652 printf("\r\nAutoRestartRxMode:"); 00653 switch (fsk.RegSyncConfig.bits.AutoRestartRxMode) { 00654 case 0: printf("off "); break; 00655 case 1: printf("no-pll-wait "); break; 00656 case 2: printf("pll-wait "); break; 00657 case 3: printf("3 "); break; 00658 } 00659 //...todo 00660 00661 printf("PreambleSize:%d ", radio.read_u16(REG_FSK_PREAMBLEMSB)); 00662 00663 fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); 00664 if (fsk.RegOokPeak.bits.barker_en) 00665 printf("barker "); 00666 if (!fsk.RegOokPeak.bits.BitSyncOn) 00667 printf("BitSyncOff "); 00668 //...todo 00669 00670 fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); 00671 if (fsk.RegPktConfig1.bits.PacketFormatVariable) 00672 printf("variable"); 00673 else 00674 printf("fixed"); 00675 printf("-length\r\ncrc"); 00676 if (fsk.RegPktConfig1.bits.CrcOn) { 00677 printf("On"); 00678 } else 00679 printf("Off"); 00680 printf(" crctype:"); 00681 if (fsk.RegPktConfig1.bits.CrCWhiteningType) 00682 printf("IBM"); 00683 else 00684 printf("CCITT"); 00685 printf(" dcFree:"); 00686 switch (fsk.RegPktConfig1.bits.DcFree) { 00687 case 0: printf("none "); break; 00688 case 1: printf("Manchester "); break; 00689 case 2: printf("Whitening "); break; 00690 case 3: printf("[41mreserved[0m "); break; 00691 } 00692 fsk_printAddressFiltering(); 00693 00694 printf("\r\n"); 00695 fsk_print_IrqFlags2(); 00696 } else { 00697 /* continuous mode */ 00698 printf("[7mcontinuous[27m "); 00699 } 00700 00701 fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); 00702 printf("PreambleDetect:"); 00703 if (fsk.RegPreambleDetect.bits.PreambleDetectorOn) { 00704 printf("size=%d,tol=%d ", 00705 fsk.RegPreambleDetect.bits.PreambleDetectorSize, 00706 fsk.RegPreambleDetect.bits.PreambleDetectorTol); 00707 } else 00708 printf("Off "); 00709 00710 printf(" syncsize:%d ", fsk.RegSyncConfig.bits.SyncSize); 00711 printf(" : %02x ", radio.read_reg(REG_FSK_SYNCVALUE1)); 00712 printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE2)); 00713 printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE3)); 00714 printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE4)); 00715 printf("\r\n"); // end sync config 00716 00717 fsk.RegAfcFei.octet = radio.read_reg(REG_FSK_AFCFEI); 00718 printf("afcAutoClear:"); 00719 if (fsk.RegAfcFei.bits.AfcAutoClearOn) 00720 printf("On"); 00721 else 00722 printf("OFF"); 00723 printf(" afc:%dHz ", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); 00724 00725 printf("fei:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_FEIMSB))); 00726 00727 fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); 00728 printf("RxTrigger:"); 00729 switch (fsk.RegRxConfig.bits.RxTrigger) { 00730 case 0: printf("none "); break; 00731 case 1: printf("rssi "); break; 00732 case 6: printf("preamble "); break; 00733 case 7: printf("both "); break; 00734 default: printf("-%d- ", fsk.RegRxConfig.bits.RxTrigger); break; 00735 } 00736 printf("AfcAuto:"); 00737 if (fsk.RegRxConfig.bits.AfcAutoOn) 00738 printf("On "); 00739 else 00740 printf("OFF "); 00741 if (fsk.RegRxConfig.bits.AgcAutoOn) { 00742 printf("AgcAutoOn "); 00743 } else { 00744 radio.RegLna.octet = radio.read_reg(REG_LNA); 00745 printf("AgcAutoOff:G%d ", radio.RegLna.bits.LnaGain); 00746 } 00747 00748 fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); 00749 if (fsk.RegTimerResol.bits.hlm_started) 00750 printf("[35mhlm_started[0m "); 00751 else 00752 printf("hlm_stopped "); 00753 00754 fsk.RegRssiThresh = radio.read_reg(REG_FSK_RSSITHRESH); 00755 printf("rssiThreshold:-%.1f@%02x ", fsk.RegRssiThresh / 2.0, REG_FSK_RSSITHRESH); 00756 00757 radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); 00758 if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || 00759 radio.RegOpMode.bits.Mode == RF_OPMODE_SYNTHESIZER_RX) 00760 { 00761 printf("rssi:-%.1f ", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); 00762 } 00763 00764 fsk.RegSeqConfig1.octet = radio.read_reg(REG_FSK_SEQCONFIG1); 00765 printf("\r\nsequencer: "); 00766 printf("FromStart:"); 00767 switch (fsk.RegSeqConfig1.bits.FromStart) { 00768 case 0: 00769 printf("lowPowerSelection-"); 00770 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00771 printf("idle"); 00772 else 00773 printf("sequencerOff"); 00774 break; 00775 case 1: printf("rx"); break; 00776 case 2: printf("tx"); break; 00777 case 3: printf("tx on fifolevel"); break; 00778 } 00779 printf(" lowPowerSelection:"); 00780 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00781 printf("idle"); 00782 else 00783 printf("SequencerOff"); 00784 if (fsk.RegSeqConfig1.bits.FromStart != 0 && 00785 fsk.RegSeqConfig1.bits.LowPowerSelection != 0) 00786 { // if sequencer enabled: 00787 printf("\r\nsequencer: IdleMode:"); 00788 if (fsk.RegSeqConfig1.bits.IdleMode) 00789 printf("Sleep"); 00790 else 00791 printf("standby"); 00792 printf("\r\nsequencer: FromIdle to:"); 00793 if (fsk.RegSeqConfig1.bits.FromIdle) 00794 printf("rx"); 00795 else 00796 printf("tx"); 00797 printf("\r\nsequencer: FromTransmit to:"); 00798 if (fsk.RegSeqConfig1.bits.FromTransmit) 00799 printf("rx-on-PacketSent"); 00800 else { 00801 printf("lowPowerSelection-"); 00802 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00803 printf("idle"); 00804 else 00805 printf("SequencerOff"); 00806 printf("-on-PacketSent"); 00807 } 00808 fsk.RegSeqConfig2.octet = radio.read_reg(REG_FSK_SEQCONFIG2); 00809 printf("\r\nsequencer: FromReceive:"); 00810 switch (fsk.RegSeqConfig2.bits.FromReceive) { 00811 case 1: printf("PacketRecevied on PayloadReady"); break; 00812 case 2: 00813 printf("lowPowerSelection-"); 00814 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00815 printf("idle"); 00816 else 00817 printf("SequencerOff"); 00818 printf("-on-payloadReady"); 00819 break; 00820 case 3: printf("PacketRecevied-on-CrcOk"); break; 00821 case 4: printf("SequencerOff-on-Rssi"); break; 00822 case 5: printf("SequencerOff-on-SyncAddress"); break; 00823 case 6: printf("SequencerOff-PreambleDetect"); break; 00824 default: printf("-%d-", fsk.RegSeqConfig2.bits.FromReceive); break; 00825 } 00826 printf("\r\nsequencer: FromRxTimeout:"); 00827 switch (fsk.RegSeqConfig2.bits.FromRxTimeout) { 00828 case 0: printf("rx"); break; 00829 case 1: printf("tx"); break; 00830 case 2: 00831 printf("lowPowerSelection-"); 00832 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00833 printf("idle"); 00834 else 00835 printf("SequencerOff"); 00836 break; 00837 case 3: printf("SequencerOff"); break; 00838 } 00839 printf("\r\nsequencer: FromPacketReceived to:"); 00840 switch (fsk.RegSeqConfig2.bits.FromPacketReceived) { 00841 case 0: printf("SequencerOff"); break; 00842 case 1: printf("tx on FifoEmpty"); break; 00843 case 2: 00844 printf("lowPowerSelection-"); 00845 if (fsk.RegSeqConfig1.bits.LowPowerSelection) 00846 printf("idle"); 00847 else 00848 printf("sequencerOff"); 00849 break; 00850 case 3: printf("rx via fs"); break; 00851 case 4: printf("rx"); break; 00852 } 00853 00854 fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); 00855 printf("\r\nsequencer: timer1:"); 00856 switch (fsk.RegTimerResol.bits.timer1_resol) { 00857 case 0: printf("off"); break; 00858 case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER1COEF) * 64); break; 00859 case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER1COEF) * 4.1); break; 00860 case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER1COEF) * 0.262); break; 00861 } 00862 00863 printf(" timer2:"); 00864 switch (fsk.RegTimerResol.bits.timer2_resol) { 00865 case 0: printf("off"); break; 00866 case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER2COEF) * 64); break; 00867 case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER2COEF) * 4.1); break; 00868 case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER2COEF) * 0.262); break; 00869 } 00870 } // ..if sequencer enabled 00871 00872 printf("\r\nIrqFlags1:"); 00873 RegIrqFlags1.octet = radio.read_reg(REG_FSK_IRQFLAGS1); 00874 if (RegIrqFlags1.bits.ModeReady) 00875 printf("ModeReady "); 00876 if (RegIrqFlags1.bits.RxReady) 00877 printf("RxReady "); 00878 if (RegIrqFlags1.bits.TxReady) 00879 printf("TxReady "); 00880 if (RegIrqFlags1.bits.PllLock) 00881 printf("PllLock "); 00882 if (RegIrqFlags1.bits.Rssi) 00883 printf("Rssi "); 00884 if (RegIrqFlags1.bits.Timeout) 00885 printf("Timeout "); 00886 if (RegIrqFlags1.bits.PreambleDetect) 00887 printf("PreambleDetect "); 00888 if (RegIrqFlags1.bits.SyncAddressMatch) 00889 printf("SyncAddressMatch "); 00890 00891 printf("\r\n"); 00892 00893 /* TODO if (!SX1272FSK->RegPktConfig1.bits.PacketFormatVariable) { // if fixed-length packet format: 00894 s = fsk_get_PayloadLength(); 00895 if (s > FSK_LARGE_PKT_THRESHOLD) 00896 flags.fifo_flow_ctl = 1; 00897 else 00898 flags.fifo_flow_ctl = 0; 00899 }*/ 00900 00901 fsk.RegImageCal.octet = radio.read_reg(REG_FSK_IMAGECAL); 00902 if (fsk.RegImageCal.bits.TempMonitorOff) { 00903 printf("[42mTempMonitorOff[\r0m\r\n"); 00904 } else { 00905 printf("TempThreshold:"); 00906 switch (fsk.RegImageCal.bits.TempThreshold) { 00907 case 0: printf("5C"); break; 00908 case 1: printf("10C"); break; 00909 case 2: printf("15C"); break; 00910 case 3: printf("20C"); break; 00911 } 00912 printf("\r\n"); 00913 } 00914 if (fsk.RegImageCal.bits.ImageCalRunning) 00915 printf("[33mImageCalRunning[\r0m\r\n"); 00916 00917 /* printf("flags.fifo_flow_ctl:%d pktidx:%d rx_pktlen:%d", flags.fifo_flow_ctl, pktidx, rx_pktlen); 00918 printf("\r\n"); 00919 00920 //printf("DIO0_PIN:%d\r\n", digitalRead(DIO0_PIN)); 00921 printf("pkt_buf_len=%d remaining=%d\r\n", pk*/ 00922 } 00923 00924 void printOpMode() 00925 { 00926 radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); 00927 switch (radio.RegOpMode.bits.Mode) { 00928 case RF_OPMODE_SLEEP: printf("[7msleep[0m"); break; 00929 case RF_OPMODE_STANDBY: printf("[7mstby[0m"); break; 00930 case RF_OPMODE_SYNTHESIZER_TX: printf("[33mfstx[0m"); break; 00931 case RF_OPMODE_TRANSMITTER: printf("[31mtx[0m"); break; 00932 case RF_OPMODE_SYNTHESIZER_RX: printf("[33mfsrx[0m"); break; 00933 case RF_OPMODE_RECEIVER: printf("[32mrx[0m"); break; 00934 case 6: 00935 if (radio.RegOpMode.bits.LongRangeMode) 00936 printf("[42mrxs[0m"); 00937 else 00938 printf("-6-"); 00939 break; // todo: different lora/fsk 00940 case 7: 00941 if (radio.RegOpMode.bits.LongRangeMode) 00942 printf("[45mcad[0m"); 00943 else 00944 printf("-7-"); 00945 break; // todo: different lora/fsk 00946 } 00947 } 00948 00949 void 00950 printPa() 00951 { 00952 RegPdsTrim1_t pds_trim; 00953 00954 pds_trim.octet = radio.read_reg(REG_PDSTRIM1_SX1272); 00955 printf(" txdac=%.1fuA", 2.5 + (pds_trim.bits.prog_txdac * 0.625)); 00956 radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); 00957 if (radio.RegPaConfig.bits.PaSelect) { 00958 //float output_dBm = 17 - (15-radio.RegPaConfig.bits.OutputPower); 00959 float output_dBm = (pds_trim.bits.prog_txdac+13) - (15-radio.RegPaConfig.bits.OutputPower); 00960 printf(" PABOOST OutputPower=%.1fdBm", output_dBm); 00961 } else { 00962 float pmax = (0.6*radio.RegPaConfig.bits.MaxPower) + 10.8; 00963 float output_dBm = pmax - (15-radio.RegPaConfig.bits.OutputPower); 00964 printf(" RFO pmax=%.1fdBm OutputPower=%.1fdBm", pmax, output_dBm); 00965 } 00966 } 00967 00968 void /* things always present, whether lora or fsk */ 00969 common_print_status() 00970 { 00971 printf("PD2:%d version:0x%02x %.3fMHz ", pd2.read(), radio.read_reg(REG_VERSION), radio.get_frf_MHz()); 00972 printOpMode(); 00973 00974 printPa(); 00975 00976 radio.RegOcp.octet = radio.read_reg(REG_OCP); 00977 if (radio.RegOcp.bits.OcpOn) { 00978 int imax = 0; 00979 if (radio.RegOcp.bits.OcpTrim < 16) 00980 imax = (5 * radio.RegOcp.bits.OcpTrim) + 45; 00981 else if (radio.RegOcp.bits.OcpTrim < 28) 00982 imax = (10 * radio.RegOcp.bits.OcpTrim) - 30; 00983 else 00984 imax = 240; 00985 printf(" OcpOn %dmA ", imax); 00986 } else 00987 printf(" OcpOFF "); 00988 00989 printf("\r\n"); 00990 00991 if (per_en) { 00992 printf("per_tx_delay:%f\r\n", per_tx_delay); 00993 printf("PER device ID:%d\r\n", per_id); 00994 } 00995 printf("GPS enabled:%d ", gps.enabled()); 00996 if (mote_version == MOTE_V2) 00997 printf("MOTE_V2\r\n"); 00998 else if (mote_version == MOTE_V3) 00999 printf("MOTE_V3\r\n"); 01000 } 01001 01002 void per_cb() 01003 { 01004 int i; 01005 01006 PacketTxCnt++; 01007 01008 radio.tx_buf[0] = per_id; 01009 radio.tx_buf[1] = PacketTxCnt >> 24; 01010 radio.tx_buf[2] = PacketTxCnt >> 16; 01011 radio.tx_buf[3] = PacketTxCnt >> 8; 01012 radio.tx_buf[4] = PacketTxCnt; 01013 radio.tx_buf[5] = 'P'; 01014 radio.tx_buf[6] = 'E'; 01015 radio.tx_buf[7] = 'R'; 01016 radio.tx_buf[8] = 0; 01017 for (i = 0; i < 8; i++) 01018 radio.tx_buf[8] += radio.tx_buf[i]; 01019 red_led = LED_ON; 01020 01021 if (radio.RegOpMode.bits.LongRangeMode) { 01022 lora.start_tx(lora.RegPayloadLength); 01023 } else { 01024 fsk.start_tx(9); 01025 } 01026 } 01027 01028 01029 01030 void dio3_cb() 01031 { 01032 //green_led = LED_ON; 01033 clear_valid_header = true; 01034 } 01035 01036 bool lora_sync_sweep_hi; 01037 uint8_t lora_sync_byte; 01038 void lora_sync_sweep() 01039 { 01040 if (abort_key) { 01041 abort_key = false; 01042 return; 01043 } 01044 01045 hop_timeout.attach(&lora_sync_sweep, 0.1); 01046 if (lora_sync_sweep_hi) { 01047 lora_sync_byte += 0x10; 01048 } else { 01049 if ((lora_sync_byte & 0x0f) == 0x0f) 01050 lora_sync_byte &= 0xf0; 01051 else 01052 lora_sync_byte++; 01053 } 01054 printf("%02x\r\n", lora_sync_byte); 01055 radio.write_reg(REG_LR_SYNC_BYTE, lora_sync_byte); 01056 01057 lora.start_tx(lora.RegPayloadLength); 01058 } 01059 01060 #ifdef FCC_TEST 01061 float hop_MHz; 01062 bool new_hop; 01063 uint8_t hop_ofs = 0; 01064 01065 void hop_cb() 01066 { 01067 static uint8_t prev_ofs; 01068 int shift; 01069 01070 radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); 01071 if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) 01072 hop_timeout.attach(&hop_cb, 0.4); 01073 else 01074 return; 01075 01076 do { 01077 shift = rand() & 0x1f; 01078 if (hop_type == HOP_TYPE_64CH) 01079 hop_ofs = (rand() >> shift) & 0x3f; 01080 else if (hop_type == HOP_TYPE_4CH) 01081 hop_ofs = (rand() >> shift) & 0x3; 01082 } while (hop_ofs == prev_ofs); 01083 01084 prev_ofs = hop_ofs; 01085 hop_MHz = hop_base_MHz + (hop_ofs * hop_step_MHz); 01086 new_hop = true; 01087 01088 radio.set_frf_MHz(hop_MHz); 01089 01090 radio.set_opmode(RF_OPMODE_STANDBY); 01091 radio.set_opmode(RF_OPMODE_TRANSMITTER); 01092 01093 if (pc_7.read()) 01094 pc_7 = 0; 01095 else 01096 pc_7 = 1; 01097 } 01098 #endif /* #ifdef FCC_TEST */ 01099 01100 void print_rx_buf(int len) 01101 { 01102 int i; 01103 01104 printf("000:"); 01105 for (i = 0; i < len; i++) { 01106 //printf("(%d)%02x ", i % 16, rx_buf[i]); 01107 printf("%02x ", radio.rx_buf[i]); 01108 if (i % 16 == 15 && i != len-1) 01109 printf("\r\n%03d:", i+1); 01110 01111 } 01112 printf("\r\n"); 01113 } 01114 01115 void print_rx_verbose(uint8_t dlen) 01116 { 01117 float dbm; 01118 printLoraIrqs_(false); 01119 if (lora.RegHopPeriod > 0) { 01120 lora.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); 01121 printf("HopCH:%d ", lora.RegHopChannel.bits.FhssPresentChannel); 01122 } 01123 printf("%dHz ", lora.get_freq_error_Hz()); 01124 lora_printCodingRate(true); // true: of received packet 01125 dbm = lora.get_pkt_rssi(); 01126 printf(" crc%s %.1fdB %.1fdBm\r\n", 01127 lora.RegHopChannel.bits.RxPayloadCrcOn ? "On" : "OFF", 01128 lora.RegPktSnrValue / 4.0, 01129 dbm 01130 ); 01131 print_rx_buf(/*lora.RegRxNbBytes*/dlen); 01132 01133 } 01134 01135 int per_parse_rx(uint8_t len) 01136 { 01137 if (len > 8 && radio.rx_buf[5] == 'P' && radio.rx_buf[6] == 'E' && radio.rx_buf[7] == 'R') { 01138 int i; 01139 float per; 01140 01141 /* this is PER packet */ 01142 uint32_t PacketRxSequence = (radio.rx_buf[1] << 24) | (radio.rx_buf[2] << 16) | (radio.rx_buf[3] << 8) | radio.rx_buf[4]; 01143 PacketPerOkCnt++; 01144 01145 if( PacketRxSequence <= PacketRxSequencePrev ) 01146 { // Sequence went back => resynchronization 01147 // dont count missed packets this time 01148 i = 0; 01149 } 01150 else 01151 { 01152 // determine number of missed packets 01153 i = PacketRxSequence - PacketRxSequencePrev - 1; 01154 } 01155 01156 red_led = !red_led.read(); 01157 // be ready for the next 01158 PacketRxSequencePrev = PacketRxSequence; 01159 // increment 'missed' counter for the RX session 01160 PacketPerKoCnt += i; 01161 per = ( 1.0 - ( float )PacketPerOkCnt / ( float )( PacketPerOkCnt + PacketPerKoCnt ) ) * 100.0; 01162 printf("%" PRIu32 ", ok=%" PRIu32 " missed=%" PRIu32 " normal=%" PRIu32 " per:%.3f ", PacketRxSequence, PacketPerOkCnt, PacketPerKoCnt, PacketNormalCnt, per); 01163 if (radio.RegOpMode.bits.LongRangeMode) 01164 printf("pkt:%ddBm, snr:%.1fdB, %ddBm\r\n", lora.get_pkt_rssi(), lora.RegPktSnrValue / 4.0, lora.get_current_rssi()); 01165 else { 01166 wait_us(10000); 01167 printf(" -%.1fdBm\r\n", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); 01168 } 01169 01170 return 1; 01171 } else { 01172 return 0; 01173 } 01174 } 01175 01176 void 01177 service_radio() 01178 { 01179 service_action_e act; 01180 static uint8_t rssi = 0; 01181 01182 if (radio.RegOpMode.bits.LongRangeMode) { 01183 01184 act = lora.service(); 01185 01186 switch (act) { 01187 case SERVICE_READ_FIFO: 01188 //green_led = LED_OFF; // ValidHeader indication 01189 01190 if (app == APP_NONE) { 01191 if (per_en) { 01192 if (!per_parse_rx(lora.RegRxNbBytes)) { 01193 PacketNormalCnt++; 01194 print_rx_verbose(lora.RegRxNbBytes); 01195 } 01196 } else 01197 print_rx_verbose(lora.RegRxNbBytes); 01198 fflush(stdout); 01199 } else if (app == APP_CHAT) { 01200 if (lora.RegHopChannel.bits.RxPayloadCrcOn) { 01201 if (lora.RegIrqFlags.bits.PayloadCrcError) 01202 printf("crcError\r\n"); 01203 else { 01204 int n = lora.RegRxNbBytes; 01205 radio.rx_buf[n++] = '\r'; 01206 radio.rx_buf[n++] = '\n'; 01207 radio.rx_buf[n] = 0; // null terminate 01208 printf((char *)radio.rx_buf); 01209 } 01210 } else 01211 printf("crcOff\r\n"); 01212 01213 // clear Irq flags 01214 radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); 01215 // should still be in receive mode 01216 } 01217 break; 01218 case SERVICE_TX_DONE: 01219 red_led = LED_OFF; 01220 hdr_fem_csd = 0; //debug 01221 if (app == APP_CHAT) { 01222 lora.start_rx(RF_OPMODE_RECEIVER); 01223 } else if (per_en) 01224 per_timeout.attach(&per_cb, per_tx_delay); // start next TX 01225 else if (rx_after_tx) 01226 lora.start_rx(RF_OPMODE_RECEIVER); 01227 break; 01228 case SERVICE_ERROR: 01229 printf("error\r\n"); 01230 break; 01231 case SERVICE_NONE: 01232 break; 01233 } // ...switch (act) 01234 } else { 01235 /* FSK: */ 01236 act = fsk.service(); 01237 01238 switch (act) { 01239 case SERVICE_READ_FIFO: 01240 if (app == APP_CHAT) { 01241 int n = fsk.rx_buf_length; 01242 radio.rx_buf[n++] = '\r'; 01243 radio.rx_buf[n++] = '\n'; 01244 radio.rx_buf[n] = 0; // null terminate 01245 printf((char *)radio.rx_buf); 01246 } else { 01247 if (fsk.RegRxConfig.bits.AfcAutoOn) { 01248 printf("%dHz ", (int)(FREQ_STEP_HZ * fsk.RegAfcValue)); 01249 if (rssi != 0) { 01250 printf("pkt:-%.1fdBm ", rssi / 2.0); 01251 rssi = 0; 01252 } 01253 } 01254 if (per_en) { 01255 if (!per_parse_rx(fsk.rx_buf_length)) { 01256 PacketNormalCnt++; 01257 print_rx_buf(fsk.rx_buf_length); 01258 } 01259 } else { 01260 print_rx_buf(fsk.rx_buf_length); 01261 } 01262 fflush(stdout); 01263 } 01264 break; 01265 case SERVICE_TX_DONE: 01266 if (app == APP_CHAT) { 01267 fsk.start_rx(); 01268 } else if (per_en) { 01269 per_timeout.attach(&per_cb, per_tx_delay); // start next TX 01270 } 01271 break; 01272 case SERVICE_ERROR: 01273 case SERVICE_NONE: 01274 break; 01275 } // ...switch (act) 01276 01277 /* fsk sync address */ 01278 if (dio2 && radio.RegDioMapping1.bits.Dio2Mapping == 3) { 01279 // syncAdrs when in RX mode 01280 if (rssi == 0) { 01281 rssi = radio.read_reg(REG_FSK_RSSIVALUE); 01282 } 01283 } 01284 01285 } 01286 01287 if (clear_valid_header) { 01288 RegIrqFlags_t irqs; 01289 irqs.octet = 0; 01290 irqs.bits.ValidHeader = 1; 01291 radio.write_reg(REG_LR_IRQFLAGS, irqs.octet); 01292 clear_valid_header = false; 01293 } 01294 01295 #ifdef FCC_TEST 01296 if (new_hop) { 01297 new_hop = false; 01298 printf("%02d %.1f\r\n", hop_ofs, hop_MHz); 01299 } 01300 #endif /* #ifdef FCC_TEST */ 01301 } 01302 01303 void 01304 gps_service() 01305 { 01306 gps.service(); 01307 if (gps.enabled()) { 01308 if (gps.LatitudeBinary != 0) { 01309 gps.LatitudeBinary = 0; 01310 printf("gps long:%f, lat:%f Vbat:%.2fV\r\n", gps.Longitude, gps.Latitude, ain_bat->read()*AIN_VREF*AIN_VBAT_DIV); 01311 } 01312 } 01313 } 01314 01315 RCC_OscInitTypeDef prev_RCC_OscInitStruct; 01316 01317 void all_peripherals_off() 01318 { 01319 // TODO: PD2 low, has pulldown 01320 01321 HAL_RCC_GetOscConfig(&prev_RCC_OscInitStruct); 01322 /*printf("hsiState:%d\r\n", osc_init.HSIState); 01323 wait(0.05);*/ 01324 01325 #ifndef USE_DEBUGGER 01326 /* PA13 to undriven JTMS/SWDIO pin (from AF0 to GPIO), and PA2 */ 01327 GPIOA->MODER &= 0xf7ffffdf; 01328 GPIOB->MODER &= 0xffffdfff; // PB6 UART_TX to input 01329 #endif 01330 01331 sx9500.set_active(false); 01332 mpl3115a2.SetModeStandby(); 01333 mma8451q.set_active(0); 01334 gps.enable(false); 01335 01336 if (GPIOB->ODR & 0x1000) { // if SX1272_NSS (PB12) wasnt forced low 01337 radio.set_opmode(RF_OPMODE_SLEEP); 01338 } 01339 } 01340 01341 01342 01343 void restore_from_sleep() 01344 { 01345 RCC_OscInitTypeDef osc_init; 01346 #ifndef USE_DEBUGGER 01347 /* PA13 back to JTMS/SWDIO pin (from GPIO to AF0), and PA2 */ 01348 GPIOA->MODER |= 0x08000020; 01349 GPIOB->MODER |= 0x00002000; // PB6 input to UART_TX 01350 #endif 01351 01352 if (prev_RCC_OscInitStruct.HSIState == RCC_HSI_ON) { 01353 HAL_RCC_GetOscConfig(&osc_init); 01354 if (osc_init.HSIState != RCC_HSI_ON) { 01355 printf("hsi-restore\r\n"); 01356 // Enable the HSI (to clock the ADC) 01357 osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSI; 01358 osc_init.HSIState = RCC_HSI_ON; 01359 osc_init.PLL.PLLState = RCC_PLL_NONE; 01360 HAL_RCC_OscConfig(&osc_init); 01361 } 01362 } 01363 } 01364 01365 int get_kbd_str(char* buf, int size) 01366 { 01367 char c; 01368 int i; 01369 static int prev_len; 01370 01371 for (i = 0;;) { 01372 01373 if (pc.readable()) { 01374 c = pc.getc(); 01375 if (c == 8) { // backspace 01376 if (i > 0) { 01377 pc.putc(8); 01378 pc.putc(' '); 01379 pc.putc(8); 01380 i--; 01381 } 01382 } else if (c == '\r') { 01383 if (i == 0) { 01384 return prev_len; // repeat previous 01385 } else { 01386 buf[i] = 0; // null terminate 01387 prev_len = i; 01388 return i; 01389 } 01390 } else if (c == 3) { 01391 // ctrl-C abort 01392 per_en = false; 01393 abort_key = true; 01394 return -1; 01395 } else if (i < size) { 01396 buf[i++] = c; 01397 pc.putc(c); 01398 } 01399 } else { 01400 if (service_en) { 01401 service_radio(); 01402 } 01403 gps_service(); 01404 sx9500.service(); 01405 mma8451q.service(); 01406 mpl3115a2.service(); 01407 01408 } 01409 } // ...for() 01410 } 01411 01412 void 01413 console_chat() 01414 { 01415 int i, len = get_kbd_str(pcbuf, sizeof(pcbuf)); 01416 if (len < 0) { 01417 printf("chat abort\r\n"); 01418 app = APP_NONE; 01419 return; 01420 } else { 01421 for (i = 0; i < len; i++) 01422 radio.tx_buf[i] = pcbuf[i]; 01423 if (radio.RegOpMode.bits.LongRangeMode) { 01424 lora.RegPayloadLength = len; 01425 radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); 01426 red_led = LED_ON; 01427 lora.start_tx(len); 01428 } else { 01429 fsk.start_tx(len); 01430 } 01431 printf("\r\n"); 01432 } 01433 } 01434 01435 uint8_t last_RxCurrentAddr; 01436 uint8_t last_RxNbBytes; 01437 01438 01439 01440 01441 void 01442 console() 01443 { 01444 int len, i; 01445 uint32_t ui; 01446 uint8_t a, d; 01447 static uint16_t fsk_tx_length; 01448 01449 len = get_kbd_str(pcbuf, sizeof(pcbuf)); 01450 if (len < 0) { 01451 printf("abort\r\n"); 01452 return; 01453 } 01454 01455 printf("\r\n"); 01456 if (len == 1) { 01457 switch (pcbuf[0]) { 01458 case 'i': 01459 printf("init\r\n"); 01460 radio.init(); 01461 if (!radio.RegOpMode.bits.LongRangeMode) { 01462 fsk.init(); // put FSK modem to some functioning default 01463 } else { 01464 // lora configuration is more simple 01465 } 01466 break; 01467 case 'h': 01468 printf("hw_reset()\r\n"); 01469 radio.hw_reset(); 01470 break; 01471 case 'R': 01472 // read all registers 01473 for (a = 1; a < 0x71; a++) { 01474 d = radio.read_reg(a); 01475 //update_shadow_regs(selected_radio, a, d); 01476 printf("%02x: %02x\r\n", a, d); 01477 } 01478 break; 01479 case 'T': 01480 if (radio.RegOpMode.bits.LongRangeMode) { 01481 lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); 01482 //printf("a %02x\r\n", lora.RegModemConfig2.octet); 01483 lora.RegModemConfig2.sx1276bits.TxContinuousMode ^= 1; // same for sx1272 and sx1276 01484 //printf("b %02x\r\n", lora.RegModemConfig2.octet); 01485 radio.write_reg(REG_LR_MODEMCONFIG2, lora.RegModemConfig2.octet); 01486 lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); 01487 //printf("c %02x\r\n", lora.RegModemConfig2.octet); 01488 lora_printTxContinuousMode(); 01489 printf("\r\n"); 01490 } else 01491 printf("(fsk)\r\n"); 01492 break; 01493 case 'c': 01494 if (!radio.RegOpMode.bits.LongRangeMode) { 01495 printf("%" PRIu32 "bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); 01496 printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); 01497 printf("afcbw:%" PRIu32 "Hz preambleLen:%d\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); 01498 } 01499 break; 01500 case 'C': 01501 if (radio.RegOpMode.bits.LongRangeMode) { 01502 lora.setRxPayloadCrcOn(!lora.getRxPayloadCrcOn()); 01503 lora_printRxPayloadCrcOn(); 01504 } else { 01505 printf("CrcOn:"); 01506 fsk.RegPktConfig1.bits.CrcOn ^= 1; 01507 radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); 01508 if (fsk.RegPktConfig1.bits.CrcOn) 01509 printf("On\r\n"); 01510 else 01511 printf("Off\r\n"); 01512 if (fsk.RegPktConfig2.bits.DataModePacket && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { 01513 fsk.config_dio0_for_pktmode_rx(); 01514 } 01515 } 01516 printf("\r\n"); 01517 break; 01518 case 'B': 01519 radio.RegPaConfig.bits.PaSelect ^= 1; 01520 radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); 01521 printPa(); 01522 printf("\r\n"); 01523 break; 01524 case 'L': 01525 if (radio.RegOpMode.bits.LongRangeMode) 01526 fsk.enable(false); 01527 else 01528 lora.enable(); 01529 01530 radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); 01531 if (radio.RegOpMode.bits.LongRangeMode) 01532 printf("LoRa\r\n"); 01533 else 01534 printf("FSK\r\n"); 01535 break; 01536 case 's': 01537 if (!radio.RegOpMode.bits.LongRangeMode) { 01538 fsk.RegFifoThreshold.bits.TxStartCondition ^= 1; 01539 radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); 01540 printf("TxStartCondition:"); 01541 if (fsk.RegFifoThreshold.bits.TxStartCondition) 01542 printf("!FifoEmpty\r\n"); 01543 else 01544 printf("FifoLevel\r\n"); 01545 } 01546 break; 01547 case 'f': 01548 if (!radio.RegOpMode.bits.LongRangeMode) { 01549 printf("PacketFormat:"); 01550 fsk.RegPktConfig1.bits.PacketFormatVariable ^= 1; 01551 radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); 01552 if (fsk.RegPktConfig1.bits.PacketFormatVariable) 01553 printf("variable\r\n"); 01554 else 01555 printf("fixed\r\n"); 01556 /*if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) 01557 reset_flow();*/ 01558 } 01559 break; 01560 case 'E': 01561 if (!radio.RegOpMode.bits.LongRangeMode) { 01562 RegIrqFlags2_t RegIrqFlags2; 01563 RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); 01564 while (!RegIrqFlags2.bits.FifoEmpty) { 01565 if (pc.readable()) 01566 break; 01567 printf("%02x\r\n", radio.read_reg(REG_FIFO)); 01568 RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); 01569 } 01570 } 01571 break; 01572 case 'A': 01573 if (!radio.RegOpMode.bits.LongRangeMode) { 01574 fsk.RegRxConfig.bits.AfcAutoOn ^= 1; 01575 radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); 01576 printf("AfcAuto:"); 01577 if (fsk.RegRxConfig.bits.AfcAutoOn) 01578 printf("On\r\n"); 01579 else 01580 printf("OFF\r\n"); 01581 break; 01582 } 01583 break; 01584 case '?': 01585 printf("G<portABCD><MO><pin0-f>[0123] pin control (M=MODER, O=BSRR) see RM0038 section 7.4\r\n"); 01586 printf("cs%%d deepsleep for seconds\r\n"); 01587 printf("cl%%d sleep for seconds\r\n"); 01588 printf("CS%%d repeated sleep for seconds (hold down key to stop)\r\n"); 01589 printf("r %%x read sx1272 register (addr)\r\n"); 01590 printf("w %%x %%x write sx1272 register (addr data)\r\n"); 01591 printf("ge toggle GPS enable\r\n"); 01592 printf("L toggle LongRangeMode/FSK\r\n"); 01593 printf("i radio_init\r\n"); 01594 printf("h hw_reset\r\n"); 01595 printf("tx[%%d] transmit [length]\r\n"); 01596 printf("rx receive\r\n"); 01597 printf("stb put radio into standby\r\n"); 01598 printf("sle put radio to sleep\r\n"); 01599 printf("C toggle crcOn\r\n"); 01600 printf("op[%%d] get/set output power\r\n"); 01601 printf("ocp[%%d] get/set over-current protection (mA)\r\n"); 01602 printf("d[0-5] change DIO pin assignment\r\n"); 01603 printf("frf[%%f] get/set operating frequency (MHz)\r\n"); 01604 printf("pd2 toggle PA_High_Power\r\n"); 01605 printf("bgr[%%d] get/set prog_txdac BGR bias for TXDAC (7=+20dBm)\r\n"); 01606 printf("per toggle PER enable (\"tx\" to start, ctrl-C to stop)\r\n"); 01607 printf("pin[%%f] get/set per_tx_delay (seconds)\r\n"); 01608 printf("pid[%%d] get/set PER device ID\r\n"); 01609 #ifdef FCC_TEST 01610 printf("hop change hop type (off, 64ch, 4ch)\r\n"); 01611 printf("hb[%%f] get/set hop base MHz\r\n"); 01612 printf("hs[%%f] get/set hop step MHz\r\n"); 01613 #endif /* #ifdef FCC_TEST */ 01614 if (radio.RegOpMode.bits.LongRangeMode) { 01615 printf("pl[%%d] LORA get/set RegPayloadLength\r\n"); 01616 printf("cr[1234] LORA set coding rate \r\n"); 01617 printf("bw[%%d] LORA get/set bandwidth\r\n"); 01618 printf("sf[%%d] LORA get/set spreading factor\r\n"); 01619 printf("T LORA toggle TxContinuousMode\r\n"); 01620 printf("hp[%%d] LORA get/set hop period\r\n"); 01621 printf("hm LORA toggle explicit/explicit header mode\r\n"); 01622 printf("rin LORA toggle RX invert_i_q\r\n"); 01623 printf("tin LORA toggle chirp_invert_tx\r\n"); 01624 printf("ld LORA toggle LowDataRateOptimize\r\n"); 01625 } else { 01626 printf("bw[a][%%d] FSK get-set rxbw (bwa=afcbw)\r\n"); 01627 printf("br[%%d] FSK get-set bitrate\r\n"); 01628 printf("c[%%d] FSK set test case\r\n"); 01629 printf("fdev[%%d] FSK get-set TX frequency deviation (hz)\r\n"); 01630 printf("rt FSK change RxTrigger\r\n"); 01631 printf("pd FSK enable/disable preamble detector\r\n"); 01632 printf("pt FSK get-set PreambleDetectorTol\r\n"); 01633 printf("ss[%%d] FSK get-set SyncSize\r\n"); 01634 printf("S[%%x] FSK get-set sync word\r\n"); 01635 printf("s FSK toggle TxStartCondition\r\n"); 01636 printf("f FSK toggle PacketFormat fixed-variable\r\n"); 01637 printf("E FSK empty out the fifo\r\n"); 01638 printf("ac FSK AfcClear\r\n"); 01639 printf("A FSK toggle AfcAutoOn\r\n"); 01640 printf("mp FSK toggle MapPreambleDetect\r\n"); 01641 printf("ar FSK change AutoRestartRxMode\r\n"); 01642 printf("alc FSK toggle AfcAutoClearOn\r\n"); 01643 printf("ag FSK toggle AgcAutoOn\r\n"); 01644 printf("pre[%%d} FSK get-set TX preamble length\r\n"); 01645 } 01646 printf("mp? MPL3115 help (tempurature/pressure sensor)\r\n"); 01647 printf("mm? MMA8451 help (accelerometer)\r\n"); 01648 printf("95? SX9500 help (touch sensor)\r\n"); 01649 break; 01650 case '.': 01651 if (radio.RegOpMode.bits.LongRangeMode) 01652 lora_print_status(); 01653 else 01654 fsk_print_status(); 01655 common_print_status(); 01656 break; 01657 } // ...switch (pcbuf[0]) 01658 } else { 01659 if (pcbuf[0] == 't' && pcbuf[1] == 'x') { // TX 01660 if (per_en) { 01661 printf("timeout attach %f\r\n", per_tx_delay); 01662 PacketTxCnt = 0; 01663 per_timeout.attach(&per_cb, per_tx_delay); 01664 } else { 01665 if (radio.RegOpMode.bits.LongRangeMode) { 01666 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01667 sscanf(pcbuf+2, "%d", &i); 01668 lora.RegPayloadLength = i; 01669 radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); 01670 } 01671 tx_cnt++; 01672 for (i = 0; i < lora.RegPayloadLength; i++) 01673 radio.tx_buf[i] = tx_cnt; 01674 red_led = LED_ON; 01675 lora.start_tx(lora.RegPayloadLength); 01676 if (pcbuf[2] == 'r') 01677 rx_after_tx = true; 01678 else 01679 rx_after_tx = false; 01680 } else { // FSK: 01681 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01682 sscanf(pcbuf+2, "%d", &i); 01683 fsk_tx_length = i; 01684 } 01685 if (radio.RegOpMode.bits.Mode != RF_OPMODE_TRANSMITTER) { // if not already busy transmitting 01686 tx_cnt++; 01687 for (i = 0; i < fsk_tx_length; i++) { 01688 radio.tx_buf[i] = tx_cnt; 01689 } 01690 fsk.start_tx(fsk_tx_length); 01691 } 01692 } // ...fsk 01693 } // ..!per_en 01694 #ifdef FCC_TEST 01695 if (hop_type != HOP_TYPE_NONE) 01696 hop_timeout.attach(&hop_cb, 0.4); 01697 #endif /* #ifdef FCC_TEST */ 01698 } else if (pcbuf[0] == 'r' && pcbuf[1] == 'n' && pcbuf[2] == 'd') { 01699 uint8_t of = rand() & 0x3f; 01700 01701 printf("%02d %.2f\r\n", of, 902.3 + (of * 0.2)); 01702 } 01703 #ifdef FCC_TEST 01704 else if (pcbuf[0] == 'h' && pcbuf[1] == 'b') { 01705 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01706 sscanf(pcbuf+2, "%f", &hop_base_MHz); 01707 } 01708 printf("hop_base:%f\r\n", hop_base_MHz); 01709 } else if (pcbuf[0] == 'h' && pcbuf[1] == 's') { 01710 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01711 sscanf(pcbuf+2, "%f", &hop_step_MHz); 01712 } 01713 printf("hop_step:%f\r\n", hop_step_MHz); 01714 } else if (pcbuf[0] == 'h' && pcbuf[1] == 'o' && pcbuf[2] == 'p') { 01715 switch (hop_type) { 01716 case HOP_TYPE_NONE: 01717 hop_type = HOP_TYPE_64CH; 01718 printf("64ch hop\r\n"); 01719 break; 01720 case HOP_TYPE_64CH: 01721 hop_type = HOP_TYPE_4CH; 01722 printf("4ch hop\r\n"); 01723 break; 01724 case HOP_TYPE_4CH: 01725 hop_type = HOP_TYPE_NONE; 01726 printf("hop off\r\n"); 01727 break; 01728 } 01729 } 01730 #endif /* #ifdef FCC_TEST */ 01731 else if (pcbuf[0] == 'h' && pcbuf[1] == 'p' && radio.RegOpMode.bits.LongRangeMode) { 01732 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01733 sscanf(pcbuf+2, "%d", &i); 01734 lora.RegHopPeriod = i; 01735 radio.write_reg(REG_LR_HOPPERIOD, lora.RegHopPeriod); 01736 if (radio.RegDioMapping1.bits.Dio1Mapping != 1) { 01737 radio.RegDioMapping1.bits.Dio1Mapping = 1; 01738 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 01739 } 01740 } 01741 lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); 01742 printf("HopPeriod:0x%02x\r\n", lora.RegHopPeriod); 01743 } else if (pcbuf[0] == 'r' && pcbuf[1] == 't' && !radio.RegOpMode.bits.LongRangeMode) { 01744 printf("RxTrigger:"); 01745 switch (fsk.RegRxConfig.bits.RxTrigger) { 01746 case 0: fsk.RegRxConfig.bits.RxTrigger = 1; 01747 printf("rssi\r\n"); 01748 break; 01749 case 1: fsk.RegRxConfig.bits.RxTrigger = 6; 01750 printf("preamble\r\n"); 01751 break; 01752 case 6: fsk.RegRxConfig.bits.RxTrigger = 7; 01753 printf("both\r\n"); 01754 break; 01755 case 7: fsk.RegRxConfig.bits.RxTrigger = 0; 01756 printf("none\r\n"); 01757 break; 01758 default: fsk.RegRxConfig.bits.RxTrigger = 0; 01759 printf("none\r\n"); 01760 break; 01761 } 01762 radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); 01763 } else if (pcbuf[0] == 'r' && pcbuf[1] == 'x') { // RX 01764 if (per_en) { 01765 red_led = LED_OFF; 01766 //green_led = LED_OFF; 01767 PacketNormalCnt = 0; 01768 PacketRxSequencePrev = -1; 01769 PacketPerKoCnt = 0; 01770 PacketPerOkCnt = 0; 01771 dio3.rise(&dio3_cb); 01772 } 01773 if (radio.RegOpMode.bits.LongRangeMode) { 01774 last_RxCurrentAddr = radio.read_reg(REG_LR_FIFORXCURRENTADDR); 01775 lora.start_rx(RF_OPMODE_RECEIVER); 01776 } else { 01777 fsk.start_rx(); 01778 radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to syncadrs 01779 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 01780 01781 fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); 01782 fsk.RegRssiConfig.bits.RssiOffset = FSK_RSSI_OFFSET; 01783 fsk.RegRssiConfig.bits.RssiSmoothing = FSK_RSSI_SMOOTHING; 01784 radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); 01785 } 01786 } else if (pcbuf[0] == 'r' && pcbuf[1] == ' ') { // read single register 01787 sscanf(pcbuf+2, "%x", &i); 01788 printf("%02x: %02x\r\n", i, radio.read_reg(i)); 01789 } else if (pcbuf[0] == 'w' && pcbuf[1] == ' ') { // write single register 01790 sscanf(pcbuf+2, "%x %x", &i, &len); 01791 radio.write_reg(i, len); 01792 printf("%02x: %02x\r\n", i, radio.read_reg(i)); 01793 } 01794 #ifdef I2C_PIN_TEST 01795 else if (pcbuf[0] == 'b' && pcbuf[1] == '8') { 01796 printf("SCL:"); 01797 switch (pcbuf[2]) { 01798 case '0': 01799 pb8.output(); 01800 pb8 = 0; 01801 printf("lo"); 01802 break; 01803 case '1': 01804 pb8.output(); 01805 pb8 = 1; 01806 printf("hi"); 01807 break; 01808 case 'z': 01809 pb8.input(); 01810 printf("z"); 01811 break; 01812 } 01813 printf("\r\n"); 01814 } else if (pcbuf[0] == 'b' && pcbuf[1] == '9') { 01815 printf("SDA:"); 01816 switch (pcbuf[2]) { 01817 case '0': 01818 pb9.output(); 01819 pb9 = 0; 01820 printf("lo"); 01821 break; 01822 case '1': 01823 pb9.output(); 01824 pb9 = 1; 01825 printf("hi"); 01826 break; 01827 case 'z': 01828 pb9.input(); 01829 printf("z"); 01830 break; 01831 } 01832 printf("\r\n"); 01833 } 01834 #else 01835 /************************** MMA8451Q... **************************************/ 01836 else if (pcbuf[0] == 'm' && pcbuf[1] == 'm') { 01837 if (pcbuf[2] == '?') { 01838 printf("mm. get status\r\n"); 01839 printf("mm, print XYZ\r\n"); 01840 printf("mma toggle stby/active\r\n"); 01841 printf("mmtd configure for transient detection\r\n"); 01842 printf("mmod configure for orientation detection\r\n"); 01843 } else if (pcbuf[2] == '.') { 01844 printf("active:%d\r\n", mma8451q.get_active()); 01845 mma8451q.print_regs(); 01846 printf("i2c_int_pin:%d\r\n", i2c_int_pin.read()); 01847 } else if (pcbuf[2] == ',') { 01848 mma8451q.read(MMA8451_OUT_X_MSB, mma8451q.out.octets, 6); 01849 mma8451q.out.v.x >>= 4; // 12bit data 01850 mma8451q.out.v.y >>= 4; // 12bit data 01851 mma8451q.out.v.z >>= 4; // 12bit data 01852 printf("x:%d y:%d z:%d\r\n", mma8451q.out.v.x, mma8451q.out.v.y, mma8451q.out.v.z); 01853 } else if (pcbuf[2] == 'o' && pcbuf[3] == 'd') { 01854 printf("orientation "); 01855 d = mma8451q.read_single(MMA8451_PL_CFG); 01856 if (d & 0x40) { // PL_EN? 01857 d &= ~0x40; 01858 mma8451q.write(MMA8451_PL_CFG, d); 01859 printf("off\r\n"); 01860 } else { 01861 mpl3115a2.write(CTRL_REG4, 0); // turn off: shares same interrupt pin 01862 mma8451q.orient_detect(); 01863 printf("on\r\n"); 01864 } 01865 } else if (pcbuf[2] == 't' && pcbuf[3] == 'd') { 01866 printf("transient "); 01867 if (mma8451q.transient_cfg.bits.ELE) { 01868 mma8451q.transient_cfg.octet = 0; 01869 mma8451q.write(MMA8451_TRANSIENT_CFG, mma8451q.transient_cfg.octet); 01870 mma8451q.ctrl_reg4.bits.INT_EN_TRANS = 0; 01871 mma8451q.write(MMA8451_CTRL_REG4, mma8451q.ctrl_reg4.octet); 01872 printf("off\r\n"); 01873 } else { 01874 mpl3115a2.write(CTRL_REG4, 0); // turn off: shares same interrupt pin 01875 mma8451q.transient_detect(); 01876 //poll_timeout.attach(on_poll, 0.3); 01877 printf("on\r\n"); 01878 } 01879 } else if (pcbuf[2] == 'a') { 01880 if (mma8451q.get_active()) { 01881 mma8451q.set_active(0); 01882 } else { 01883 mma8451q.set_active(1); 01884 } 01885 printf("active:%d\r\n", mma8451q.get_active()); 01886 } 01887 } 01888 /************************** MPL3115... **************************************/ 01889 else if (pcbuf[0] == 'm' && pcbuf[1] == 'p') { 01890 if (pcbuf[2] == '?') { 01891 printf("mp. get status\r\n"); 01892 printf("mpt get temperature\r\n"); 01893 printf("mpa get altitude\r\n"); 01894 printf("mpb get barometer\r\n"); 01895 printf("mpo[%%d] get/set oversampling (0-7)\r\n"); 01896 } else if (pcbuf[2] == '.') { 01897 printf("active:%d\r\n", mpl3115a2.GetModeActive()); 01898 printf("int src:%02x\r\n", mpl3115a2.read(INT_SOURCE_REG)); 01899 printf("CTRL1:%02x\r\n", mpl3115a2.read(CTRL_REG1)); 01900 /* only INT1 is connected */ 01901 printf("CTRL3:%02x\r\n", mpl3115a2.read(CTRL_REG3)); /* TODO: PP_OD1 for open-drain operation */ 01902 printf("CTRL4:%02x\r\n", mpl3115a2.read(CTRL_REG4)); 01903 printf("CTRL5:%02x\r\n", mpl3115a2.read(CTRL_REG5)); 01904 printf("OFF_H:%02x\r\n", mpl3115a2.read(OFF_H_REG)); 01905 01906 printf("i2c_int_pin:%d\r\n", i2c_int_pin.read()); 01907 } else if (pcbuf[2] == 't') { 01908 printf("temp:%.4f\r\n", mpl3115a2.ReadTemperature()); 01909 } else if (pcbuf[2] == 'a') { 01910 printf("alt:%.4f\r\n", mpl3115a2.ReadAltitude()); 01911 } else if (pcbuf[2] == 'b') { 01912 printf("bar:%.2f\r\n", mpl3115a2.ReadBarometer()); 01913 } else if (pcbuf[2] == 'o') { 01914 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 01915 sscanf(pcbuf+3, "%d", &i); 01916 mpl3115a2.setOSR(i); 01917 } 01918 printf("OSR:%d\r\n", mpl3115a2.getOSR()); 01919 } 01920 } 01921 /************************** sx9500... **************************************/ 01922 else if (pcbuf[0] == '9' && pcbuf[1] == '5') { 01923 if (pcbuf[2] == '?') { 01924 printf("95R reset\r\n"); 01925 printf("95. read status\r\n"); 01926 printf("95t[%%d] get/set PROXTHRESH\r\n"); 01927 printf("95s[%%d] get/set SCANPERIOD\r\n"); 01928 printf("95a toggle txen\r\n"); 01929 } else if (pcbuf[2] == '.') { 01930 printf("(txen) active:%d\r\n", sx9500.get_active()); 01931 printf("RegStat:%02x\r\n", sx9500.read_single(SX9500_REG_STAT)); 01932 printf("RegProxCtrl0:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL0)); 01933 printf("RegProxCtrl1:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL1)); 01934 printf("RegProxCtrl2:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL2)); 01935 printf("RegProxCtrl3:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL3)); 01936 printf("RegProxCtrl4:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL4)); 01937 printf("RegProxCtrl5:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL5)); 01938 printf("RegProxCtrl6:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL6)); 01939 } else if (pcbuf[2] == 'a') { 01940 if (sx9500.get_active()) { 01941 sx9500.set_active(false); 01942 } else { 01943 sx9500.RegProxCtrl0.octet = sx9500.read_single(SX9500_REG_PROXCTRL0); 01944 sx9500.RegProxCtrl0.bits.sensor_en = 3; // CS0 and CS1 on 01945 sx9500.write(SX9500_REG_PROXCTRL0, sx9500.RegProxCtrl0.octet); 01946 sx9500.write(SX9500_REG_PROXCTRL6, 1); // threshold to 20 for CS1 release 01947 sx9500.write(SX9500_REG_IRQMSK, 0x60); // enable near and far interrupts 01948 sx9500.set_active(true); 01949 printf("RegProxCtrl0:%02x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL0)); /* sensor-enable and scan period */ 01950 } 01951 printf("(txen) active:%d\r\n", sx9500.get_active()); 01952 } else if (pcbuf[2] == 'R') { 01953 sx9500.reset(); 01954 } else if (pcbuf[2] == 'i') { 01955 if (pcbuf[3] != 0) { 01956 sscanf(pcbuf+3, "%x", &i); 01957 sx9500.write(SX9500_REG_IRQMSK, i); 01958 } 01959 printf("irqmsk:%02x\r\n", sx9500.read_single(SX9500_REG_IRQMSK)); 01960 } else if (pcbuf[2] == 't') { 01961 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 01962 sscanf(pcbuf+3, "%d", &i); 01963 sx9500.write(SX9500_REG_PROXCTRL6, i); 01964 } 01965 printf("proxthresh:0x%x\r\n", sx9500.read_single(SX9500_REG_PROXCTRL6)); 01966 } else if (pcbuf[2] == 'p') { 01967 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 01968 sscanf(pcbuf+2, "%d", &i); 01969 sx9500.RegProxCtrl0.bits.scan_period = i; 01970 sx9500.write(SX9500_REG_PROXCTRL0, sx9500.RegProxCtrl0.octet); 01971 } 01972 sx9500.RegProxCtrl0.octet = sx9500.read_single(SX9500_REG_PROXCTRL0); 01973 printf("scan period:%d\r\n", sx9500.RegProxCtrl0.bits.scan_period); 01974 } 01975 } 01976 #endif /* !I2C_PIN_TEST */ 01977 else if (pcbuf[0] == 'm' && pcbuf[1] == 'p' && !radio.RegOpMode.bits.LongRangeMode) { 01978 radio.RegDioMapping2.bits.MapPreambleDetect ^= 1; 01979 radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); 01980 printf("MapPreambleDetect:"); 01981 if (radio.RegDioMapping2.bits.MapPreambleDetect) 01982 printf("preamble\r\n"); 01983 else 01984 printf("rssi\r\n"); 01985 } else if (pcbuf[0] == 'o' && pcbuf[1] == 'p') { 01986 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 01987 sscanf(pcbuf+2, "%d", &i); 01988 radio.RegPaConfig.bits.OutputPower = i; 01989 radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); 01990 } 01991 radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); 01992 printf("OutputPower:%d\r\n", radio.RegPaConfig.bits.OutputPower); 01993 } else if (pcbuf[0] == 'c' && (pcbuf[1] >= '0' && pcbuf[1] <= '9') && !radio.RegOpMode.bits.LongRangeMode) { 01994 radio.set_opmode(RF_OPMODE_STANDBY); 01995 per_tx_delay = 0.3; 01996 01997 fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); 01998 fsk.RegFifoThreshold.bits.TxStartCondition = 1; // to nFifoEmpty 01999 radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); 02000 02001 if (radio.read_reg(REG_FSK_SYNCVALUE1) == 0x55 && radio.read_reg(REG_FSK_SYNCVALUE2)) { 02002 fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); 02003 fsk.RegSyncConfig.bits.SyncSize = 2; 02004 radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); 02005 radio.write_reg(REG_FSK_SYNCVALUE3, 0x90); 02006 radio.write_reg(REG_FSK_SYNCVALUE2, 0x4e); 02007 radio.write_reg(REG_FSK_SYNCVALUE1, 0x63); 02008 } 02009 02010 fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); 02011 fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; 02012 radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); 02013 02014 fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); 02015 fsk.RegRxConfig.bits.AfcAutoOn = 1; 02016 fsk.RegRxConfig.bits.AgcAutoOn = 1; 02017 fsk.RegRxConfig.bits.RxTrigger = 7; 02018 radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); 02019 02020 fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; 02021 fsk.RegPreambleDetect.bits.PreambleDetectorSize = 1; 02022 fsk.RegPreambleDetect.bits.PreambleDetectorTol = 10; 02023 radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); 02024 02025 switch (pcbuf[1]) { 02026 case '0': 02027 fsk.set_bitrate(4800); 02028 fsk.set_tx_fdev_hz(5005); 02029 fsk.set_rx_dcc_bw_hz(10417, 0); // rxbw 02030 fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw 02031 radio.write_u16(REG_FSK_PREAMBLEMSB, 8); 02032 break; 02033 case '1': 02034 fsk.set_bitrate(50000); 02035 fsk.set_tx_fdev_hz(25000); 02036 fsk.set_rx_dcc_bw_hz(62500, 0); // rxbw 02037 fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw 02038 radio.write_u16(REG_FSK_PREAMBLEMSB, 9); 02039 break; 02040 case '2': 02041 fsk.set_bitrate(38400); 02042 fsk.set_tx_fdev_hz(20020); 02043 fsk.set_rx_dcc_bw_hz(50000, 0); // rxbw 02044 fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw 02045 radio.write_u16(REG_FSK_PREAMBLEMSB, 8); 02046 break; 02047 case '3': 02048 fsk.set_bitrate(1201); 02049 fsk.set_tx_fdev_hz(20020); 02050 fsk.set_rx_dcc_bw_hz(25000, 0); // rxbw 02051 fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw 02052 radio.write_u16(REG_FSK_PREAMBLEMSB, 8); 02053 break; 02054 case '4': 02055 fsk.set_bitrate(1201); 02056 fsk.set_tx_fdev_hz(4028); 02057 fsk.set_rx_dcc_bw_hz(7813, 0); // rxbw 02058 fsk.set_rx_dcc_bw_hz(25000, 1); // afcbw 02059 radio.write_u16(REG_FSK_PREAMBLEMSB, 8); 02060 break; 02061 case '5': 02062 fsk.set_bitrate(1201); 02063 fsk.set_tx_fdev_hz(4028); 02064 fsk.set_rx_dcc_bw_hz(5208, 0); // rxbw 02065 fsk.set_rx_dcc_bw_hz(10417, 1); // afcbw 02066 radio.write_u16(REG_FSK_PREAMBLEMSB, 8); 02067 break; 02068 } // ...switch (pcbuf[1]) 02069 printf("%" PRIu32" bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); 02070 printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); 02071 printf("afcbw:%" PRIu32 "Hz preambleLen:%d\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); 02072 } else if (pcbuf[0] == 'o' && pcbuf[1] == 'c' && pcbuf[2] == 'p') { 02073 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02074 sscanf(pcbuf+3, "%d", &i); 02075 if (i < 130) 02076 radio.RegOcp.bits.OcpTrim = (i - 45) / 5; 02077 else 02078 radio.RegOcp.bits.OcpTrim = (i + 30) / 10; 02079 radio.write_reg(REG_OCP, radio.RegOcp.octet); 02080 } 02081 radio.RegOcp.octet = radio.read_reg(REG_OCP); 02082 if (radio.RegOcp.bits.OcpTrim < 16) 02083 i = 45 + (5 * radio.RegOcp.bits.OcpTrim); 02084 else if (radio.RegOcp.bits.OcpTrim < 28) 02085 i = (10 * radio.RegOcp.bits.OcpTrim) - 30; 02086 else 02087 i = 240; 02088 printf("Ocp: %dmA\r\n", i); 02089 } else if (pcbuf[0] == 'c' && pcbuf[1] == 'r' && radio.RegOpMode.bits.LongRangeMode) { 02090 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') 02091 lora.setCodingRate(pcbuf[2] - '0'); 02092 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 02093 lora_printCodingRate(false); // false: transmitted 02094 printf("\r\n"); 02095 } else if (pcbuf[0] == 'h' && pcbuf[1] == 'm' && radio.RegOpMode.bits.LongRangeMode) { // toggle implicit/explicit 02096 lora.setHeaderMode(!lora.getHeaderMode()); 02097 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 02098 lora_printHeaderMode(); 02099 printf("\r\n"); 02100 } else if (pcbuf[0] == 'a' && pcbuf[1] == 'g' && !radio.RegOpMode.bits.LongRangeMode) { 02101 fsk.RegRxConfig.bits.AgcAutoOn ^= 1; 02102 radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); 02103 printf("AgcAutoOn:%d\r\n", fsk.RegRxConfig.bits.AgcAutoOn); 02104 } else if (pcbuf[0] == 'a' && pcbuf[1] == 'l' && !radio.RegOpMode.bits.LongRangeMode) { 02105 fsk.RegAfcFei.bits.AfcAutoClearOn ^= 1; 02106 printf("AfcAutoClearOn: "); 02107 radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); 02108 if (fsk.RegAfcFei.bits.AfcAutoClearOn) 02109 printf("ON\r\n"); 02110 else 02111 printf("off\r\n"); 02112 } else if (pcbuf[0] == 'a' && pcbuf[1] == 'r' && !radio.RegOpMode.bits.LongRangeMode) { 02113 fsk.RegSyncConfig.bits.AutoRestartRxMode++; 02114 radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); 02115 fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); 02116 printf("AutoRestartRxMode:"); 02117 switch (fsk.RegSyncConfig.bits.AutoRestartRxMode) { 02118 case 0: printf("off "); break; 02119 case 1: printf("no-pll-wait "); break; 02120 case 2: printf("pll-wait "); break; 02121 case 3: printf("3 "); break; 02122 } 02123 printf("\r\n"); 02124 } else if (pcbuf[0] == 'a' && pcbuf[1] == 'c' && !radio.RegOpMode.bits.LongRangeMode) { 02125 printf("clear afc: "); 02126 fsk.RegAfcFei.bits.AfcClear = 1; 02127 radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); 02128 fsk.RegAfcFei.bits.AfcClear = 0; 02129 printf("%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); 02130 } else if (pcbuf[0] == 'b' && pcbuf[1] == 'g' && pcbuf[2] == 'r') { 02131 RegPdsTrim1_t pds_trim; 02132 pds_trim.octet = radio.read_reg(REG_PDSTRIM1_SX1272); 02133 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02134 sscanf(&pcbuf[3], "%d", &i); 02135 pds_trim.bits.prog_txdac = i; 02136 } 02137 radio.write_reg(REG_PDSTRIM1_SX1272, pds_trim.octet); 02138 printf("prog_txdac:%.1fuA\r\n", 2.5 + (pds_trim.bits.prog_txdac * 0.625)); 02139 /* increase OCP threshold to allow more power */ 02140 radio.RegOcp.octet = radio.read_reg(REG_OCP); 02141 if (radio.RegOcp.bits.OcpTrim < 16) { 02142 radio.RegOcp.bits.OcpTrim = 16; 02143 radio.write_reg(REG_OCP, radio.RegOcp.octet); 02144 } 02145 } else if (pcbuf[0] == 'b' && pcbuf[1] == 'r' && !radio.RegOpMode.bits.LongRangeMode) { 02146 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02147 sscanf(&pcbuf[2], "%d", &i); 02148 fsk.set_bitrate(i); 02149 } 02150 printf("%" PRIu32 "bps\r\n", fsk.get_bitrate()); 02151 } else if (pcbuf[0] == 'b' && pcbuf[1] == 'w') { 02152 if (radio.RegOpMode.bits.LongRangeMode) { 02153 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02154 radio.set_opmode(RF_OPMODE_STANDBY); 02155 sscanf(&pcbuf[2], "%d", &i); 02156 lora.setBw(i); 02157 } else 02158 lora_printAllBw(); 02159 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 02160 printf("current "); 02161 lora_printBw(); 02162 printf("\r\n"); 02163 } else { // FSK: 02164 if (pcbuf[2] == 'a') { 02165 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02166 radio.set_opmode(RF_OPMODE_STANDBY); 02167 sscanf(&pcbuf[3], "%d", &i); 02168 fsk.set_rx_dcc_bw_hz(i, 1); 02169 } 02170 printf("afcbw:%" PRIu32 "Hz\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW)); 02171 } else { 02172 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02173 radio.set_opmode(RF_OPMODE_STANDBY); 02174 sscanf(&pcbuf[2], "%d", &i); 02175 fsk.set_rx_dcc_bw_hz(i, 0); 02176 } 02177 printf("rxbw:%" PRIu32 "Hz\r\n", fsk.get_rx_bw_hz(REG_FSK_RXBW)); 02178 } 02179 } 02180 } else if (pcbuf[0] == 'v' && pcbuf[1] == 'h') { 02181 lora.poll_vh ^= 1; 02182 printf("poll_vh:%d\r\n", lora.poll_vh); 02183 } else if (pcbuf[0] == 'S' && !radio.RegOpMode.bits.LongRangeMode) { 02184 if (pcbuf[1] == '0') { 02185 sscanf(pcbuf+1, "%" SCNu32, &ui); 02186 if (ui < 0x100) { 02187 fsk.RegSyncConfig.bits.SyncSize = 0; 02188 radio.write_reg(REG_FSK_SYNCVALUE1, ui); 02189 } else if (ui < 0x10000) { 02190 fsk.RegSyncConfig.bits.SyncSize = 1; 02191 radio.write_reg(REG_FSK_SYNCVALUE2, ui & 0xff); 02192 radio.write_reg(REG_FSK_SYNCVALUE1, ui >> 8); 02193 } else if (ui < 0x1000000) { 02194 fsk.RegSyncConfig.bits.SyncSize = 2; 02195 radio.write_reg(REG_FSK_SYNCVALUE3, ui & 0xff); 02196 radio.write_reg(REG_FSK_SYNCVALUE2, (ui >> 8) & 0xff); 02197 radio.write_reg(REG_FSK_SYNCVALUE1, ui >> 16); 02198 } else { 02199 fsk.RegSyncConfig.bits.SyncSize = 3; 02200 radio.write_reg(REG_FSK_SYNCVALUE4, ui & 0xff); 02201 radio.write_reg(REG_FSK_SYNCVALUE3, (ui >> 8) & 0xff); 02202 radio.write_reg(REG_FSK_SYNCVALUE2, (ui >> 16) & 0xff); 02203 radio.write_reg(REG_FSK_SYNCVALUE1, ui >> 24); 02204 } 02205 radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); 02206 } 02207 fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); 02208 printf("%d: ", fsk.RegSyncConfig.bits.SyncSize); 02209 for (i = 0; i <= fsk.RegSyncConfig.bits.SyncSize; i++) 02210 printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE1+i)); 02211 printf("\r\n"); 02212 } else if (pcbuf[0] == 's' && pcbuf[1] == 'e' && pcbuf[2] == 'r') { 02213 service_en ^= 1; 02214 printf("service_en:%d\r\n", service_en); 02215 } else if (pcbuf[0] == 's' && pcbuf[1] == 's') { 02216 if (radio.RegOpMode.bits.LongRangeMode) { // sweep test on lora sync 02217 if (pcbuf[2] == 'h') { // sweep high nibble 02218 lora_sync_sweep_hi = 1; 02219 } else if (pcbuf[2] == 'l') { // sweep low nibble 02220 lora_sync_sweep_hi = 0; 02221 } 02222 lora_sync_byte = radio.read_reg(REG_LR_SYNC_BYTE); 02223 hop_timeout.attach(&lora_sync_sweep, 0.1); 02224 } else { 02225 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02226 sscanf(pcbuf+2, "%d", &i); 02227 fsk.RegSyncConfig.bits.SyncSize = i; 02228 radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); 02229 } 02230 fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); 02231 printf("SyncSize:%d\r\n", fsk.RegSyncConfig.bits.SyncSize); 02232 } 02233 } else if (pcbuf[0] == 's' && pcbuf[1] == 'f' && radio.RegOpMode.bits.LongRangeMode) { 02234 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02235 sscanf(pcbuf+2, "%d", &i); 02236 lora.setSf(i); 02237 if (i == 6 && !lora.getHeaderMode()) { 02238 printf("SF6: to implicit header mode\r\n"); 02239 lora.setHeaderMode(true); 02240 } 02241 } 02242 lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); 02243 lora_printSf(); 02244 printf("\r\n"); 02245 } else if (pcbuf[0] == 'f' && pcbuf[1] == 'i' && !radio.RegOpMode.bits.LongRangeMode) { 02246 fsk.init(); 02247 printf("fsk.init\r\n"); 02248 } else if (pcbuf[0] == 'f' && pcbuf[1] == 'd' && pcbuf[2] == 'e' && !radio.RegOpMode.bits.LongRangeMode) { 02249 if (pcbuf[4] >= '0' && pcbuf[4] <= '9') { 02250 sscanf(pcbuf+4, "%d", &i); 02251 fsk.set_tx_fdev_hz(i); 02252 } 02253 printf("fdev:%" PRIu32 "Hz\r\n", fsk.get_tx_fdev_hz()); 02254 } else if (pcbuf[0] == 'f' && pcbuf[1] == 'r' && pcbuf[2] == 'f') { 02255 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02256 float MHz; 02257 sscanf(pcbuf+3, "%f", &MHz); 02258 //printf("MHz:%f\r\n", MHz); 02259 radio.set_frf_MHz(MHz); 02260 } 02261 printf("%fMHz\r\n", radio.get_frf_MHz()); 02262 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'i' && pcbuf[2] == 'd') { 02263 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02264 sscanf(pcbuf+3, "%d", &per_id); 02265 } 02266 printf("PER device ID:%d\r\n", per_id); 02267 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'i' && pcbuf[2] == 'n') { 02268 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02269 sscanf(pcbuf+3, "%f", &per_tx_delay); 02270 } 02271 printf("per_tx_delay:%f\r\n", per_tx_delay); 02272 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'e' && pcbuf[2] == 'r') { 02273 per_en ^= 1; 02274 printf("per_en:%d\r\n", per_en); 02275 if (per_en && radio.RegOpMode.bits.LongRangeMode) { 02276 if (radio.type == SX1272) { 02277 lora.RegModemConfig.sx1272bits.LowDataRateOptimize = 1; 02278 radio.write_reg(REG_LR_MODEMCONFIG, lora.RegModemConfig.octet); 02279 } else if (radio.type == SX1276) { 02280 lora.RegModemConfig3.sx1276bits.LowDataRateOptimize = 1; 02281 radio.write_reg(REG_LR_MODEMCONFIG3, lora.RegModemConfig3.octet); 02282 } 02283 lora.RegPayloadLength = 9; 02284 radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); 02285 radio.RegDioMapping1.bits.Dio3Mapping = 1; // to ValidHeader 02286 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 02287 } 02288 PacketRxSequencePrev = -1; 02289 //PacketRxSequence = 0; 02290 PacketPerKoCnt = 0; 02291 PacketPerOkCnt = 0; 02292 PacketNormalCnt = 0; 02293 if (!per_en) { 02294 per_timeout.detach(); 02295 } 02296 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'r' && pcbuf[2] == 'e') { 02297 if (radio.RegOpMode.bits.LongRangeMode) { 02298 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02299 sscanf(pcbuf+3, "%d", &i); 02300 radio.write_u16(REG_LR_PREAMBLEMSB, i); 02301 } 02302 lora.RegPreamble = radio.read_u16(REG_LR_PREAMBLEMSB); 02303 printf("lora PreambleLength:%d\r\n", lora.RegPreamble); 02304 } else { 02305 if (pcbuf[3] >= '0' && pcbuf[3] <= '9') { 02306 sscanf(pcbuf+3, "%d", &i); 02307 radio.write_u16(REG_FSK_PREAMBLEMSB, i); 02308 } 02309 printf("FSK TX PreambleSize:%d\r\n", radio.read_u16(REG_FSK_PREAMBLEMSB)); 02310 } 02311 } else if (pcbuf[0] == 'p' && pcbuf[1] == 't' && !radio.RegOpMode.bits.LongRangeMode) { 02312 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02313 sscanf(pcbuf+2, "%d", &i); 02314 fsk.RegPreambleDetect.bits.PreambleDetectorTol = i; 02315 radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); 02316 } 02317 fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); 02318 printf("PreambleDetectorTol:%d\r\n", fsk.RegPreambleDetect.bits.PreambleDetectorTol); 02319 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'd' && pcbuf[2] == '2') { 02320 if (pd2.read()) 02321 pd2 = 0; 02322 else 02323 pd2 = 1; 02324 printf("pd2:%d\r\n", pd2.read()); 02325 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'd' && !radio.RegOpMode.bits.LongRangeMode) { 02326 fsk.RegPreambleDetect.bits.PreambleDetectorOn ^= 1; 02327 radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); 02328 printf("PreambleDetector:"); 02329 if (fsk.RegPreambleDetect.bits.PreambleDetectorOn) 02330 printf("On\r\n"); 02331 else 02332 printf("OFF\r\n"); 02333 } else if (pcbuf[0] == 'p' && pcbuf[1] == 'l' && radio.RegOpMode.bits.LongRangeMode) { 02334 if (pcbuf[2] >= '0' && pcbuf[2] <= '9') { 02335 sscanf(pcbuf+2, "%d", &i); 02336 lora.RegPayloadLength = i; 02337 radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); 02338 } 02339 lora.RegPayloadLength = radio.read_reg(REG_LR_PAYLOADLENGTH); 02340 printf("PayloadLength:%d\r\n", lora.RegPayloadLength); 02341 } else if (pcbuf[0] == 'l' && pcbuf[1] == 'd' && radio.RegOpMode.bits.LongRangeMode) { 02342 if (radio.type == SX1272) { 02343 lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); 02344 lora.RegModemConfig.sx1272bits.LowDataRateOptimize ^= 1; 02345 printf("LowDataRateOptimize:%d\r\n", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); 02346 radio.write_reg(REG_LR_MODEMCONFIG, lora.RegModemConfig.octet); 02347 } else if (radio.type == SX1276) { 02348 lora.RegModemConfig3.octet = radio.read_reg(REG_LR_MODEMCONFIG3); 02349 lora.RegModemConfig3.sx1276bits.LowDataRateOptimize ^= 1; 02350 printf("LowDataRateOptimize:%d\r\n", lora.RegModemConfig3.sx1276bits.LowDataRateOptimize); 02351 radio.write_reg(REG_LR_MODEMCONFIG3, lora.RegModemConfig3.octet); 02352 } 02353 } else if (pcbuf[0] == 't' && pcbuf[1] == 'i' && pcbuf[2] == 'n' && radio.RegOpMode.bits.LongRangeMode) { 02354 lora.invert_tx(lora.RegTest33.bits.chirp_invert_tx); 02355 printf("chirp_invert_tx :%d\r\n", lora.RegTest33.bits.chirp_invert_tx); 02356 } else if (pcbuf[0] == 'r' && pcbuf[1] == 'i' && pcbuf[2] == 'n' && radio.RegOpMode.bits.LongRangeMode) { 02357 lora.invert_rx(!lora.RegTest33.bits.invert_i_q); 02358 printf("rx invert_i_q:%d\r\n", lora.RegTest33.bits.invert_i_q); 02359 } else if (pcbuf[0] == 'd' && pcbuf[1] == 'i' && pcbuf[2] == 'o') { 02360 if (radio.RegOpMode.bits.LongRangeMode) 02361 lora_print_dio(); 02362 else 02363 fsk_print_dio(); 02364 printf("dio0:%d, dio1:%d\r\n", radio.dio0.read(), radio.dio0.read()); 02365 lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); 02366 printLoraIrqs_(false); 02367 } else if (pcbuf[0] == 'd' && pcbuf[1] >= '0' && pcbuf[1] <= '5') { 02368 switch (pcbuf[1]) { 02369 case '0': 02370 radio.RegDioMapping1.bits.Dio0Mapping++; 02371 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 02372 break; 02373 case '1': 02374 radio.RegDioMapping1.bits.Dio1Mapping++; 02375 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 02376 break; 02377 case '2': 02378 radio.RegDioMapping1.bits.Dio2Mapping++; 02379 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 02380 break; 02381 case '3': 02382 radio.RegDioMapping1.bits.Dio3Mapping++; 02383 radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); 02384 break; 02385 case '4': 02386 radio.RegDioMapping2.bits.Dio4Mapping++; 02387 radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); 02388 break; 02389 case '5': 02390 radio.RegDioMapping2.bits.Dio5Mapping++; 02391 radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); 02392 break; 02393 } // ...switch (pcbuf[1]) 02394 if (radio.RegOpMode.bits.LongRangeMode) 02395 lora_print_dio(); 02396 else 02397 fsk_print_dio(); 02398 } else if (pcbuf[0] == 'g') { /******* GPS... **********/ 02399 if (pcbuf[1] == 'e') { 02400 //gps.enable(!gps.enabled()); 02401 if (gps.enabled()) { 02402 gps.enable(false); 02403 printf("gps disabled\r\n"); 02404 } else { 02405 gps.enable(true); 02406 printf("GPS enabled\r\n"); 02407 } 02408 } else if (pcbuf[1] == 'v') { 02409 gps.verbose ^= 1; 02410 printf("gps.verbose:%d\r\n", gps.verbose); 02411 } 02412 } else if (pcbuf[0] == 'G') { // gpio registers. G<portABCD><MO><pin0-f>[0123] 02413 GPIO_TypeDef *gpiox; 02414 char bp[2]; 02415 bp[0] = pcbuf[3]; 02416 bp[1] = 0; 02417 sscanf(bp, "%x", &i); 02418 switch (pcbuf[1]) { 02419 case 'A': gpiox = GPIOA; break; 02420 case 'B': gpiox = GPIOB; break; 02421 case 'C': gpiox = GPIOC; break; 02422 case 'D': gpiox = GPIOD; break; 02423 default: gpiox = NULL; break; 02424 } 02425 if (gpiox != NULL) { 02426 if (pcbuf[2] == 'M') { // GPIOx->MODER 02427 if (pcbuf[4] >= '0' && pcbuf[4] <= '3') { 02428 a = i << 1; 02429 ui = 3 << a; 02430 d = pcbuf[4] - '0'; 02431 //gpiox->MODER &= ~ui; 02432 gpiox->MODER &= ~ui; 02433 gpiox->MODER |= d << a;; 02434 printf("ui:%08" PRIx32 ", d<<a:%08x\r\n", ui, d<<a); 02435 } 02436 for (len = 0; len < 16; len++) { 02437 i = len << 1; 02438 ui = gpiox->MODER >> i; 02439 printf("%02d:", len); 02440 switch (ui & 3) { 02441 case 0: printf("input\r\n"); break; 02442 case 1: printf("output\r\n"); break; 02443 case 2: printf("AF\r\n"); break; 02444 case 3: printf("analog\r\n"); break; 02445 } 02446 } 02447 printf("MODER:%08" PRIx32 "\r\n", gpiox->MODER); 02448 } else if (pcbuf[2] == 'O') { // GPIOx->BSRR 02449 ui = 1 << i; 02450 if (pcbuf[4] == '0') { 02451 gpiox->BSRR = ui << 16; 02452 } else if (pcbuf[4] == '1') { 02453 gpiox->BSRR = ui; 02454 } 02455 printf("ODR:%08" PRIx32 "\r\n", gpiox->ODR); 02456 } 02457 } 02458 02459 } else if (pcbuf[0] == 's' && pcbuf[1] == 't' && pcbuf[2] == 'b') { 02460 radio.set_opmode(RF_OPMODE_STANDBY); 02461 //green_led = LED_OFF; 02462 red_led = LED_OFF; 02463 } else if (pcbuf[0] == 's' && pcbuf[1] == 'l' && pcbuf[2] == 'e') { 02464 radio.set_opmode(RF_OPMODE_SLEEP); 02465 //green_led = LED_OFF; 02466 red_led = LED_OFF; 02467 } else if (pcbuf[0] == 'c' && pcbuf[1] == 'h' && pcbuf[2] == 'a') { 02468 app = APP_CHAT; 02469 lora.start_rx(RF_OPMODE_RECEIVER); 02470 printf("chat start\r\n"); 02471 } 02472 } 02473 printf("> "); 02474 fflush(stdout); 02475 02476 } 02477 02478 void get_mote_version() 02479 { 02480 char first; 02481 02482 /*DigitalOut pc_7(PC_7); 02483 DigitalIn pc_1(PC_1);*/ 02484 02485 pc_7 = 1; 02486 first = pc_1; 02487 pc_7 = 0; 02488 if (first && !pc_1) { 02489 //printf("v2-mote\r\n"); 02490 mote_version = MOTE_V2; 02491 ain_bat = new AnalogIn(PA_0); 02492 } else { 02493 //printf("v3-mote\r\n"); 02494 mote_version = MOTE_V3; 02495 ain_bat = new AnalogIn(PA_1); 02496 } 02497 02498 } 02499 02500 int main() 02501 { 02502 set_time(0); // start RTC 02503 02504 pc.baud(57600); 02505 gps.init(); 02506 02507 printf("\nreset\r\n"); 02508 //green_led = LED_OFF; 02509 red_led = LED_OFF; 02510 led2 = LED_OFF; 02511 yellow_led = LED_OFF; 02512 02513 radio.rf_switch = rfsw_callback; 02514 02515 if (radio.RegOpMode.bits.LongRangeMode) 02516 last_RxCurrentAddr = radio.read_reg(REG_LR_FIFORXCURRENTADDR); 02517 02518 get_mote_version(); 02519 if (mote_version == MOTE_V3) 02520 gps.en_invert = false; 02521 else 02522 gps.en_invert = true; 02523 02524 gps.enable(false); 02525 02526 sx9500.RegProxCtrl0.bits.sensor_en = 3; // only CS0 and CS1 connected 02527 sx9500.write(SX9500_REG_PROXCTRL0, sx9500.RegProxCtrl0.octet); 02528 02529 // set PROXTHRESH to 80 because CS1 has 48 showing always on PROXDIFF 02530 sx9500.write(SX9500_REG_PROXCTRL6, 0x04); 02531 02532 mma8451q.set_active(0); 02533 mma8451q.verbose = true; 02534 mpl3115a2.init(); 02535 mpl3115a2.SetModeStandby(); 02536 02537 GPIOA->MODER |= 0x01415500; // unused pins as outputs: PA4, PA5, PA6, PA7, PA8, (PA11,PA12 USB) 02538 //printf("GPIOA->MODER:%08x\r\n", GPIOA->MODER); 02539 02540 GPIOB->MODER |= 0x00000401; // unused pins as outputs: PB0(HDR_DIO1), PB5 (PB10 pulled hi by LED), PB3-T_SWO 02541 //printf("GPIOB->MODER:%08x\r\n", GPIOB->MODER); 02542 02543 GPIOC->MODER |= 0x00000045; // unused pins as outputs: PC0(hdr_fem_csd) PC1(hdr_fem_ctx) PC3(SPI3_enable) 02544 //printf("GPIOC->MODER:%08x\r\n", GPIOC->MODER); 02545 02546 while(1) { 02547 switch (app) { 02548 case APP_NONE: 02549 console(); 02550 break; 02551 case APP_CHAT: 02552 console_chat(); 02553 break; 02554 } // ...switch (app) 02555 } // ...while(1) 02556 }
Generated on Fri Jul 15 2022 02:44:33 by
1.7.2