Flying Sea Glider / Mbed 2 deprecated 2019_10may_firstflight_jcw_nosd

most functionality to splashdwon, find neutral and start mission. short timeouts still in code for testing, will adjust to go directly to sit_idle after splashdown

Dependencies:   mbed MODSERIAL FATFileSystem

SDFileSystem/SDFileSystem.cpp@92:52a91656458a, 2019-05-13 (annotated)

Committer:
joel_ssc
Date:
Mon May 13 19:25:26 2019 +0000
Revision:
92:52a91656458a
Parent:
81:7ff2c6467892 
version for first flight test, timeouts not yet set correctly

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tnhnrl 81:7ff2c6467892 1 /* mbed Microcontroller Library
tnhnrl 81:7ff2c6467892 2 * Copyright (c) 2006-2012 ARM Limited
tnhnrl 81:7ff2c6467892 3 *
tnhnrl 81:7ff2c6467892 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
tnhnrl 81:7ff2c6467892 5 * of this software and associated documentation files (the "Software"), to deal
tnhnrl 81:7ff2c6467892 6 * in the Software without restriction, including without limitation the rights
tnhnrl 81:7ff2c6467892 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
tnhnrl 81:7ff2c6467892 8 * copies of the Software, and to permit persons to whom the Software is
tnhnrl 81:7ff2c6467892 9 * furnished to do so, subject to the following conditions:
tnhnrl 81:7ff2c6467892 10 *
tnhnrl 81:7ff2c6467892 11 * The above copyright notice and this permission notice shall be included in
tnhnrl 81:7ff2c6467892 12 * all copies or substantial portions of the Software.
tnhnrl 81:7ff2c6467892 13 *
tnhnrl 81:7ff2c6467892 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
tnhnrl 81:7ff2c6467892 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
tnhnrl 81:7ff2c6467892 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
tnhnrl 81:7ff2c6467892 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
tnhnrl 81:7ff2c6467892 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
tnhnrl 81:7ff2c6467892 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
tnhnrl 81:7ff2c6467892 20 * SOFTWARE.
tnhnrl 81:7ff2c6467892 21 */
tnhnrl 81:7ff2c6467892 22 /* Introduction
tnhnrl 81:7ff2c6467892 23 * ------------
tnhnrl 81:7ff2c6467892 24 * SD and MMC cards support a number of interfaces, but common to them all
tnhnrl 81:7ff2c6467892 25 * is one based on SPI. This is the one I'm implmenting because it means
tnhnrl 81:7ff2c6467892 26 * it is much more portable even though not so performant, and we already
tnhnrl 81:7ff2c6467892 27 * have the mbed SPI Interface!
tnhnrl 81:7ff2c6467892 28 *
tnhnrl 81:7ff2c6467892 29 * The main reference I'm using is Chapter 7, "SPI Mode" of:
tnhnrl 81:7ff2c6467892 30 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
tnhnrl 81:7ff2c6467892 31 *
tnhnrl 81:7ff2c6467892 32 * SPI Startup
tnhnrl 81:7ff2c6467892 33 * -----------
tnhnrl 81:7ff2c6467892 34 * The SD card powers up in SD mode. The SPI interface mode is selected by
tnhnrl 81:7ff2c6467892 35 * asserting CS low and sending the reset command (CMD0). The card will
tnhnrl 81:7ff2c6467892 36 * respond with a (R1) response.
tnhnrl 81:7ff2c6467892 37 *
tnhnrl 81:7ff2c6467892 38 * CMD8 is optionally sent to determine the voltage range supported, and
tnhnrl 81:7ff2c6467892 39 * indirectly determine whether it is a version 1.x SD/non-SD card or
tnhnrl 81:7ff2c6467892 40 * version 2.x. I'll just ignore this for now.
tnhnrl 81:7ff2c6467892 41 *
tnhnrl 81:7ff2c6467892 42 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
tnhnrl 81:7ff2c6467892 43 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
tnhnrl 81:7ff2c6467892 44 *
tnhnrl 81:7ff2c6467892 45 * You should also indicate whether the host supports High Capicity cards,
tnhnrl 81:7ff2c6467892 46 * and check whether the card is high capacity - i'll also ignore this
tnhnrl 81:7ff2c6467892 47 *
tnhnrl 81:7ff2c6467892 48 * SPI Protocol
tnhnrl 81:7ff2c6467892 49 * ------------
tnhnrl 81:7ff2c6467892 50 * The SD SPI protocol is based on transactions made up of 8-bit words, with
tnhnrl 81:7ff2c6467892 51 * the host starting every bus transaction by asserting the CS signal low. The
tnhnrl 81:7ff2c6467892 52 * card always responds to commands, data blocks and errors.
tnhnrl 81:7ff2c6467892 53 *
tnhnrl 81:7ff2c6467892 54 * The protocol supports a CRC, but by default it is off (except for the
tnhnrl 81:7ff2c6467892 55 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
tnhnrl 81:7ff2c6467892 56 * I'll leave the CRC off I think!
tnhnrl 81:7ff2c6467892 57 *
tnhnrl 81:7ff2c6467892 58 * Standard capacity cards have variable data block sizes, whereas High
tnhnrl 81:7ff2c6467892 59 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
tnhnrl 81:7ff2c6467892 60 * just always use the Standard Capacity cards with a block size of 512 bytes.
tnhnrl 81:7ff2c6467892 61 * This is set with CMD16.
tnhnrl 81:7ff2c6467892 62 *
tnhnrl 81:7ff2c6467892 63 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
tnhnrl 81:7ff2c6467892 64 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
tnhnrl 81:7ff2c6467892 65 * the card gets a read command, it responds with a response token, and then
tnhnrl 81:7ff2c6467892 66 * a data token or an error.
tnhnrl 81:7ff2c6467892 67 *
tnhnrl 81:7ff2c6467892 68 * SPI Command Format
tnhnrl 81:7ff2c6467892 69 * ------------------
tnhnrl 81:7ff2c6467892 70 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
tnhnrl 81:7ff2c6467892 71 *
tnhnrl 81:7ff2c6467892 72 * +---------------+------------+------------+-----------+----------+--------------+
tnhnrl 81:7ff2c6467892 73 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
tnhnrl 81:7ff2c6467892 74 * +---------------+------------+------------+-----------+----------+--------------+
tnhnrl 81:7ff2c6467892 75 *
tnhnrl 81:7ff2c6467892 76 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
tnhnrl 81:7ff2c6467892 77 *
tnhnrl 81:7ff2c6467892 78 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
tnhnrl 81:7ff2c6467892 79 *
tnhnrl 81:7ff2c6467892 80 * SPI Response Format
tnhnrl 81:7ff2c6467892 81 * -------------------
tnhnrl 81:7ff2c6467892 82 * The main response format (R1) is a status byte (normally zero). Key flags:
tnhnrl 81:7ff2c6467892 83 * idle - 1 if the card is in an idle state/initialising
tnhnrl 81:7ff2c6467892 84 * cmd - 1 if an illegal command code was detected
tnhnrl 81:7ff2c6467892 85 *
tnhnrl 81:7ff2c6467892 86 * +-------------------------------------------------+
tnhnrl 81:7ff2c6467892 87 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
tnhnrl 81:7ff2c6467892 88 * +-------------------------------------------------+
tnhnrl 81:7ff2c6467892 89 *
tnhnrl 81:7ff2c6467892 90 * R1b is the same, except it is followed by a busy signal (zeros) until
tnhnrl 81:7ff2c6467892 91 * the first non-zero byte when it is ready again.
tnhnrl 81:7ff2c6467892 92 *
tnhnrl 81:7ff2c6467892 93 * Data Response Token
tnhnrl 81:7ff2c6467892 94 * -------------------
tnhnrl 81:7ff2c6467892 95 * Every data block written to the card is acknowledged by a byte
tnhnrl 81:7ff2c6467892 96 * response token
tnhnrl 81:7ff2c6467892 97 *
tnhnrl 81:7ff2c6467892 98 * +----------------------+
tnhnrl 81:7ff2c6467892 99 * | xxx | 0 | status | 1 |
tnhnrl 81:7ff2c6467892 100 * +----------------------+
tnhnrl 81:7ff2c6467892 101 * 010 - OK!
tnhnrl 81:7ff2c6467892 102 * 101 - CRC Error
tnhnrl 81:7ff2c6467892 103 * 110 - Write Error
tnhnrl 81:7ff2c6467892 104 *
tnhnrl 81:7ff2c6467892 105 * Single Block Read and Write
tnhnrl 81:7ff2c6467892 106 * ---------------------------
tnhnrl 81:7ff2c6467892 107 *
tnhnrl 81:7ff2c6467892 108 * Block transfers have a byte header, followed by the data, followed
tnhnrl 81:7ff2c6467892 109 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
tnhnrl 81:7ff2c6467892 110 *
tnhnrl 81:7ff2c6467892 111 * +------+---------+---------+- - - -+---------+-----------+----------+
tnhnrl 81:7ff2c6467892 112 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
tnhnrl 81:7ff2c6467892 113 * +------+---------+---------+- - - -+---------+-----------+----------+
tnhnrl 81:7ff2c6467892 114 */
tnhnrl 81:7ff2c6467892 115 #include "SDFileSystem.h"
tnhnrl 81:7ff2c6467892 116 #include "mbed_debug.h"
tnhnrl 81:7ff2c6467892 117
tnhnrl 81:7ff2c6467892 118 #define SD_COMMAND_TIMEOUT 5000
tnhnrl 81:7ff2c6467892 119
tnhnrl 81:7ff2c6467892 120 #define SD_DBG 0
tnhnrl 81:7ff2c6467892 121
tnhnrl 81:7ff2c6467892 122 SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
tnhnrl 81:7ff2c6467892 123 FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) {
tnhnrl 81:7ff2c6467892 124 _cs = 1;
tnhnrl 81:7ff2c6467892 125
tnhnrl 81:7ff2c6467892 126 // Set default to 100kHz for initialisation and 1MHz for data transfer
tnhnrl 81:7ff2c6467892 127 _init_sck = 100000;
tnhnrl 81:7ff2c6467892 128 _transfer_sck = 1000000;
tnhnrl 81:7ff2c6467892 129 }
tnhnrl 81:7ff2c6467892 130
tnhnrl 81:7ff2c6467892 131 #define R1_IDLE_STATE (1 << 0)
tnhnrl 81:7ff2c6467892 132 #define R1_ERASE_RESET (1 << 1)
tnhnrl 81:7ff2c6467892 133 #define R1_ILLEGAL_COMMAND (1 << 2)
tnhnrl 81:7ff2c6467892 134 #define R1_COM_CRC_ERROR (1 << 3)
tnhnrl 81:7ff2c6467892 135 #define R1_ERASE_SEQUENCE_ERROR (1 << 4)
tnhnrl 81:7ff2c6467892 136 #define R1_ADDRESS_ERROR (1 << 5)
tnhnrl 81:7ff2c6467892 137 #define R1_PARAMETER_ERROR (1 << 6)
tnhnrl 81:7ff2c6467892 138
tnhnrl 81:7ff2c6467892 139 // Types
tnhnrl 81:7ff2c6467892 140 // - v1.x Standard Capacity
tnhnrl 81:7ff2c6467892 141 // - v2.x Standard Capacity
tnhnrl 81:7ff2c6467892 142 // - v2.x High Capacity
tnhnrl 81:7ff2c6467892 143 // - Not recognised as an SD Card
tnhnrl 81:7ff2c6467892 144 #define SDCARD_FAIL 0
tnhnrl 81:7ff2c6467892 145 #define SDCARD_V1 1
tnhnrl 81:7ff2c6467892 146 #define SDCARD_V2 2
tnhnrl 81:7ff2c6467892 147 #define SDCARD_V2HC 3
tnhnrl 81:7ff2c6467892 148
tnhnrl 81:7ff2c6467892 149 int SDFileSystem::initialise_card() {
tnhnrl 81:7ff2c6467892 150 // Set to SCK for initialisation, and clock card with cs = 1
tnhnrl 81:7ff2c6467892 151 _spi.frequency(_init_sck);
tnhnrl 81:7ff2c6467892 152 _cs = 1;
tnhnrl 81:7ff2c6467892 153 for (int i = 0; i < 16; i++) {
tnhnrl 81:7ff2c6467892 154 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 155 }
tnhnrl 81:7ff2c6467892 156
tnhnrl 81:7ff2c6467892 157 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
tnhnrl 81:7ff2c6467892 158 if (_cmd(0, 0) != R1_IDLE_STATE) {
tnhnrl 81:7ff2c6467892 159 debug("No disk, or could not put SD card in to SPI idle state\n");
tnhnrl 81:7ff2c6467892 160 return SDCARD_FAIL;
tnhnrl 81:7ff2c6467892 161 }
tnhnrl 81:7ff2c6467892 162
tnhnrl 81:7ff2c6467892 163 // send CMD8 to determine whther it is ver 2.x
tnhnrl 81:7ff2c6467892 164 int r = _cmd8();
tnhnrl 81:7ff2c6467892 165 if (r == R1_IDLE_STATE) {
tnhnrl 81:7ff2c6467892 166 return initialise_card_v2();
tnhnrl 81:7ff2c6467892 167 } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
tnhnrl 81:7ff2c6467892 168 return initialise_card_v1();
tnhnrl 81:7ff2c6467892 169 } else {
tnhnrl 81:7ff2c6467892 170 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
tnhnrl 81:7ff2c6467892 171 return SDCARD_FAIL;
tnhnrl 81:7ff2c6467892 172 }
tnhnrl 81:7ff2c6467892 173 }
tnhnrl 81:7ff2c6467892 174
tnhnrl 81:7ff2c6467892 175 int SDFileSystem::initialise_card_v1() {
tnhnrl 81:7ff2c6467892 176 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
tnhnrl 81:7ff2c6467892 177 _cmd(55, 0);
tnhnrl 81:7ff2c6467892 178 if (_cmd(41, 0) == 0) {
tnhnrl 81:7ff2c6467892 179 cdv = 512;
tnhnrl 81:7ff2c6467892 180 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
tnhnrl 81:7ff2c6467892 181 return SDCARD_V1;
tnhnrl 81:7ff2c6467892 182 }
tnhnrl 81:7ff2c6467892 183 }
tnhnrl 81:7ff2c6467892 184
tnhnrl 81:7ff2c6467892 185 debug("Timeout waiting for v1.x card\n");
tnhnrl 81:7ff2c6467892 186 return SDCARD_FAIL;
tnhnrl 81:7ff2c6467892 187 }
tnhnrl 81:7ff2c6467892 188
tnhnrl 81:7ff2c6467892 189 int SDFileSystem::initialise_card_v2() {
tnhnrl 81:7ff2c6467892 190 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
tnhnrl 81:7ff2c6467892 191 wait_ms(50);
tnhnrl 81:7ff2c6467892 192 _cmd58();
tnhnrl 81:7ff2c6467892 193 _cmd(55, 0);
tnhnrl 81:7ff2c6467892 194 if (_cmd(41, 0x40000000) == 0) {
tnhnrl 81:7ff2c6467892 195 _cmd58();
tnhnrl 81:7ff2c6467892 196 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
tnhnrl 81:7ff2c6467892 197 cdv = 1;
tnhnrl 81:7ff2c6467892 198 return SDCARD_V2;
tnhnrl 81:7ff2c6467892 199 }
tnhnrl 81:7ff2c6467892 200 }
tnhnrl 81:7ff2c6467892 201
tnhnrl 81:7ff2c6467892 202 debug("Timeout waiting for v2.x card\n");
tnhnrl 81:7ff2c6467892 203 return SDCARD_FAIL;
tnhnrl 81:7ff2c6467892 204 }
tnhnrl 81:7ff2c6467892 205
tnhnrl 81:7ff2c6467892 206 int SDFileSystem::disk_initialize() {
tnhnrl 81:7ff2c6467892 207 _is_initialized = initialise_card();
tnhnrl 81:7ff2c6467892 208 if (_is_initialized == 0) {
tnhnrl 81:7ff2c6467892 209 debug("Fail to initialize card\n");
tnhnrl 81:7ff2c6467892 210 return 1;
tnhnrl 81:7ff2c6467892 211 }
tnhnrl 81:7ff2c6467892 212 debug_if(SD_DBG, "init card = %d\n", _is_initialized);
tnhnrl 81:7ff2c6467892 213 _sectors = _sd_sectors();
tnhnrl 81:7ff2c6467892 214
tnhnrl 81:7ff2c6467892 215 // Set block length to 512 (CMD16)
tnhnrl 81:7ff2c6467892 216 if (_cmd(16, 512) != 0) {
tnhnrl 81:7ff2c6467892 217 debug("Set 512-byte block timed out\n");
tnhnrl 81:7ff2c6467892 218 return 1;
tnhnrl 81:7ff2c6467892 219 }
tnhnrl 81:7ff2c6467892 220
tnhnrl 81:7ff2c6467892 221 // Set SCK for data transfer
tnhnrl 81:7ff2c6467892 222 _spi.frequency(_transfer_sck);
tnhnrl 81:7ff2c6467892 223 return 0;
tnhnrl 81:7ff2c6467892 224 }
tnhnrl 81:7ff2c6467892 225
tnhnrl 81:7ff2c6467892 226 int SDFileSystem::disk_write(const uint8_t* buffer, uint32_t block_number, uint32_t count) {
tnhnrl 81:7ff2c6467892 227 if (!_is_initialized) {
tnhnrl 81:7ff2c6467892 228 return -1;
tnhnrl 81:7ff2c6467892 229 }
tnhnrl 81:7ff2c6467892 230
tnhnrl 81:7ff2c6467892 231 for (uint32_t b = block_number; b < block_number + count; b++) {
tnhnrl 81:7ff2c6467892 232 // set write address for single block (CMD24)
tnhnrl 81:7ff2c6467892 233 if (_cmd(24, b * cdv) != 0) {
tnhnrl 81:7ff2c6467892 234 return 1;
tnhnrl 81:7ff2c6467892 235 }
tnhnrl 81:7ff2c6467892 236
tnhnrl 81:7ff2c6467892 237 // send the data block
tnhnrl 81:7ff2c6467892 238 _write(buffer, 512);
tnhnrl 81:7ff2c6467892 239 buffer += 512;
tnhnrl 81:7ff2c6467892 240 }
tnhnrl 81:7ff2c6467892 241
tnhnrl 81:7ff2c6467892 242 return 0;
tnhnrl 81:7ff2c6467892 243 }
tnhnrl 81:7ff2c6467892 244
tnhnrl 81:7ff2c6467892 245 int SDFileSystem::disk_read(uint8_t* buffer, uint32_t block_number, uint32_t count) {
tnhnrl 81:7ff2c6467892 246 if (!_is_initialized) {
tnhnrl 81:7ff2c6467892 247 return -1;
tnhnrl 81:7ff2c6467892 248 }
tnhnrl 81:7ff2c6467892 249
tnhnrl 81:7ff2c6467892 250 for (uint32_t b = block_number; b < block_number + count; b++) {
tnhnrl 81:7ff2c6467892 251 // set read address for single block (CMD17)
tnhnrl 81:7ff2c6467892 252 if (_cmd(17, b * cdv) != 0) {
tnhnrl 81:7ff2c6467892 253 return 1;
tnhnrl 81:7ff2c6467892 254 }
tnhnrl 81:7ff2c6467892 255
tnhnrl 81:7ff2c6467892 256 // receive the data
tnhnrl 81:7ff2c6467892 257 _read(buffer, 512);
tnhnrl 81:7ff2c6467892 258 buffer += 512;
tnhnrl 81:7ff2c6467892 259 }
tnhnrl 81:7ff2c6467892 260
tnhnrl 81:7ff2c6467892 261 return 0;
tnhnrl 81:7ff2c6467892 262 }
tnhnrl 81:7ff2c6467892 263
tnhnrl 81:7ff2c6467892 264 int SDFileSystem::disk_status() {
tnhnrl 81:7ff2c6467892 265 // FATFileSystem::disk_status() returns 0 when initialized
tnhnrl 81:7ff2c6467892 266 if (_is_initialized) {
tnhnrl 81:7ff2c6467892 267 return 0;
tnhnrl 81:7ff2c6467892 268 } else {
tnhnrl 81:7ff2c6467892 269 return 1;
tnhnrl 81:7ff2c6467892 270 }
tnhnrl 81:7ff2c6467892 271 }
tnhnrl 81:7ff2c6467892 272
tnhnrl 81:7ff2c6467892 273 int SDFileSystem::disk_sync() { return 0; }
tnhnrl 81:7ff2c6467892 274 uint32_t SDFileSystem::disk_sectors() { return _sectors; }
tnhnrl 81:7ff2c6467892 275
tnhnrl 81:7ff2c6467892 276
tnhnrl 81:7ff2c6467892 277 // PRIVATE FUNCTIONS
tnhnrl 81:7ff2c6467892 278 int SDFileSystem::_cmd(int cmd, int arg) {
tnhnrl 81:7ff2c6467892 279 _cs = 0;
tnhnrl 81:7ff2c6467892 280
tnhnrl 81:7ff2c6467892 281 // send a command
tnhnrl 81:7ff2c6467892 282 _spi.write(0x40 | cmd);
tnhnrl 81:7ff2c6467892 283 _spi.write(arg >> 24);
tnhnrl 81:7ff2c6467892 284 _spi.write(arg >> 16);
tnhnrl 81:7ff2c6467892 285 _spi.write(arg >> 8);
tnhnrl 81:7ff2c6467892 286 _spi.write(arg >> 0);
tnhnrl 81:7ff2c6467892 287 _spi.write(0x95);
tnhnrl 81:7ff2c6467892 288
tnhnrl 81:7ff2c6467892 289 // wait for the repsonse (response[7] == 0)
tnhnrl 81:7ff2c6467892 290 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
tnhnrl 81:7ff2c6467892 291 int response = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 292 if (!(response & 0x80)) {
tnhnrl 81:7ff2c6467892 293 _cs = 1;
tnhnrl 81:7ff2c6467892 294 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 295 return response;
tnhnrl 81:7ff2c6467892 296 }
tnhnrl 81:7ff2c6467892 297 }
tnhnrl 81:7ff2c6467892 298 _cs = 1;
tnhnrl 81:7ff2c6467892 299 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 300 return -1; // timeout
tnhnrl 81:7ff2c6467892 301 }
tnhnrl 81:7ff2c6467892 302 int SDFileSystem::_cmdx(int cmd, int arg) {
tnhnrl 81:7ff2c6467892 303 _cs = 0;
tnhnrl 81:7ff2c6467892 304
tnhnrl 81:7ff2c6467892 305 // send a command
tnhnrl 81:7ff2c6467892 306 _spi.write(0x40 | cmd);
tnhnrl 81:7ff2c6467892 307 _spi.write(arg >> 24);
tnhnrl 81:7ff2c6467892 308 _spi.write(arg >> 16);
tnhnrl 81:7ff2c6467892 309 _spi.write(arg >> 8);
tnhnrl 81:7ff2c6467892 310 _spi.write(arg >> 0);
tnhnrl 81:7ff2c6467892 311 _spi.write(0x95);
tnhnrl 81:7ff2c6467892 312
tnhnrl 81:7ff2c6467892 313 // wait for the repsonse (response[7] == 0)
tnhnrl 81:7ff2c6467892 314 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
tnhnrl 81:7ff2c6467892 315 int response = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 316 if (!(response & 0x80)) {
tnhnrl 81:7ff2c6467892 317 return response;
tnhnrl 81:7ff2c6467892 318 }
tnhnrl 81:7ff2c6467892 319 }
tnhnrl 81:7ff2c6467892 320 _cs = 1;
tnhnrl 81:7ff2c6467892 321 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 322 return -1; // timeout
tnhnrl 81:7ff2c6467892 323 }
tnhnrl 81:7ff2c6467892 324
tnhnrl 81:7ff2c6467892 325
tnhnrl 81:7ff2c6467892 326 int SDFileSystem::_cmd58() {
tnhnrl 81:7ff2c6467892 327 _cs = 0;
tnhnrl 81:7ff2c6467892 328 int arg = 0;
tnhnrl 81:7ff2c6467892 329
tnhnrl 81:7ff2c6467892 330 // send a command
tnhnrl 81:7ff2c6467892 331 _spi.write(0x40 | 58);
tnhnrl 81:7ff2c6467892 332 _spi.write(arg >> 24);
tnhnrl 81:7ff2c6467892 333 _spi.write(arg >> 16);
tnhnrl 81:7ff2c6467892 334 _spi.write(arg >> 8);
tnhnrl 81:7ff2c6467892 335 _spi.write(arg >> 0);
tnhnrl 81:7ff2c6467892 336 _spi.write(0x95);
tnhnrl 81:7ff2c6467892 337
tnhnrl 81:7ff2c6467892 338 // wait for the repsonse (response[7] == 0)
tnhnrl 81:7ff2c6467892 339 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
tnhnrl 81:7ff2c6467892 340 int response = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 341 if (!(response & 0x80)) {
tnhnrl 81:7ff2c6467892 342 int ocr = _spi.write(0xFF) << 24;
tnhnrl 81:7ff2c6467892 343 ocr |= _spi.write(0xFF) << 16;
tnhnrl 81:7ff2c6467892 344 ocr |= _spi.write(0xFF) << 8;
tnhnrl 81:7ff2c6467892 345 ocr |= _spi.write(0xFF) << 0;
tnhnrl 81:7ff2c6467892 346 _cs = 1;
tnhnrl 81:7ff2c6467892 347 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 348 return response;
tnhnrl 81:7ff2c6467892 349 }
tnhnrl 81:7ff2c6467892 350 }
tnhnrl 81:7ff2c6467892 351 _cs = 1;
tnhnrl 81:7ff2c6467892 352 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 353 return -1; // timeout
tnhnrl 81:7ff2c6467892 354 }
tnhnrl 81:7ff2c6467892 355
tnhnrl 81:7ff2c6467892 356 int SDFileSystem::_cmd8() {
tnhnrl 81:7ff2c6467892 357 _cs = 0;
tnhnrl 81:7ff2c6467892 358
tnhnrl 81:7ff2c6467892 359 // send a command
tnhnrl 81:7ff2c6467892 360 _spi.write(0x40 | 8); // CMD8
tnhnrl 81:7ff2c6467892 361 _spi.write(0x00); // reserved
tnhnrl 81:7ff2c6467892 362 _spi.write(0x00); // reserved
tnhnrl 81:7ff2c6467892 363 _spi.write(0x01); // 3.3v
tnhnrl 81:7ff2c6467892 364 _spi.write(0xAA); // check pattern
tnhnrl 81:7ff2c6467892 365 _spi.write(0x87); // crc
tnhnrl 81:7ff2c6467892 366
tnhnrl 81:7ff2c6467892 367 // wait for the repsonse (response[7] == 0)
tnhnrl 81:7ff2c6467892 368 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
tnhnrl 81:7ff2c6467892 369 char response[5];
tnhnrl 81:7ff2c6467892 370 response[0] = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 371 if (!(response[0] & 0x80)) {
tnhnrl 81:7ff2c6467892 372 for (int j = 1; j < 5; j++) {
tnhnrl 81:7ff2c6467892 373 response[i] = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 374 }
tnhnrl 81:7ff2c6467892 375 _cs = 1;
tnhnrl 81:7ff2c6467892 376 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 377 return response[0];
tnhnrl 81:7ff2c6467892 378 }
tnhnrl 81:7ff2c6467892 379 }
tnhnrl 81:7ff2c6467892 380 _cs = 1;
tnhnrl 81:7ff2c6467892 381 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 382 return -1; // timeout
tnhnrl 81:7ff2c6467892 383 }
tnhnrl 81:7ff2c6467892 384
tnhnrl 81:7ff2c6467892 385 int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
tnhnrl 81:7ff2c6467892 386 _cs = 0;
tnhnrl 81:7ff2c6467892 387
tnhnrl 81:7ff2c6467892 388 // read until start byte (0xFF)
tnhnrl 81:7ff2c6467892 389 while (_spi.write(0xFF) != 0xFE);
tnhnrl 81:7ff2c6467892 390
tnhnrl 81:7ff2c6467892 391 // read data
tnhnrl 81:7ff2c6467892 392 for (uint32_t i = 0; i < length; i++) {
tnhnrl 81:7ff2c6467892 393 buffer[i] = _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 394 }
tnhnrl 81:7ff2c6467892 395 _spi.write(0xFF); // checksum
tnhnrl 81:7ff2c6467892 396 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 397
tnhnrl 81:7ff2c6467892 398 _cs = 1;
tnhnrl 81:7ff2c6467892 399 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 400 return 0;
tnhnrl 81:7ff2c6467892 401 }
tnhnrl 81:7ff2c6467892 402
tnhnrl 81:7ff2c6467892 403 int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
tnhnrl 81:7ff2c6467892 404 _cs = 0;
tnhnrl 81:7ff2c6467892 405
tnhnrl 81:7ff2c6467892 406 // indicate start of block
tnhnrl 81:7ff2c6467892 407 _spi.write(0xFE);
tnhnrl 81:7ff2c6467892 408
tnhnrl 81:7ff2c6467892 409 // write the data
tnhnrl 81:7ff2c6467892 410 for (uint32_t i = 0; i < length; i++) {
tnhnrl 81:7ff2c6467892 411 _spi.write(buffer[i]);
tnhnrl 81:7ff2c6467892 412 }
tnhnrl 81:7ff2c6467892 413
tnhnrl 81:7ff2c6467892 414 // write the checksum
tnhnrl 81:7ff2c6467892 415 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 416 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 417
tnhnrl 81:7ff2c6467892 418 // check the response token
tnhnrl 81:7ff2c6467892 419 if ((_spi.write(0xFF) & 0x1F) != 0x05) {
tnhnrl 81:7ff2c6467892 420 _cs = 1;
tnhnrl 81:7ff2c6467892 421 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 422 return 1;
tnhnrl 81:7ff2c6467892 423 }
tnhnrl 81:7ff2c6467892 424
tnhnrl 81:7ff2c6467892 425 // wait for write to finish
tnhnrl 81:7ff2c6467892 426 while (_spi.write(0xFF) == 0);
tnhnrl 81:7ff2c6467892 427
tnhnrl 81:7ff2c6467892 428 _cs = 1;
tnhnrl 81:7ff2c6467892 429 _spi.write(0xFF);
tnhnrl 81:7ff2c6467892 430 return 0;
tnhnrl 81:7ff2c6467892 431 }
tnhnrl 81:7ff2c6467892 432
tnhnrl 81:7ff2c6467892 433 static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
tnhnrl 81:7ff2c6467892 434 uint32_t bits = 0;
tnhnrl 81:7ff2c6467892 435 uint32_t size = 1 + msb - lsb;
tnhnrl 81:7ff2c6467892 436 for (uint32_t i = 0; i < size; i++) {
tnhnrl 81:7ff2c6467892 437 uint32_t position = lsb + i;
tnhnrl 81:7ff2c6467892 438 uint32_t byte = 15 - (position >> 3);
tnhnrl 81:7ff2c6467892 439 uint32_t bit = position & 0x7;
tnhnrl 81:7ff2c6467892 440 uint32_t value = (data[byte] >> bit) & 1;
tnhnrl 81:7ff2c6467892 441 bits |= value << i;
tnhnrl 81:7ff2c6467892 442 }
tnhnrl 81:7ff2c6467892 443 return bits;
tnhnrl 81:7ff2c6467892 444 }
tnhnrl 81:7ff2c6467892 445
tnhnrl 81:7ff2c6467892 446 uint32_t SDFileSystem::_sd_sectors() {
tnhnrl 81:7ff2c6467892 447 uint32_t c_size, c_size_mult, read_bl_len;
tnhnrl 81:7ff2c6467892 448 uint32_t block_len, mult, blocknr, capacity;
tnhnrl 81:7ff2c6467892 449 uint32_t hc_c_size;
tnhnrl 81:7ff2c6467892 450 uint32_t blocks;
tnhnrl 81:7ff2c6467892 451
tnhnrl 81:7ff2c6467892 452 // CMD9, Response R2 (R1 byte + 16-byte block read)
tnhnrl 81:7ff2c6467892 453 if (_cmdx(9, 0) != 0) {
tnhnrl 81:7ff2c6467892 454 debug("Didn't get a response from the disk\n");
tnhnrl 81:7ff2c6467892 455 return 0;
tnhnrl 81:7ff2c6467892 456 }
tnhnrl 81:7ff2c6467892 457
tnhnrl 81:7ff2c6467892 458 uint8_t csd[16];
tnhnrl 81:7ff2c6467892 459 if (_read(csd, 16) != 0) {
tnhnrl 81:7ff2c6467892 460 debug("Couldn't read csd response from disk\n");
tnhnrl 81:7ff2c6467892 461 return 0;
tnhnrl 81:7ff2c6467892 462 }
tnhnrl 81:7ff2c6467892 463
tnhnrl 81:7ff2c6467892 464 // csd_structure : csd[127:126]
tnhnrl 81:7ff2c6467892 465 // c_size : csd[73:62]
tnhnrl 81:7ff2c6467892 466 // c_size_mult : csd[49:47]
tnhnrl 81:7ff2c6467892 467 // read_bl_len : csd[83:80] - the *maximum* read block length
tnhnrl 81:7ff2c6467892 468
tnhnrl 81:7ff2c6467892 469 int csd_structure = ext_bits(csd, 127, 126);
tnhnrl 81:7ff2c6467892 470
tnhnrl 81:7ff2c6467892 471 switch (csd_structure) {
tnhnrl 81:7ff2c6467892 472 case 0:
tnhnrl 81:7ff2c6467892 473 cdv = 512;
tnhnrl 81:7ff2c6467892 474 c_size = ext_bits(csd, 73, 62);
tnhnrl 81:7ff2c6467892 475 c_size_mult = ext_bits(csd, 49, 47);
tnhnrl 81:7ff2c6467892 476 read_bl_len = ext_bits(csd, 83, 80);
tnhnrl 81:7ff2c6467892 477
tnhnrl 81:7ff2c6467892 478 block_len = 1 << read_bl_len;
tnhnrl 81:7ff2c6467892 479 mult = 1 << (c_size_mult + 2);
tnhnrl 81:7ff2c6467892 480 blocknr = (c_size + 1) * mult;
tnhnrl 81:7ff2c6467892 481 capacity = blocknr * block_len;
tnhnrl 81:7ff2c6467892 482 blocks = capacity / 512;
tnhnrl 81:7ff2c6467892 483 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
tnhnrl 81:7ff2c6467892 484 break;
tnhnrl 81:7ff2c6467892 485
tnhnrl 81:7ff2c6467892 486 case 1:
tnhnrl 81:7ff2c6467892 487 cdv = 1;
tnhnrl 81:7ff2c6467892 488 hc_c_size = ext_bits(csd, 63, 48);
tnhnrl 81:7ff2c6467892 489 blocks = (hc_c_size+1)*1024;
tnhnrl 81:7ff2c6467892 490 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
tnhnrl 81:7ff2c6467892 491 break;
tnhnrl 81:7ff2c6467892 492
tnhnrl 81:7ff2c6467892 493 default:
tnhnrl 81:7ff2c6467892 494 debug("CSD struct unsupported\r\n");
tnhnrl 81:7ff2c6467892 495 return 0;
tnhnrl 81:7ff2c6467892 496 };
tnhnrl 81:7ff2c6467892 497 return blocks;
tnhnrl 81:7ff2c6467892 498 }