Maxim Integrated
MBED driver for Max1471.
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MAX1471.cpp
00001 /* 00002 * MAX1471.cpp 00003 * 00004 * Created on: Dec 17, 2018 00005 */ 00006 00007 #include <limits.h> 00008 #include "spim.h" 00009 #include "max32630fthr.h" 00010 #include "MAX1471.h" 00011 #include "tmr.h" 00012 #include "gpio.h" 00013 00014 00015 #define GPIO_P3_IN (uint32_t)0x4000A18C 00016 00017 using namespace std; 00018 00019 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ 00020 (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) 00021 00022 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 00023 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 00024 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 00025 00026 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) { \ 00027 int ret; \ 00028 ret = read_register(address, (uint8_t *)&(reg_name), 1); \ 00029 if (ret) { \ 00030 return ret; \ 00031 } \ 00032 bit_field_name = value; \ 00033 ret = write_register(address, (uint8_t *)&(reg_name), 1); \ 00034 if (ret) { \ 00035 return ret; \ 00036 }} 00037 00038 //Constructors 00039 00040 int MAX1471::ASKPeakDetectorEnable(bool enable) 00041 { 00042 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.askpd_en, enable ); 00043 00044 return 0; 00045 } 00046 00047 int MAX1471::FSKPeakDetectorEnable(bool enable) 00048 { 00049 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.fskpd_en, enable ); 00050 00051 return 0; 00052 } 00053 00054 int MAX1471::ASKBaseBandReceiverEnable(bool enable) 00055 { 00056 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.askbb_en, enable ); 00057 00058 return 0; 00059 } 00060 00061 int MAX1471::FSKBaseBandReceiverEnable(bool enable) 00062 { 00063 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.fskbb_en, enable ); 00064 00065 return 0; 00066 } 00067 00068 int MAX1471::RFMixerEnable(bool enable) 00069 { 00070 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.mixer_en, enable ); 00071 00072 return 0; 00073 } 00074 00075 int MAX1471::AGCEnable(bool enable) 00076 { 00077 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.agc_en, enable ); 00078 00079 return 0; 00080 } 00081 00082 int MAX1471::LNAEnable(bool enable) 00083 { 00084 SET_BIT_FIELD( PWR_CFG_ADDR, this -> reg->reg_pwr_cfg, this -> reg->reg_pwr_cfg.bits.lna_en, enable ); 00085 00086 return 0; 00087 } 00088 00089 int MAX1471::DRXEnable(bool enable) 00090 { 00091 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this -> reg->reg_cfg.bits.drx_mode, enable ); 00092 00093 return 0; 00094 } 00095 00096 00097 int MAX1471::SetFDATAasDOUTPin(bool enable) 00098 { 00099 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.dout_fsk, enable ); 00100 00101 return 0; 00102 } 00103 00104 int MAX1471::SetADATAasDOUTPin(bool enable) 00105 { 00106 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.dout_ask, enable ); 00107 00108 return 0; 00109 } 00110 00111 int MAX1471::LongerFSKCalibrationEnable(bool enable) 00112 { 00113 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.fskcallsb, enable ); 00114 00115 return 0; 00116 } 00117 00118 int MAX1471::LNAGainState(bool isHighGain) 00119 { 00120 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.gainset, isHighGain ); 00121 00122 return 0; 00123 } 00124 00125 int MAX1471::FSKCalibrationDone(bool enable) 00126 { 00127 SET_BIT_FIELD( CTRL_ADDR, this -> reg->reg_ctrl, this->reg->reg_ctrl.bits.fsk_cal_en, enable ); 00128 00129 return 0; 00130 } 00131 00132 int MAX1471::PollTimerCalibrationEnable(bool enable) 00133 { 00134 SET_BIT_FIELD( CTRL_ADDR, this -> reg->reg_ctrl, this->reg->reg_ctrl.bits.pol_cal_en, enable ); 00135 00136 return 0; 00137 } 00138 00139 int MAX1471::ASKPeakDetectorTrackEnable(bool enable) 00140 { 00141 SET_BIT_FIELD( CTRL_ADDR, this -> reg->reg_ctrl, this->reg->reg_ctrl.bits.asktrk_en, enable ); 00142 00143 return 0; 00144 } 00145 00146 int MAX1471::FSKPeakDetectorTrackEnable(bool enable) 00147 { 00148 SET_BIT_FIELD( CTRL_ADDR, this -> reg->reg_ctrl, this->reg->reg_ctrl.bits.fsktrk_en, enable ); 00149 00150 return 0; 00151 } 00152 00153 int MAX1471::LockAGCCurrentState() 00154 { 00155 SET_BIT_FIELD( CTRL_ADDR, this -> reg->reg_ctrl, this->reg->reg_ctrl.bits.agclock, 1 ); 00156 00157 return 0; 00158 } 00159 00160 int MAX1471::GetPollTimerCalibrationDoneStatus( unsigned char *valuePtr ) 00161 { 00162 read_register( STAT_ADDR, &this -> reg->reg_stat.raw, 1 ); 00163 00164 *valuePtr = this -> reg->reg_stat.bits.pol_cal_done; 00165 00166 return 0; 00167 } 00168 00169 int MAX1471::GetFSKCalibrationDoneStatus( unsigned char *valuePtr ) 00170 { 00171 read_register( STAT_ADDR, &this -> reg->reg_stat.raw, 1 ); 00172 00173 *valuePtr = this -> reg->reg_stat.bits.fsk_cal_done; 00174 00175 return 0; 00176 } 00177 00178 int MAX1471::GetClockAliveStatus( unsigned char *valuePtr ) 00179 { 00180 read_register( STAT_ADDR, &this -> reg->reg_stat.raw, 1 ); 00181 00182 *valuePtr = this -> reg->reg_stat.bits.clkalive; 00183 00184 return 0; 00185 } 00186 00187 int MAX1471::GetAGCStatus( unsigned char *valuePtr ) 00188 { 00189 read_register( STAT_ADDR, &this -> reg->reg_stat.raw, 1 ); 00190 00191 *valuePtr = this -> reg->reg_stat.bits.agcst; 00192 00193 return 0; 00194 } 00195 00196 int MAX1471::GetPLLLockStatus( unsigned char *valuePtr ) 00197 { 00198 read_register( STAT_ADDR, &this -> reg->reg_stat.raw, 1 ); 00199 00200 *valuePtr = this -> reg->reg_stat.bits.lockdet; 00201 00202 return 0; 00203 } 00204 00205 int MAX1471::GetOffTimerPrescale( unsigned char *valuePtr ) 00206 { 00207 read_register( CFG_ADDR, &this -> reg->reg_cfg.raw, 1 ); 00208 00209 *valuePtr = this->reg->reg_cfg.bits.toff_ps1; 00210 *valuePtr = ( *valuePtr << 1 ) | this->reg->reg_cfg.bits.toff_ps0; 00211 00212 return 0; 00213 } 00214 00215 int MAX1471::SetOffTimerPrescale( unsigned char value ) 00216 { 00217 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.toff_ps0, value & 0x01 ); 00218 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.toff_ps1, !!( value & 0x02 ) ); 00219 00220 return 0; 00221 } 00222 00223 int MAX1471::GetAGCDwellTimer( unsigned char *valuePtr ) 00224 { 00225 return read_register( AGC_DWL_TMR_ADDR, valuePtr, 1 ); 00226 } 00227 00228 int MAX1471::SetAGCDwellTimer( unsigned char value ) 00229 { 00230 return write_register( AGC_DWL_TMR_ADDR, value & 0x1F, 1); 00231 } 00232 00233 int MAX1471::SetRFSettleTimer( unsigned short int value ) 00234 { 00235 write_register( RF_ST_UP_ADDR, ( value >> 8 ), 1 ); 00236 write_register( RF_ST_DWN_ADDR, ( value & 0x00FF ), 1 ); 00237 00238 return 0; 00239 } 00240 00241 int MAX1471::GetRFSettleTimer( unsigned short int *valuePtr ) 00242 { 00243 unsigned char *valueUint8Ptr; 00244 00245 00246 valueUint8Ptr = ( unsigned char * )valuePtr; 00247 00248 read_register( RF_ST_UP_ADDR, &valueUint8Ptr[1], 1 ); 00249 read_register( RF_ST_DWN_ADDR, &valueUint8Ptr[0], 1 ); 00250 00251 return 0; 00252 } 00253 00254 int MAX1471::SetOFFTimer( unsigned short int value ) 00255 { 00256 write_register( OFF_TMR_UP_ADDR, ( value >> 8 ), 1 ); 00257 00258 return write_register( OFF_TMR_DWN_ADDR, ( value & 0x00FF ), 1 );; 00259 } 00260 00261 int MAX1471::GetOFFTimer( unsigned short int *valuePtr ) 00262 { 00263 unsigned char *valueUint8Ptr; 00264 00265 00266 valueUint8Ptr = ( unsigned char * )valuePtr; 00267 00268 read_register( OFF_TMR_UP_ADDR, &valueUint8Ptr[1], 1 ); 00269 00270 return read_register( OFF_TMR_DWN_ADDR, &valueUint8Ptr[0], 1 );; 00271 } 00272 00273 int MAX1471::SetCPURecoveryTimer( unsigned char value ) 00274 { 00275 return write_register( CPU_REC_ADDR, value, 1 );; 00276 } 00277 00278 int MAX1471::GetCPURecoveryTimer( unsigned char *valuePtr ) 00279 { 00280 return read_register( CPU_REC_ADDR, valuePtr, 1 ); 00281 } 00282 00283 int MAX1471::SetRFOscillatorFreq( float frequency ) 00284 { 00285 if( frequency >= 9.0406 && frequency <= 13.7281 ) 00286 { 00287 unsigned char regValue = ( unsigned char )( ( frequency * 10 ) + 0.5 ); 00288 oscFrequency = frequency; 00289 return write_register( OSC_FREQ_ADDR, regValue, 1 ); 00290 } 00291 00292 return -1; 00293 } 00294 00295 int MAX1471::GetRFOscillatorFreq( float *freqPtr ) 00296 { 00297 *freqPtr = oscFrequency; 00298 return 0; 00299 } 00300 00301 MAX1471::MAX1471(DigitalOut *cs) 00302 { 00303 modulation = ASK; /*!< Current modulation mode */ 00304 oscFrequency = 0; /*!< Extern oscillator frequency */ 00305 #if defined(TARGET_MAX32630FTHR) 00306 this->spi_handler = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00307 #endif 00308 00309 #if defined(TARGET_MAX32625PICO) 00310 this->spi_handler = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00311 #endif 00312 00313 this->spi_handler->format(8,0); 00314 this->spi_handler->frequency(100000); 00315 00316 this->ssel = cs; 00317 *(this->ssel) = 1; 00318 00319 this->spi_mode = 0; 00320 00321 this->reg = new max1471_reg_map_t(); 00322 00323 this->set_spi_type(0); 00324 } 00325 00326 int MAX1471::read_register(uint8_t reg, uint8_t *value, uint8_t len) 00327 { 00328 int rtn_val = -1; 00329 00330 if (value == NULL) { 00331 return -1; 00332 } 00333 00334 if (this->reg == NULL) { 00335 return -1; 00336 } 00337 00338 #if defined(TARGET_MAX32630FTHR) 00339 SPI *spi = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00340 mxc_spim_regs_t *MAX1471_SPI = MXC_SPIM2; 00341 #endif 00342 00343 #if defined(TARGET_MAX32625PICO) 00344 SPI *spi = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00345 mxc_spim_regs_t *MAX1471_SPI = MXC_SPIM0; 00346 #endif 00347 00348 spi->format(8,0); 00349 spi->frequency(400000); 00350 00351 if (ssel != NULL) { 00352 *ssel = 0; 00353 } 00354 00355 spi->write((uint8_t)0x20 | reg); 00356 spi->write(0x00); // dummy write command for waiting data read 00357 00358 if (ssel != NULL) { 00359 *ssel = 1; 00360 } 00361 00362 wait_us(1); 00363 00364 if (ssel != NULL) { 00365 *ssel = 0; 00366 } 00367 00368 if (this->spi_mode == 0) { 00369 00370 MAX1471_SPI->mstr_cfg |= MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE; 00371 00372 // Disable SPI for General Control Configuration 00373 MAX1471_SPI->gen_ctrl = 0; 00374 MAX1471_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (1 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header 00375 00376 MAX1471_SPI->simple_headers &= 0x0000FFFF; 00377 MAX1471_SPI->simple_headers |= 0x2016<<16; 00378 MAX1471_SPI->gen_ctrl |=MXC_F_SPIM_GEN_CTRL_START_RX_ONLY; 00379 00380 // Enable the SPI 00381 MAX1471_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN; 00382 00383 volatile mxc_spim_fifo_regs_t *fifo; 00384 00385 fifo = MXC_SPIM_GET_SPIM_FIFO(MXC_SPIM_GET_IDX(MAX1471_SPI)); 00386 00387 int avail = ((MAX1471_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); 00388 00389 Timer t; 00390 00391 t.start(); 00392 00393 while (avail < 1) { 00394 if (t.read_ms() > 1000) { 00395 break; 00396 } else { 00397 avail = ((MAX1471_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); 00398 } 00399 } 00400 00401 t.stop(); 00402 00403 for (int i = 0; i < avail; i++) { 00404 *(value++) = fifo->rslts_8[i]; 00405 } 00406 00407 while (MAX1471_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) { 00408 fifo->rslts_8[0]; 00409 } 00410 00411 MAX1471_SPI->gen_ctrl = 0; 00412 MAX1471_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (0 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header 00413 00414 MAX1471_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN; 00415 00416 } else { 00417 MAX1471_SPI->mstr_cfg &= ~MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE; 00418 00419 for (uint8_t i = 0; i < len; i++) { 00420 *(value++) = spi->write(0x00); // read back data bytes 00421 } 00422 } 00423 00424 if (ssel != NULL) { 00425 *ssel = 1; 00426 } 00427 00428 delete spi; 00429 00430 return 0; 00431 } 00432 00433 int MAX1471::write_register(uint8_t reg, const uint8_t *value, uint8_t len) 00434 { 00435 int rtn_val = -1; 00436 00437 if (value == NULL) { 00438 return -1; 00439 } 00440 00441 #if defined(TARGET_MAX32630FTHR) 00442 SPI *spi = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00443 #endif 00444 00445 #if defined(TARGET_MAX32625PICO) 00446 SPI *spi = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00447 #endif 00448 00449 spi->format(8,0); 00450 spi->frequency(100000); 00451 00452 if (ssel != NULL) { 00453 *ssel = 0; 00454 } 00455 00456 rtn_val = spi->write(0x10 | reg); // write mode and adress send 00457 00458 rtn_val = spi->write((int)*value); // write adress 00459 00460 00461 if (ssel != NULL) { 00462 *ssel = 1; 00463 } 00464 00465 delete spi; 00466 00467 if (rtn_val != 0) { 00468 return rtn_val; 00469 } 00470 00471 return 0; 00472 } 00473 00474 int MAX1471::write_register(uint8_t reg, const uint8_t value, uint8_t len) 00475 { 00476 int rtn_val = -1; 00477 00478 00479 #if defined(TARGET_MAX32630FTHR) 00480 SPI *spi = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00481 #endif 00482 00483 #if defined(TARGET_MAX32625PICO) 00484 SPI *spi = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00485 #endif 00486 00487 spi->format(8,0); 00488 spi->frequency(100000); 00489 00490 if (ssel != NULL) { 00491 *ssel = 0; 00492 } 00493 00494 rtn_val = spi->write(0x10 | reg); // write mode and adress send 00495 00496 rtn_val = spi->write((int)value); // write adress 00497 00498 00499 if (ssel != NULL) { 00500 *ssel = 1; 00501 } 00502 00503 delete spi; 00504 00505 if (rtn_val != 0) { 00506 return rtn_val; 00507 } 00508 00509 return 0; 00510 } 00511 00512 int MAX1471::set_spi_type(uint8_t type) 00513 { 00514 /* 00515 * 0 -> 3-Wire Default 00516 * 1 -> 4-Wire (DOUT_FSK) enabled 00517 * 2 -> 4-Wire (DOUT_ASK) enabled 00518 */ 00519 00520 switch (type) 00521 { 00522 case 0: 00523 this->reg->reg_cfg.bits.dout_ask = 0; 00524 this->reg->reg_cfg.bits.dout_fsk = 0; 00525 break; 00526 case 1: 00527 this->reg->reg_cfg.bits.dout_ask = 0; 00528 this->reg->reg_cfg.bits.dout_fsk = 1; 00529 break; 00530 case 2: 00531 this->reg->reg_cfg.bits.dout_ask = 1; 00532 this->reg->reg_cfg.bits.dout_fsk = 0; 00533 break; 00534 default: 00535 break; 00536 } 00537 00538 if (this->write_register(CFG_ADDR, (uint8_t *)&this->reg->reg_cfg.raw, 1) == 0) { 00539 spi_mode = type; 00540 } 00541 00542 return 0; 00543 } 00544 00545 int MAX1471::reset() 00546 { 00547 #if defined(TARGET_MAX32630FTHR) 00548 SPI *spi = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00549 #endif 00550 00551 #if defined(TARGET_MAX32625PICO) 00552 SPI *spi = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00553 #endif 00554 00555 spi->format(8,0); 00556 spi->frequency(100000); 00557 00558 if (ssel != NULL) { 00559 *ssel = 0; 00560 } 00561 00562 int rtrn = spi->write(0x30); // write mode and adress send 00563 00564 if (ssel != NULL) { 00565 *ssel = 1; 00566 } 00567 00568 delete spi; 00569 00570 return rtrn; 00571 00572 } 00573 00574 int MAX1471::nop() 00575 { 00576 #if defined(TARGET_MAX32630FTHR) 00577 SPI *spi = new SPI(P5_1, P5_2, P5_0); /* mosi, miso, sclk */ 00578 #endif 00579 00580 #if defined(TARGET_MAX32625PICO) 00581 SPI *spi = new SPI(P0_5, P0_6, P0_4); /* mosi, miso, sclk */ 00582 #endif 00583 00584 spi->format(8,0); 00585 spi->frequency(100000); 00586 00587 if (ssel != NULL) { 00588 *ssel = 0; 00589 } 00590 00591 int rtrn = spi->write(0x00); // write mode and adress send 00592 00593 if (ssel != NULL) { 00594 *ssel = 1; 00595 } 00596 00597 delete spi; 00598 00599 return rtrn; 00600 00601 } 00602 00603 int MAX1471::InitMAX1471() 00604 { 00605 // Write 0x3000 to reset the part 00606 this->reset(); 00607 // wait for 100ms 00608 Thread::wait(100); 00609 // Write 0x10FE to enable all RF and baseband sections. 00610 uint8_t value = 0xF4; 00611 this->write_register(PWR_CFG_ADDR, &value, 1); 00612 00613 // Write 0x135F to set the oscillator frequency register to work with a 315MHz crystal. 00614 // Write 0x1384 to set the oscillator frequency register to work with a 433.92MHz crystal. 00615 value = 0x84; 00616 this->write_register(OSC_FREQ_ADDR, &value, 1); 00617 00618 return 0; 00619 } 00620 00621 00622 int MAX1471::PrepMAX1471RX( modulation_type_t modType ) { 00623 uint8_t value = 0x20; 00624 uint8_t *readValue = &value; 00625 00626 00627 if( modType == ASK ){ 00628 this->ASKBaseBandReceiverEnable(true); 00629 this->ASKPeakDetectorEnable(true); 00630 this->RFMixerEnable(true); 00631 00632 this->LNAEnable(true); 00633 00634 this->AGCEnable(true); 00635 this->LNAGainState(true); 00636 this->AGCEnable(false); 00637 } 00638 else if( modType == FSK ){ 00639 this->FSKBaseBandReceiverEnable(true); 00640 this->FSKPeakDetectorEnable(true); 00641 00642 this->RFMixerEnable(true); 00643 00644 this->LNAEnable(true); 00645 00646 this->LongerFSKCalibrationEnable(true); 00647 00648 this->AGCEnable(true); 00649 this->LNAGainState(true); 00650 this->AGCEnable(false); 00651 00652 this->FSKCalibrationDone(true); 00653 00654 uint8_t *readValue = &value; 00655 00656 *readValue = 0; 00657 00658 while (*readValue == 0) { 00659 this->GetFSKCalibrationDoneStatus( readValue ); 00660 } 00661 } 00662 else{ 00663 this->PrepMAX1471RX(); 00664 } 00665 00666 return 0; 00667 00668 } 00669 00670 int MAX1471::PrepMAX1471RX() { 00671 uint8_t value; 00672 00673 this->ASKBaseBandReceiverEnable(true); 00674 this->ASKPeakDetectorEnable(true); 00675 00676 this->FSKBaseBandReceiverEnable(true); 00677 this->FSKPeakDetectorEnable(true); 00678 00679 this->RFMixerEnable(true); 00680 00681 this->LNAEnable(true); 00682 00683 this->LongerFSKCalibrationEnable(true); 00684 00685 this->AGCEnable(true); 00686 this->LNAGainState(true); 00687 this->AGCEnable(false); 00688 00689 this->FSKCalibrationDone(true); 00690 00691 uint8_t *readValue = &value; 00692 00693 *readValue = 0; 00694 00695 while (*readValue == 0) { 00696 this->GetFSKCalibrationDoneStatus( readValue ); 00697 } 00698 00699 return 0; 00700 } 00701 00702 int MAX1471::PrepMAX1471Sleep(bool enable) { 00703 /* This routine is used to prepare the MAX7032 for sleep mode */ 00704 00705 SET_BIT_FIELD( CFG_ADDR, this -> reg->reg_cfg, this->reg->reg_cfg.bits.toff_ps0, enable ); 00706 00707 return 0; 00708 } 00709 00710 00711 00712 00713 00714 00715
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