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(Working) Code to interface 3 LoadCells to ADISense1000 and display values using the Labview code.
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ADISENSE1000_REGISTERS.h
00001 /* ================================================================================ 00002 00003 Created by : sherry 00004 Created on : 2017 Nov 14, 10:55 GMT 00005 00006 Project : ADISENSE1000_REGISTERS 00007 File : ADISENSE1000_REGISTERS.h 00008 Description : Register Definitions 00009 00010 !! ADI Confidential !! 00011 INTERNAL USE ONLY 00012 00013 Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. 00014 This software is proprietary and confidential to Analog Devices, Inc. and 00015 its licensors. 00016 00017 This file was auto-generated. Do not make local changes to this file. 00018 00019 Auto generation script information: 00020 Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders 00021 Last modified: 26-SEP-2017 00022 00023 ================================================================================ */ 00024 00025 #ifndef _DEF_ADISENSE1000_REGISTERS_H 00026 #define _DEF_ADISENSE1000_REGISTERS_H 00027 00028 #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) 00029 #include <stdint.h> 00030 #endif /* _LANGUAGE_C */ 00031 00032 #ifndef __ADI_GENERATED_DEF_HEADERS__ 00033 #define __ADI_GENERATED_DEF_HEADERS__ 1 00034 #endif 00035 00036 #define __ADI_HAS_ADISENSE_CORE__ 1 00037 #define __ADI_HAS_ADISENSE_SPI__ 1 00038 #define __ADI_HAS_ADISENSE_TEST__ 1 00039 00040 /* ============================================================================================================================ 00041 00042 ============================================================================================================================ */ 00043 00044 /* ============================================================================================================================ 00045 ADISENSE_SPI 00046 ============================================================================================================================ */ 00047 #define MOD_ADISENSE_SPI_BASE 0x00000000 /* */ 00048 #define MOD_ADISENSE_SPI_MASK 0x00007FFF /* */ 00049 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */ 00050 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_A 0x00000000 /* ADISENSE_SPI Interface Configuration A */ 00051 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */ 00052 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_B 0x00000001 /* ADISENSE_SPI Interface Configuration B */ 00053 #define REG_ADISENSE_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */ 00054 #define REG_ADISENSE_SPI_DEVICE_CONFIG 0x00000002 /* ADISENSE_SPI Device Configuration */ 00055 #define REG_ADISENSE_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */ 00056 #define REG_ADISENSE_SPI_CHIP_TYPE 0x00000003 /* ADISENSE_SPI Chip Type */ 00057 #define REG_ADISENSE_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */ 00058 #define REG_ADISENSE_SPI_PRODUCT_ID_L 0x00000004 /* ADISENSE_SPI Product ID Low */ 00059 #define REG_ADISENSE_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */ 00060 #define REG_ADISENSE_SPI_PRODUCT_ID_H 0x00000005 /* ADISENSE_SPI Product ID High */ 00061 #define REG_ADISENSE_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */ 00062 #define REG_ADISENSE_SPI_CHIP_GRADE 0x00000006 /* ADISENSE_SPI Chip Grade */ 00063 #define REG_ADISENSE_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */ 00064 #define REG_ADISENSE_SPI_SCRATCH_PAD 0x0000000A /* ADISENSE_SPI Scratch Pad */ 00065 #define REG_ADISENSE_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */ 00066 #define REG_ADISENSE_SPI_SPI_REVISION 0x0000000B /* ADISENSE_SPI SPI Revision */ 00067 #define REG_ADISENSE_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */ 00068 #define REG_ADISENSE_SPI_VENDOR_L 0x0000000C /* ADISENSE_SPI Vendor ID Low */ 00069 #define REG_ADISENSE_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */ 00070 #define REG_ADISENSE_SPI_VENDOR_H 0x0000000D /* ADISENSE_SPI Vendor ID High */ 00071 #define REG_ADISENSE_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */ 00072 #define REG_ADISENSE_SPI_STREAM_MODE 0x0000000E /* ADISENSE_SPI Stream Mode */ 00073 #define REG_ADISENSE_SPI_TRANSFER_CONFIG_RESET 0x00000000 /* Reset Value for Transfer_Config */ 00074 #define REG_ADISENSE_SPI_TRANSFER_CONFIG 0x0000000F /* ADISENSE_SPI Transfer Config */ 00075 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_C_RESET 0x00000033 /* Reset Value for Interface_Config_C */ 00076 #define REG_ADISENSE_SPI_INTERFACE_CONFIG_C 0x00000010 /* ADISENSE_SPI Interface Configuration C */ 00077 #define REG_ADISENSE_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */ 00078 #define REG_ADISENSE_SPI_INTERFACE_STATUS_A 0x00000011 /* ADISENSE_SPI Interface Status A */ 00079 00080 /* ============================================================================================================================ 00081 ADISENSE_SPI Register BitMasks, Positions & Enumerations 00082 ============================================================================================================================ */ 00083 /* ------------------------------------------------------------------------------------------------------------------------- 00084 ADISENSE_SPI_INTERFACE_CONFIG_A Pos/Masks Description 00085 ------------------------------------------------------------------------------------------------------------------------- */ 00086 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of SW_RESET Bits. */ 00087 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */ 00088 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* SDO Pin Enable */ 00089 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of SW_RESET Bits. */ 00090 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of SW_RESET Bits. */ 00091 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */ 00092 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* SDO Pin Enable */ 00093 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of SW_RESET Bits. */ 00094 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */ 00095 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */ 00096 00097 /* ------------------------------------------------------------------------------------------------------------------------- 00098 ADISENSE_SPI_INTERFACE_CONFIG_B Pos/Masks Description 00099 ------------------------------------------------------------------------------------------------------------------------- */ 00100 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 /* Select Streaming or Single Instruction Mode */ 00101 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 /* Select Streaming or Single Instruction Mode */ 00102 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_B_STREAMING_MODE 0x00000000 /* Single_Inst: Streaming mode is enabled */ 00103 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */ 00104 00105 /* ------------------------------------------------------------------------------------------------------------------------- 00106 ADISENSE_SPI_DEVICE_CONFIG Pos/Masks Description 00107 ------------------------------------------------------------------------------------------------------------------------- */ 00108 #define BITP_ADISENSE_SPI_DEVICE_CONFIG_OPERATING_MODES 0 /* Power Modes */ 00109 #define BITM_ADISENSE_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 /* Power Modes */ 00110 #define ENUM_ADISENSE_SPI_DEVICE_CONFIG_NORMAL 0x00000000 /* Operating_Modes: Normal Operating Mode */ 00111 #define ENUM_ADISENSE_SPI_DEVICE_CONFIG_SLEEP 0x00000003 /* Operating_Modes: Low Power Mode */ 00112 00113 /* ------------------------------------------------------------------------------------------------------------------------- 00114 ADISENSE_SPI_CHIP_TYPE Pos/Masks Description 00115 ------------------------------------------------------------------------------------------------------------------------- */ 00116 #define BITP_ADISENSE_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */ 00117 #define BITM_ADISENSE_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F /* Precision ADC */ 00118 00119 /* ------------------------------------------------------------------------------------------------------------------------- 00120 ADISENSE_SPI_PRODUCT_ID_L Pos/Masks Description 00121 ------------------------------------------------------------------------------------------------------------------------- */ 00122 #define BITP_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 /* These Bits are Fixed on Die Configured for Multiple Generics */ 00123 #define BITP_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 /* These Bits Vary on Die Configured for Multiple Generics */ 00124 #define BITM_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 /* These Bits are Fixed on Die Configured for Multiple Generics */ 00125 #define BITM_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F /* These Bits Vary on Die Configured for Multiple Generics */ 00126 00127 /* ------------------------------------------------------------------------------------------------------------------------- 00128 ADISENSE_SPI_PRODUCT_ID_H Pos/Masks Description 00129 ------------------------------------------------------------------------------------------------------------------------- */ 00130 #define BITP_ADISENSE_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 /* These Bits are Fixed on Die Configured for Multiple Generics */ 00131 #define BITM_ADISENSE_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF /* These Bits are Fixed on Die Configured for Multiple Generics */ 00132 00133 /* ------------------------------------------------------------------------------------------------------------------------- 00134 ADISENSE_SPI_CHIP_GRADE Pos/Masks Description 00135 ------------------------------------------------------------------------------------------------------------------------- */ 00136 #define BITP_ADISENSE_SPI_CHIP_GRADE_GRADE 4 /* This is the Device Performance Grade */ 00137 #define BITP_ADISENSE_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* This is the Device Hardware Revision */ 00138 #define BITM_ADISENSE_SPI_CHIP_GRADE_GRADE 0x000000F0 /* This is the Device Performance Grade */ 00139 #define BITM_ADISENSE_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* This is the Device Hardware Revision */ 00140 00141 /* ------------------------------------------------------------------------------------------------------------------------- 00142 ADISENSE_SPI_SCRATCH_PAD Pos/Masks Description 00143 ------------------------------------------------------------------------------------------------------------------------- */ 00144 #define BITP_ADISENSE_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 /* Software Scratchpad */ 00145 #define BITM_ADISENSE_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF /* Software Scratchpad */ 00146 00147 /* ------------------------------------------------------------------------------------------------------------------------- 00148 ADISENSE_SPI_SPI_REVISION Pos/Masks Description 00149 ------------------------------------------------------------------------------------------------------------------------- */ 00150 #define BITP_ADISENSE_SPI_SPI_REVISION_SPI_TYPE 6 /* Always Reads as 0x2 */ 00151 #define BITP_ADISENSE_SPI_SPI_REVISION_VERSION 0 /* SPI Version */ 00152 #define BITM_ADISENSE_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */ 00153 #define BITM_ADISENSE_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */ 00154 #define ENUM_ADISENSE_SPI_SPI_REVISION_ADI_SPI 0x00000000 00155 #define ENUM_ADISENSE_SPI_SPI_REVISION_LPT_SPI 0x00000080 00156 #define ENUM_ADISENSE_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */ 00157 00158 /* ------------------------------------------------------------------------------------------------------------------------- 00159 ADISENSE_SPI_VENDOR_L Pos/Masks Description 00160 ------------------------------------------------------------------------------------------------------------------------- */ 00161 #define BITP_ADISENSE_SPI_VENDOR_L_VID 0 /* Analog Devices Vendor ID */ 00162 #define BITM_ADISENSE_SPI_VENDOR_L_VID 0x000000FF /* Analog Devices Vendor ID */ 00163 00164 /* ------------------------------------------------------------------------------------------------------------------------- 00165 ADISENSE_SPI_VENDOR_H Pos/Masks Description 00166 ------------------------------------------------------------------------------------------------------------------------- */ 00167 #define BITP_ADISENSE_SPI_VENDOR_H_VID 0 /* Analog Devices Vendor ID */ 00168 #define BITM_ADISENSE_SPI_VENDOR_H_VID 0x000000FF /* Analog Devices Vendor ID */ 00169 00170 /* ------------------------------------------------------------------------------------------------------------------------- 00171 ADISENSE_SPI_STREAM_MODE Pos/Masks Description 00172 ------------------------------------------------------------------------------------------------------------------------- */ 00173 #define BITP_ADISENSE_SPI_STREAM_MODE_LOOP_COUNT 0 /* Sets the Data Byte Count Before Looping to Start Address */ 00174 #define BITM_ADISENSE_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Sets the Data Byte Count Before Looping to Start Address */ 00175 00176 /* ------------------------------------------------------------------------------------------------------------------------- 00177 ADISENSE_SPI_TRANSFER_CONFIG Pos/Masks Description 00178 ------------------------------------------------------------------------------------------------------------------------- */ 00179 #define BITP_ADISENSE_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Controls Master-Slave Transfer */ 00180 #define BITM_ADISENSE_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Controls Master-Slave Transfer */ 00181 #define ENUM_ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */ 00182 #define ENUM_ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */ 00183 00184 /* ------------------------------------------------------------------------------------------------------------------------- 00185 ADISENSE_SPI_INTERFACE_CONFIG_C Pos/Masks Description 00186 ------------------------------------------------------------------------------------------------------------------------- */ 00187 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */ 00188 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multi-byte Registers Must Be Read/Written in Full */ 00189 #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */ 00190 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */ 00191 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multi-byte Registers Must Be Read/Written in Full */ 00192 #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */ 00193 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */ 00194 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */ 00195 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS 0x00000000 /* Strict_Register_Access: Normal mode, no access restrictions */ 00196 #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS 0x00000020 /* Strict_Register_Access: Strict mode, multi-byte registers require all bytes read/written */ 00197 00198 /* ------------------------------------------------------------------------------------------------------------------------- 00199 ADISENSE_SPI_INTERFACE_STATUS_A Pos/Masks Description 00200 ------------------------------------------------------------------------------------------------------------------------- */ 00201 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */ 00202 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */ 00203 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */ 00204 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read-Only Register Attempted */ 00205 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */ 00206 #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Non-existent Register Address */ 00207 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */ 00208 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */ 00209 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */ 00210 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read-Only Register Attempted */ 00211 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */ 00212 #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Non-existent Register Address */ 00213 00214 00215 /* ============================================================================================================================ 00216 ADISENSE1000 Core Registers 00217 ============================================================================================================================ */ 00218 00219 /* ============================================================================================================================ 00220 ADISENSE_CORE 00221 ============================================================================================================================ */ 00222 #define MOD_ADISENSE_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */ 00223 #define MOD_ADISENSE_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */ 00224 #define REG_ADISENSE_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */ 00225 #define REG_ADISENSE_CORE_COMMAND 0x00000014 /* ADISENSE_CORE Special Command */ 00226 #define REG_ADISENSE_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */ 00227 #define REG_ADISENSE_CORE_MODE 0x00000016 /* ADISENSE_CORE Operating Mode and DRDY Control */ 00228 #define REG_ADISENSE_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */ 00229 #define REG_ADISENSE_CORE_POWER_CONFIG 0x00000017 /* ADISENSE_CORE General Configuration */ 00230 #define REG_ADISENSE_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */ 00231 #define REG_ADISENSE_CORE_CYCLE_CONTROL 0x00000018 /* ADISENSE_CORE Measurement Cycle */ 00232 #define REG_ADISENSE_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */ 00233 #define REG_ADISENSE_CORE_FIFO_NUM_CYCLES 0x0000001A /* ADISENSE_CORE Number of Measurement Cycles to Store in FIFO */ 00234 #define REG_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_RESET 0x00000000 /* Reset Value for Multi_Cycle_Repeat_Interval */ 00235 #define REG_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL 0x0000001C /* ADISENSE_CORE Time Between Repeats of Multi-Cycle Conversions.... */ 00236 #define REG_ADISENSE_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */ 00237 #define REG_ADISENSE_CORE_STATUS 0x00000020 /* ADISENSE_CORE General Status */ 00238 #define REG_ADISENSE_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */ 00239 #define REG_ADISENSE_CORE_DIAGNOSTICS_STATUS 0x00000024 /* ADISENSE_CORE Diagnostics Status */ 00240 #define REG_ADISENSE_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */ 00241 #define REG_ADISENSE_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* ADISENSE_CORE Alert Status Summary */ 00242 #define REG_ADISENSE_CORE_ALERT_STATUS_2_RESET 0x00000000 /* Reset Value for Alert_Status_2 */ 00243 #define REG_ADISENSE_CORE_ALERT_STATUS_2 0x00000028 /* ADISENSE_CORE Additional Alert Status Information */ 00244 #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */ 00245 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH0 */ 00246 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH1 */ 00247 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH2 */ 00248 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH3 */ 00249 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH4 */ 00250 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH5 */ 00251 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH6 */ 00252 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH7 */ 00253 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH8 */ 00254 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH9 */ 00255 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH10 */ 00256 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH11 */ 00257 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH12 */ 00258 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH0 0x0000002A /* ADISENSE_CORE Detailed Error Information */ 00259 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH1 0x0000002C /* ADISENSE_CORE Detailed Error Information */ 00260 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH2 0x0000002E /* ADISENSE_CORE Detailed Error Information */ 00261 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH3 0x00000030 /* ADISENSE_CORE Detailed Error Information */ 00262 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH4 0x00000032 /* ADISENSE_CORE Detailed Error Information */ 00263 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH5 0x00000034 /* ADISENSE_CORE Detailed Error Information */ 00264 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH6 0x00000036 /* ADISENSE_CORE Detailed Error Information */ 00265 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH7 0x00000038 /* ADISENSE_CORE Detailed Error Information */ 00266 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH8 0x0000003A /* ADISENSE_CORE Detailed Error Information */ 00267 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH9 0x0000003C /* ADISENSE_CORE Detailed Error Information */ 00268 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH10 0x0000003E /* ADISENSE_CORE Detailed Error Information */ 00269 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH11 0x00000040 /* ADISENSE_CORE Detailed Error Information */ 00270 #define REG_ADISENSE_CORE_ALERT_DETAIL_CH12 0x00000042 /* ADISENSE_CORE Detailed Error Information */ 00271 #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn(i) (REG_ADISENSE_CORE_ALERT_DETAIL_CH0 + ((i) * 2)) 00272 #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn_COUNT 13 00273 #define REG_ADISENSE_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */ 00274 #define REG_ADISENSE_CORE_ERROR_CODE 0x0000004C /* ADISENSE_CORE Code Indicating Source of Error */ 00275 #define REG_ADISENSE_CORE_ALERT_CODE_RESET 0x00000000 /* Reset Value for Alert_Code */ 00276 #define REG_ADISENSE_CORE_ALERT_CODE 0x0000004E /* ADISENSE_CORE Code Indicating Source of Alert */ 00277 #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */ 00278 #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE1 0x00000050 /* ADISENSE_CORE External Reference Information */ 00279 #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */ 00280 #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE2 0x00000054 /* ADISENSE_CORE External Reference Information */ 00281 #define REG_ADISENSE_CORE_AVDD_VOLTAGE_RESET 0x40533333 /* Reset Value for AVDD_Voltage */ 00282 #define REG_ADISENSE_CORE_AVDD_VOLTAGE 0x00000058 /* ADISENSE_CORE AVDD Voltage */ 00283 #define REG_ADISENSE_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */ 00284 #define REG_ADISENSE_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* ADISENSE_CORE Diagnostic Control */ 00285 #define REG_ADISENSE_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */ 00286 #define REG_ADISENSE_CORE_DATA_FIFO 0x00000060 /* ADISENSE_CORE FIFO of Sensor Results */ 00287 #define REG_ADISENSE_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */ 00288 #define REG_ADISENSE_CORE_LUT_SELECT 0x00000070 /* ADISENSE_CORE Read/Write Strobe */ 00289 #define REG_ADISENSE_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */ 00290 #define REG_ADISENSE_CORE_LUT_OFFSET 0x00000072 /* ADISENSE_CORE Offset into Selected LUT */ 00291 #define REG_ADISENSE_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */ 00292 #define REG_ADISENSE_CORE_LUT_DATA 0x00000074 /* ADISENSE_CORE Data to Read/Write from Addressed LUT Entry */ 00293 #define REG_ADISENSE_CORE_CAL_OFFSET_RESET 0x00000000 /* Reset Value for CAL_Offset */ 00294 #define REG_ADISENSE_CORE_CAL_OFFSET 0x0000007A /* ADISENSE_CORE Offset into Selected Calibration Values */ 00295 #define REG_ADISENSE_CORE_CAL_DATA_RESET 0x00000000 /* Reset Value for CAL_Data */ 00296 #define REG_ADISENSE_CORE_CAL_DATA 0x0000007C /* ADISENSE_CORE Data to Read/Write from Addressed Calibration Values */ 00297 #define REG_ADISENSE_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */ 00298 #define REG_ADISENSE_CORE_REVISION 0x0000008C /* ADISENSE_CORE Hardware, Firmware Revision */ 00299 #define REG_ADISENSE_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */ 00300 #define REG_ADISENSE_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT0 */ 00301 #define REG_ADISENSE_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT1 */ 00302 #define REG_ADISENSE_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT2 */ 00303 #define REG_ADISENSE_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT3 */ 00304 #define REG_ADISENSE_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT4 */ 00305 #define REG_ADISENSE_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT5 */ 00306 #define REG_ADISENSE_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT6 */ 00307 #define REG_ADISENSE_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT7 */ 00308 #define REG_ADISENSE_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT8 */ 00309 #define REG_ADISENSE_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT9 */ 00310 #define REG_ADISENSE_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT10 */ 00311 #define REG_ADISENSE_CORE_CHANNEL_COUNT0 0x00000090 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00312 #define REG_ADISENSE_CORE_CHANNEL_COUNT1 0x000000D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00313 #define REG_ADISENSE_CORE_CHANNEL_COUNT2 0x00000110 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00314 #define REG_ADISENSE_CORE_CHANNEL_COUNT3 0x00000150 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00315 #define REG_ADISENSE_CORE_CHANNEL_COUNT4 0x00000190 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00316 #define REG_ADISENSE_CORE_CHANNEL_COUNT5 0x000001D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00317 #define REG_ADISENSE_CORE_CHANNEL_COUNT6 0x00000210 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00318 #define REG_ADISENSE_CORE_CHANNEL_COUNT7 0x00000250 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00319 #define REG_ADISENSE_CORE_CHANNEL_COUNT8 0x00000290 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00320 #define REG_ADISENSE_CORE_CHANNEL_COUNT9 0x000002D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00321 #define REG_ADISENSE_CORE_CHANNEL_COUNT10 0x00000310 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ 00322 #define REG_ADISENSE_CORE_CHANNEL_COUNTn(i) (REG_ADISENSE_CORE_CHANNEL_COUNT0 + ((i) * 64)) 00323 #define REG_ADISENSE_CORE_CHANNEL_COUNTn_COUNT 11 00324 #define REG_ADISENSE_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */ 00325 #define REG_ADISENSE_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE0 */ 00326 #define REG_ADISENSE_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE1 */ 00327 #define REG_ADISENSE_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE2 */ 00328 #define REG_ADISENSE_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE3 */ 00329 #define REG_ADISENSE_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE4 */ 00330 #define REG_ADISENSE_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE5 */ 00331 #define REG_ADISENSE_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE6 */ 00332 #define REG_ADISENSE_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE7 */ 00333 #define REG_ADISENSE_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE8 */ 00334 #define REG_ADISENSE_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE9 */ 00335 #define REG_ADISENSE_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE10 */ 00336 #define REG_ADISENSE_CORE_SENSOR_TYPE0 0x00000092 /* ADISENSE_CORE Sensor Select */ 00337 #define REG_ADISENSE_CORE_SENSOR_TYPE1 0x000000D2 /* ADISENSE_CORE Sensor Select */ 00338 #define REG_ADISENSE_CORE_SENSOR_TYPE2 0x00000112 /* ADISENSE_CORE Sensor Select */ 00339 #define REG_ADISENSE_CORE_SENSOR_TYPE3 0x00000152 /* ADISENSE_CORE Sensor Select */ 00340 #define REG_ADISENSE_CORE_SENSOR_TYPE4 0x00000192 /* ADISENSE_CORE Sensor Select */ 00341 #define REG_ADISENSE_CORE_SENSOR_TYPE5 0x000001D2 /* ADISENSE_CORE Sensor Select */ 00342 #define REG_ADISENSE_CORE_SENSOR_TYPE6 0x00000212 /* ADISENSE_CORE Sensor Select */ 00343 #define REG_ADISENSE_CORE_SENSOR_TYPE7 0x00000252 /* ADISENSE_CORE Sensor Select */ 00344 #define REG_ADISENSE_CORE_SENSOR_TYPE8 0x00000292 /* ADISENSE_CORE Sensor Select */ 00345 #define REG_ADISENSE_CORE_SENSOR_TYPE9 0x000002D2 /* ADISENSE_CORE Sensor Select */ 00346 #define REG_ADISENSE_CORE_SENSOR_TYPE10 0x00000312 /* ADISENSE_CORE Sensor Select */ 00347 #define REG_ADISENSE_CORE_SENSOR_TYPEn(i) (REG_ADISENSE_CORE_SENSOR_TYPE0 + ((i) * 64)) 00348 #define REG_ADISENSE_CORE_SENSOR_TYPEn_COUNT 11 00349 #define REG_ADISENSE_CORE_SENSOR_DETAILSn_RESET 0x0000FFF0 /* Reset Value for Sensor_Details[n] */ 00350 #define REG_ADISENSE_CORE_SENSOR_DETAILS0_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS0 */ 00351 #define REG_ADISENSE_CORE_SENSOR_DETAILS1_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS1 */ 00352 #define REG_ADISENSE_CORE_SENSOR_DETAILS2_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS2 */ 00353 #define REG_ADISENSE_CORE_SENSOR_DETAILS3_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS3 */ 00354 #define REG_ADISENSE_CORE_SENSOR_DETAILS4_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS4 */ 00355 #define REG_ADISENSE_CORE_SENSOR_DETAILS5_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS5 */ 00356 #define REG_ADISENSE_CORE_SENSOR_DETAILS6_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS6 */ 00357 #define REG_ADISENSE_CORE_SENSOR_DETAILS7_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS7 */ 00358 #define REG_ADISENSE_CORE_SENSOR_DETAILS8_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS8 */ 00359 #define REG_ADISENSE_CORE_SENSOR_DETAILS9_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS9 */ 00360 #define REG_ADISENSE_CORE_SENSOR_DETAILS10_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS10 */ 00361 #define REG_ADISENSE_CORE_SENSOR_DETAILS0 0x00000094 /* ADISENSE_CORE Sensor Details */ 00362 #define REG_ADISENSE_CORE_SENSOR_DETAILS1 0x000000D4 /* ADISENSE_CORE Sensor Details */ 00363 #define REG_ADISENSE_CORE_SENSOR_DETAILS2 0x00000114 /* ADISENSE_CORE Sensor Details */ 00364 #define REG_ADISENSE_CORE_SENSOR_DETAILS3 0x00000154 /* ADISENSE_CORE Sensor Details */ 00365 #define REG_ADISENSE_CORE_SENSOR_DETAILS4 0x00000194 /* ADISENSE_CORE Sensor Details */ 00366 #define REG_ADISENSE_CORE_SENSOR_DETAILS5 0x000001D4 /* ADISENSE_CORE Sensor Details */ 00367 #define REG_ADISENSE_CORE_SENSOR_DETAILS6 0x00000214 /* ADISENSE_CORE Sensor Details */ 00368 #define REG_ADISENSE_CORE_SENSOR_DETAILS7 0x00000254 /* ADISENSE_CORE Sensor Details */ 00369 #define REG_ADISENSE_CORE_SENSOR_DETAILS8 0x00000294 /* ADISENSE_CORE Sensor Details */ 00370 #define REG_ADISENSE_CORE_SENSOR_DETAILS9 0x000002D4 /* ADISENSE_CORE Sensor Details */ 00371 #define REG_ADISENSE_CORE_SENSOR_DETAILS10 0x00000314 /* ADISENSE_CORE Sensor Details */ 00372 #define REG_ADISENSE_CORE_SENSOR_DETAILSn(i) (REG_ADISENSE_CORE_SENSOR_DETAILS0 + ((i) * 64)) 00373 #define REG_ADISENSE_CORE_SENSOR_DETAILSn_COUNT 11 00374 #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */ 00375 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION0 */ 00376 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION1 */ 00377 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION2 */ 00378 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION3 */ 00379 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION4 */ 00380 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION5 */ 00381 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION6 */ 00382 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION7 */ 00383 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION8 */ 00384 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION9 */ 00385 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION10 */ 00386 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION0 0x00000098 /* ADISENSE_CORE Excitation Current */ 00387 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION1 0x000000D8 /* ADISENSE_CORE Excitation Current */ 00388 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION2 0x00000118 /* ADISENSE_CORE Excitation Current */ 00389 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION3 0x00000158 /* ADISENSE_CORE Excitation Current */ 00390 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION4 0x00000198 /* ADISENSE_CORE Excitation Current */ 00391 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION5 0x000001D8 /* ADISENSE_CORE Excitation Current */ 00392 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION6 0x00000218 /* ADISENSE_CORE Excitation Current */ 00393 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION7 0x00000258 /* ADISENSE_CORE Excitation Current */ 00394 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION8 0x00000298 /* ADISENSE_CORE Excitation Current */ 00395 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION9 0x000002D8 /* ADISENSE_CORE Excitation Current */ 00396 #define REG_ADISENSE_CORE_CHANNEL_EXCITATION10 0x00000318 /* ADISENSE_CORE Excitation Current */ 00397 #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn(i) (REG_ADISENSE_CORE_CHANNEL_EXCITATION0 + ((i) * 64)) 00398 #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn_COUNT 11 00399 #define REG_ADISENSE_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */ 00400 #define REG_ADISENSE_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME0 */ 00401 #define REG_ADISENSE_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME1 */ 00402 #define REG_ADISENSE_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME2 */ 00403 #define REG_ADISENSE_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME3 */ 00404 #define REG_ADISENSE_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME4 */ 00405 #define REG_ADISENSE_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME5 */ 00406 #define REG_ADISENSE_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME6 */ 00407 #define REG_ADISENSE_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME7 */ 00408 #define REG_ADISENSE_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME8 */ 00409 #define REG_ADISENSE_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME9 */ 00410 #define REG_ADISENSE_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME10 */ 00411 #define REG_ADISENSE_CORE_SETTLING_TIME0 0x0000009A /* ADISENSE_CORE Settling Time */ 00412 #define REG_ADISENSE_CORE_SETTLING_TIME1 0x000000DA /* ADISENSE_CORE Settling Time */ 00413 #define REG_ADISENSE_CORE_SETTLING_TIME2 0x0000011A /* ADISENSE_CORE Settling Time */ 00414 #define REG_ADISENSE_CORE_SETTLING_TIME3 0x0000015A /* ADISENSE_CORE Settling Time */ 00415 #define REG_ADISENSE_CORE_SETTLING_TIME4 0x0000019A /* ADISENSE_CORE Settling Time */ 00416 #define REG_ADISENSE_CORE_SETTLING_TIME5 0x000001DA /* ADISENSE_CORE Settling Time */ 00417 #define REG_ADISENSE_CORE_SETTLING_TIME6 0x0000021A /* ADISENSE_CORE Settling Time */ 00418 #define REG_ADISENSE_CORE_SETTLING_TIME7 0x0000025A /* ADISENSE_CORE Settling Time */ 00419 #define REG_ADISENSE_CORE_SETTLING_TIME8 0x0000029A /* ADISENSE_CORE Settling Time */ 00420 #define REG_ADISENSE_CORE_SETTLING_TIME9 0x000002DA /* ADISENSE_CORE Settling Time */ 00421 #define REG_ADISENSE_CORE_SETTLING_TIME10 0x0000031A /* ADISENSE_CORE Settling Time */ 00422 #define REG_ADISENSE_CORE_SETTLING_TIMEn(i) (REG_ADISENSE_CORE_SETTLING_TIME0 + ((i) * 64)) 00423 #define REG_ADISENSE_CORE_SETTLING_TIMEn_COUNT 11 00424 #define REG_ADISENSE_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */ 00425 #define REG_ADISENSE_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT0 */ 00426 #define REG_ADISENSE_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT1 */ 00427 #define REG_ADISENSE_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT2 */ 00428 #define REG_ADISENSE_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT3 */ 00429 #define REG_ADISENSE_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT4 */ 00430 #define REG_ADISENSE_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT5 */ 00431 #define REG_ADISENSE_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT6 */ 00432 #define REG_ADISENSE_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT7 */ 00433 #define REG_ADISENSE_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT8 */ 00434 #define REG_ADISENSE_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT9 */ 00435 #define REG_ADISENSE_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT10 */ 00436 #define REG_ADISENSE_CORE_FILTER_SELECT0 0x0000009C /* ADISENSE_CORE ADC Digital Filter Selection */ 00437 #define REG_ADISENSE_CORE_FILTER_SELECT1 0x000000DC /* ADISENSE_CORE ADC Digital Filter Selection */ 00438 #define REG_ADISENSE_CORE_FILTER_SELECT2 0x0000011C /* ADISENSE_CORE ADC Digital Filter Selection */ 00439 #define REG_ADISENSE_CORE_FILTER_SELECT3 0x0000015C /* ADISENSE_CORE ADC Digital Filter Selection */ 00440 #define REG_ADISENSE_CORE_FILTER_SELECT4 0x0000019C /* ADISENSE_CORE ADC Digital Filter Selection */ 00441 #define REG_ADISENSE_CORE_FILTER_SELECT5 0x000001DC /* ADISENSE_CORE ADC Digital Filter Selection */ 00442 #define REG_ADISENSE_CORE_FILTER_SELECT6 0x0000021C /* ADISENSE_CORE ADC Digital Filter Selection */ 00443 #define REG_ADISENSE_CORE_FILTER_SELECT7 0x0000025C /* ADISENSE_CORE ADC Digital Filter Selection */ 00444 #define REG_ADISENSE_CORE_FILTER_SELECT8 0x0000029C /* ADISENSE_CORE ADC Digital Filter Selection */ 00445 #define REG_ADISENSE_CORE_FILTER_SELECT9 0x000002DC /* ADISENSE_CORE ADC Digital Filter Selection */ 00446 #define REG_ADISENSE_CORE_FILTER_SELECT10 0x0000031C /* ADISENSE_CORE ADC Digital Filter Selection */ 00447 #define REG_ADISENSE_CORE_FILTER_SELECTn(i) (REG_ADISENSE_CORE_FILTER_SELECT0 + ((i) * 64)) 00448 #define REG_ADISENSE_CORE_FILTER_SELECTn_COUNT 11 00449 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */ 00450 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 */ 00451 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1 */ 00452 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2 */ 00453 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3 */ 00454 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4 */ 00455 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5 */ 00456 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6 */ 00457 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7 */ 00458 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8 */ 00459 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9 */ 00460 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10 */ 00461 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11 */ 00462 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12 */ 00463 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* ADISENSE_CORE High Threshold */ 00464 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* ADISENSE_CORE High Threshold */ 00465 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* ADISENSE_CORE High Threshold */ 00466 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3 0x00000160 /* ADISENSE_CORE High Threshold */ 00467 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A0 /* ADISENSE_CORE High Threshold */ 00468 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E0 /* ADISENSE_CORE High Threshold */ 00469 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6 0x00000220 /* ADISENSE_CORE High Threshold */ 00470 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7 0x00000260 /* ADISENSE_CORE High Threshold */ 00471 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A0 /* ADISENSE_CORE High Threshold */ 00472 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E0 /* ADISENSE_CORE High Threshold */ 00473 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10 0x00000320 /* ADISENSE_CORE High Threshold */ 00474 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11 0x00000360 /* ADISENSE_CORE High Threshold */ 00475 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* ADISENSE_CORE High Threshold */ 00476 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64)) 00477 #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13 00478 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */ 00479 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 */ 00480 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1 */ 00481 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2 */ 00482 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3 */ 00483 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4 */ 00484 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5 */ 00485 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6 */ 00486 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7 */ 00487 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8 */ 00488 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9 */ 00489 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10 */ 00490 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11 */ 00491 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12 */ 00492 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* ADISENSE_CORE Low Threshold */ 00493 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* ADISENSE_CORE Low Threshold */ 00494 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* ADISENSE_CORE Low Threshold */ 00495 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3 0x00000164 /* ADISENSE_CORE Low Threshold */ 00496 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4 0x000001A4 /* ADISENSE_CORE Low Threshold */ 00497 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5 0x000001E4 /* ADISENSE_CORE Low Threshold */ 00498 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6 0x00000224 /* ADISENSE_CORE Low Threshold */ 00499 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7 0x00000264 /* ADISENSE_CORE Low Threshold */ 00500 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8 0x000002A4 /* ADISENSE_CORE Low Threshold */ 00501 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9 0x000002E4 /* ADISENSE_CORE Low Threshold */ 00502 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10 0x00000324 /* ADISENSE_CORE Low Threshold */ 00503 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11 0x00000364 /* ADISENSE_CORE Low Threshold */ 00504 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12 0x000003A4 /* ADISENSE_CORE Low Threshold */ 00505 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn(i) (REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64)) 00506 #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn_COUNT 13 00507 #define REG_ADISENSE_CORE_SENSOR_OFFSETn_RESET 0x00000000 /* Reset Value for Sensor_Offset[n] */ 00508 #define REG_ADISENSE_CORE_SENSOR_OFFSET0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET0 */ 00509 #define REG_ADISENSE_CORE_SENSOR_OFFSET1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET1 */ 00510 #define REG_ADISENSE_CORE_SENSOR_OFFSET2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET2 */ 00511 #define REG_ADISENSE_CORE_SENSOR_OFFSET3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET3 */ 00512 #define REG_ADISENSE_CORE_SENSOR_OFFSET4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET4 */ 00513 #define REG_ADISENSE_CORE_SENSOR_OFFSET5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET5 */ 00514 #define REG_ADISENSE_CORE_SENSOR_OFFSET6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET6 */ 00515 #define REG_ADISENSE_CORE_SENSOR_OFFSET7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET7 */ 00516 #define REG_ADISENSE_CORE_SENSOR_OFFSET8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET8 */ 00517 #define REG_ADISENSE_CORE_SENSOR_OFFSET9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET9 */ 00518 #define REG_ADISENSE_CORE_SENSOR_OFFSET10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET10 */ 00519 #define REG_ADISENSE_CORE_SENSOR_OFFSET11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET11 */ 00520 #define REG_ADISENSE_CORE_SENSOR_OFFSET12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET12 */ 00521 #define REG_ADISENSE_CORE_SENSOR_OFFSET0 0x000000A8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00522 #define REG_ADISENSE_CORE_SENSOR_OFFSET1 0x000000E8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00523 #define REG_ADISENSE_CORE_SENSOR_OFFSET2 0x00000128 /* ADISENSE_CORE Sensor Offset Adjustment */ 00524 #define REG_ADISENSE_CORE_SENSOR_OFFSET3 0x00000168 /* ADISENSE_CORE Sensor Offset Adjustment */ 00525 #define REG_ADISENSE_CORE_SENSOR_OFFSET4 0x000001A8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00526 #define REG_ADISENSE_CORE_SENSOR_OFFSET5 0x000001E8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00527 #define REG_ADISENSE_CORE_SENSOR_OFFSET6 0x00000228 /* ADISENSE_CORE Sensor Offset Adjustment */ 00528 #define REG_ADISENSE_CORE_SENSOR_OFFSET7 0x00000268 /* ADISENSE_CORE Sensor Offset Adjustment */ 00529 #define REG_ADISENSE_CORE_SENSOR_OFFSET8 0x000002A8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00530 #define REG_ADISENSE_CORE_SENSOR_OFFSET9 0x000002E8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00531 #define REG_ADISENSE_CORE_SENSOR_OFFSET10 0x00000328 /* ADISENSE_CORE Sensor Offset Adjustment */ 00532 #define REG_ADISENSE_CORE_SENSOR_OFFSET11 0x00000368 /* ADISENSE_CORE Sensor Offset Adjustment */ 00533 #define REG_ADISENSE_CORE_SENSOR_OFFSET12 0x000003A8 /* ADISENSE_CORE Sensor Offset Adjustment */ 00534 #define REG_ADISENSE_CORE_SENSOR_OFFSETn(i) (REG_ADISENSE_CORE_SENSOR_OFFSET0 + ((i) * 64)) 00535 #define REG_ADISENSE_CORE_SENSOR_OFFSETn_COUNT 13 00536 #define REG_ADISENSE_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */ 00537 #define REG_ADISENSE_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN0 */ 00538 #define REG_ADISENSE_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN1 */ 00539 #define REG_ADISENSE_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN2 */ 00540 #define REG_ADISENSE_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN3 */ 00541 #define REG_ADISENSE_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN4 */ 00542 #define REG_ADISENSE_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN5 */ 00543 #define REG_ADISENSE_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN6 */ 00544 #define REG_ADISENSE_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN7 */ 00545 #define REG_ADISENSE_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN8 */ 00546 #define REG_ADISENSE_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN9 */ 00547 #define REG_ADISENSE_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN10 */ 00548 #define REG_ADISENSE_CORE_SENSOR_GAIN11_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN11 */ 00549 #define REG_ADISENSE_CORE_SENSOR_GAIN12_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN12 */ 00550 #define REG_ADISENSE_CORE_SENSOR_GAIN0 0x000000AC /* ADISENSE_CORE Sensor Gain Adjustment */ 00551 #define REG_ADISENSE_CORE_SENSOR_GAIN1 0x000000EC /* ADISENSE_CORE Sensor Gain Adjustment */ 00552 #define REG_ADISENSE_CORE_SENSOR_GAIN2 0x0000012C /* ADISENSE_CORE Sensor Gain Adjustment */ 00553 #define REG_ADISENSE_CORE_SENSOR_GAIN3 0x0000016C /* ADISENSE_CORE Sensor Gain Adjustment */ 00554 #define REG_ADISENSE_CORE_SENSOR_GAIN4 0x000001AC /* ADISENSE_CORE Sensor Gain Adjustment */ 00555 #define REG_ADISENSE_CORE_SENSOR_GAIN5 0x000001EC /* ADISENSE_CORE Sensor Gain Adjustment */ 00556 #define REG_ADISENSE_CORE_SENSOR_GAIN6 0x0000022C /* ADISENSE_CORE Sensor Gain Adjustment */ 00557 #define REG_ADISENSE_CORE_SENSOR_GAIN7 0x0000026C /* ADISENSE_CORE Sensor Gain Adjustment */ 00558 #define REG_ADISENSE_CORE_SENSOR_GAIN8 0x000002AC /* ADISENSE_CORE Sensor Gain Adjustment */ 00559 #define REG_ADISENSE_CORE_SENSOR_GAIN9 0x000002EC /* ADISENSE_CORE Sensor Gain Adjustment */ 00560 #define REG_ADISENSE_CORE_SENSOR_GAIN10 0x0000032C /* ADISENSE_CORE Sensor Gain Adjustment */ 00561 #define REG_ADISENSE_CORE_SENSOR_GAIN11 0x0000036C /* ADISENSE_CORE Sensor Gain Adjustment */ 00562 #define REG_ADISENSE_CORE_SENSOR_GAIN12 0x000003AC /* ADISENSE_CORE Sensor Gain Adjustment */ 00563 #define REG_ADISENSE_CORE_SENSOR_GAINn(i) (REG_ADISENSE_CORE_SENSOR_GAIN0 + ((i) * 64)) 00564 #define REG_ADISENSE_CORE_SENSOR_GAINn_COUNT 13 00565 #define REG_ADISENSE_CORE_ALERT_CODE_CHn_RESET 0x00000000 /* Reset Value for Alert_Code_Ch[n] */ 00566 #define REG_ADISENSE_CORE_ALERT_CODE_CH0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH0 */ 00567 #define REG_ADISENSE_CORE_ALERT_CODE_CH1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH1 */ 00568 #define REG_ADISENSE_CORE_ALERT_CODE_CH2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH2 */ 00569 #define REG_ADISENSE_CORE_ALERT_CODE_CH3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH3 */ 00570 #define REG_ADISENSE_CORE_ALERT_CODE_CH4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH4 */ 00571 #define REG_ADISENSE_CORE_ALERT_CODE_CH5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH5 */ 00572 #define REG_ADISENSE_CORE_ALERT_CODE_CH6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH6 */ 00573 #define REG_ADISENSE_CORE_ALERT_CODE_CH7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH7 */ 00574 #define REG_ADISENSE_CORE_ALERT_CODE_CH8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH8 */ 00575 #define REG_ADISENSE_CORE_ALERT_CODE_CH9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH9 */ 00576 #define REG_ADISENSE_CORE_ALERT_CODE_CH10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH10 */ 00577 #define REG_ADISENSE_CORE_ALERT_CODE_CH11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH11 */ 00578 #define REG_ADISENSE_CORE_ALERT_CODE_CH12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH12 */ 00579 #define REG_ADISENSE_CORE_ALERT_CODE_CH0 0x000000B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00580 #define REG_ADISENSE_CORE_ALERT_CODE_CH1 0x000000F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00581 #define REG_ADISENSE_CORE_ALERT_CODE_CH2 0x00000130 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00582 #define REG_ADISENSE_CORE_ALERT_CODE_CH3 0x00000170 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00583 #define REG_ADISENSE_CORE_ALERT_CODE_CH4 0x000001B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00584 #define REG_ADISENSE_CORE_ALERT_CODE_CH5 0x000001F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00585 #define REG_ADISENSE_CORE_ALERT_CODE_CH6 0x00000230 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00586 #define REG_ADISENSE_CORE_ALERT_CODE_CH7 0x00000270 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00587 #define REG_ADISENSE_CORE_ALERT_CODE_CH8 0x000002B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00588 #define REG_ADISENSE_CORE_ALERT_CODE_CH9 0x000002F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00589 #define REG_ADISENSE_CORE_ALERT_CODE_CH10 0x00000330 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00590 #define REG_ADISENSE_CORE_ALERT_CODE_CH11 0x00000370 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00591 #define REG_ADISENSE_CORE_ALERT_CODE_CH12 0x000003B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ 00592 #define REG_ADISENSE_CORE_ALERT_CODE_CHn(i) (REG_ADISENSE_CORE_ALERT_CODE_CH0 + ((i) * 64)) 00593 #define REG_ADISENSE_CORE_ALERT_CODE_CHn_COUNT 13 00594 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */ 00595 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 */ 00596 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1 */ 00597 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2 */ 00598 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3 */ 00599 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4 */ 00600 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5 */ 00601 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6 */ 00602 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7 */ 00603 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8 */ 00604 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9 */ 00605 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10 */ 00606 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 0x000000B8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00607 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1 0x000000F8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00608 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2 0x00000138 /* ADISENSE_CORE Digital Sensor Data Coding */ 00609 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3 0x00000178 /* ADISENSE_CORE Digital Sensor Data Coding */ 00610 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4 0x000001B8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00611 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5 0x000001F8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00612 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6 0x00000238 /* ADISENSE_CORE Digital Sensor Data Coding */ 00613 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7 0x00000278 /* ADISENSE_CORE Digital Sensor Data Coding */ 00614 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8 0x000002B8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00615 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9 0x000002F8 /* ADISENSE_CORE Digital Sensor Data Coding */ 00616 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10 0x00000338 /* ADISENSE_CORE Digital Sensor Data Coding */ 00617 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 + ((i) * 64)) 00618 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn_COUNT 11 00619 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */ 00620 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 */ 00621 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1 */ 00622 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2 */ 00623 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3 */ 00624 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4 */ 00625 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5 */ 00626 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6 */ 00627 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7 */ 00628 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8 */ 00629 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9 */ 00630 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10 */ 00631 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000BA /* ADISENSE_CORE Sensor Address */ 00632 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000FA /* ADISENSE_CORE Sensor Address */ 00633 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000013A /* ADISENSE_CORE Sensor Address */ 00634 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000017A /* ADISENSE_CORE Sensor Address */ 00635 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001BA /* ADISENSE_CORE Sensor Address */ 00636 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001FA /* ADISENSE_CORE Sensor Address */ 00637 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000023A /* ADISENSE_CORE Sensor Address */ 00638 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000027A /* ADISENSE_CORE Sensor Address */ 00639 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002BA /* ADISENSE_CORE Sensor Address */ 00640 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002FA /* ADISENSE_CORE Sensor Address */ 00641 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000033A /* ADISENSE_CORE Sensor Address */ 00642 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64)) 00643 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 11 00644 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Num_Cmds[n] */ 00645 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 */ 00646 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1 */ 00647 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2 */ 00648 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3 */ 00649 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4 */ 00650 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5 */ 00651 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6 */ 00652 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7 */ 00653 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8 */ 00654 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9 */ 00655 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10 */ 00656 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 0x000000BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00657 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1 0x000000FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00658 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2 0x0000013B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00659 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3 0x0000017B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00660 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4 0x000001BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00661 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5 0x000001FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00662 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6 0x0000023B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00663 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7 0x0000027B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00664 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8 0x000002BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00665 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9 0x000002FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00666 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10 0x0000033B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ 00667 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 + ((i) * 64)) 00668 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn_COUNT 11 00669 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */ 00670 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 */ 00671 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11 */ 00672 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12 */ 00673 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13 */ 00674 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14 */ 00675 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15 */ 00676 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16 */ 00677 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17 */ 00678 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18 */ 00679 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19 */ 00680 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110 */ 00681 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 0x000000C0 /* ADISENSE_CORE Sensor Configuration Command1 */ 00682 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11 0x00000100 /* ADISENSE_CORE Sensor Configuration Command1 */ 00683 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12 0x00000140 /* ADISENSE_CORE Sensor Configuration Command1 */ 00684 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13 0x00000180 /* ADISENSE_CORE Sensor Configuration Command1 */ 00685 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14 0x000001C0 /* ADISENSE_CORE Sensor Configuration Command1 */ 00686 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15 0x00000200 /* ADISENSE_CORE Sensor Configuration Command1 */ 00687 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16 0x00000240 /* ADISENSE_CORE Sensor Configuration Command1 */ 00688 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17 0x00000280 /* ADISENSE_CORE Sensor Configuration Command1 */ 00689 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18 0x000002C0 /* ADISENSE_CORE Sensor Configuration Command1 */ 00690 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19 0x00000300 /* ADISENSE_CORE Sensor Configuration Command1 */ 00691 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110 0x00000340 /* ADISENSE_CORE Sensor Configuration Command1 */ 00692 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64)) 00693 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 11 00694 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */ 00695 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 */ 00696 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21 */ 00697 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22 */ 00698 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23 */ 00699 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24 */ 00700 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25 */ 00701 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26 */ 00702 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27 */ 00703 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28 */ 00704 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29 */ 00705 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210 */ 00706 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 0x000000C1 /* ADISENSE_CORE Sensor Configuration Command2 */ 00707 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21 0x00000101 /* ADISENSE_CORE Sensor Configuration Command2 */ 00708 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22 0x00000141 /* ADISENSE_CORE Sensor Configuration Command2 */ 00709 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23 0x00000181 /* ADISENSE_CORE Sensor Configuration Command2 */ 00710 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24 0x000001C1 /* ADISENSE_CORE Sensor Configuration Command2 */ 00711 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25 0x00000201 /* ADISENSE_CORE Sensor Configuration Command2 */ 00712 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26 0x00000241 /* ADISENSE_CORE Sensor Configuration Command2 */ 00713 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27 0x00000281 /* ADISENSE_CORE Sensor Configuration Command2 */ 00714 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28 0x000002C1 /* ADISENSE_CORE Sensor Configuration Command2 */ 00715 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29 0x00000301 /* ADISENSE_CORE Sensor Configuration Command2 */ 00716 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210 0x00000341 /* ADISENSE_CORE Sensor Configuration Command2 */ 00717 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64)) 00718 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 11 00719 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */ 00720 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 */ 00721 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31 */ 00722 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32 */ 00723 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33 */ 00724 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34 */ 00725 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35 */ 00726 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36 */ 00727 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37 */ 00728 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38 */ 00729 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39 */ 00730 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310 */ 00731 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 0x000000C2 /* ADISENSE_CORE Sensor Configuration Command3 */ 00732 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31 0x00000102 /* ADISENSE_CORE Sensor Configuration Command3 */ 00733 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32 0x00000142 /* ADISENSE_CORE Sensor Configuration Command3 */ 00734 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33 0x00000182 /* ADISENSE_CORE Sensor Configuration Command3 */ 00735 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34 0x000001C2 /* ADISENSE_CORE Sensor Configuration Command3 */ 00736 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35 0x00000202 /* ADISENSE_CORE Sensor Configuration Command3 */ 00737 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36 0x00000242 /* ADISENSE_CORE Sensor Configuration Command3 */ 00738 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37 0x00000282 /* ADISENSE_CORE Sensor Configuration Command3 */ 00739 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38 0x000002C2 /* ADISENSE_CORE Sensor Configuration Command3 */ 00740 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39 0x00000302 /* ADISENSE_CORE Sensor Configuration Command3 */ 00741 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310 0x00000342 /* ADISENSE_CORE Sensor Configuration Command3 */ 00742 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64)) 00743 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 11 00744 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command4[n] */ 00745 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 */ 00746 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41 */ 00747 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42 */ 00748 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43 */ 00749 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44 */ 00750 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45 */ 00751 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46 */ 00752 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47 */ 00753 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48 */ 00754 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49 */ 00755 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410 */ 00756 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 0x000000C3 /* ADISENSE_CORE Sensor Configuration Command4 */ 00757 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41 0x00000103 /* ADISENSE_CORE Sensor Configuration Command4 */ 00758 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42 0x00000143 /* ADISENSE_CORE Sensor Configuration Command4 */ 00759 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43 0x00000183 /* ADISENSE_CORE Sensor Configuration Command4 */ 00760 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44 0x000001C3 /* ADISENSE_CORE Sensor Configuration Command4 */ 00761 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45 0x00000203 /* ADISENSE_CORE Sensor Configuration Command4 */ 00762 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46 0x00000243 /* ADISENSE_CORE Sensor Configuration Command4 */ 00763 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47 0x00000283 /* ADISENSE_CORE Sensor Configuration Command4 */ 00764 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48 0x000002C3 /* ADISENSE_CORE Sensor Configuration Command4 */ 00765 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49 0x00000303 /* ADISENSE_CORE Sensor Configuration Command4 */ 00766 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410 0x00000343 /* ADISENSE_CORE Sensor Configuration Command4 */ 00767 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 + ((i) * 64)) 00768 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n_COUNT 11 00769 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command5[n] */ 00770 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 */ 00771 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51 */ 00772 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52 */ 00773 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53 */ 00774 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54 */ 00775 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55 */ 00776 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56 */ 00777 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57 */ 00778 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58 */ 00779 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59 */ 00780 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510 */ 00781 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 0x000000C4 /* ADISENSE_CORE Sensor Configuration Command5 */ 00782 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51 0x00000104 /* ADISENSE_CORE Sensor Configuration Command5 */ 00783 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52 0x00000144 /* ADISENSE_CORE Sensor Configuration Command5 */ 00784 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53 0x00000184 /* ADISENSE_CORE Sensor Configuration Command5 */ 00785 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54 0x000001C4 /* ADISENSE_CORE Sensor Configuration Command5 */ 00786 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55 0x00000204 /* ADISENSE_CORE Sensor Configuration Command5 */ 00787 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56 0x00000244 /* ADISENSE_CORE Sensor Configuration Command5 */ 00788 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57 0x00000284 /* ADISENSE_CORE Sensor Configuration Command5 */ 00789 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58 0x000002C4 /* ADISENSE_CORE Sensor Configuration Command5 */ 00790 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59 0x00000304 /* ADISENSE_CORE Sensor Configuration Command5 */ 00791 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510 0x00000344 /* ADISENSE_CORE Sensor Configuration Command5 */ 00792 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 + ((i) * 64)) 00793 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n_COUNT 11 00794 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command6[n] */ 00795 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 */ 00796 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61 */ 00797 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62 */ 00798 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63 */ 00799 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64 */ 00800 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65 */ 00801 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66 */ 00802 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67 */ 00803 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68 */ 00804 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69 */ 00805 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610 */ 00806 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 0x000000C5 /* ADISENSE_CORE Sensor Configuration Command6 */ 00807 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61 0x00000105 /* ADISENSE_CORE Sensor Configuration Command6 */ 00808 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62 0x00000145 /* ADISENSE_CORE Sensor Configuration Command6 */ 00809 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63 0x00000185 /* ADISENSE_CORE Sensor Configuration Command6 */ 00810 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64 0x000001C5 /* ADISENSE_CORE Sensor Configuration Command6 */ 00811 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65 0x00000205 /* ADISENSE_CORE Sensor Configuration Command6 */ 00812 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66 0x00000245 /* ADISENSE_CORE Sensor Configuration Command6 */ 00813 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67 0x00000285 /* ADISENSE_CORE Sensor Configuration Command6 */ 00814 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68 0x000002C5 /* ADISENSE_CORE Sensor Configuration Command6 */ 00815 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69 0x00000305 /* ADISENSE_CORE Sensor Configuration Command6 */ 00816 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610 0x00000345 /* ADISENSE_CORE Sensor Configuration Command6 */ 00817 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 + ((i) * 64)) 00818 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n_COUNT 11 00819 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command7[n] */ 00820 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 */ 00821 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71 */ 00822 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72 */ 00823 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73 */ 00824 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74 */ 00825 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75 */ 00826 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76 */ 00827 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77 */ 00828 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78 */ 00829 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79 */ 00830 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710 */ 00831 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 0x000000C6 /* ADISENSE_CORE Sensor Configuration Command7 */ 00832 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71 0x00000106 /* ADISENSE_CORE Sensor Configuration Command7 */ 00833 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72 0x00000146 /* ADISENSE_CORE Sensor Configuration Command7 */ 00834 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73 0x00000186 /* ADISENSE_CORE Sensor Configuration Command7 */ 00835 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74 0x000001C6 /* ADISENSE_CORE Sensor Configuration Command7 */ 00836 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75 0x00000206 /* ADISENSE_CORE Sensor Configuration Command7 */ 00837 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76 0x00000246 /* ADISENSE_CORE Sensor Configuration Command7 */ 00838 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77 0x00000286 /* ADISENSE_CORE Sensor Configuration Command7 */ 00839 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78 0x000002C6 /* ADISENSE_CORE Sensor Configuration Command7 */ 00840 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79 0x00000306 /* ADISENSE_CORE Sensor Configuration Command7 */ 00841 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710 0x00000346 /* ADISENSE_CORE Sensor Configuration Command7 */ 00842 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 + ((i) * 64)) 00843 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n_COUNT 11 00844 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd1[n] */ 00845 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 */ 00846 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11 */ 00847 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12 */ 00848 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13 */ 00849 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14 */ 00850 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15 */ 00851 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16 */ 00852 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17 */ 00853 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18 */ 00854 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19 */ 00855 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110 */ 00856 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 0x000000C8 /* ADISENSE_CORE Sensor Read Command1 */ 00857 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11 0x00000108 /* ADISENSE_CORE Sensor Read Command1 */ 00858 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12 0x00000148 /* ADISENSE_CORE Sensor Read Command1 */ 00859 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13 0x00000188 /* ADISENSE_CORE Sensor Read Command1 */ 00860 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14 0x000001C8 /* ADISENSE_CORE Sensor Read Command1 */ 00861 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15 0x00000208 /* ADISENSE_CORE Sensor Read Command1 */ 00862 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16 0x00000248 /* ADISENSE_CORE Sensor Read Command1 */ 00863 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17 0x00000288 /* ADISENSE_CORE Sensor Read Command1 */ 00864 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18 0x000002C8 /* ADISENSE_CORE Sensor Read Command1 */ 00865 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19 0x00000308 /* ADISENSE_CORE Sensor Read Command1 */ 00866 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110 0x00000348 /* ADISENSE_CORE Sensor Read Command1 */ 00867 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 + ((i) * 64)) 00868 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n_COUNT 11 00869 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd2[n] */ 00870 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 */ 00871 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21 */ 00872 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22 */ 00873 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23 */ 00874 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24 */ 00875 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25 */ 00876 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26 */ 00877 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27 */ 00878 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28 */ 00879 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29 */ 00880 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210 */ 00881 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 0x000000C9 /* ADISENSE_CORE Sensor Read Command2 */ 00882 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21 0x00000109 /* ADISENSE_CORE Sensor Read Command2 */ 00883 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22 0x00000149 /* ADISENSE_CORE Sensor Read Command2 */ 00884 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23 0x00000189 /* ADISENSE_CORE Sensor Read Command2 */ 00885 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24 0x000001C9 /* ADISENSE_CORE Sensor Read Command2 */ 00886 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25 0x00000209 /* ADISENSE_CORE Sensor Read Command2 */ 00887 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26 0x00000249 /* ADISENSE_CORE Sensor Read Command2 */ 00888 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27 0x00000289 /* ADISENSE_CORE Sensor Read Command2 */ 00889 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28 0x000002C9 /* ADISENSE_CORE Sensor Read Command2 */ 00890 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29 0x00000309 /* ADISENSE_CORE Sensor Read Command2 */ 00891 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210 0x00000349 /* ADISENSE_CORE Sensor Read Command2 */ 00892 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 + ((i) * 64)) 00893 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n_COUNT 11 00894 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd3[n] */ 00895 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 */ 00896 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31 */ 00897 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32 */ 00898 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33 */ 00899 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34 */ 00900 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35 */ 00901 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36 */ 00902 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37 */ 00903 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38 */ 00904 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39 */ 00905 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310 */ 00906 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 0x000000CA /* ADISENSE_CORE Sensor Read Command3 */ 00907 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31 0x0000010A /* ADISENSE_CORE Sensor Read Command3 */ 00908 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32 0x0000014A /* ADISENSE_CORE Sensor Read Command3 */ 00909 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33 0x0000018A /* ADISENSE_CORE Sensor Read Command3 */ 00910 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34 0x000001CA /* ADISENSE_CORE Sensor Read Command3 */ 00911 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35 0x0000020A /* ADISENSE_CORE Sensor Read Command3 */ 00912 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36 0x0000024A /* ADISENSE_CORE Sensor Read Command3 */ 00913 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37 0x0000028A /* ADISENSE_CORE Sensor Read Command3 */ 00914 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38 0x000002CA /* ADISENSE_CORE Sensor Read Command3 */ 00915 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39 0x0000030A /* ADISENSE_CORE Sensor Read Command3 */ 00916 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310 0x0000034A /* ADISENSE_CORE Sensor Read Command3 */ 00917 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 + ((i) * 64)) 00918 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n_COUNT 11 00919 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd4[n] */ 00920 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 */ 00921 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41 */ 00922 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42 */ 00923 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43 */ 00924 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44 */ 00925 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45 */ 00926 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46 */ 00927 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47 */ 00928 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48 */ 00929 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49 */ 00930 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410 */ 00931 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 0x000000CB /* ADISENSE_CORE Sensor Read Command4 */ 00932 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41 0x0000010B /* ADISENSE_CORE Sensor Read Command4 */ 00933 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42 0x0000014B /* ADISENSE_CORE Sensor Read Command4 */ 00934 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43 0x0000018B /* ADISENSE_CORE Sensor Read Command4 */ 00935 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44 0x000001CB /* ADISENSE_CORE Sensor Read Command4 */ 00936 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45 0x0000020B /* ADISENSE_CORE Sensor Read Command4 */ 00937 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46 0x0000024B /* ADISENSE_CORE Sensor Read Command4 */ 00938 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47 0x0000028B /* ADISENSE_CORE Sensor Read Command4 */ 00939 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48 0x000002CB /* ADISENSE_CORE Sensor Read Command4 */ 00940 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49 0x0000030B /* ADISENSE_CORE Sensor Read Command4 */ 00941 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410 0x0000034B /* ADISENSE_CORE Sensor Read Command4 */ 00942 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 + ((i) * 64)) 00943 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n_COUNT 11 00944 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd5[n] */ 00945 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 */ 00946 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51 */ 00947 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52 */ 00948 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53 */ 00949 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54 */ 00950 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55 */ 00951 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56 */ 00952 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57 */ 00953 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58 */ 00954 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59 */ 00955 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510 */ 00956 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 0x000000CC /* ADISENSE_CORE Sensor Read Command5 */ 00957 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51 0x0000010C /* ADISENSE_CORE Sensor Read Command5 */ 00958 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52 0x0000014C /* ADISENSE_CORE Sensor Read Command5 */ 00959 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53 0x0000018C /* ADISENSE_CORE Sensor Read Command5 */ 00960 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54 0x000001CC /* ADISENSE_CORE Sensor Read Command5 */ 00961 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55 0x0000020C /* ADISENSE_CORE Sensor Read Command5 */ 00962 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56 0x0000024C /* ADISENSE_CORE Sensor Read Command5 */ 00963 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57 0x0000028C /* ADISENSE_CORE Sensor Read Command5 */ 00964 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58 0x000002CC /* ADISENSE_CORE Sensor Read Command5 */ 00965 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59 0x0000030C /* ADISENSE_CORE Sensor Read Command5 */ 00966 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510 0x0000034C /* ADISENSE_CORE Sensor Read Command5 */ 00967 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 + ((i) * 64)) 00968 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n_COUNT 11 00969 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd6[n] */ 00970 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 */ 00971 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61 */ 00972 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62 */ 00973 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63 */ 00974 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64 */ 00975 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65 */ 00976 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66 */ 00977 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67 */ 00978 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68 */ 00979 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69 */ 00980 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610 */ 00981 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 0x000000CD /* ADISENSE_CORE Sensor Read Command6 */ 00982 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61 0x0000010D /* ADISENSE_CORE Sensor Read Command6 */ 00983 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62 0x0000014D /* ADISENSE_CORE Sensor Read Command6 */ 00984 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63 0x0000018D /* ADISENSE_CORE Sensor Read Command6 */ 00985 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64 0x000001CD /* ADISENSE_CORE Sensor Read Command6 */ 00986 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65 0x0000020D /* ADISENSE_CORE Sensor Read Command6 */ 00987 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66 0x0000024D /* ADISENSE_CORE Sensor Read Command6 */ 00988 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67 0x0000028D /* ADISENSE_CORE Sensor Read Command6 */ 00989 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68 0x000002CD /* ADISENSE_CORE Sensor Read Command6 */ 00990 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69 0x0000030D /* ADISENSE_CORE Sensor Read Command6 */ 00991 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610 0x0000034D /* ADISENSE_CORE Sensor Read Command6 */ 00992 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 + ((i) * 64)) 00993 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n_COUNT 11 00994 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd7[n] */ 00995 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 */ 00996 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71 */ 00997 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72 */ 00998 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73 */ 00999 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74 */ 01000 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75 */ 01001 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76 */ 01002 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77 */ 01003 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78 */ 01004 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79 */ 01005 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710 */ 01006 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 0x000000CE /* ADISENSE_CORE Sensor Read Command7 */ 01007 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71 0x0000010E /* ADISENSE_CORE Sensor Read Command7 */ 01008 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72 0x0000014E /* ADISENSE_CORE Sensor Read Command7 */ 01009 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73 0x0000018E /* ADISENSE_CORE Sensor Read Command7 */ 01010 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74 0x000001CE /* ADISENSE_CORE Sensor Read Command7 */ 01011 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75 0x0000020E /* ADISENSE_CORE Sensor Read Command7 */ 01012 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76 0x0000024E /* ADISENSE_CORE Sensor Read Command7 */ 01013 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77 0x0000028E /* ADISENSE_CORE Sensor Read Command7 */ 01014 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78 0x000002CE /* ADISENSE_CORE Sensor Read Command7 */ 01015 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79 0x0000030E /* ADISENSE_CORE Sensor Read Command7 */ 01016 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710 0x0000034E /* ADISENSE_CORE Sensor Read Command7 */ 01017 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 + ((i) * 64)) 01018 #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n_COUNT 11 01019 01020 /* ============================================================================================================================ 01021 ADISENSE_CORE Register BitMasks, Positions & Enumerations 01022 ============================================================================================================================ */ 01023 /* ------------------------------------------------------------------------------------------------------------------------- 01024 ADISENSE_CORE_COMMAND Pos/Masks Description 01025 ------------------------------------------------------------------------------------------------------------------------- */ 01026 #define BITP_ADISENSE_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */ 01027 #define BITM_ADISENSE_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */ 01028 #define ENUM_ADISENSE_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */ 01029 #define ENUM_ADISENSE_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */ 01030 #define ENUM_ADISENSE_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */ 01031 #define ENUM_ADISENSE_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */ 01032 #define ENUM_ADISENSE_CORE_COMMAND_SELF_CALIBRATION 0x00000004 /* Special_Command: Initiate a Self-Calibration Cycle */ 01033 #define ENUM_ADISENSE_CORE_COMMAND_LOAD_CONFIG 0x00000005 /* Special_Command: Load Registers with Configuration from FLASH */ 01034 #define ENUM_ADISENSE_CORE_COMMAND_SAVE_CONFIG 0x00000006 /* Special_Command: Store Current Register Configuration to FLASH */ 01035 #define ENUM_ADISENSE_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch Configuration. */ 01036 #define ENUM_ADISENSE_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */ 01037 #define ENUM_ADISENSE_CORE_COMMAND_SAVE_LUT2 0x00000009 /* Special_Command: Save LUT to FLASH */ 01038 #define ENUM_ADISENSE_CORE_COMMAND_SYSTEM_CHECK 0x0000000A /* Special_Command: Full Suite of Measurement Diagnostics */ 01039 01040 /* ------------------------------------------------------------------------------------------------------------------------- 01041 ADISENSE_CORE_MODE Pos/Masks Description 01042 ------------------------------------------------------------------------------------------------------------------------- */ 01043 #define BITP_ADISENSE_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */ 01044 #define BITP_ADISENSE_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */ 01045 #define BITM_ADISENSE_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */ 01046 #define BITM_ADISENSE_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */ 01047 #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */ 01048 #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */ 01049 #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill */ 01050 #define ENUM_ADISENSE_CORE_MODE_DRDY_MODE3 0x0000000C /* Drdy_Mode: Undefined */ 01051 #define ENUM_ADISENSE_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */ 01052 #define ENUM_ADISENSE_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */ 01053 #define ENUM_ADISENSE_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */ 01054 #define ENUM_ADISENSE_CORE_MODE_MODE3 0x00000003 /* Conversion_Mode: Undefined */ 01055 01056 /* ------------------------------------------------------------------------------------------------------------------------- 01057 ADISENSE_CORE_POWER_CONFIG Pos/Masks Description 01058 ------------------------------------------------------------------------------------------------------------------------- */ 01059 #define BITP_ADISENSE_CORE_POWER_CONFIG_STDBY_EN 4 /* Standby */ 01060 #define BITP_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_MCU 2 /* MCU Power Mode */ 01061 #define BITP_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */ 01062 #define BITM_ADISENSE_CORE_POWER_CONFIG_STDBY_EN 0x00000010 /* Standby */ 01063 #define BITM_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_MCU 0x0000000C /* MCU Power Mode */ 01064 #define BITM_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */ 01065 #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_LOW_POWER 0x00000000 /* Power_Mode_ADC: ADC Low Power Mode */ 01066 #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_MID_POWER 0x00000001 /* Power_Mode_ADC: ADC Mid Power Mode */ 01067 #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER 0x00000002 /* Power_Mode_ADC: ADC Full Power Mode */ 01068 #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER2 0x00000003 /* Power_Mode_ADC: ADC Full Power Mode2 */ 01069 01070 /* ------------------------------------------------------------------------------------------------------------------------- 01071 ADISENSE_CORE_CYCLE_CONTROL Pos/Masks Description 01072 ------------------------------------------------------------------------------------------------------------------------- */ 01073 #define BITP_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */ 01074 #define BITP_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */ 01075 #define BITM_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */ 01076 #define BITM_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */ 01077 #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */ 01078 #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */ 01079 #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */ 01080 #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_UNDEFINED 0x0000C000 /* Cycle_Time_Units: Undefined */ 01081 01082 /* ------------------------------------------------------------------------------------------------------------------------- 01083 ADISENSE_CORE_FIFO_NUM_CYCLES Pos/Masks Description 01084 ------------------------------------------------------------------------------------------------------------------------- */ 01085 #define BITP_ADISENSE_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */ 01086 #define BITM_ADISENSE_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */ 01087 01088 /* ------------------------------------------------------------------------------------------------------------------------- 01089 ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL Pos/Masks Description 01090 ------------------------------------------------------------------------------------------------------------------------- */ 01091 #define BITP_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0 /* Defines Time Between Repetitions of Measurement Cycles. */ 01092 #define BITM_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0x00FFFFFF /* Defines Time Between Repetitions of Measurement Cycles. */ 01093 01094 /* ------------------------------------------------------------------------------------------------------------------------- 01095 ADISENSE_CORE_STATUS Pos/Masks Description 01096 ------------------------------------------------------------------------------------------------------------------------- */ 01097 #define BITP_ADISENSE_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */ 01098 #define BITP_ADISENSE_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */ 01099 #define BITP_ADISENSE_CORE_STATUS_DRDY 3 /* Indicates a New Sensor Result is Available to Be Read */ 01100 #define BITP_ADISENSE_CORE_STATUS_ERROR 2 /* Indicates an Error */ 01101 #define BITP_ADISENSE_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensors Alerts are Active */ 01102 #define BITM_ADISENSE_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */ 01103 #define BITM_ADISENSE_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */ 01104 #define BITM_ADISENSE_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor Result is Available to Be Read */ 01105 #define BITM_ADISENSE_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */ 01106 #define BITM_ADISENSE_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensors Alerts are Active */ 01107 01108 /* ------------------------------------------------------------------------------------------------------------------------- 01109 ADISENSE_CORE_DIAGNOSTICS_STATUS Pos/Masks Description 01110 ------------------------------------------------------------------------------------------------------------------------- */ 01111 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS_SUNDRY 14 /* Sundry Diagnostics Status */ 01112 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 13 /* Indicates Error During Internal Device Calibrations */ 01113 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 12 /* Indicates Error During Internal ADC Conversions */ 01114 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 11 /* Indicates Over-Voltage Error on Positive Analog Input */ 01115 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 10 /* Indicates Under-Voltage Error on Positive Analog Input */ 01116 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 9 /* Indicates Over-Voltage Error on Negative Analog Input */ 01117 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 8 /* Indicates Under-Voltage Error on Negative Analog Input */ 01118 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 3 /* Indicates Fault on Internal Supply Regulator Capacitor */ 01119 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 2 /* Indicates Low Voltage on Internal Supply Voltages */ 01120 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 1 /* Indicates Error on Internal Device Communications */ 01121 #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0 /* Indicates Error on Internal Checksum Calculations */ 01122 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS_SUNDRY 0x0000C000 /* Sundry Diagnostics Status */ 01123 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 0x00002000 /* Indicates Error During Internal Device Calibrations */ 01124 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 0x00001000 /* Indicates Error During Internal ADC Conversions */ 01125 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 0x00000800 /* Indicates Over-Voltage Error on Positive Analog Input */ 01126 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 0x00000400 /* Indicates Under-Voltage Error on Positive Analog Input */ 01127 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 0x00000200 /* Indicates Over-Voltage Error on Negative Analog Input */ 01128 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 0x00000100 /* Indicates Under-Voltage Error on Negative Analog Input */ 01129 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 0x00000008 /* Indicates Fault on Internal Supply Regulator Capacitor */ 01130 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 0x00000004 /* Indicates Low Voltage on Internal Supply Voltages */ 01131 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 0x00000002 /* Indicates Error on Internal Device Communications */ 01132 #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0x00000001 /* Indicates Error on Internal Checksum Calculations */ 01133 01134 /* ------------------------------------------------------------------------------------------------------------------------- 01135 ADISENSE_CORE_CHANNEL_ALERT_STATUS Pos/Masks Description 01136 ------------------------------------------------------------------------------------------------------------------------- */ 01137 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel Alert is Active */ 01138 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel Alert is Active */ 01139 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel Alert is Active */ 01140 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel Alert is Active */ 01141 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel Alert is Active */ 01142 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel Alert is Active */ 01143 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel Alert is Active */ 01144 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel Alert is Active */ 01145 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel Alert is Active */ 01146 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel Alert is Active */ 01147 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel Alert is Active */ 01148 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel Alert is Active */ 01149 #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel Alert is Active */ 01150 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel Alert is Active */ 01151 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel Alert is Active */ 01152 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel Alert is Active */ 01153 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel Alert is Active */ 01154 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel Alert is Active */ 01155 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel Alert is Active */ 01156 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel Alert is Active */ 01157 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel Alert is Active */ 01158 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel Alert is Active */ 01159 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel Alert is Active */ 01160 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel Alert is Active */ 01161 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel Alert is Active */ 01162 #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel Alert is Active */ 01163 01164 /* ------------------------------------------------------------------------------------------------------------------------- 01165 ADISENSE_CORE_ALERT_STATUS_2 Pos/Masks Description 01166 ------------------------------------------------------------------------------------------------------------------------- */ 01167 #define BITP_ADISENSE_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 2 /* Indicates Error with Programmed Configuration */ 01168 #define BITP_ADISENSE_CORE_ALERT_STATUS_2_LUT_ERROR 1 /* Indicates Error with One or More Look-Up-Tables */ 01169 #define BITM_ADISENSE_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 0x00000004 /* Indicates Error with Programmed Configuration */ 01170 #define BITM_ADISENSE_CORE_ALERT_STATUS_2_LUT_ERROR 0x00000002 /* Indicates Error with One or More Look-Up-Tables */ 01171 01172 /* ------------------------------------------------------------------------------------------------------------------------- 01173 ADISENSE_CORE_ALERT_DETAIL_CH[n] Pos/Masks Description 01174 ------------------------------------------------------------------------------------------------------------------------- */ 01175 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 15 /* Indicates Compensation Channel Not Ready When Required */ 01176 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 14 /* Indicates Digital Sensor Not Ready When Read */ 01177 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 13 /* Indicates Result Larger Than LUT/Equation Range */ 01178 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 12 /* Indicates Result Less Than LUT/Equation Range */ 01179 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 11 /* Indicates Channel Over-Voltage */ 01180 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 10 /* Indicates Channel Under-Voltage */ 01181 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 9 /* Indicates Error with Channel Look-Up-Table */ 01182 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CONFIG_ERR 8 /* Indicates Configuration Error on Channel */ 01183 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */ 01184 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */ 01185 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */ 01186 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */ 01187 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */ 01188 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */ 01189 #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */ 01190 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 0x00008000 /* Indicates Compensation Channel Not Ready When Required */ 01191 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 0x00004000 /* Indicates Digital Sensor Not Ready When Read */ 01192 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 0x00002000 /* Indicates Result Larger Than LUT/Equation Range */ 01193 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 0x00001000 /* Indicates Result Less Than LUT/Equation Range */ 01194 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 0x00000800 /* Indicates Channel Over-Voltage */ 01195 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 0x00000400 /* Indicates Channel Under-Voltage */ 01196 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 0x00000200 /* Indicates Error with Channel Look-Up-Table */ 01197 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CONFIG_ERR 0x00000100 /* Indicates Configuration Error on Channel */ 01198 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */ 01199 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */ 01200 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */ 01201 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */ 01202 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */ 01203 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */ 01204 #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */ 01205 01206 /* ------------------------------------------------------------------------------------------------------------------------- 01207 ADISENSE_CORE_ERROR_CODE Pos/Masks Description 01208 ------------------------------------------------------------------------------------------------------------------------- */ 01209 #define BITP_ADISENSE_CORE_ERROR_CODE_ERROR_CODE 0 /* Code Indicating Type of Error */ 01210 #define BITM_ADISENSE_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */ 01211 01212 /* ------------------------------------------------------------------------------------------------------------------------- 01213 ADISENSE_CORE_ALERT_CODE Pos/Masks Description 01214 ------------------------------------------------------------------------------------------------------------------------- */ 01215 #define BITP_ADISENSE_CORE_ALERT_CODE_ALERT_CODE 0 /* Code Indicating Type of Alert */ 01216 #define BITM_ADISENSE_CORE_ALERT_CODE_ALERT_CODE 0x0000FFFF /* Code Indicating Type of Alert */ 01217 01218 /* ------------------------------------------------------------------------------------------------------------------------- 01219 ADISENSE_CORE_EXTERNAL_REFERENCE1 Pos/Masks Description 01220 ------------------------------------------------------------------------------------------------------------------------- */ 01221 #define BITP_ADISENSE_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */ 01222 #define BITM_ADISENSE_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */ 01223 01224 /* ------------------------------------------------------------------------------------------------------------------------- 01225 ADISENSE_CORE_EXTERNAL_REFERENCE2 Pos/Masks Description 01226 ------------------------------------------------------------------------------------------------------------------------- */ 01227 #define BITP_ADISENSE_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */ 01228 #define BITM_ADISENSE_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */ 01229 01230 /* ------------------------------------------------------------------------------------------------------------------------- 01231 ADISENSE_CORE_AVDD_VOLTAGE Pos/Masks Description 01232 ------------------------------------------------------------------------------------------------------------------------- */ 01233 #define BITP_ADISENSE_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0 /* AVDD Voltage */ 01234 #define BITM_ADISENSE_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0xFFFFFFFF /* AVDD Voltage */ 01235 01236 /* ------------------------------------------------------------------------------------------------------------------------- 01237 ADISENSE_CORE_DIAGNOSTICS_CONTROL Pos/Masks Description 01238 ------------------------------------------------------------------------------------------------------------------------- */ 01239 #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAGNOSTICS_EXTRA 8 /* Additional Diagnostics Control */ 01240 #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 2 /* Diagnostics Open Sensor Detect Frequency */ 01241 #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */ 01242 #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */ 01243 #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAGNOSTICS_EXTRA 0x0000FF00 /* Additional Diagnostics Control */ 01244 #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x0000000C /* Diagnostics Open Sensor Detect Frequency */ 01245 #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */ 01246 #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */ 01247 #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_OFF 0x00000000 /* Diag_OSD_Freq: No Open-Circuit Detection During Measurement */ 01248 #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */ 01249 #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000008 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */ 01250 #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES 0x0000000C /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */ 01251 01252 /* ------------------------------------------------------------------------------------------------------------------------- 01253 ADISENSE_CORE_DATA_FIFO Pos/Masks Description 01254 ------------------------------------------------------------------------------------------------------------------------- */ 01255 #define BITP_ADISENSE_CORE_DATA_FIFO_RAW_SAMPLE 40 /* ADC Result */ 01256 #define BITP_ADISENSE_CORE_DATA_FIFO_CH_VALID 39 /* Indicates Whether Valid Data Read from FIFO */ 01257 #define BITP_ADISENSE_CORE_DATA_FIFO_CH_RAW 38 /* Indicates If RAW Data is Valid */ 01258 #define BITP_ADISENSE_CORE_DATA_FIFO_CH_ALERT 37 /* Indicates Alert on Channel */ 01259 #define BITP_ADISENSE_CORE_DATA_FIFO_CH_ERROR 36 /* Indicates Error on Channel */ 01260 #define BITP_ADISENSE_CORE_DATA_FIFO_CHANNEL_ID 32 /* Indicates Which Channel This FIFO Data Corresponds to */ 01261 #define BITP_ADISENSE_CORE_DATA_FIFO_SENSOR_RESULT 0 /* Linearized and Compensated Sensor Result */ 01262 #define BITM_ADISENSE_CORE_DATA_FIFO_RAW_SAMPLE 0xFFFFFF0000000000 /* ADC Result */ 01263 #define BITM_ADISENSE_CORE_DATA_FIFO_CH_VALID 0x8000000000 /* Indicates Whether Valid Data Read from FIFO */ 01264 #define BITM_ADISENSE_CORE_DATA_FIFO_CH_RAW 0x4000000000 /* Indicates If RAW Data is Valid */ 01265 #define BITM_ADISENSE_CORE_DATA_FIFO_CH_ALERT 0x2000000000 /* Indicates Alert on Channel */ 01266 #define BITM_ADISENSE_CORE_DATA_FIFO_CH_ERROR 0x1000000000 /* Indicates Error on Channel */ 01267 #define BITM_ADISENSE_CORE_DATA_FIFO_CHANNEL_ID 0xF00000000 /* Indicates Which Channel This FIFO Data Corresponds to */ 01268 #define BITM_ADISENSE_CORE_DATA_FIFO_SENSOR_RESULT 0xFFFFFFFF /* Linearized and Compensated Sensor Result */ 01269 01270 /* ------------------------------------------------------------------------------------------------------------------------- 01271 ADISENSE_CORE_LUT_SELECT Pos/Masks Description 01272 ------------------------------------------------------------------------------------------------------------------------- */ 01273 #define BITP_ADISENSE_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */ 01274 #define BITM_ADISENSE_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */ 01275 #define ENUM_ADISENSE_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read Addressed LUT Data */ 01276 #define ENUM_ADISENSE_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write Addressed LUT Data */ 01277 01278 /* ------------------------------------------------------------------------------------------------------------------------- 01279 ADISENSE_CORE_LUT_OFFSET Pos/Masks Description 01280 ------------------------------------------------------------------------------------------------------------------------- */ 01281 #define BITP_ADISENSE_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */ 01282 #define BITM_ADISENSE_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */ 01283 01284 /* ------------------------------------------------------------------------------------------------------------------------- 01285 ADISENSE_CORE_LUT_DATA Pos/Masks Description 01286 ------------------------------------------------------------------------------------------------------------------------- */ 01287 #define BITP_ADISENSE_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */ 01288 #define BITM_ADISENSE_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */ 01289 01290 /* ------------------------------------------------------------------------------------------------------------------------- 01291 ADISENSE_CORE_CAL_OFFSET Pos/Masks Description 01292 ------------------------------------------------------------------------------------------------------------------------- */ 01293 #define BITP_ADISENSE_CORE_CAL_OFFSET_CAL_OFFSET 0 /* Offset into Calibration Data */ 01294 #define BITM_ADISENSE_CORE_CAL_OFFSET_CAL_OFFSET 0x00003FFF /* Offset into Calibration Data */ 01295 01296 /* ------------------------------------------------------------------------------------------------------------------------- 01297 ADISENSE_CORE_CAL_DATA Pos/Masks Description 01298 ------------------------------------------------------------------------------------------------------------------------- */ 01299 #define BITP_ADISENSE_CORE_CAL_DATA_CAL_DATA 0 /* Data to Write to / Read from Calibration Data */ 01300 #define BITM_ADISENSE_CORE_CAL_DATA_CAL_DATA 0x000000FF /* Data to Write to / Read from Calibration Data */ 01301 01302 /* ------------------------------------------------------------------------------------------------------------------------- 01303 ADISENSE_CORE_REVISION Pos/Masks Description 01304 ------------------------------------------------------------------------------------------------------------------------- */ 01305 #define BITP_ADISENSE_CORE_REVISION_COMMS_PROTOCOL 16 /* ID Info */ 01306 #define BITP_ADISENSE_CORE_REVISION_HARDWARE_REVISION 8 /* ID Info */ 01307 #define BITP_ADISENSE_CORE_REVISION_FIRMWARE_REVISION 0 /* ID Info */ 01308 #define BITM_ADISENSE_CORE_REVISION_COMMS_PROTOCOL 0x00FF0000 /* ID Info */ 01309 #define BITM_ADISENSE_CORE_REVISION_HARDWARE_REVISION 0x0000FF00 /* ID Info */ 01310 #define BITM_ADISENSE_CORE_REVISION_FIRMWARE_REVISION 0x000000FF /* ID Info */ 01311 01312 /* ------------------------------------------------------------------------------------------------------------------------- 01313 ADISENSE_CORE_CHANNEL_COUNT[n] Pos/Masks Description 01314 ------------------------------------------------------------------------------------------------------------------------- */ 01315 #define BITP_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */ 01316 #define BITP_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */ 01317 #define BITM_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */ 01318 #define BITM_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */ 01319 01320 /* ------------------------------------------------------------------------------------------------------------------------- 01321 ADISENSE_CORE_SENSOR_TYPE[n] Pos/Masks Description 01322 ------------------------------------------------------------------------------------------------------------------------- */ 01323 #define BITP_ADISENSE_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */ 01324 #define BITM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */ 01325 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_DEF_L1 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor Defined Level 1 */ 01326 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_DEF_L1 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor Defined Level 1 */ 01327 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_DEF_L1 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor Defined Level 1 */ 01328 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_DEF_L2 0x0000000C /* Sensor_Type: Thermocouple Sensor 1 Defined Level 2 */ 01329 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_DEF_L2 0x0000000D /* Sensor_Type: Thermocouple Sensor 2 Defined Level 2 */ 01330 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_DEF_L2 0x0000000E /* Sensor_Type: Thermocouple Sensor 3 Defined Level 2 */ 01331 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_DEF_L2 0x0000000F /* Sensor_Type: Thermocouple Sensor 4 Defined Level 2 */ 01332 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_ADV_L1 0x00000010 /* Sensor_Type: Thermocouple T-Type Sensor Advanced Level 1 */ 01333 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_ADV_L1 0x00000011 /* Sensor_Type: Thermocouple J-Type Sensor Advanced Level 1 */ 01334 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_ADV_L1 0x00000012 /* Sensor_Type: Thermocouple K-Type Sensor Advanced Level 1 */ 01335 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_ADV_L2 0x0000001C /* Sensor_Type: Thermocouple Sensor 1 Advanced Level 2 */ 01336 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_ADV_L2 0x0000001D /* Sensor_Type: Thermocouple Sensor 2 Advanced Level 2 */ 01337 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_ADV_L2 0x0000001E /* Sensor_Type: Thermocouple Sensor 3 Advanced Level 2 */ 01338 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_ADV_L2 0x0000001F /* Sensor_Type: Thermocouple Sensor 4 Advanced Level 2 */ 01339 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_DEF_L1 0x00000020 /* Sensor_Type: RTD 2 Wire PT100 Sensor Defined Level 1 */ 01340 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_DEF_L1 0x00000021 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Defined Level 1 */ 01341 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_DEF_L2 0x0000002C /* Sensor_Type: RTD 2 Wire Sensor 1 Defined Level 2 */ 01342 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_DEF_L2 0x0000002D /* Sensor_Type: RTD 2 Wire Sensor 2 Defined Level 2 */ 01343 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_DEF_L2 0x0000002E /* Sensor_Type: RTD 2 Wire Sensor 3 Defined Level 2 */ 01344 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_DEF_L2 0x0000002F /* Sensor_Type: RTD 2 Wire Sensor 4 Defined Level 2 */ 01345 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_ADV_L1 0x00000030 /* Sensor_Type: RTD 2 Wire PT100 Sensor Advanced Level 1 */ 01346 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_ADV_L1 0x00000031 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Advanced Level 1 */ 01347 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_ADV_L2 0x0000003C /* Sensor_Type: RTD 2 Wire Sensor 1 Advanced Level 2 */ 01348 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_ADV_L2 0x0000003D /* Sensor_Type: RTD 2 Wire Sensor 2 Advanced Level 2 */ 01349 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_ADV_L2 0x0000003E /* Sensor_Type: RTD 2 Wire Sensor 3 Advanced Level 2 */ 01350 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_ADV_L2 0x0000003F /* Sensor_Type: RTD 2 Wire Sensor 4 Advanced Level 2 */ 01351 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_DEF_L1 0x00000040 /* Sensor_Type: RTD 3 Wire PT100 Sensor Defined Level 1 */ 01352 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_DEF_L1 0x00000041 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Defined Level 1 */ 01353 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_DEF_L2 0x0000004C /* Sensor_Type: RTD 3 Wire Sensor 1 Defined Level 2 */ 01354 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_DEF_L2 0x0000004D /* Sensor_Type: RTD 3 Wire Sensor 2 Defined Level 2 */ 01355 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_DEF_L2 0x0000004E /* Sensor_Type: RTD 3 Wire Sensor 3 Defined Level 2 */ 01356 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_DEF_L2 0x0000004F /* Sensor_Type: RTD 3 Wire Sensor 4 Defined Level 2 */ 01357 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ADV_L1 0x00000050 /* Sensor_Type: RTD 3 Wire PT100 Sensor Advanced Level 1 */ 01358 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ADV_L1 0x00000051 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Advanced Level 1 */ 01359 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_ADV_L2 0x0000005C /* Sensor_Type: RTD 3 Wire Sensor 1 Advanced Level 2 */ 01360 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_ADV_L2 0x0000005D /* Sensor_Type: RTD 3 Wire Sensor 2 Advanced Level 2 */ 01361 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_ADV_L2 0x0000005E /* Sensor_Type: RTD 3 Wire Sensor 3 Advanced Level 2 */ 01362 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_ADV_L2 0x0000005F /* Sensor_Type: RTD 3 Wire Sensor 4 Advanced Level 2 */ 01363 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_DEF_L1 0x00000060 /* Sensor_Type: RTD 4 Wire PT100 Sensor Defined Level 1 */ 01364 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_DEF_L1 0x00000061 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Defined Level 1 */ 01365 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_DEF_L2 0x0000006C /* Sensor_Type: RTD 4 Wire Sensor 1 Defined Level 2 */ 01366 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_DEF_L2 0x0000006D /* Sensor_Type: RTD 4 Wire Sensor 2 Defined Level 2 */ 01367 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_DEF_L2 0x0000006E /* Sensor_Type: RTD 4 Wire Sensor 3 Defined Level 2 */ 01368 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_DEF_L2 0x0000006F /* Sensor_Type: RTD 4 Wire Sensor 4 Defined Level 2 */ 01369 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_ADV_L1 0x00000070 /* Sensor_Type: RTD 4 Wire PT100 Sensor Advanced Level 1 */ 01370 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_ADV_L1 0x00000071 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Advanced Level 1 */ 01371 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_ADV_L2 0x0000007C /* Sensor_Type: RTD 4 Wire Sensor 1 Advanced Level 2 */ 01372 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_ADV_L2 0x0000007D /* Sensor_Type: RTD 4 Wire Sensor 2 Advanced Level 2 */ 01373 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_ADV_L2 0x0000007E /* Sensor_Type: RTD 4 Wire Sensor 3 Advanced Level 2 */ 01374 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_ADV_L2 0x0000007F /* Sensor_Type: RTD 4 Wire Sensor 4 Advanced Level 2 */ 01375 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_DEF_L1 0x00000080 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Defined Level 1 */ 01376 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_DEF_L1 0x00000081 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Defined Level 1 */ 01377 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_DEF_L2 0x0000008C /* Sensor_Type: Thermistor Sensor 1 Defined Level 2 */ 01378 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_DEF_L2 0x0000008D /* Sensor_Type: Thermistor Sensor 2 Defined Level 2 */ 01379 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_DEF_L2 0x0000008E /* Sensor_Type: Thermistor Sensor 3 Defined Level 2 */ 01380 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_DEF_L2 0x0000008F /* Sensor_Type: Thermistor Sensor 4 Defined Level 2 */ 01381 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_ADV_L1 0x00000090 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Advanced Level 1 */ 01382 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_ADV_L1 0x00000091 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Advanced Level 1 */ 01383 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_ADV_L2 0x0000009C /* Sensor_Type: Thermistor Sensor 1 Advanced Level 2 */ 01384 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_ADV_L2 0x0000009D /* Sensor_Type: Thermistor Sensor 2 Advanced Level 2 */ 01385 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_ADV_L2 0x0000009E /* Sensor_Type: Thermistor Sensor 3 Advanced Level 2 */ 01386 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_ADV_L2 0x0000009F /* Sensor_Type: Thermistor Sensor 4 Advanced Level 2 */ 01387 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_DEF_L2 0x000000A0 /* Sensor_Type: Bridge 4 Wire Sensor 1 Defined Level 2 */ 01388 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_DEF_L2 0x000000A1 /* Sensor_Type: Bridge 4 Wire Sensor 2 Defined Level 2 */ 01389 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_DEF_L2 0x000000A2 /* Sensor_Type: Bridge 4 Wire Sensor 3 Defined Level 2 */ 01390 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_DEF_L2 0x000000A3 /* Sensor_Type: Bridge 4 Wire Sensor 4 Defined Level 2 */ 01391 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_ADV_L2 0x000000B0 /* Sensor_Type: Bridge 4 Wire Sensor 1 Advanced Level 2 */ 01392 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_ADV_L2 0x000000B1 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ 01393 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_ADV_L2 0x000000B2 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ 01394 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_ADV_L2 0x000000B3 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ 01395 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_DEF_L2 0x000000C0 /* Sensor_Type: Bridge 6 Wire Sensor 1 Defined Level 2 */ 01396 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_DEF_L2 0x000000C1 /* Sensor_Type: Bridge 6 Wire Sensor 2 Defined Level 2 */ 01397 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_DEF_L2 0x000000C2 /* Sensor_Type: Bridge 6 Wire Sensor 3 Defined Level 2 */ 01398 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_DEF_L2 0x000000C3 /* Sensor_Type: Bridge 6 Wire Sensor 4 Defined Level 2 */ 01399 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_ADV_L2 0x000000D0 /* Sensor_Type: Bridge 6 Wire Sensor 1 Advanced Level 2 */ 01400 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_ADV_L2 0x000000D1 /* Sensor_Type: Bridge 6 Wire Sensor 2 Advanced Level 2 */ 01401 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_ADV_L2 0x000000D2 /* Sensor_Type: Bridge 6 Wire Sensor 3 Advanced Level 2 */ 01402 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_ADV_L2 0x000000D3 /* Sensor_Type: Bridge 6 Wire Sensor 4 Advanced Level 2 */ 01403 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000100 /* Sensor_Type: Voltage Input */ 01404 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_HONEYWELL_TRUSTABILITY 0x00000110 /* Sensor_Type: Voltage Output Pressure Sensor 1 */ 01405 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_AMPHENOL_NPA300X 0x00000111 /* Sensor_Type: Voltage Output Pressure Sensor 2 */ 01406 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_3_DEF 0x00000112 /* Sensor_Type: Voltage Output Pressure Sensor 3 */ 01407 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000180 /* Sensor_Type: Current Input */ 01408 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_HONEYWELL_PX2 0x00000181 /* Sensor_Type: Current Output Pressure Sensor 1 */ 01409 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_2 0x00000182 /* Sensor_Type: Current Output Pressure Sensor 2 */ 01410 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_CUSTOM1 0x00000200 /* Sensor_Type: Custom1 */ 01411 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_1 0x00000800 /* Sensor_Type: I2C Pressure Sensor 1 */ 01412 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_2 0x00000801 /* Sensor_Type: I2C Pressure Sensor 2 */ 01413 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_HONEYWELL_HUMIDICON 0x00000840 /* Sensor_Type: I2C Humidity Sensor 1 */ 01414 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_SENSIRION_SHT3X 0x00000841 /* Sensor_Type: I2C Humidity Sensor 2 */ 01415 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_HONEYWELL_TRUSTABILITY 0x00000C00 /* Sensor_Type: SPI Pressure Sensor 1 */ 01416 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_2 0x00000C01 /* Sensor_Type: SPI Pressure Sensor 2 */ 01417 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_1 0x00000C40 /* Sensor_Type: SPI Humidity Sensor Type 1 */ 01418 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_2 0x00000C41 /* Sensor_Type: SPI Humidity Sensor Type 2 */ 01419 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_1 0x00000C80 /* Sensor_Type: SPI Accelerometer Sensor Type 1 3-Axis */ 01420 #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_2 0x00000C81 /* Sensor_Type: SPI Accelerometer Sensor Type 2 3-Axis */ 01421 01422 /* ------------------------------------------------------------------------------------------------------------------------- 01423 ADISENSE_CORE_SENSOR_DETAILS[n] Pos/Masks Description 01424 ------------------------------------------------------------------------------------------------------------------------- */ 01425 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */ 01426 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */ 01427 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */ 01428 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */ 01429 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */ 01430 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */ 01431 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 12 /* Indicates Channel for Third Term of Compensation */ 01432 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 8 /* Indicates Channel for Second Term of Compensation */ 01433 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */ 01434 #define BITP_ADISENSE_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */ 01435 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */ 01436 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */ 01437 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */ 01438 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */ 01439 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */ 01440 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */ 01441 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 0x0000F000 /* Indicates Channel for Third Term of Compensation */ 01442 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 0x00000F00 /* Indicates Channel for Second Term of Compensation */ 01443 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */ 01444 #define BITM_ADISENSE_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */ 01445 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */ 01446 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */ 01447 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */ 01448 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_8 0x03000000 /* PGA_Gain: Gain of 8 */ 01449 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_16 0x04000000 /* PGA_Gain: Gain of 16 */ 01450 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_32 0x05000000 /* PGA_Gain: Gain of 32 */ 01451 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */ 01452 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */ 01453 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_INT 0x00000000 /* Reference_Select: Internal Reference */ 01454 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_AVDD 0x00100000 /* Reference_Select: AVDD */ 01455 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT1 0x00200000 /* Reference_Select: External Voltage on Refin1 */ 01456 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT2 0x00300000 /* Reference_Select: External Voltage on Refin2 */ 01457 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_RINT1 0x00400000 /* Reference_Select: Internal Resistor1 */ 01458 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_RINT2 0x00500000 /* Reference_Select: Internal Resistor2 */ 01459 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_REXT1 0x00600000 /* Reference_Select: External Resistor on Refin1 */ 01460 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_REXT2 0x00700000 /* Reference_Select: External Resistor on Refin2 */ 01461 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_EXC 0x00800000 /* Reference_Select: Bridge Excitation Voltage */ 01462 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000000 /* Measurement_Units: Degrees C */ 01463 #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000001 /* Measurement_Units: Degrees F */ 01464 01465 /* ------------------------------------------------------------------------------------------------------------------------- 01466 ADISENSE_CORE_CHANNEL_EXCITATION[n] Pos/Masks Description 01467 ------------------------------------------------------------------------------------------------------------------------- */ 01468 #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ 01469 #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_STATIC_SWAP_3WIRE 6 /* Indicates 3-Wire Excitation Currents Should Be Swapped */ 01470 #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 4 /* Disable Second Current Source */ 01471 #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 3 /* Disable First Current Source */ 01472 #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */ 01473 #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ 01474 #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_STATIC_SWAP_3WIRE 0x00000040 /* Indicates 3-Wire Excitation Currents Should Be Swapped */ 01475 #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 0x00000010 /* Disable Second Current Source */ 01476 #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 0x00000008 /* Disable First Current Source */ 01477 #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */ 01478 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_OFF 0x00000000 /* IOUT_Excitation_Current: Disabled */ 01479 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_50UA 0x00000001 /* IOUT_Excitation_Current: 50 \mu;A */ 01480 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_100UA 0x00000002 /* IOUT_Excitation_Current: 100 \mu;A */ 01481 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000003 /* IOUT_Excitation_Current: 250 \mu;A */ 01482 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000004 /* IOUT_Excitation_Current: 500 \mu;A */ 01483 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_750UA 0x00000005 /* IOUT_Excitation_Current: 750 \mu;A */ 01484 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000006 /* IOUT_Excitation_Current: 1000 \mu;A */ 01485 #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA_2 0x00000007 /* IOUT_Excitation_Current: 1000 \mu;A */ 01486 01487 /* ------------------------------------------------------------------------------------------------------------------------- 01488 ADISENSE_CORE_SETTLING_TIME[n] Pos/Masks Description 01489 ------------------------------------------------------------------------------------------------------------------------- */ 01490 #define BITP_ADISENSE_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */ 01491 #define BITM_ADISENSE_CORE_SETTLING_TIME_SETTLING_TIME 0x0000FFFF /* Settling Time to Allow When Switching to Channel */ 01492 01493 /* ------------------------------------------------------------------------------------------------------------------------- 01494 ADISENSE_CORE_FILTER_SELECT[n] Pos/Masks Description 01495 ------------------------------------------------------------------------------------------------------------------------- */ 01496 #define BITP_ADISENSE_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */ 01497 #define BITP_ADISENSE_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */ 01498 #define BITM_ADISENSE_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x0000F800 /* ADC Digital Filter Type */ 01499 #define BITM_ADISENSE_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */ 01500 #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_25SPS 0x00000000 /* ADC_Filter_Type: FIR Filter 25 SPS */ 01501 #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_20SPS 0x00000800 /* ADC_Filter_Type: FIR Filter 20 SPS */ 01502 #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_SINC4 0x00001000 /* ADC_Filter_Type: Sinc4 Filter */ 01503 #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_TBD 0x00001800 /* ADC_Filter_Type: TBD Filter */ 01504 01505 /* ------------------------------------------------------------------------------------------------------------------------- 01506 ADISENSE_CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description 01507 ------------------------------------------------------------------------------------------------------------------------- */ 01508 #define BITP_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */ 01509 #define BITM_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */ 01510 01511 /* ------------------------------------------------------------------------------------------------------------------------- 01512 ADISENSE_CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description 01513 ------------------------------------------------------------------------------------------------------------------------- */ 01514 #define BITP_ADISENSE_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */ 01515 #define BITM_ADISENSE_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */ 01516 01517 /* ------------------------------------------------------------------------------------------------------------------------- 01518 ADISENSE_CORE_SENSOR_OFFSET[n] Pos/Masks Description 01519 ------------------------------------------------------------------------------------------------------------------------- */ 01520 #define BITP_ADISENSE_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */ 01521 #define BITM_ADISENSE_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */ 01522 01523 /* ------------------------------------------------------------------------------------------------------------------------- 01524 ADISENSE_CORE_SENSOR_GAIN[n] Pos/Masks Description 01525 ------------------------------------------------------------------------------------------------------------------------- */ 01526 #define BITP_ADISENSE_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */ 01527 #define BITM_ADISENSE_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */ 01528 01529 /* ------------------------------------------------------------------------------------------------------------------------- 01530 ADISENSE_CORE_ALERT_CODE_CH[n] Pos/Masks Description 01531 ------------------------------------------------------------------------------------------------------------------------- */ 01532 #define BITP_ADISENSE_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0 /* Per-Channel Code Indicating Type of Alert */ 01533 #define BITM_ADISENSE_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0x0000FFFF /* Per-Channel Code Indicating Type of Alert */ 01534 01535 /* ------------------------------------------------------------------------------------------------------------------------- 01536 ADISENSE_CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description 01537 ------------------------------------------------------------------------------------------------------------------------- */ 01538 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */ 01539 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 8 /* Number of bytes to read from the sensor */ 01540 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 4 /* Data Bit Offset, relative to alignment */ 01541 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 3 /* Data Alignment within the data frame */ 01542 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 2 /* Data Endianness of Sensor Result */ 01543 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0 /* Data Encoding of Sensor Result */ 01544 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 0x000F800 /* Number of Relevant Data Bits */ 01545 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 0x0000700 /* Number of bytes to read from the sensor */ 01546 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 0x000000F0 /* Data Bit Offset, relative to alignment */ 01547 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFTALIGNED 0x00000008 /* Data Alignment within the data frame */ 01548 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTEENDIAN 0x00000004 /* Data Endianness of Sensor Result */ 01549 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */ 01550 #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */ 01551 #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */ 01552 #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos Complement */ 01553 #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset Binary */ 01554 01555 /* ------------------------------------------------------------------------------------------------------------------------- 01556 ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description 01557 ------------------------------------------------------------------------------------------------------------------------- */ 01558 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */ 01559 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */ 01560 01561 /* ------------------------------------------------------------------------------------------------------------------------- 01562 ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS[n] Pos/Masks Description 01563 ------------------------------------------------------------------------------------------------------------------------- */ 01564 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 4 /* Number of Read Commands for Digital Sensor */ 01565 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0 /* Number of Configuration Commands for Digital Sensor */ 01566 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 0x00000070 /* Number of Read Commands for Digital Sensor */ 01567 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0x00000007 /* Number of Configuration Commands for Digital Sensor */ 01568 01569 /* ------------------------------------------------------------------------------------------------------------------------- 01570 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description 01571 ------------------------------------------------------------------------------------------------------------------------- */ 01572 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01573 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01574 01575 /* ------------------------------------------------------------------------------------------------------------------------- 01576 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description 01577 ------------------------------------------------------------------------------------------------------------------------- */ 01578 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01579 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01580 01581 /* ------------------------------------------------------------------------------------------------------------------------- 01582 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description 01583 ------------------------------------------------------------------------------------------------------------------------- */ 01584 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01585 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01586 01587 /* ------------------------------------------------------------------------------------------------------------------------- 01588 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4[n] Pos/Masks Description 01589 ------------------------------------------------------------------------------------------------------------------------- */ 01590 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01591 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01592 01593 /* ------------------------------------------------------------------------------------------------------------------------- 01594 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5[n] Pos/Masks Description 01595 ------------------------------------------------------------------------------------------------------------------------- */ 01596 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01597 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01598 01599 /* ------------------------------------------------------------------------------------------------------------------------- 01600 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6[n] Pos/Masks Description 01601 ------------------------------------------------------------------------------------------------------------------------- */ 01602 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01603 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01604 01605 /* ------------------------------------------------------------------------------------------------------------------------- 01606 ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7[n] Pos/Masks Description 01607 ------------------------------------------------------------------------------------------------------------------------- */ 01608 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01609 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ 01610 01611 /* ------------------------------------------------------------------------------------------------------------------------- 01612 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1[n] Pos/Masks Description 01613 ------------------------------------------------------------------------------------------------------------------------- */ 01614 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01615 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01616 01617 /* ------------------------------------------------------------------------------------------------------------------------- 01618 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2[n] Pos/Masks Description 01619 ------------------------------------------------------------------------------------------------------------------------- */ 01620 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01621 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01622 01623 /* ------------------------------------------------------------------------------------------------------------------------- 01624 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3[n] Pos/Masks Description 01625 ------------------------------------------------------------------------------------------------------------------------- */ 01626 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01627 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01628 01629 /* ------------------------------------------------------------------------------------------------------------------------- 01630 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4[n] Pos/Masks Description 01631 ------------------------------------------------------------------------------------------------------------------------- */ 01632 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01633 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01634 01635 /* ------------------------------------------------------------------------------------------------------------------------- 01636 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5[n] Pos/Masks Description 01637 ------------------------------------------------------------------------------------------------------------------------- */ 01638 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01639 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01640 01641 /* ------------------------------------------------------------------------------------------------------------------------- 01642 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6[n] Pos/Masks Description 01643 ------------------------------------------------------------------------------------------------------------------------- */ 01644 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01645 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01646 01647 /* ------------------------------------------------------------------------------------------------------------------------- 01648 ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7[n] Pos/Masks Description 01649 ------------------------------------------------------------------------------------------------------------------------- */ 01650 #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01651 #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ 01652 01653 01654 /* ============================================================================================================================ 01655 Test Registers 01656 ============================================================================================================================ */ 01657 01658 /* ============================================================================================================================ 01659 ADISENSE_TEST 01660 ============================================================================================================================ */ 01661 #define MOD_ADISENSE_TEST_BASE 0x00000400 /* Test Registers */ 01662 #define MOD_ADISENSE_TEST_MASK 0x00007FFF /* Test Registers */ 01663 #define REG_ADISENSE_TEST_TEST_REG_0_RESET 0x00000000 /* Reset Value for test_reg_0 */ 01664 #define REG_ADISENSE_TEST_TEST_REG_0 0x00000400 /* ADISENSE_TEST Test Register 0 */ 01665 #define REG_ADISENSE_TEST_ADC_CAL_TEMP_RESET 0x7fc00000 /* Reset Value for ADISENSE_TEST_ADC_CAL_TEMP */ 01666 #define REG_ADISENSE_TEST_ADC_CAL_TEMP 0x00000404 /* ADC-sourced temperature used for calibration (read-only) */ 01667 #define REG_ADISENSE_TEST_USER_CAL_TEMP_RESET 0x7fc00000 /* Reset Value for ADISENSE_TEST_USER_CAL_TEMP */ 01668 #define REG_ADISENSE_TEST_USER_CAL_TEMP 0x00000408 /* User-specified temperature override for calibration */ 01669 01670 /* ============================================================================================================================ 01671 ADISENSE_TEST Register BitMasks, Positions & Enumerations 01672 ============================================================================================================================ */ 01673 /* ------------------------------------------------------------------------------------------------------------------------- 01674 ADISENSE_TEST_TEST_REG_0 Pos/Masks Description 01675 ------------------------------------------------------------------------------------------------------------------------- */ 01676 #define BITP_ADISENSE_TEST_TEST_REG_0_TEST_COMMAND 0 /* Test_Command */ 01677 #define BITM_ADISENSE_TEST_TEST_REG_0_TEST_COMMAND 0x000000FF /* Test_Command */ 01678 01679 01680 /* ADISENSE_SPI Parameters */ 01681 01682 /***** ADISENSE_SPI */ 01683 #define PARAM_ADISENSE_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */ 01684 #define PARAM_ADISENSE_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */ 01685 #define PARAM_ADISENSE_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */ 01686 #define PARAM_ADISENSE_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */ 01687 #define PARAM_ADISENSE_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */ 01688 #define PARAM_ADISENSE_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */ 01689 #define PARAM_ADISENSE_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */ 01690 #define PARAM_ADISENSE_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */ 01691 #define PARAM_ADISENSE_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */ 01692 #define PARAM_ADISENSE_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */ 01693 #define PARAM_ADISENSE_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */ 01694 #define PARAM_ADISENSE_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */ 01695 #define PARAM_ADISENSE_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */ 01696 #define PARAM_ADISENSE_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */ 01697 #define PARAM_ADISENSE_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */ 01698 #define PARAM_ADISENSE_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */ 01699 #define PARAM_ADISENSE_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */ 01700 #define PARAM_ADISENSE_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */ 01701 #define PARAM_ADISENSE_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */ 01702 #define PARAM_ADISENSE_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */ 01703 #define PARAM_ADISENSE_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */ 01704 #define PARAM_ADISENSE_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */ 01705 #define PARAM_ADISENSE_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */ 01706 #define PARAM_ADISENSE_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */ 01707 #define PARAM_ADISENSE_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */ 01708 #define PARAM_ADISENSE_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */ 01709 #define PARAM_ADISENSE_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */ 01710 #define PARAM_ADISENSE_SPI_SEND_STATUS_SUPPORT "NO_SEND_STATUS" /* Determines if and how the part supports the SEND_STATUS feature */ 01711 #define PARAM_ADISENSE_SPI_SEND_STATUS_SUPPORT_ENABLE 0 /* This is used to enable various send status features */ 01712 #define PARAM_ADISENSE_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */ 01713 #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */ 01714 #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */ 01715 #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */ 01716 #define PARAM_ADISENSE_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */ 01717 #define PARAM_ADISENSE_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */ 01718 #define PARAM_ADISENSE_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */ 01719 #define PARAM_ADISENSE_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */ 01720 #define PARAM_ADISENSE_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */ 01721 #define PARAM_ADISENSE_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */ 01722 #define PARAM_ADISENSE_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */ 01723 #define PARAM_ADISENSE_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */ 01724 #define PARAM_ADISENSE_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */ 01725 #define PARAM_ADISENSE_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */ 01726 #define PARAM_ADISENSE_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */ 01727 #define PARAM_ADISENSE_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */ 01728 #define PARAM_ADISENSE_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */ 01729 #define PARAM_ADISENSE_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */ 01730 #define PARAM_ADISENSE_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */ 01731 01732 #endif /* end ifndef _DEF_ADISENSE1000_REGISTERS_H */ 01733
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