MPU9250_register.h

00001 #ifndef MPU9250_REGISTER_H
00002 #define MPU9250_REGISTER_H
00003 
00004 // See also MPU-9250 Register Map and Descriptions, Revision 4.0, RM-MPU-9250A-00, Rev. 1.4, 9/9/2013 for registers not listed in 
00005 // above document; the MPU9250 and MPU9150 are virtually identical but the latter has a different register map
00006 
00007 //AK8963 registers
00008 #define WHO_AM_I_AK8963  0x00 // should return 0x48
00009 #define INFO             0x01
00010 #define AK8963_ST1       0x02  // data ready status bit 0
00011 #define AK8963_XOUT_L    0x03  // data
00012 #define AK8963_XOUT_H    0x04
00013 #define AK8963_YOUT_L    0x05
00014 #define AK8963_YOUT_H    0x06
00015 #define AK8963_ZOUT_L    0x07
00016 #define AK8963_ZOUT_H    0x08
00017 #define AK8963_ST2       0x09  // Data overflow bit 3 and data read error status bit 2
00018 #define AK8963_CNTL      0x0A  // Power down (0000), single-measurement (0001), self-test (1000) and Fuse ROM (1111) modes on bits 3:0
00019 #define AK8963_ASTC      0x0C  // Self test control
00020 #define AK8963_I2CDIS    0x0F  // I2C disable
00021 #define AK8963_ASAX      0x10  // Fuse ROM x-axis sensitivity adjustment value
00022 #define AK8963_ASAY      0x11  // Fuse ROM y-axis sensitivity adjustment value
00023 #define AK8963_ASAZ      0x12  // Fuse ROM z-axis sensitivity adjustment value
00024 
00025 
00026 
00027 //MPU6500 register
00028 #define SELF_TEST_X_GYRO 0x00                  
00029 #define SELF_TEST_Y_GYRO 0x01                                                                          
00030 #define SELF_TEST_Z_GYRO 0x02
00031 
00032 #define SELF_TEST_X_ACCEL 0x0D
00033 #define SELF_TEST_Y_ACCEL 0x0E    
00034 #define SELF_TEST_Z_ACCEL 0x0F
00035 
00036 #define SELF_TEST_A      0x10
00037 
00038 #define XG_OFFSET_H      0x13  // User-defined trim values for gyroscope
00039 #define XG_OFFSET_L      0x14
00040 #define YG_OFFSET_H      0x15
00041 #define YG_OFFSET_L      0x16
00042 #define ZG_OFFSET_H      0x17
00043 #define ZG_OFFSET_L      0x18
00044 #define SMPLRT_DIV       0x19
00045 #define CONFIG           0x1A
00046 #define GYRO_CONFIG      0x1B
00047 #define ACCEL_CONFIG     0x1C
00048 #define ACCEL_CONFIG2    0x1D
00049 #define LP_ACCEL_ODR     0x1E   
00050 #define WOM_THR          0x1F   
00051 
00052 #define MOT_DUR          0x20  // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms
00053 #define ZMOT_THR         0x21  // Zero-motion detection threshold bits [7:0]
00054 #define ZRMOT_DUR        0x22  // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms
00055 
00056 #define FIFO_EN          0x23
00057 #define I2C_MST_CTRL     0x24   
00058 #define I2C_SLV0_ADDR    0x25
00059 #define I2C_SLV0_REG     0x26
00060 #define I2C_SLV0_CTRL    0x27
00061 #define I2C_SLV1_ADDR    0x28
00062 #define I2C_SLV1_REG     0x29
00063 #define I2C_SLV1_CTRL    0x2A
00064 #define I2C_SLV2_ADDR    0x2B
00065 #define I2C_SLV2_REG     0x2C
00066 #define I2C_SLV2_CTRL    0x2D
00067 #define I2C_SLV3_ADDR    0x2E
00068 #define I2C_SLV3_REG     0x2F
00069 #define I2C_SLV3_CTRL    0x30
00070 #define I2C_SLV4_ADDR    0x31
00071 #define I2C_SLV4_REG     0x32
00072 #define I2C_SLV4_DO      0x33
00073 #define I2C_SLV4_CTRL    0x34
00074 #define I2C_SLV4_DI      0x35
00075 #define I2C_MST_STATUS   0x36
00076 #define INT_PIN_CFG      0x37
00077 #define INT_ENABLE       0x38
00078 #define DMP_INT_STATUS   0x39  // Check DMP interrupt
00079 #define INT_STATUS       0x3A
00080 #define ACCEL_XOUT_H     0x3B
00081 #define ACCEL_XOUT_L     0x3C
00082 #define ACCEL_YOUT_H     0x3D
00083 #define ACCEL_YOUT_L     0x3E
00084 #define ACCEL_ZOUT_H     0x3F
00085 #define ACCEL_ZOUT_L     0x40
00086 #define TEMP_OUT_H       0x41
00087 #define TEMP_OUT_L       0x42
00088 #define GYRO_XOUT_H      0x43
00089 #define GYRO_XOUT_L      0x44
00090 #define GYRO_YOUT_H      0x45
00091 #define GYRO_YOUT_L      0x46
00092 #define GYRO_ZOUT_H      0x47
00093 #define GYRO_ZOUT_L      0x48
00094 #define EXT_SENS_DATA_00 0x49
00095 #define EXT_SENS_DATA_01 0x4A
00096 #define EXT_SENS_DATA_02 0x4B
00097 #define EXT_SENS_DATA_03 0x4C
00098 #define EXT_SENS_DATA_04 0x4D
00099 #define EXT_SENS_DATA_05 0x4E
00100 #define EXT_SENS_DATA_06 0x4F
00101 #define EXT_SENS_DATA_07 0x50
00102 #define EXT_SENS_DATA_08 0x51
00103 #define EXT_SENS_DATA_09 0x52
00104 #define EXT_SENS_DATA_10 0x53
00105 #define EXT_SENS_DATA_11 0x54
00106 #define EXT_SENS_DATA_12 0x55
00107 #define EXT_SENS_DATA_13 0x56
00108 #define EXT_SENS_DATA_14 0x57
00109 #define EXT_SENS_DATA_15 0x58
00110 #define EXT_SENS_DATA_16 0x59
00111 #define EXT_SENS_DATA_17 0x5A
00112 #define EXT_SENS_DATA_18 0x5B
00113 #define EXT_SENS_DATA_19 0x5C
00114 #define EXT_SENS_DATA_20 0x5D
00115 #define EXT_SENS_DATA_21 0x5E
00116 #define EXT_SENS_DATA_22 0x5F
00117 #define EXT_SENS_DATA_23 0x60
00118 #define MOT_DETECT_STATUS 0x61
00119 #define I2C_SLV0_DO      0x63
00120 #define I2C_SLV1_DO      0x64
00121 #define I2C_SLV2_DO      0x65
00122 #define I2C_SLV3_DO      0x66
00123 #define I2C_MST_DELAY_CTRL 0x67
00124 #define SIGNAL_PATH_RESET  0x68
00125 #define MOT_DETECT_CTRL  0x69
00126 #define USER_CTRL        0x6A  // Bit 7 enable DMP, bit 3 reset DMP
00127 #define PWR_MGMT_1       0x6B // Device defaults to the SLEEP mode
00128 #define PWR_MGMT_2       0x6C
00129 #define DMP_BANK         0x6D  // Activates a specific bank in the DMP
00130 #define DMP_RW_PNT       0x6E  // Set read/write pointer to a specific start address in specified DMP bank
00131 #define DMP_REG          0x6F  // Register in DMP from which to read or to which to write
00132 #define DMP_REG_1        0x70
00133 #define DMP_REG_2        0x71 
00134 #define FIFO_COUNTH      0x72
00135 #define FIFO_COUNTL      0x73
00136 #define FIFO_R_W         0x74
00137 #define WHO_AM_I_MPU9250 0x75 // Should return 0x71
00138 #define XA_OFFSET_H      0x77
00139 #define XA_OFFSET_L      0x78
00140 #define YA_OFFSET_H      0x7A
00141 #define YA_OFFSET_L      0x7B
00142 #define ZA_OFFSET_H      0x7D
00143 #define ZA_OFFSET_L      0x7E
00144 
00145 #endif