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4 years, 7 months ago.
EMAC ETH_IRQ Trigger
Dear all,
I'm currently working on an EMAC driver for the ENC28J60 and also looked at drivers for build-in MACs and external MACs (SMSC9220 -> https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h) as reference. I noticed that the receive task is triggered by an ETH-IRQ. But I didn't find an implementation of the interrupt line anywhere that would trigger an ETH-IRQ. Is this interrupt line read/used at all? How else is an ETH-IRQ triggered to read the interrupt registers of the Smsc9220 and trigger a routine? I recognized the interrupt handler as such. The external Ethernet controller receives a package and signals this to the controller by means of a signal line. This should theoretically be detected by a GPIO-InterruptIn, which then triggers a NVIC_SetPendingIRQ(ETH). There is no such implementation. So what triggers ETH_IRQ if it is not the interrupt line from the IC to the controller? Thanks T. Jaster