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4 years, 3 months ago.
I am slightly confused when reading the documentation for the operation of the PLL Interrupt bit.
PLL Unlocked Interrupt. Indicates that the PLL has not yet achieved or has lost its phase lock. PLLINT will only be asserted when the PLL is powered up and active (ECG and/or BIOZ Channel enabled). Remains asserted while the PLL unlocked condition persists, then held until cleared by STATUS read back (32nd SCLK).
The first sentence leads me to believe that this bit will be 1 when the PLL has not achieved, or has lost, its phase lock. The second sentence, to me, sounds like the bit will be high when the PLL is operating correctly and is locked. The third sentence leads me to believe that the bit will then be high again if the unlocked condition triggers. Finally, a status read will clear this interrupt.
So, if I am constantly (every 7.8125ms) polling the status register, should I expect the PLLINT bit to be high or low if it is running successfully?
Question relating to:
4 years, 2 months ago.
We read that slightly differently. The PLL can only generate an unlock interrupt if it's actually powered and active (otherwise it will never go high). During normal operation it should read low as the STATUS register description states that all interrupt terms are active high.
-Ralph, Team Mbed