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9 years, 5 months ago.
Random numbers on K64F: stuck at execution
I am trying to get the RNGA hardware number generator to work on the K64F. I was able to get the code to compile but it is stuck when I execute it. Everytime I try to access any register in the RNG the execution stops. In the code below it hangs at "RNG_CR &= RNG_CR_SLP_MASK;" line. Any idea/comments?
#include "mbed.h"
Serial pc(USBTX, USBRX);
unsigned int out;
int main()
{
//pc.baud(115200);
int output;
int i;
/* turn on RNGA module */
SIM_SCGC3 |= SIM_SCGC3_RNGA_MASK;
printf("1\r\n");
/* set SLP bit to 0 - "RNGA is not in sleep mode" */
RNG_CR &= ~RNG_CR_SLP_MASK;
printf("2\r\n");
/* set HA bit to 1 - "security violations masked" */
RNG_CR |= RNG_CR_HA_MASK;
printf("3\r\n");
/* set GO bit to 1 - "output register loaded with data" */
RNG_CR |= RNG_CR_GO_MASK;
printf("4\r\n");
/* wait for RNG FIFO to be full */
while((RNG_SR & RNG_SR_OREG_LVL(0xF)) == 0) {}
/* get value */
output = RNG_OR;
printf(">%d\r\n",output);
}
1 Answer
9 years, 5 months ago.
What you describe is what I am used to happening when you don't clock a peripheral on a Freescale target. You do enable the clock, however from the reference manual:
Quote:
FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing through AIPS1, define the clock gate control bits in the SCGC3. When accessing through AIPS0, define the clock gate control bits in SCGC6.
And:
Quote:
RNGA can be accessed through both AIPS0 and AIPS1. When accessed through AIPS0, the base address is 4002_9000h and when accessed through AIPS1, the base address is 400A_0000h.
Add to that from the register definitions:
#define RNG_BASE (0x40029000u)
In other words you need to use:
SIM_SCGC6 |= SIM_SCGC6_RNGA_MASK;
(I just replaced numbers, assuming that the name is kept the same).