9 years, 11 months ago.

Trying to synchronise a signal

Dear all, I am trying to generate a signal inverted and synchronous to an input signal on an LPC1768 Arch Pro. The input signal has a 28us period of which 24us is low, 4 is high. I want the mbed to always output the inverse of this signal, but when it "sees" the signal coming in to synchronise the generated one to the input.

My question is why my code fails.

mycode

#include "mbed.h"
#include "FastIO.h"

InterruptIn trigger(P0_23);
DigitalOut sync_out(P1_31);
FastOut<P2_2> fast_out;


Timer clk; 

void synch()
{
clk.reset();
}


int main()
{
    clk.start();
    trigger.rise(&synch);

    while (1) {
        if(clk.read_us()<24){
        sync_out = 1;
        }
        else if (clk.read_us()>28){
        clk.reset();
        }
        else{
        sync_out = 0;
        }
        
    }
}

I tested both fast and normal outs and when the trigger signal is not connected output is fine, but when the trigger is connected, it's missing wuite a few interrupt pulses. The problem goes away when reducing the input signal frequency (from 35K to <30) or increase the duty cycle.

Any ideas? Thank you in advance

1 Answer

9 years, 11 months ago.

Hi geo,

it seems to me that you only need a simple inverter. Something like this:

sync_out = !signal_in

In this case you don't need interrupts, and other stuffs, just an input and an output.

From your initial statement turns out that the input signal has constant parameters, later statements say that you are modifying the input signal's frequency/duty cycle. Am I missing something?

Interrupts are time consuming steps. That is why you obtain better results with lower input frequencies.

Regards,

Dear Gyozo, Thank you for your answer. The input signal has constant parameters as described. However, it's not always there.

My generated signal is always there, and it's the same period as the incoming signal (but it can be different - just so happens in this case I want the inverse). When there is a signal coming in I need my output to be synchronous - phase locked- to the input.

I only changed the input signal to figure out what's wrong, because I was suspecting something not happening fast enough.

posted by geo konst 23 May 2014