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sx1272Regs-Fsk.h
1 /**
2  / _____) _ | |
3 ( (____ _____ ____ _| |_ _____ ____| |__
4  \____ \| ___ | (_ _) ___ |/ ___) _ \
5  _____) ) ____| | | || |_| ____( (___| | | |
6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
7  (C) 2015 Semtech
8 
9 Description: SX1272 FSK modem registers and bits definitions
10 
11 License: Revised BSD License, see LICENSE.TXT file include in the project
12 
13 Maintainer: Miguel Luis and Gregory Cristian
14 
15 Copyright (c) 2017, Arm Limited and affiliates.
16 
17 SPDX-License-Identifier: BSD-3-Clause
18 */
19 #ifndef __SX1272_REGS_FSK_H__
20 #define __SX1272_REGS_FSK_H__
21 
22 /*!
23  * ============================================================================
24  * SX1272 Internal registers Address
25  * ============================================================================
26  */
27 #define REG_FIFO 0x00
28 // Common settings
29 #define REG_OPMODE 0x01
30 #define REG_BITRATEMSB 0x02
31 #define REG_BITRATELSB 0x03
32 #define REG_FDEVMSB 0x04
33 #define REG_FDEVLSB 0x05
34 #define REG_FRFMSB 0x06
35 #define REG_FRFMID 0x07
36 #define REG_FRFLSB 0x08
37 // Tx settings
38 #define REG_PACONFIG 0x09
39 #define REG_PARAMP 0x0A
40 #define REG_OCP 0x0B
41 // Rx settings
42 #define REG_LNA 0x0C
43 #define REG_RXCONFIG 0x0D
44 #define REG_RSSICONFIG 0x0E
45 #define REG_RSSICOLLISION 0x0F
46 #define REG_RSSITHRESH 0x10
47 #define REG_RSSIVALUE 0x11
48 #define REG_RXBW 0x12
49 #define REG_AFCBW 0x13
50 #define REG_OOKPEAK 0x14
51 #define REG_OOKFIX 0x15
52 #define REG_OOKAVG 0x16
53 #define REG_RES17 0x17
54 #define REG_RES18 0x18
55 #define REG_RES19 0x19
56 #define REG_AFCFEI 0x1A
57 #define REG_AFCMSB 0x1B
58 #define REG_AFCLSB 0x1C
59 #define REG_FEIMSB 0x1D
60 #define REG_FEILSB 0x1E
61 #define REG_PREAMBLEDETECT 0x1F
62 #define REG_RXTIMEOUT1 0x20
63 #define REG_RXTIMEOUT2 0x21
64 #define REG_RXTIMEOUT3 0x22
65 #define REG_RXDELAY 0x23
66 // Oscillator settings
67 #define REG_OSC 0x24
68 // Packet handler settings
69 #define REG_PREAMBLEMSB 0x25
70 #define REG_PREAMBLELSB 0x26
71 #define REG_SYNCCONFIG 0x27
72 #define REG_SYNCVALUE1 0x28
73 #define REG_SYNCVALUE2 0x29
74 #define REG_SYNCVALUE3 0x2A
75 #define REG_SYNCVALUE4 0x2B
76 #define REG_SYNCVALUE5 0x2C
77 #define REG_SYNCVALUE6 0x2D
78 #define REG_SYNCVALUE7 0x2E
79 #define REG_SYNCVALUE8 0x2F
80 #define REG_PACKETCONFIG1 0x30
81 #define REG_PACKETCONFIG2 0x31
82 #define REG_PAYLOADLENGTH 0x32
83 #define REG_NODEADRS 0x33
84 #define REG_BROADCASTADRS 0x34
85 #define REG_FIFOTHRESH 0x35
86 // SM settings
87 #define REG_SEQCONFIG1 0x36
88 #define REG_SEQCONFIG2 0x37
89 #define REG_TIMERRESOL 0x38
90 #define REG_TIMER1COEF 0x39
91 #define REG_TIMER2COEF 0x3A
92 // Service settings
93 #define REG_IMAGECAL 0x3B
94 #define REG_TEMP 0x3C
95 #define REG_LOWBAT 0x3D
96 // Status
97 #define REG_IRQFLAGS1 0x3E
98 #define REG_IRQFLAGS2 0x3F
99 // I/O settings
100 #define REG_DIOMAPPING1 0x40
101 #define REG_DIOMAPPING2 0x41
102 // Version
103 #define REG_VERSION 0x42
104 // Additional settings
105 #define REG_AGCREF 0x43
106 #define REG_AGCTHRESH1 0x44
107 #define REG_AGCTHRESH2 0x45
108 #define REG_AGCTHRESH3 0x46
109 #define REG_PLLHOP 0x4B
110 #define REG_TCXO 0x58
111 #define REG_PADAC 0x5A
112 #define REG_PLL 0x5C
113 #define REG_PLLLOWPN 0x5E
114 #define REG_FORMERTEMP 0x6C
115 #define REG_BITRATEFRAC 0x70
116 
117 /*!
118  * ============================================================================
119  * SX1272 FSK bits control definition
120  * ============================================================================
121  */
122 
123 /*!
124  * RegFifo
125  */
126 
127 /*!
128  * RegOpMode
129  */
130 #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F
131 #define RF_OPMODE_LONGRANGEMODE_OFF 0x00
132 #define RF_OPMODE_LONGRANGEMODE_ON 0x80
133 
134 #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F
135 #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default
136 #define RF_OPMODE_MODULATIONTYPE_OOK 0x20
137 
138 #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7
139 #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default
140 #define RF_OPMODE_MODULATIONSHAPING_01 0x08
141 #define RF_OPMODE_MODULATIONSHAPING_10 0x10
142 #define RF_OPMODE_MODULATIONSHAPING_11 0x18
143 
144 #define RF_OPMODE_MASK 0xF8
145 #define RF_OPMODE_SLEEP 0x00
146 #define RF_OPMODE_STANDBY 0x01 // Default
147 #define RF_OPMODE_SYNTHESIZER_TX 0x02
148 #define RF_OPMODE_TRANSMITTER 0x03
149 #define RF_OPMODE_SYNTHESIZER_RX 0x04
150 #define RF_OPMODE_RECEIVER 0x05
151 
152 /*!
153  * RegBitRate (bits/sec)
154  */
155 #define RF_BITRATEMSB_1200_BPS 0x68
156 #define RF_BITRATELSB_1200_BPS 0x2B
157 #define RF_BITRATEMSB_2400_BPS 0x34
158 #define RF_BITRATELSB_2400_BPS 0x15
159 #define RF_BITRATEMSB_4800_BPS 0x1A // Default
160 #define RF_BITRATELSB_4800_BPS 0x0B // Default
161 #define RF_BITRATEMSB_9600_BPS 0x0D
162 #define RF_BITRATELSB_9600_BPS 0x05
163 #define RF_BITRATEMSB_15000_BPS 0x08
164 #define RF_BITRATELSB_15000_BPS 0x55
165 #define RF_BITRATEMSB_19200_BPS 0x06
166 #define RF_BITRATELSB_19200_BPS 0x83
167 #define RF_BITRATEMSB_38400_BPS 0x03
168 #define RF_BITRATELSB_38400_BPS 0x41
169 #define RF_BITRATEMSB_76800_BPS 0x01
170 #define RF_BITRATELSB_76800_BPS 0xA1
171 #define RF_BITRATEMSB_153600_BPS 0x00
172 #define RF_BITRATELSB_153600_BPS 0xD0
173 #define RF_BITRATEMSB_57600_BPS 0x02
174 #define RF_BITRATELSB_57600_BPS 0x2C
175 #define RF_BITRATEMSB_115200_BPS 0x01
176 #define RF_BITRATELSB_115200_BPS 0x16
177 #define RF_BITRATEMSB_12500_BPS 0x0A
178 #define RF_BITRATELSB_12500_BPS 0x00
179 #define RF_BITRATEMSB_25000_BPS 0x05
180 #define RF_BITRATELSB_25000_BPS 0x00
181 #define RF_BITRATEMSB_50000_BPS 0x02
182 #define RF_BITRATELSB_50000_BPS 0x80
183 #define RF_BITRATEMSB_100000_BPS 0x01
184 #define RF_BITRATELSB_100000_BPS 0x40
185 #define RF_BITRATEMSB_150000_BPS 0x00
186 #define RF_BITRATELSB_150000_BPS 0xD5
187 #define RF_BITRATEMSB_200000_BPS 0x00
188 #define RF_BITRATELSB_200000_BPS 0xA0
189 #define RF_BITRATEMSB_250000_BPS 0x00
190 #define RF_BITRATELSB_250000_BPS 0x80
191 #define RF_BITRATEMSB_32768_BPS 0x03
192 #define RF_BITRATELSB_32768_BPS 0xD1
193 
194 /*!
195  * RegFdev (Hz)
196  */
197 #define RF_FDEVMSB_2000_HZ 0x00
198 #define RF_FDEVLSB_2000_HZ 0x21
199 #define RF_FDEVMSB_5000_HZ 0x00 // Default
200 #define RF_FDEVLSB_5000_HZ 0x52 // Default
201 #define RF_FDEVMSB_10000_HZ 0x00
202 #define RF_FDEVLSB_10000_HZ 0xA4
203 #define RF_FDEVMSB_15000_HZ 0x00
204 #define RF_FDEVLSB_15000_HZ 0xF6
205 #define RF_FDEVMSB_20000_HZ 0x01
206 #define RF_FDEVLSB_20000_HZ 0x48
207 #define RF_FDEVMSB_25000_HZ 0x01
208 #define RF_FDEVLSB_25000_HZ 0x9A
209 #define RF_FDEVMSB_30000_HZ 0x01
210 #define RF_FDEVLSB_30000_HZ 0xEC
211 #define RF_FDEVMSB_35000_HZ 0x02
212 #define RF_FDEVLSB_35000_HZ 0x3D
213 #define RF_FDEVMSB_40000_HZ 0x02
214 #define RF_FDEVLSB_40000_HZ 0x8F
215 #define RF_FDEVMSB_45000_HZ 0x02
216 #define RF_FDEVLSB_45000_HZ 0xE1
217 #define RF_FDEVMSB_50000_HZ 0x03
218 #define RF_FDEVLSB_50000_HZ 0x33
219 #define RF_FDEVMSB_55000_HZ 0x03
220 #define RF_FDEVLSB_55000_HZ 0x85
221 #define RF_FDEVMSB_60000_HZ 0x03
222 #define RF_FDEVLSB_60000_HZ 0xD7
223 #define RF_FDEVMSB_65000_HZ 0x04
224 #define RF_FDEVLSB_65000_HZ 0x29
225 #define RF_FDEVMSB_70000_HZ 0x04
226 #define RF_FDEVLSB_70000_HZ 0x7B
227 #define RF_FDEVMSB_75000_HZ 0x04
228 #define RF_FDEVLSB_75000_HZ 0xCD
229 #define RF_FDEVMSB_80000_HZ 0x05
230 #define RF_FDEVLSB_80000_HZ 0x1F
231 #define RF_FDEVMSB_85000_HZ 0x05
232 #define RF_FDEVLSB_85000_HZ 0x71
233 #define RF_FDEVMSB_90000_HZ 0x05
234 #define RF_FDEVLSB_90000_HZ 0xC3
235 #define RF_FDEVMSB_95000_HZ 0x06
236 #define RF_FDEVLSB_95000_HZ 0x14
237 #define RF_FDEVMSB_100000_HZ 0x06
238 #define RF_FDEVLSB_100000_HZ 0x66
239 #define RF_FDEVMSB_110000_HZ 0x07
240 #define RF_FDEVLSB_110000_HZ 0x0A
241 #define RF_FDEVMSB_120000_HZ 0x07
242 #define RF_FDEVLSB_120000_HZ 0xAE
243 #define RF_FDEVMSB_130000_HZ 0x08
244 #define RF_FDEVLSB_130000_HZ 0x52
245 #define RF_FDEVMSB_140000_HZ 0x08
246 #define RF_FDEVLSB_140000_HZ 0xF6
247 #define RF_FDEVMSB_150000_HZ 0x09
248 #define RF_FDEVLSB_150000_HZ 0x9A
249 #define RF_FDEVMSB_160000_HZ 0x0A
250 #define RF_FDEVLSB_160000_HZ 0x3D
251 #define RF_FDEVMSB_170000_HZ 0x0A
252 #define RF_FDEVLSB_170000_HZ 0xE1
253 #define RF_FDEVMSB_180000_HZ 0x0B
254 #define RF_FDEVLSB_180000_HZ 0x85
255 #define RF_FDEVMSB_190000_HZ 0x0C
256 #define RF_FDEVLSB_190000_HZ 0x29
257 #define RF_FDEVMSB_200000_HZ 0x0C
258 #define RF_FDEVLSB_200000_HZ 0xCD
259 
260 /*!
261  * RegFrf (MHz)
262  */
263 #define RF_FRFMSB_863_MHZ 0xD7
264 #define RF_FRFMID_863_MHZ 0xC0
265 #define RF_FRFLSB_863_MHZ 0x00
266 #define RF_FRFMSB_864_MHZ 0xD8
267 #define RF_FRFMID_864_MHZ 0x00
268 #define RF_FRFLSB_864_MHZ 0x00
269 #define RF_FRFMSB_865_MHZ 0xD8
270 #define RF_FRFMID_865_MHZ 0x40
271 #define RF_FRFLSB_865_MHZ 0x00
272 #define RF_FRFMSB_866_MHZ 0xD8
273 #define RF_FRFMID_866_MHZ 0x80
274 #define RF_FRFLSB_866_MHZ 0x00
275 #define RF_FRFMSB_867_MHZ 0xD8
276 #define RF_FRFMID_867_MHZ 0xC0
277 #define RF_FRFLSB_867_MHZ 0x00
278 #define RF_FRFMSB_868_MHZ 0xD9
279 #define RF_FRFMID_868_MHZ 0x00
280 #define RF_FRFLSB_868_MHZ 0x00
281 #define RF_FRFMSB_869_MHZ 0xD9
282 #define RF_FRFMID_869_MHZ 0x40
283 #define RF_FRFLSB_869_MHZ 0x00
284 #define RF_FRFMSB_870_MHZ 0xD9
285 #define RF_FRFMID_870_MHZ 0x80
286 #define RF_FRFLSB_870_MHZ 0x00
287 
288 #define RF_FRFMSB_902_MHZ 0xE1
289 #define RF_FRFMID_902_MHZ 0x80
290 #define RF_FRFLSB_902_MHZ 0x00
291 #define RF_FRFMSB_903_MHZ 0xE1
292 #define RF_FRFMID_903_MHZ 0xC0
293 #define RF_FRFLSB_903_MHZ 0x00
294 #define RF_FRFMSB_904_MHZ 0xE2
295 #define RF_FRFMID_904_MHZ 0x00
296 #define RF_FRFLSB_904_MHZ 0x00
297 #define RF_FRFMSB_905_MHZ 0xE2
298 #define RF_FRFMID_905_MHZ 0x40
299 #define RF_FRFLSB_905_MHZ 0x00
300 #define RF_FRFMSB_906_MHZ 0xE2
301 #define RF_FRFMID_906_MHZ 0x80
302 #define RF_FRFLSB_906_MHZ 0x00
303 #define RF_FRFMSB_907_MHZ 0xE2
304 #define RF_FRFMID_907_MHZ 0xC0
305 #define RF_FRFLSB_907_MHZ 0x00
306 #define RF_FRFMSB_908_MHZ 0xE3
307 #define RF_FRFMID_908_MHZ 0x00
308 #define RF_FRFLSB_908_MHZ 0x00
309 #define RF_FRFMSB_909_MHZ 0xE3
310 #define RF_FRFMID_909_MHZ 0x40
311 #define RF_FRFLSB_909_MHZ 0x00
312 #define RF_FRFMSB_910_MHZ 0xE3
313 #define RF_FRFMID_910_MHZ 0x80
314 #define RF_FRFLSB_910_MHZ 0x00
315 #define RF_FRFMSB_911_MHZ 0xE3
316 #define RF_FRFMID_911_MHZ 0xC0
317 #define RF_FRFLSB_911_MHZ 0x00
318 #define RF_FRFMSB_912_MHZ 0xE4
319 #define RF_FRFMID_912_MHZ 0x00
320 #define RF_FRFLSB_912_MHZ 0x00
321 #define RF_FRFMSB_913_MHZ 0xE4
322 #define RF_FRFMID_913_MHZ 0x40
323 #define RF_FRFLSB_913_MHZ 0x00
324 #define RF_FRFMSB_914_MHZ 0xE4
325 #define RF_FRFMID_914_MHZ 0x80
326 #define RF_FRFLSB_914_MHZ 0x00
327 #define RF_FRFMSB_915_MHZ 0xE4 // Default
328 #define RF_FRFMID_915_MHZ 0xC0 // Default
329 #define RF_FRFLSB_915_MHZ 0x00 // Default
330 #define RF_FRFMSB_916_MHZ 0xE5
331 #define RF_FRFMID_916_MHZ 0x00
332 #define RF_FRFLSB_916_MHZ 0x00
333 #define RF_FRFMSB_917_MHZ 0xE5
334 #define RF_FRFMID_917_MHZ 0x40
335 #define RF_FRFLSB_917_MHZ 0x00
336 #define RF_FRFMSB_918_MHZ 0xE5
337 #define RF_FRFMID_918_MHZ 0x80
338 #define RF_FRFLSB_918_MHZ 0x00
339 #define RF_FRFMSB_919_MHZ 0xE5
340 #define RF_FRFMID_919_MHZ 0xC0
341 #define RF_FRFLSB_919_MHZ 0x00
342 #define RF_FRFMSB_920_MHZ 0xE6
343 #define RF_FRFMID_920_MHZ 0x00
344 #define RF_FRFLSB_920_MHZ 0x00
345 #define RF_FRFMSB_921_MHZ 0xE6
346 #define RF_FRFMID_921_MHZ 0x40
347 #define RF_FRFLSB_921_MHZ 0x00
348 #define RF_FRFMSB_922_MHZ 0xE6
349 #define RF_FRFMID_922_MHZ 0x80
350 #define RF_FRFLSB_922_MHZ 0x00
351 #define RF_FRFMSB_923_MHZ 0xE6
352 #define RF_FRFMID_923_MHZ 0xC0
353 #define RF_FRFLSB_923_MHZ 0x00
354 #define RF_FRFMSB_924_MHZ 0xE7
355 #define RF_FRFMID_924_MHZ 0x00
356 #define RF_FRFLSB_924_MHZ 0x00
357 #define RF_FRFMSB_925_MHZ 0xE7
358 #define RF_FRFMID_925_MHZ 0x40
359 #define RF_FRFLSB_925_MHZ 0x00
360 #define RF_FRFMSB_926_MHZ 0xE7
361 #define RF_FRFMID_926_MHZ 0x80
362 #define RF_FRFLSB_926_MHZ 0x00
363 #define RF_FRFMSB_927_MHZ 0xE7
364 #define RF_FRFMID_927_MHZ 0xC0
365 #define RF_FRFLSB_927_MHZ 0x00
366 #define RF_FRFMSB_928_MHZ 0xE8
367 #define RF_FRFMID_928_MHZ 0x00
368 #define RF_FRFLSB_928_MHZ 0x00
369 
370 /*!
371  * RegPaConfig
372  */
373 #define RF_PACONFIG_PASELECT_MASK 0x7F
374 #define RF_PACONFIG_PASELECT_PABOOST 0x80
375 #define RF_PACONFIG_PASELECT_RFO 0x00 // Default
376 
377 #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0
378 
379 /*!
380  * RegPaRamp
381  */
382 #define RF_PARAMP_LOWPNTXPLL_MASK 0xEF
383 #define RF_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
384 #define RF_PARAMP_LOWPNTXPLL_ON 0x00
385 
386 #define RF_PARAMP_MASK 0xF0
387 #define RF_PARAMP_3400_US 0x00
388 #define RF_PARAMP_2000_US 0x01
389 #define RF_PARAMP_1000_US 0x02
390 #define RF_PARAMP_0500_US 0x03
391 #define RF_PARAMP_0250_US 0x04
392 #define RF_PARAMP_0125_US 0x05
393 #define RF_PARAMP_0100_US 0x06
394 #define RF_PARAMP_0062_US 0x07
395 #define RF_PARAMP_0050_US 0x08
396 #define RF_PARAMP_0040_US 0x09 // Default
397 #define RF_PARAMP_0031_US 0x0A
398 #define RF_PARAMP_0025_US 0x0B
399 #define RF_PARAMP_0020_US 0x0C
400 #define RF_PARAMP_0015_US 0x0D
401 #define RF_PARAMP_0012_US 0x0E
402 #define RF_PARAMP_0010_US 0x0F
403 
404 /*!
405  * RegOcp
406  */
407 #define RF_OCP_MASK 0xDF
408 #define RF_OCP_ON 0x20 // Default
409 #define RF_OCP_OFF 0x00
410 
411 #define RF_OCP_TRIM_MASK 0xE0
412 #define RF_OCP_TRIM_045_MA 0x00
413 #define RF_OCP_TRIM_050_MA 0x01
414 #define RF_OCP_TRIM_055_MA 0x02
415 #define RF_OCP_TRIM_060_MA 0x03
416 #define RF_OCP_TRIM_065_MA 0x04
417 #define RF_OCP_TRIM_070_MA 0x05
418 #define RF_OCP_TRIM_075_MA 0x06
419 #define RF_OCP_TRIM_080_MA 0x07
420 #define RF_OCP_TRIM_085_MA 0x08
421 #define RF_OCP_TRIM_090_MA 0x09
422 #define RF_OCP_TRIM_095_MA 0x0A
423 #define RF_OCP_TRIM_100_MA 0x0B // Default
424 #define RF_OCP_TRIM_105_MA 0x0C
425 #define RF_OCP_TRIM_110_MA 0x0D
426 #define RF_OCP_TRIM_115_MA 0x0E
427 #define RF_OCP_TRIM_120_MA 0x0F
428 #define RF_OCP_TRIM_130_MA 0x10
429 #define RF_OCP_TRIM_140_MA 0x11
430 #define RF_OCP_TRIM_150_MA 0x12
431 #define RF_OCP_TRIM_160_MA 0x13
432 #define RF_OCP_TRIM_170_MA 0x14
433 #define RF_OCP_TRIM_180_MA 0x15
434 #define RF_OCP_TRIM_190_MA 0x16
435 #define RF_OCP_TRIM_200_MA 0x17
436 #define RF_OCP_TRIM_210_MA 0x18
437 #define RF_OCP_TRIM_220_MA 0x19
438 #define RF_OCP_TRIM_230_MA 0x1A
439 #define RF_OCP_TRIM_240_MA 0x1B
440 
441 /*!
442  * RegLna
443  */
444 #define RF_LNA_GAIN_MASK 0x1F
445 #define RF_LNA_GAIN_G1 0x20 // Default
446 #define RF_LNA_GAIN_G2 0x40
447 #define RF_LNA_GAIN_G3 0x60
448 #define RF_LNA_GAIN_G4 0x80
449 #define RF_LNA_GAIN_G5 0xA0
450 #define RF_LNA_GAIN_G6 0xC0
451 
452 #define RF_LNA_BOOST_MASK 0xFC
453 #define RF_LNA_BOOST_OFF 0x00 // Default
454 #define RF_LNA_BOOST_ON 0x03
455 
456 /*!
457  * RegRxConfig
458  */
459 #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F
460 #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80
461 #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default
462 
463 #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only
464 
465 #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only
466 
467 #define RF_RXCONFIG_AFCAUTO_MASK 0xEF
468 #define RF_RXCONFIG_AFCAUTO_ON 0x10
469 #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default
470 
471 #define RF_RXCONFIG_AGCAUTO_MASK 0xF7
472 #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default
473 #define RF_RXCONFIG_AGCAUTO_OFF 0x00
474 
475 #define RF_RXCONFIG_RXTRIGER_MASK 0xF8
476 #define RF_RXCONFIG_RXTRIGER_OFF 0x00
477 #define RF_RXCONFIG_RXTRIGER_RSSI 0x01
478 #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default
479 #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07
480 
481 /*!
482  * RegRssiConfig
483  */
484 #define RF_RSSICONFIG_OFFSET_MASK 0x07
485 #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default
486 #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08
487 #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10
488 #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18
489 #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20
490 #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28
491 #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30
492 #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38
493 #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40
494 #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48
495 #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50
496 #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58
497 #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60
498 #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68
499 #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70
500 #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78
501 #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80
502 #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88
503 #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90
504 #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98
505 #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0
506 #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8
507 #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0
508 #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8
509 #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0
510 #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8
511 #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0
512 #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8
513 #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0
514 #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8
515 #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0
516 #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8
517 
518 #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8
519 #define RF_RSSICONFIG_SMOOTHING_2 0x00
520 #define RF_RSSICONFIG_SMOOTHING_4 0x01
521 #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default
522 #define RF_RSSICONFIG_SMOOTHING_16 0x03
523 #define RF_RSSICONFIG_SMOOTHING_32 0x04
524 #define RF_RSSICONFIG_SMOOTHING_64 0x05
525 #define RF_RSSICONFIG_SMOOTHING_128 0x06
526 #define RF_RSSICONFIG_SMOOTHING_256 0x07
527 
528 /*!
529  * RegRssiCollision
530  */
531 #define RF_RSSICOLISION_THRESHOLD 0x0A // Default
532 
533 /*!
534  * RegRssiThresh
535  */
536 #define RF_RSSITHRESH_THRESHOLD 0xFF // Default
537 
538 /*!
539  * RegRssiValue (Read Only)
540  */
541 
542 /*!
543  * RegRxBw
544  */
545 #define RF_RXBW_MANT_MASK 0xE7
546 #define RF_RXBW_MANT_16 0x00
547 #define RF_RXBW_MANT_20 0x08
548 #define RF_RXBW_MANT_24 0x10 // Default
549 
550 #define RF_RXBW_EXP_MASK 0xF8
551 #define RF_RXBW_EXP_0 0x00
552 #define RF_RXBW_EXP_1 0x01
553 #define RF_RXBW_EXP_2 0x02
554 #define RF_RXBW_EXP_3 0x03
555 #define RF_RXBW_EXP_4 0x04
556 #define RF_RXBW_EXP_5 0x05 // Default
557 #define RF_RXBW_EXP_6 0x06
558 #define RF_RXBW_EXP_7 0x07
559 
560 /*!
561  * RegAfcBw
562  */
563 #define RF_AFCBW_MANTAFC_MASK 0xE7
564 #define RF_AFCBW_MANTAFC_16 0x00
565 #define RF_AFCBW_MANTAFC_20 0x08 // Default
566 #define RF_AFCBW_MANTAFC_24 0x10
567 
568 #define RF_AFCBW_EXPAFC_MASK 0xF8
569 #define RF_AFCBW_EXPAFC_0 0x00
570 #define RF_AFCBW_EXPAFC_1 0x01
571 #define RF_AFCBW_EXPAFC_2 0x02
572 #define RF_AFCBW_EXPAFC_3 0x03 // Default
573 #define RF_AFCBW_EXPAFC_4 0x04
574 #define RF_AFCBW_EXPAFC_5 0x05
575 #define RF_AFCBW_EXPAFC_6 0x06
576 #define RF_AFCBW_EXPAFC_7 0x07
577 
578 /*!
579  * RegOokPeak
580  */
581 #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default
582 #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default
583 #define RF_OOKPEAK_BITSYNC_OFF 0x00
584 
585 #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7
586 #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00
587 #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default
588 #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10
589 
590 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8
591 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default
592 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01
593 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02
594 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03
595 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04
596 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05
597 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06
598 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07
599 
600 /*!
601  * RegOokFix
602  */
603 #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default
604 
605 /*!
606  * RegOokAvg
607  */
608 #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F
609 #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default
610 #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20
611 #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40
612 #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60
613 #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80
614 #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0
615 #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0
616 #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0
617 
618 #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3
619 #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default
620 #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04
621 #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08
622 #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C
623 
624 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC
625 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00
626 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01
627 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default
628 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03
629 
630 /*!
631  * RegAfcFei
632  */
633 #define RF_AFCFEI_AGCSTART 0x10
634 
635 #define RF_AFCFEI_AFCCLEAR 0x02
636 
637 #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE
638 #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01
639 #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
640 
641 /*!
642  * RegAfcMsb (Read Only)
643  */
644 
645 /*!
646  * RegAfcLsb (Read Only)
647  */
648 
649 /*!
650  * RegFeiMsb (Read Only)
651  */
652 
653 /*!
654  * RegFeiLsb (Read Only)
655  */
656 
657 /*!
658  * RegPreambleDetect
659  */
660 #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F
661 #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default
662 #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00
663 
664 #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F
665 #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00
666 #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default
667 #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40
668 #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60
669 
670 #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0
671 #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00
672 #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01
673 #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02
674 #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03
675 #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04
676 #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05
677 #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06
678 #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07
679 #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08
680 #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09
681 #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default
682 #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B
683 #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C
684 #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D
685 #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E
686 #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F
687 #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10
688 #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11
689 #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12
690 #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13
691 #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14
692 #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15
693 #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16
694 #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17
695 #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18
696 #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19
697 #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A
698 #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B
699 #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C
700 #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D
701 #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E
702 #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F
703 
704 /*!
705  * RegRxTimeout1
706  */
707 #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default
708 
709 /*!
710  * RegRxTimeout2
711  */
712 #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default
713 
714 /*!
715  * RegRxTimeout3
716  */
717 #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default
718 
719 /*!
720  * RegRxDelay
721  */
722 #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default
723 
724 /*!
725  * RegOsc
726  */
727 #define RF_OSC_RCCALSTART 0x08
728 
729 #define RF_OSC_CLKOUT_MASK 0xF8
730 #define RF_OSC_CLKOUT_32_MHZ 0x00
731 #define RF_OSC_CLKOUT_16_MHZ 0x01
732 #define RF_OSC_CLKOUT_8_MHZ 0x02
733 #define RF_OSC_CLKOUT_4_MHZ 0x03
734 #define RF_OSC_CLKOUT_2_MHZ 0x04
735 #define RF_OSC_CLKOUT_1_MHZ 0x05
736 #define RF_OSC_CLKOUT_RC 0x06
737 #define RF_OSC_CLKOUT_OFF 0x07 // Default
738 
739 /*!
740  * RegPreambleMsb/RegPreambleLsb
741  */
742 #define RF_PREAMBLEMSB_SIZE 0x00 // Default
743 #define RF_PREAMBLELSB_SIZE 0x03 // Default
744 
745 /*!
746  * RegSyncConfig
747  */
748 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F
749 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default
750 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40
751 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00
752 
753 
754 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF
755 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20
756 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default
757 
758 #define RF_SYNCCONFIG_SYNC_MASK 0xEF
759 #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default
760 #define RF_SYNCCONFIG_SYNC_OFF 0x00
761 
762 #define RF_SYNCCONFIG_FIFOFILLCONDITION_MASK 0xF7
763 #define RF_SYNCCONFIG_FIFOFILLCONDITION_AUTO 0x00 // Default
764 #define RF_SYNCCONFIG_FIFOFILLCONDITION_MANUAL 0x08
765 
766 #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8
767 #define RF_SYNCCONFIG_SYNCSIZE_1 0x00
768 #define RF_SYNCCONFIG_SYNCSIZE_2 0x01
769 #define RF_SYNCCONFIG_SYNCSIZE_3 0x02
770 #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default
771 #define RF_SYNCCONFIG_SYNCSIZE_5 0x04
772 #define RF_SYNCCONFIG_SYNCSIZE_6 0x05
773 #define RF_SYNCCONFIG_SYNCSIZE_7 0x06
774 #define RF_SYNCCONFIG_SYNCSIZE_8 0x07
775 
776 /*!
777  * RegSyncValue1-8
778  */
779 #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default
780 #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default
781 #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default
782 #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default
783 #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default
784 #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default
785 #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default
786 #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default
787 
788 /*!
789  * RegPacketConfig1
790  */
791 #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F
792 #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00
793 #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default
794 
795 #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F
796 #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default
797 #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20
798 #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40
799 
800 #define RF_PACKETCONFIG1_CRC_MASK 0xEF
801 #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default
802 #define RF_PACKETCONFIG1_CRC_OFF 0x00
803 
804 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7
805 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default
806 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
807 
808 #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9
809 #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default
810 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02
811 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04
812 
813 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE
814 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default
815 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01
816 
817 /*!
818  * RegPacketConfig2
819  */
820 #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF
821 #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00
822 #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default
823 
824 #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF
825 #define RF_PACKETCONFIG2_IOHOME_ON 0x20
826 #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default
827 
828 #define RF_PACKETCONFIG2_BEACON_MASK 0xF7
829 #define RF_PACKETCONFIG2_BEACON_ON 0x08
830 #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default
831 
832 #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8
833 
834 /*!
835  * RegPayloadLength
836  */
837 #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default
838 
839 /*!
840  * RegNodeAdrs
841  */
842 #define RF_NODEADDRESS_ADDRESS 0x00
843 
844 /*!
845  * RegBroadcastAdrs
846  */
847 #define RF_BROADCASTADDRESS_ADDRESS 0x00
848 
849 /*!
850  * RegFifoThresh
851  */
852 #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F
853 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00
854 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 // Default
855 
856 #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0
857 #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default
858 
859 /*!
860  * RegSeqConfig1
861  */
862 #define RF_SEQCONFIG1_SEQUENCER_START 0x80
863 
864 #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40
865 
866 #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF
867 #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20
868 #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default
869 
870 #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7
871 #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default
872 #define RF_SEQCONFIG1_FROMSTART_TORX 0x08
873 #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10
874 #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18
875 
876 #define RF_SEQCONFIG1_LPS_MASK 0xFB
877 #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default
878 #define RF_SEQCONFIG1_LPS_IDLE 0x04
879 
880 #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD
881 #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default
882 #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02
883 
884 #define RF_SEQCONFIG1_FROMTX_MASK 0xFE
885 #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default
886 #define RF_SEQCONFIG1_FROMTX_TORX 0x01
887 
888 /*!
889  * RegSeqConfig2
890  */
891 #define RF_SEQCONFIG2_FROMRX_MASK 0x1F
892 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default
893 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20
894 #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40
895 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60
896 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80
897 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0
898 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0
899 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0
900 
901 #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7
902 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default
903 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08
904 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10
905 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18
906 
907 #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8
908 #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default
909 #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01
910 #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02
911 #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03
912 #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04
913 
914 /*!
915  * RegTimerResol
916  */
917 #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3
918 #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default
919 #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04
920 #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08
921 #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C
922 
923 #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC
924 #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default
925 #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01
926 #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02
927 #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03
928 
929 /*!
930  * RegTimer1Coef
931  */
932 #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default
933 
934 /*!
935  * RegTimer2Coef
936  */
937 #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default
938 
939 /*!
940  * RegImageCal
941  */
942 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F
943 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80
944 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default
945 
946 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF
947 #define RF_IMAGECAL_IMAGECAL_START 0x40
948 
949 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20
950 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default
951 
952 #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08
953 #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00
954 
955 #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9
956 #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00
957 #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default
958 #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04
959 #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06
960 
961 #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE
962 #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default
963 #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01
964 
965 /*!
966  * RegTemp (Read Only)
967  */
968 
969 /*!
970  * RegLowBat
971  */
972 #define RF_LOWBAT_MASK 0xF7
973 #define RF_LOWBAT_ON 0x08
974 #define RF_LOWBAT_OFF 0x00 // Default
975 
976 #define RF_LOWBAT_TRIM_MASK 0xF8
977 #define RF_LOWBAT_TRIM_1695 0x00
978 #define RF_LOWBAT_TRIM_1764 0x01
979 #define RF_LOWBAT_TRIM_1835 0x02 // Default
980 #define RF_LOWBAT_TRIM_1905 0x03
981 #define RF_LOWBAT_TRIM_1976 0x04
982 #define RF_LOWBAT_TRIM_2045 0x05
983 #define RF_LOWBAT_TRIM_2116 0x06
984 #define RF_LOWBAT_TRIM_2185 0x07
985 
986 /*!
987  * RegIrqFlags1
988  */
989 #define RF_IRQFLAGS1_MODEREADY 0x80
990 
991 #define RF_IRQFLAGS1_RXREADY 0x40
992 
993 #define RF_IRQFLAGS1_TXREADY 0x20
994 
995 #define RF_IRQFLAGS1_PLLLOCK 0x10
996 
997 #define RF_IRQFLAGS1_RSSI 0x08
998 
999 #define RF_IRQFLAGS1_TIMEOUT 0x04
1000 
1001 #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02
1002 
1003 #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01
1004 
1005 /*!
1006  * RegIrqFlags2
1007  */
1008 #define RF_IRQFLAGS2_FIFOFULL 0x80
1009 
1010 #define RF_IRQFLAGS2_FIFOEMPTY 0x40
1011 
1012 #define RF_IRQFLAGS2_FIFOLEVEL 0x20
1013 
1014 #define RF_IRQFLAGS2_FIFOOVERRUN 0x10
1015 
1016 #define RF_IRQFLAGS2_PACKETSENT 0x08
1017 
1018 #define RF_IRQFLAGS2_PAYLOADREADY 0x04
1019 
1020 #define RF_IRQFLAGS2_CRCOK 0x02
1021 
1022 #define RF_IRQFLAGS2_LOWBAT 0x01
1023 
1024 /*!
1025  * RegDioMapping1
1026  */
1027 #define RF_DIOMAPPING1_DIO0_MASK 0x3F
1028 #define RF_DIOMAPPING1_DIO0_00 0x00 // Default
1029 #define RF_DIOMAPPING1_DIO0_01 0x40
1030 #define RF_DIOMAPPING1_DIO0_10 0x80
1031 #define RF_DIOMAPPING1_DIO0_11 0xC0
1032 
1033 #define RF_DIOMAPPING1_DIO1_MASK 0xCF
1034 #define RF_DIOMAPPING1_DIO1_00 0x00 // Default
1035 #define RF_DIOMAPPING1_DIO1_01 0x10
1036 #define RF_DIOMAPPING1_DIO1_10 0x20
1037 #define RF_DIOMAPPING1_DIO1_11 0x30
1038 
1039 #define RF_DIOMAPPING1_DIO2_MASK 0xF3
1040 #define RF_DIOMAPPING1_DIO2_00 0x00 // Default
1041 #define RF_DIOMAPPING1_DIO2_01 0x04
1042 #define RF_DIOMAPPING1_DIO2_10 0x08
1043 #define RF_DIOMAPPING1_DIO2_11 0x0C
1044 
1045 #define RF_DIOMAPPING1_DIO3_MASK 0xFC
1046 #define RF_DIOMAPPING1_DIO3_00 0x00 // Default
1047 #define RF_DIOMAPPING1_DIO3_01 0x01
1048 #define RF_DIOMAPPING1_DIO3_10 0x02
1049 #define RF_DIOMAPPING1_DIO3_11 0x03
1050 
1051 /*!
1052  * RegDioMapping2
1053  */
1054 #define RF_DIOMAPPING2_DIO4_MASK 0x3F
1055 #define RF_DIOMAPPING2_DIO4_00 0x00 // Default
1056 #define RF_DIOMAPPING2_DIO4_01 0x40
1057 #define RF_DIOMAPPING2_DIO4_10 0x80
1058 #define RF_DIOMAPPING2_DIO4_11 0xC0
1059 
1060 #define RF_DIOMAPPING2_DIO5_MASK 0xCF
1061 #define RF_DIOMAPPING2_DIO5_00 0x00 // Default
1062 #define RF_DIOMAPPING2_DIO5_01 0x10
1063 #define RF_DIOMAPPING2_DIO5_10 0x20
1064 #define RF_DIOMAPPING2_DIO5_11 0x30
1065 
1066 #define RF_DIOMAPPING2_MAP_MASK 0xFE
1067 #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
1068 #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default
1069 
1070 /*!
1071  * RegVersion (Read Only)
1072  */
1073 
1074 /*!
1075  * RegAgcRef
1076  */
1077 
1078 /*!
1079  * RegAgcThresh1
1080  */
1081 
1082 /*!
1083  * RegAgcThresh2
1084  */
1085 
1086 /*!
1087  * RegAgcThresh3
1088  */
1089 
1090 /*!
1091  * RegPllHop
1092  */
1093 #define RF_PLLHOP_FASTHOP_MASK 0x7F
1094 #define RF_PLLHOP_FASTHOP_ON 0x80
1095 #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default
1096 
1097 /*!
1098  * RegTcxo
1099  */
1100 #define RF_TCXO_TCXOINPUT_MASK 0xEF
1101 #define RF_TCXO_TCXOINPUT_ON 0x10
1102 #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default
1103 
1104 /*!
1105  * RegPaDac
1106  */
1107 #define RF_PADAC_20DBM_MASK 0xF8
1108 #define RF_PADAC_20DBM_ON 0x07
1109 #define RF_PADAC_20DBM_OFF 0x04 // Default
1110 
1111 /*!
1112  * RegPll
1113  */
1114 #define RF_PLL_BANDWIDTH_MASK 0x3F
1115 #define RF_PLL_BANDWIDTH_75 0x00
1116 #define RF_PLL_BANDWIDTH_150 0x40
1117 #define RF_PLL_BANDWIDTH_225 0x80
1118 #define RF_PLL_BANDWIDTH_300 0xC0 // Default
1119 
1120 /*!
1121  * RegPllLowPn
1122  */
1123 #define RF_PLLLOWPN_BANDWIDTH_MASK 0x3F
1124 #define RF_PLLLOWPN_BANDWIDTH_75 0x00
1125 #define RF_PLLLOWPN_BANDWIDTH_150 0x40
1126 #define RF_PLLLOWPN_BANDWIDTH_225 0x80
1127 #define RF_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
1128 
1129 /*!
1130  * RegFormerTemp
1131  */
1132 
1133 /*!
1134  * RegBitrateFrac
1135  */
1136 #define RF_BITRATEFRAC_MASK 0xF0
1137 
1138 #endif // __SX1272_REGS_FSK_H__
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