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driver_defs.h
1 /**************************************************************************************
2 * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved *
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34 
35 
36 
37 #ifndef _DRIVER_DEFS_H_
38 #define _DRIVER_DEFS_H_
39 
40 #ifdef __KERNEL__
41 #include <linux/types.h>
42 #define INT32_MAX 0x7FFFFFFFL
43 #else
44 #include <stdint.h>
45 #endif
46 
47 #ifndef min
48 #define min(a, b) ((a) < (b) ? (a) : (b))
49 #endif
50 
51 /******************************************************************************
52 * TYPE DEFINITIONS
53 ******************************************************************************/
54 typedef uint32_t drvError_t;
55 
56 typedef enum aesMode {
57  CIPHER_NULL_MODE = -1,
58  CIPHER_ECB = 0,
59  CIPHER_CBC = 1,
60  CIPHER_CTR = 2,
61  CIPHER_CBC_MAC = 3,
62  CIPHER_CMAC = 7,
63  CIPHER_RESERVE32B = INT32_MAX
64 }aesMode_t;
65 
66 typedef enum hashMode {
67  HASH_NULL_MODE = -1,
68  HASH_SHA1 = 0,
69  HASH_SHA256 = 1,
70  HASH_SHA224 = 2,
71  HASH_SHA512 = 3,
72  HASH_SHA384 = 4,
73  HASH_RESERVE32B = INT32_MAX
74 }hashMode_t;
75 
76 typedef enum DataBlockType {
77  FIRST_BLOCK,
78  MIDDLE_BLOCK,
79  LAST_BLOCK,
80  RESERVE32B_BLOCK = INT32_MAX
81 }DataBlockType_t;
82 
83 typedef enum dataAddrType {
84  SRAM_ADDR = 0,
85  DLLI_ADDR = 1,
86  ADDR_RESERVE32B = INT32_MAX
87 }dataAddrType_t;
88 
89 typedef enum cryptoDirection {
90  CRYPTO_DIRECTION_ENCRYPT = 0,
91  CRYPTO_DIRECTION_DECRYPT = 1,
92 
93  CRYPTO_DIRECTION_NUM_OF_ENC_MODES,
94  CRYPTO_DIRECTION_RESERVE32B = INT32_MAX
95 }cryptoDirection_t;
96 
97 typedef enum cryptoKeyType {
98  RKEK_KEY = 0,
99  USER_KEY = 1,
100  PROVISIONING_KEY = 2,
101  SESSION_KEY = 3,
102  END_OF_KEYS = INT32_MAX,
103 }cryptoKeyType_t;
104 
105 typedef enum cryptoPaddingType {
106  CRYPTO_PADDING_NONE = 0,
107  CRYPTO_PADDING_PKCS7 = 1,
108  CRYPTO_PADDING_RESERVE32B = INT32_MAX
109 }cryptoPaddingType_t;
110 
111 typedef enum chachaNonceSize {
112  NONCE_SIZE_64 = 0,
113  NONCE_SIZE_96 = 1,
114  NONCE_SIZE_RESERVE32B = INT32_MAX
115 }chachaNonceSize_t;
116 
117 /* The IOT drviers base address */
118 #define DRV_MODULE_ERROR_BASE 0x00F00000
119 #define AES_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x10000UL)
120 #define HASH_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x20000UL)
121 #define HMAC_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x30000UL)
122 #define BYPASS_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x40000UL)
123 #define CHACHA_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x50000UL)
124 
125 
126 /******************************************************************************
127 * AES DEFINITIONS
128 ******************************************************************************/
129 
130 #define AES_BLOCK_SIZE 16
131 #define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE >> 2)
132 #define AES_IV_SIZE 16
133 #define AES_IV_SIZE_WORDS (AES_IV_SIZE >> 2)
134 #define AES_128_BIT_KEY_SIZE 16
135 #define AES_128_BIT_KEY_SIZE_WORDS (AES_128_BIT_KEY_SIZE >> 2)
136 
137 
138 #define ENABLE_AES_CLOCK 0x1UL
139 #define DISABLE_AES_CLOCK 0x0UL
140 
141 #define CONFIG_DIN_AES_DOUT_VAL 0x1UL
142 
143 /* The CRYS AES module errors */
144 #define AES_DRV_OK 0
145 #define AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x00UL)
146 #define AES_DRV_ILLEGAL_OPERATION_MODE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x01UL)
147 #define AES_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x02UL)
148 #define AES_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x03UL)
149 #define AES_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x04UL)
150 #define AES_DRV_ILLEGAL_MEM_SIZE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x05UL)
151 
152 
153 /******************************************************************************
154 * HASH & HMAC DEFINITIONS
155 ******************************************************************************/
156 
157 /************************ Typedefs ****************************/
158 typedef drvError_t (*llf_hash_init_operation_func)(void *);
159 typedef drvError_t (*llf_hash_update_operation_func)(void *, uint32_t inputDataAddr, uint32_t dataInSize);
160 typedef drvError_t (*llf_hash_finish_operation_func)(void *);
161 
162 
163 /* The SHA-1 digest result size */
164 #define SHA1_DIGEST_SIZE_IN_WORDS 5
165 #define SHA1_DIGEST_SIZE_IN_BYTES (SHA1_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
166 
167 /* The SHA-256 digest result size*/
168 #define SHA224_DIGEST_SIZE_IN_WORDS 7
169 #define SHA224_DIGEST_SIZE_IN_BYTES (SHA224_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
170 
171 /* The SHA-256 digest result size */
172 #define SHA256_DIGEST_SIZE_IN_WORDS 8
173 #define SHA256_DIGEST_SIZE_IN_BYTES (SHA256_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
174 
175 /* The SHA-384 digest result size*/
176 #define SHA384_DIGEST_SIZE_IN_WORDS 12
177 #define SHA384_DIGEST_SIZE_IN_BYTES (SHA384_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
178 
179 /* The SHA-512 digest result size in bytes */
180 #define SHA512_DIGEST_SIZE_IN_WORDS 16
181 #define SHA512_DIGEST_SIZE_IN_BYTES (SHA512_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
182 
183 
184 #define MAX_DIGEST_SIZE_WORDS SHA512_DIGEST_SIZE_IN_WORDS
185 
186 /* Hash driver registers configurations */
187 #define ENABLE_HASH_CLOCK 0x1UL
188 #define DISABLE_HASH_CLOCK 0x0UL
189 
190 #define HW_HASH_CTL_SHA1_VAL 0x0001UL
191 #define HW_HASH_CTL_SHA256_VAL 0x0002UL
192 #define HW_HASH_LE_MODE_VAL 0x0001UL
193 #define HW_HASH_PAD_EN_VAL 0x1UL
194 
195 /* The SHA1 hash block size in words */
196 #define HASH_BLOCK_SIZE_IN_WORDS 16
197 #define HASH_BLOCK_SIZE_IN_BYTES (HASH_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t))
198 
199 /* The SHA2 hash block size in words */
200 #define HASH_SHA512_BLOCK_SIZE_IN_WORDS 32
201 #define HASH_SHA512_BLOCK_SIZE_IN_BYTES (HASH_SHA512_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t))
202 
203 #define CONFIG_HASH_MODE_VAL 0x7UL
204 
205 /* the MAC key IPAD and OPAD bytes */
206 #define MAC_KEY_IPAD_BYTE 0x36
207 #define MAC_KEY_OPAD_BYTE 0x5C
208 
209 #define HMAC_CONTEXT_VALIDATION_TAG 0x23456789
210 
211 /* The CRYS HASH module errors */
212 #define HASH_DRV_OK 0
213 #define HASH_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x00UL)
214 #define HASH_DRV_ILLEGAL_OPERATION_MODE_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x01UL)
215 #define HASH_DRV_USER_CONTEXT_CORRUPTED_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x02UL)
216 
217 /* The CRYS HMAC module errors */
218 #define HMAC_DRV_OK 0
219 #define HMAC_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (HMAC_DRV_MODULE_ERROR_BASE + 0x00UL)
220 
221 
222 /* SHA512 soft driver */
223 
224 /* The first padding byte */
225 #define LLF_HASH_FIRST_PADDING_BYTE 0x80
226 /* The size at the end of the padding for SHA384 and SHA512 */
227 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_BYTES (4 * sizeof(uint32_t))
228 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_WORDS 4
229 
230 /* the HASH user context validity TAG */
231 #define HASH_CONTEXT_VALIDATION_TAG 0x12345678
232 
233 /******************************************************************************
234 * BYPASS DEFINITIONS
235 ******************************************************************************/
236 
237 #define CONFIG_DIN_BYPASS_DOUT_VAL 0
238 
239 /* The CRYS BYPASS module errors */
240 #define BYPASS_DRV_OK 0
241 #define BYPASS_DRV_ILLEGAL_BLOCK_SIZE_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x01UL)
242 #define BYPASS_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x02UL)
243 #define BYPASS_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x03UL)
244 
245 /******************************************************************************
246 * CHACHA DEFINITIONS
247 ******************************************************************************/
248 
249 #define CHACHA_BLOCK_SIZE_BYTES 64
250 #define CHACHA_BLOCK_SIZE_WORDS (CHACHA_BLOCK_SIZE_BYTES >> 2)
251 #define CHACHA_NONCE_64_SIZE_BYTES 8
252 #define CHACHA_NONCE_64_SIZE_WORDS (CHACHA_NONCE_64_SIZE_BYTES >> 2)
253 #define CHACHA_NONCE_96_SIZE_BYTES 12
254 #define CHACHA_NONCE_96_SIZE_WORDS (CHACHA_NONCE_96_SIZE_BYTES >> 2)
255 #define CHACHA_256_BIT_KEY_SIZE 32
256 #define CHACHA_256_BIT_KEY_SIZE_WORDS (CHACHA_256_BIT_KEY_SIZE >> 2)
257 
258 #define ENABLE_CHACHA_CLOCK 0x1UL
259 #define DISABLE_CHACHA_CLOCK 0x0UL
260 
261 #define CONFIG_DIN_CHACHA_DOUT_VAL 0x10UL
262 
263 /* The CRYS CHACHA module errors */
264 #define CHACHA_DRV_OK 0
265 #define CHACHA_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x00UL)
266 #define CHACHA_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x01UL)
267 #define CHACHA_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x02UL)
268 #define CHACHA_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x03UL)
269 #define CHACHA_DRV_ILLEGAL_MEM_SIZE_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x04UL)
270 #define CHACHA_DRV_ILLEGAL_NONCE_SIZE_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x05UL)
271 
272 
273 /******************************************************************************
274 * MACROS
275 ******************************************************************************/
276 /* This MACRO purpose is to switch from CryptoCell definitions to crypto driver definitions, the MACRO assumes that the value is legal (encrypt or decrypt only) */
277 #define SASI_2_DRIVER_DIRECTION(ssiDirection) ((ssiDirection == SASI_AES_ENCRYPT) ? (CRYPTO_DIRECTION_ENCRYPT) : (CRYPTO_DIRECTION_DECRYPT))
278 
279 /* Poll on the DOUT MEM DMA (DLLI) busy till it is = 0 */
280 #define SASI_HAL_WAIT_ON_DOUT_MEM_DMA_BUSY()\
281  do {\
282  uint32_t regVal=1;\
283  do {\
284  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DOUT_MEM_DMA_BUSY));\
285  }while( regVal ); \
286  }while(0)
287 
288 /* Poll on the DIN MEM DMA (DLLI) busy till it is = 0 */
289 #define SASI_HAL_WAIT_ON_DIN_MEM_DMA_BUSY()\
290  do {\
291  uint32_t regVal=1;\
292  do {\
293  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DIN_MEM_DMA_BUSY));\
294  }while( regVal );\
295  }while(0)
296 
297 /* Poll on the DOUT SRAM DMA busy till it is = 0 */
298 #define SASI_HAL_WAIT_ON_DOUT_SRAM_DMA_BUSY()\
299  do {\
300  uint32_t regVal=1; \
301  do {\
302  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DOUT_SRAM_DMA_BUSY));\
303  }while( regVal );\
304  }while(0)
305 
306 /* Poll on the DIN SRAM busy till it is = 0 */
307 #define SASI_HAL_WAIT_ON_DIN_SRAM_DMA_BUSY()\
308  do {\
309  uint32_t regVal=1;\
310  do {\
311  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DIN_SRAM_DMA_BUSY));\
312  }while( regVal );\
313  }while(0)
314 
315 
316 /* Poll on the AES busy till it is = 0 */
317 #define SASI_HAL_WAIT_ON_AES_BUSY()\
318  do {\
319  uint32_t regVal=1;\
320  do {\
321  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, AES_BUSY));\
322  }while( regVal );\
323  }while(0)
324 
325 /* Poll on the HASH busy till it is = 0 */
326 #define SASI_HAL_WAIT_ON_HASH_BUSY()\
327  do {\
328  uint32_t regVal=1;\
329  do {\
330  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, HASH_BUSY));\
331  }while( regVal );\
332  }while(0)
333 
334 /* Poll on the CHACHA busy till it is = 0 */
335 #define SASI_HAL_WAIT_ON_CHACHA_BUSY() \
336  do { \
337  uint32_t regVal=1; \
338  do { \
339  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, CHACHA_BUSY)); \
340  }while( regVal ); \
341  }while(0)
342 
343 /* Poll on the crypto busy till it is = 0 */
344 #define SASI_HAL_WAIT_ON_CRYPTO_BUSY()\
345  do {\
346  uint32_t regVal=1;\
347  do {\
348  regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, CRYPTO_BUSY));\
349  }while( regVal );\
350  }while(0)
351 
352 
353 #endif /* _DRIVER_DEFS_H_ */
354 
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