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W25Q32JV_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_W25Q32JV_H
18 #define MBED_QSPI_FLASH_W25Q32JV_H
19 
20 
21 #define QSPI_FLASH_CHIP_STRING "Winbond W25Q32JV"
22 
23 // Command for reading status register
24 #define QSPI_CMD_RDSR 0x05
25 // Command for reading configuration register
26 #define QSPI_CMD_RDCR0 0x35
27 #define QSPI_CMD_RDCR1 0x15
28 // Command for writing status/configuration register
29 #define QSPI_CMD_WRSR 0x01
30 // Command for writing configuration register
31 #define QSPI_CMD_WRCR0 0x31
32 #define QSPI_CMD_WRCR1 0x11
33 // Command for reading security register
34 #define QSPI_CMD_RDSCUR 0x48
35 
36 // Command for setting Reset Enable
37 #define QSPI_CMD_RSTEN 0x66
38 // Command for setting Reset
39 #define QSPI_CMD_RST 0x99
40 
41 // Command for setting write enable
42 #define QSPI_CMD_WREN 0x06
43 // Command for setting write disable
44 #define QSPI_CMD_WRDI 0x04
45 
46 // WRSR operations max time [us] (datasheet max time + 15%)
47 #define QSPI_WRSR_MAX_TIME 34500 // 30ms
48 // general wait max time [us]
49 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
50 
51 
52 // Commands for writing (page programming)
53 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
54 
55 // write operations max time [us] (datasheet max time + 15%)
56 #define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
57 
58 #define QSPI_PAGE_SIZE 256 // 256B
59 #define QSPI_SECTOR_SIZE 4096 // 4kB
60 #define QSPI_SECTOR_COUNT 1024
61 
62 // Commands for reading
63 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
64 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
65 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
66 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
67 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
68 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
69 
70 #define QSPI_READ_1IO_DUMMY_CYCLE 0
71 #define QSPI_READ_FAST_DUMMY_CYCLE 8
72 #define QSPI_READ_2IO_DUMMY_CYCLE 4
73 #define QSPI_READ_1I2O_DUMMY_CYCLE 8
74 #define QSPI_READ_4IO_DUMMY_CYCLE 6
75 #define QSPI_READ_1I4O_DUMMY_CYCLE 8
76 
77 // Commands for erasing
78 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
79 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
80 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
81 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
82 
83 // erase operations max time [us] (datasheet max time + 15%)
84 #define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
85 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
86 #define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
87 
88 // max frequency for basic rw operation (for fast mode)
89 #define QSPI_COMMON_MAX_FREQUENCY 32000000
90 
91 #define QSPI_STATUS_REG_SIZE 1
92 #define QSPI_CONFIG_REG_0_SIZE 1
93 #define QSPI_CONFIG_REG_1_SIZE 1
94 
95 #define QSPI_SECURITY_REG_SIZE 1
96 #define QSPI_MAX_REG_SIZE 1
97 
98 // status register
99 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
100 #define STATUS_BIT_WEL (1 << 1) // write enable latch
101 #define STATUS_BIT_BP0 (1 << 2) // block protect 0
102 #define STATUS_BIT_BP1 (1 << 3) // block protect 1
103 #define STATUS_BIT_BP2 (1 << 4) // block protect 2
104 #define STATUS_BIT_BP_TB (1 << 5) // block protect top/bottom
105 #define STATUS_BIT_SP (1 << 6) // sector protect
106 #define STATUS_BIT_SRWD (1 << 7) // status register protect
107 
108 // configuration register 0
109 // bit 2 reserved
110 #define CONFIG0_BIT_SRL (1 << 0) // status register lock
111 #define CONFIG0_BIT_QE (1 << 1) // quad enable
112 #define CONFIG0_BIT_LB1 (1 << 3) // security register lock 1
113 #define CONFIG0_BIT_LB2 (1 << 4) // security register lock 2
114 #define CONFIG0_BIT_LB3 (1 << 5) // security register lock 3
115 #define CONFIG0_BIT_CMP (1 << 6) // complement protect
116 #define CONFIG0_BIT_SUS (1 << 7) // suspend status
117 
118 // configuration register 1
119 // bits 0, 1, 3, 4, 7 reserved
120 #define CONFIG1_BIT_WPS (1 << 2) // write protect selection
121 #define CONFIG1_BIT_DRV2 (1 << 5) // output driver strength 2
122 #define CONFIG1_BIT_DRV1 (1 << 6) // output driver strength 1
123 
124 
125 
126 #define QUAD_ENABLE() \
127  \
128  uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
129  \
130  memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
131  if (read_register(QSPI_CMD_RDCR0, reg_data, \
132  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
133  return QSPI_STATUS_ERROR; \
134  } \
135  if (write_enable(qspi) != QSPI_STATUS_OK) { \
136  return QSPI_STATUS_ERROR; \
137  } \
138  \
139  reg_data[0] = reg_data[0] & ~(CONFIG0_BIT_QE); \
140  if (write_register(QSPI_CMD_WRCR0, reg_data, \
141  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
142  return QSPI_STATUS_ERROR; \
143  } \
144  qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
145  WAIT_FOR(WRSR_MAX_TIME, qspi); \
146  memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
147  if (read_register(QSPI_CMD_RDCR0, reg_data, \
148  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
149  return QSPI_STATUS_ERROR; \
150  } \
151  \
152  return ((reg_data[0] & (CONFIG0_BIT_QE)) == 0 ? \
153  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
154 
155 
156 #define QUAD_DISABLE() \
157  \
158  uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
159  \
160  memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
161  if (read_register(QSPI_CMD_RDCR0, reg_data, \
162  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
163  return QSPI_STATUS_ERROR; \
164  } \
165  if (write_enable(qspi) != QSPI_STATUS_OK) { \
166  return QSPI_STATUS_ERROR; \
167  } \
168  \
169  reg_data[0] = reg_data[0] | (CONFIG0_BIT_QE); \
170  if (write_register(QSPI_CMD_WRCR0, reg_data, \
171  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
172  return QSPI_STATUS_ERROR; \
173  } \
174  WAIT_FOR(WRSR_MAX_TIME, qspi); \
175  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
176  memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
177  if (read_register(QSPI_CMD_RDCR0, reg_data, \
178  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
179  return QSPI_STATUS_ERROR; \
180  } \
181  \
182  return ((reg_data[0] & CONFIG0_BIT_QE) != 1 ? \
183  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
184 
185 #endif // MBED_QSPI_FLASH_W25Q32JV_H
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