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sx1272Regs-LoRa.h
1 /**
2  / _____) _ | |
3 ( (____ _____ ____ _| |_ _____ ____| |__
4  \____ \| ___ | (_ _) ___ |/ ___) _ \
5  _____) ) ____| | | || |_| ____( (___| | | |
6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
7  (C) 2015 Semtech
8 
9 Description: SX1272 LoRa modem registers and bits definitions
10 
11 License: Revised BSD License, see LICENSE.TXT file include in the project
12 
13 Maintainer: Miguel Luis and Gregory Cristian
14 
15 Copyright (c) 2017, Arm Limited and affiliates.
16 
17 SPDX-License-Identifier: BSD-3-Clause
18 */
19 #ifndef __SX1272_REGS_LORA_H__
20 #define __SX1272_REGS_LORA_H__
21 
22 /*!
23  * ============================================================================
24  * SX1272 Internal registers Address
25  * ============================================================================
26  */
27 #define REG_LR_FIFO 0x00
28 // Common settings
29 #define REG_LR_OPMODE 0x01
30 #define REG_LR_FRFMSB 0x06
31 #define REG_LR_FRFMID 0x07
32 #define REG_LR_FRFLSB 0x08
33 // Tx settings
34 #define REG_LR_PACONFIG 0x09
35 #define REG_LR_PARAMP 0x0A
36 #define REG_LR_OCP 0x0B
37 // Rx settings
38 #define REG_LR_LNA 0x0C
39 // LoRa registers
40 #define REG_LR_FIFOADDRPTR 0x0D
41 #define REG_LR_FIFOTXBASEADDR 0x0E
42 #define REG_LR_FIFORXBASEADDR 0x0F
43 #define REG_LR_FIFORXCURRENTADDR 0x10
44 #define REG_LR_IRQFLAGSMASK 0x11
45 #define REG_LR_IRQFLAGS 0x12
46 #define REG_LR_RXNBBYTES 0x13
47 #define REG_LR_RXHEADERCNTVALUEMSB 0x14
48 #define REG_LR_RXHEADERCNTVALUELSB 0x15
49 #define REG_LR_RXPACKETCNTVALUEMSB 0x16
50 #define REG_LR_RXPACKETCNTVALUELSB 0x17
51 #define REG_LR_MODEMSTAT 0x18
52 #define REG_LR_PKTSNRVALUE 0x19
53 #define REG_LR_PKTRSSIVALUE 0x1A
54 #define REG_LR_RSSIVALUE 0x1B
55 #define REG_LR_HOPCHANNEL 0x1C
56 #define REG_LR_MODEMCONFIG1 0x1D
57 #define REG_LR_MODEMCONFIG2 0x1E
58 #define REG_LR_SYMBTIMEOUTLSB 0x1F
59 #define REG_LR_PREAMBLEMSB 0x20
60 #define REG_LR_PREAMBLELSB 0x21
61 #define REG_LR_PAYLOADLENGTH 0x22
62 #define REG_LR_PAYLOADMAXLENGTH 0x23
63 #define REG_LR_HOPPERIOD 0x24
64 #define REG_LR_FIFORXBYTEADDR 0x25
65 #define REG_LR_FEIMSB 0x28
66 #define REG_LR_FEIMID 0x29
67 #define REG_LR_FEILSB 0x2A
68 #define REG_LR_RSSIWIDEBAND 0x2C
69 #define REG_LR_DETECTOPTIMIZE 0x31
70 #define REG_LR_INVERTIQ 0x33
71 #define REG_LR_DETECTIONTHRESHOLD 0x37
72 #define REG_LR_SYNCWORD 0x39
73 #define REG_LR_INVERTIQ2 0x3B
74 
75 // end of documented register in datasheet
76 // I/O settings
77 #define REG_LR_DIOMAPPING1 0x40
78 #define REG_LR_DIOMAPPING2 0x41
79 // Version
80 #define REG_LR_VERSION 0x42
81 // Additional settings
82 #define REG_LR_AGCREF 0x43
83 #define REG_LR_AGCTHRESH1 0x44
84 #define REG_LR_AGCTHRESH2 0x45
85 #define REG_LR_AGCTHRESH3 0x46
86 #define REG_LR_PLLHOP 0x4B
87 #define REG_LR_TCXO 0x58
88 #define REG_LR_PADAC 0x5A
89 #define REG_LR_PLL 0x5C
90 #define REG_LR_PLLLOWPN 0x5E
91 #define REG_LR_FORMERTEMP 0x6C
92 
93 /*!
94  * ============================================================================
95  * SX1272 LoRa bits control definition
96  * ============================================================================
97  */
98 
99 /*!
100  * RegFifo
101  */
102 
103 /*!
104  * RegOpMode
105  */
106 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
107 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
108 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
109 
110 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
111 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
112 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
113 
114 #define RFLR_OPMODE_MASK 0xF8
115 #define RFLR_OPMODE_SLEEP 0x00
116 #define RFLR_OPMODE_STANDBY 0x01 // Default
117 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02
118 #define RFLR_OPMODE_TRANSMITTER 0x03
119 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04
120 #define RFLR_OPMODE_RECEIVER 0x05
121 // LoRa specific modes
122 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06
123 #define RFLR_OPMODE_CAD 0x07
124 
125 /*!
126  * RegFrf (MHz)
127  */
128 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default
129 #define RFLR_FRFMID_915_MHZ 0xC0 // Default
130 #define RFLR_FRFLSB_915_MHZ 0x00 // Default
131 
132 /*!
133  * RegPaConfig
134  */
135 #define RFLR_PACONFIG_PASELECT_MASK 0x7F
136 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80
137 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
138 
139 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
140 
141 /*!
142  * RegPaRamp
143  */
144 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0
145 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
146 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00
147 
148 #define RFLR_PARAMP_MASK 0xF0
149 #define RFLR_PARAMP_3400_US 0x00
150 #define RFLR_PARAMP_2000_US 0x01
151 #define RFLR_PARAMP_1000_US 0x02
152 #define RFLR_PARAMP_0500_US 0x03
153 #define RFLR_PARAMP_0250_US 0x04
154 #define RFLR_PARAMP_0125_US 0x05
155 #define RFLR_PARAMP_0100_US 0x06
156 #define RFLR_PARAMP_0062_US 0x07
157 #define RFLR_PARAMP_0050_US 0x08
158 #define RFLR_PARAMP_0040_US 0x09 // Default
159 #define RFLR_PARAMP_0031_US 0x0A
160 #define RFLR_PARAMP_0025_US 0x0B
161 #define RFLR_PARAMP_0020_US 0x0C
162 #define RFLR_PARAMP_0015_US 0x0D
163 #define RFLR_PARAMP_0012_US 0x0E
164 #define RFLR_PARAMP_0010_US 0x0F
165 
166 /*!
167  * RegOcp
168  */
169 #define RFLR_OCP_MASK 0xDF
170 #define RFLR_OCP_ON 0x20 // Default
171 #define RFLR_OCP_OFF 0x00
172 
173 #define RFLR_OCP_TRIM_MASK 0xE0
174 #define RFLR_OCP_TRIM_045_MA 0x00
175 #define RFLR_OCP_TRIM_050_MA 0x01
176 #define RFLR_OCP_TRIM_055_MA 0x02
177 #define RFLR_OCP_TRIM_060_MA 0x03
178 #define RFLR_OCP_TRIM_065_MA 0x04
179 #define RFLR_OCP_TRIM_070_MA 0x05
180 #define RFLR_OCP_TRIM_075_MA 0x06
181 #define RFLR_OCP_TRIM_080_MA 0x07
182 #define RFLR_OCP_TRIM_085_MA 0x08
183 #define RFLR_OCP_TRIM_090_MA 0x09
184 #define RFLR_OCP_TRIM_095_MA 0x0A
185 #define RFLR_OCP_TRIM_100_MA 0x0B // Default
186 #define RFLR_OCP_TRIM_105_MA 0x0C
187 #define RFLR_OCP_TRIM_110_MA 0x0D
188 #define RFLR_OCP_TRIM_115_MA 0x0E
189 #define RFLR_OCP_TRIM_120_MA 0x0F
190 #define RFLR_OCP_TRIM_130_MA 0x10
191 #define RFLR_OCP_TRIM_140_MA 0x11
192 #define RFLR_OCP_TRIM_150_MA 0x12
193 #define RFLR_OCP_TRIM_160_MA 0x13
194 #define RFLR_OCP_TRIM_170_MA 0x14
195 #define RFLR_OCP_TRIM_180_MA 0x15
196 #define RFLR_OCP_TRIM_190_MA 0x16
197 #define RFLR_OCP_TRIM_200_MA 0x17
198 #define RFLR_OCP_TRIM_210_MA 0x18
199 #define RFLR_OCP_TRIM_220_MA 0x19
200 #define RFLR_OCP_TRIM_230_MA 0x1A
201 #define RFLR_OCP_TRIM_240_MA 0x1B
202 
203 /*!
204  * RegLna
205  */
206 #define RFLR_LNA_GAIN_MASK 0x1F
207 #define RFLR_LNA_GAIN_G1 0x20 // Default
208 #define RFLR_LNA_GAIN_G2 0x40
209 #define RFLR_LNA_GAIN_G3 0x60
210 #define RFLR_LNA_GAIN_G4 0x80
211 #define RFLR_LNA_GAIN_G5 0xA0
212 #define RFLR_LNA_GAIN_G6 0xC0
213 
214 #define RFLR_LNA_BOOST_MASK 0xFC
215 #define RFLR_LNA_BOOST_OFF 0x00 // Default
216 #define RFLR_LNA_BOOST_ON 0x03
217 
218 /*!
219  * RegFifoAddrPtr
220  */
221 #define RFLR_FIFOADDRPTR 0x00 // Default
222 
223 /*!
224  * RegFifoTxBaseAddr
225  */
226 #define RFLR_FIFOTXBASEADDR 0x80 // Default
227 
228 /*!
229  * RegFifoTxBaseAddr
230  */
231 #define RFLR_FIFORXBASEADDR 0x00 // Default
232 
233 /*!
234  * RegFifoRxCurrentAddr (Read Only)
235  */
236 
237 /*!
238  * RegIrqFlagsMask
239  */
240 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
241 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40
242 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
243 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
244 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08
245 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04
246 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
247 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
248 
249 /*!
250  * RegIrqFlags
251  */
252 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80
253 #define RFLR_IRQFLAGS_RXDONE 0x40
254 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
255 #define RFLR_IRQFLAGS_VALIDHEADER 0x10
256 #define RFLR_IRQFLAGS_TXDONE 0x08
257 #define RFLR_IRQFLAGS_CADDONE 0x04
258 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
259 #define RFLR_IRQFLAGS_CADDETECTED 0x01
260 
261 /*!
262  * RegFifoRxNbBytes (Read Only)
263  */
264 
265 /*!
266  * RegRxHeaderCntValueMsb (Read Only)
267  */
268 
269 /*!
270  * RegRxHeaderCntValueLsb (Read Only)
271  */
272 
273 /*!
274  * RegRxPacketCntValueMsb (Read Only)
275  */
276 
277 /*!
278  * RegRxPacketCntValueLsb (Read Only)
279  */
280 
281 /*!
282  * RegModemStat (Read Only)
283  */
284 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
285 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
286 
287 /*!
288  * RegPktSnrValue (Read Only)
289  */
290 
291 /*!
292  * RegPktRssiValue (Read Only)
293  */
294 
295 /*!
296  * RegRssiValue (Read Only)
297  */
298 
299 /*!
300  * RegHopChannel (Read Only)
301  */
302 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
303 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
304 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
305 
306 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
307 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
308 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
309 
310 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
311 
312 /*!
313  * RegModemConfig1
314  */
315 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F
316 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default
317 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40
318 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80
319 
320 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7
321 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08
322 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default
323 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18
324 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20
325 
326 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB
327 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04
328 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
329 
330 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD
331 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02
332 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default
333 
334 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE
335 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01
336 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
337 
338 /*!
339  * RegModemConfig2
340  */
341 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F
342 #define RFLR_MODEMCONFIG2_SF_6 0x60
343 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
344 #define RFLR_MODEMCONFIG2_SF_8 0x80
345 #define RFLR_MODEMCONFIG2_SF_9 0x90
346 #define RFLR_MODEMCONFIG2_SF_10 0xA0
347 #define RFLR_MODEMCONFIG2_SF_11 0xB0
348 #define RFLR_MODEMCONFIG2_SF_12 0xC0
349 
350 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
351 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
352 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
353 
354 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB
355 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default
356 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00
357 
358 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
359 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
360 
361 /*!
362  * RegSymbTimeoutLsb
363  */
364 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
365 
366 /*!
367  * RegPreambleLengthMsb
368  */
369 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default
370 
371 /*!
372  * RegPreambleLengthLsb
373  */
374 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default
375 
376 /*!
377  * RegPayloadLength
378  */
379 #define RFLR_PAYLOADLENGTH 0x0E // Default
380 
381 /*!
382  * RegPayloadMaxLength
383  */
384 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default
385 
386 /*!
387  * RegHopPeriod
388  */
389 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
390 
391 /*!
392  * RegFifoRxByteAddr (Read Only)
393  */
394 
395 /*!
396  * RegFeiMsb (Read Only)
397  */
398 
399 /*!
400  * RegFeiMid (Read Only)
401  */
402 
403 /*!
404  * RegFeiLsb (Read Only)
405  */
406 
407 /*!
408  * RegRssiWideband (Read Only)
409  */
410 
411 /*!
412  * RegDetectOptimize
413  */
414 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
415 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
416 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05
417 
418 /*!
419  * RegInvertIQ
420  */
421 #define RFLR_INVERTIQ_RX_MASK 0xBF
422 #define RFLR_INVERTIQ_RX_OFF 0x00
423 #define RFLR_INVERTIQ_RX_ON 0x40
424 #define RFLR_INVERTIQ_TX_MASK 0xFE
425 #define RFLR_INVERTIQ_TX_OFF 0x01
426 #define RFLR_INVERTIQ_TX_ON 0x00
427 
428 /*!
429  * RegDetectionThreshold
430  */
431 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
432 #define RFLR_DETECTIONTHRESH_SF6 0x0C
433 
434 /*!
435  * RegInvertIQ2
436  */
437 #define RFLR_INVERTIQ2_ON 0x19
438 #define RFLR_INVERTIQ2_OFF 0x1D
439 
440 /*!
441  * RegDioMapping1
442  */
443 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
444 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
445 #define RFLR_DIOMAPPING1_DIO0_01 0x40
446 #define RFLR_DIOMAPPING1_DIO0_10 0x80
447 #define RFLR_DIOMAPPING1_DIO0_11 0xC0
448 
449 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
450 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
451 #define RFLR_DIOMAPPING1_DIO1_01 0x10
452 #define RFLR_DIOMAPPING1_DIO1_10 0x20
453 #define RFLR_DIOMAPPING1_DIO1_11 0x30
454 
455 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
456 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
457 #define RFLR_DIOMAPPING1_DIO2_01 0x04
458 #define RFLR_DIOMAPPING1_DIO2_10 0x08
459 #define RFLR_DIOMAPPING1_DIO2_11 0x0C
460 
461 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
462 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
463 #define RFLR_DIOMAPPING1_DIO3_01 0x01
464 #define RFLR_DIOMAPPING1_DIO3_10 0x02
465 #define RFLR_DIOMAPPING1_DIO3_11 0x03
466 
467 /*!
468  * RegDioMapping2
469  */
470 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
471 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
472 #define RFLR_DIOMAPPING2_DIO4_01 0x40
473 #define RFLR_DIOMAPPING2_DIO4_10 0x80
474 #define RFLR_DIOMAPPING2_DIO4_11 0xC0
475 
476 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
477 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
478 #define RFLR_DIOMAPPING2_DIO5_01 0x10
479 #define RFLR_DIOMAPPING2_DIO5_10 0x20
480 #define RFLR_DIOMAPPING2_DIO5_11 0x30
481 
482 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE
483 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
484 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
485 
486 /*!
487  * RegVersion (Read Only)
488  */
489 
490 /*!
491  * RegAgcRef
492  */
493 
494 /*!
495  * RegAgcThresh1
496  */
497 
498 /*!
499  * RegAgcThresh2
500  */
501 
502 /*!
503  * RegAgcThresh3
504  */
505 
506 /*!
507  * RegPllHop
508  */
509 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F
510 #define RFLR_PLLHOP_FASTHOP_ON 0x80
511 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
512 
513 /*!
514  * RegTcxo
515  */
516 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF
517 #define RFLR_TCXO_TCXOINPUT_ON 0x10
518 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
519 
520 /*!
521  * RegPaDac
522  */
523 #define RFLR_PADAC_20DBM_MASK 0xF8
524 #define RFLR_PADAC_20DBM_ON 0x07
525 #define RFLR_PADAC_20DBM_OFF 0x04 // Default
526 
527 /*!
528  * RegPll
529  */
530 #define RFLR_PLL_BANDWIDTH_MASK 0x3F
531 #define RFLR_PLL_BANDWIDTH_75 0x00
532 #define RFLR_PLL_BANDWIDTH_150 0x40
533 #define RFLR_PLL_BANDWIDTH_225 0x80
534 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
535 
536 /*!
537  * RegPllLowPn
538  */
539 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
540 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
541 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
542 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
543 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
544 
545 /*!
546  * RegFormerTemp
547  */
548 
549 #endif // __SX1272_REGS_LORA_H__
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