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sx1276Regs-Fsk.h
1 /**
2  / _____) _ | |
3 ( (____ _____ ____ _| |_ _____ ____| |__
4  \____ \| ___ | (_ _) ___ |/ ___) _ \
5  _____) ) ____| | | || |_| ____( (___| | | |
6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
7  (C) 2014 Semtech
8 
9 Description: SX1276 FSK modem registers and bits definitions
10 
11 License: Revised BSD License, see LICENSE.TXT file include in the project
12 
13 Maintainer: Miguel Luis and Gregory Cristian
14 
15 Copyright (c) 2017, Arm Limited and affiliates.
16 
17 SPDX-License-Identifier: BSD-3-Clause
18 */
19 #ifndef __SX1276_REGS_FSK_H__
20 #define __SX1276_REGS_FSK_H__
21 
22 /*!
23  * ============================================================================
24  * SX1276 Internal registers Address
25  * ============================================================================
26  */
27 #define REG_FIFO 0x00
28 // Common settings
29 #define REG_OPMODE 0x01
30 #define REG_BITRATEMSB 0x02
31 #define REG_BITRATELSB 0x03
32 #define REG_FDEVMSB 0x04
33 #define REG_FDEVLSB 0x05
34 #define REG_FRFMSB 0x06
35 #define REG_FRFMID 0x07
36 #define REG_FRFLSB 0x08
37 // Tx settings
38 #define REG_PACONFIG 0x09
39 #define REG_PARAMP 0x0A
40 #define REG_OCP 0x0B
41 // Rx settings
42 #define REG_LNA 0x0C
43 #define REG_RXCONFIG 0x0D
44 #define REG_RSSICONFIG 0x0E
45 #define REG_RSSICOLLISION 0x0F
46 #define REG_RSSITHRESH 0x10
47 #define REG_RSSIVALUE 0x11
48 #define REG_RXBW 0x12
49 #define REG_AFCBW 0x13
50 #define REG_OOKPEAK 0x14
51 #define REG_OOKFIX 0x15
52 #define REG_OOKAVG 0x16
53 #define REG_RES17 0x17
54 #define REG_RES18 0x18
55 #define REG_RES19 0x19
56 #define REG_AFCFEI 0x1A
57 #define REG_AFCMSB 0x1B
58 #define REG_AFCLSB 0x1C
59 #define REG_FEIMSB 0x1D
60 #define REG_FEILSB 0x1E
61 #define REG_PREAMBLEDETECT 0x1F
62 #define REG_RXTIMEOUT1 0x20
63 #define REG_RXTIMEOUT2 0x21
64 #define REG_RXTIMEOUT3 0x22
65 #define REG_RXDELAY 0x23
66 // Oscillator settings
67 #define REG_OSC 0x24
68 // Packet handler settings
69 #define REG_PREAMBLEMSB 0x25
70 #define REG_PREAMBLELSB 0x26
71 #define REG_SYNCCONFIG 0x27
72 #define REG_SYNCVALUE1 0x28
73 #define REG_SYNCVALUE2 0x29
74 #define REG_SYNCVALUE3 0x2A
75 #define REG_SYNCVALUE4 0x2B
76 #define REG_SYNCVALUE5 0x2C
77 #define REG_SYNCVALUE6 0x2D
78 #define REG_SYNCVALUE7 0x2E
79 #define REG_SYNCVALUE8 0x2F
80 #define REG_PACKETCONFIG1 0x30
81 #define REG_PACKETCONFIG2 0x31
82 #define REG_PAYLOADLENGTH 0x32
83 #define REG_NODEADRS 0x33
84 #define REG_BROADCASTADRS 0x34
85 #define REG_FIFOTHRESH 0x35
86 // SM settings
87 #define REG_SEQCONFIG1 0x36
88 #define REG_SEQCONFIG2 0x37
89 #define REG_TIMERRESOL 0x38
90 #define REG_TIMER1COEF 0x39
91 #define REG_TIMER2COEF 0x3A
92 // Service settings
93 #define REG_IMAGECAL 0x3B
94 #define REG_TEMP 0x3C
95 #define REG_LOWBAT 0x3D
96 // Status
97 #define REG_IRQFLAGS1 0x3E
98 #define REG_IRQFLAGS2 0x3F
99 // I/O settings
100 #define REG_DIOMAPPING1 0x40
101 #define REG_DIOMAPPING2 0x41
102 // Version
103 #define REG_VERSION 0x42
104 // Additional settings
105 #define REG_PLLHOP 0x44
106 #define REG_TCXO 0x4B
107 #define REG_PADAC 0x4D
108 #define REG_FORMERTEMP 0x5B
109 #define REG_BITRATEFRAC 0x5D
110 #define REG_AGCREF 0x61
111 #define REG_AGCTHRESH1 0x62
112 #define REG_AGCTHRESH2 0x63
113 #define REG_AGCTHRESH3 0x64
114 #define REG_PLL 0x70
115 
116 /*!
117  * ============================================================================
118  * SX1276 FSK bits control definition
119  * ============================================================================
120  */
121 
122 /*!
123  * RegFifo
124  */
125 
126 /*!
127  * RegOpMode
128  */
129 #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F
130 #define RF_OPMODE_LONGRANGEMODE_OFF 0x00
131 #define RF_OPMODE_LONGRANGEMODE_ON 0x80
132 
133 #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F
134 #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default
135 #define RF_OPMODE_MODULATIONTYPE_OOK 0x20
136 
137 #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7
138 #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default
139 #define RF_OPMODE_MODULATIONSHAPING_01 0x08
140 #define RF_OPMODE_MODULATIONSHAPING_10 0x10
141 #define RF_OPMODE_MODULATIONSHAPING_11 0x18
142 
143 #define RF_OPMODE_MASK 0xF8
144 #define RF_OPMODE_SLEEP 0x00
145 #define RF_OPMODE_STANDBY 0x01 // Default
146 #define RF_OPMODE_SYNTHESIZER_TX 0x02
147 #define RF_OPMODE_TRANSMITTER 0x03
148 #define RF_OPMODE_SYNTHESIZER_RX 0x04
149 #define RF_OPMODE_RECEIVER 0x05
150 
151 /*!
152  * RegBitRate (bits/sec)
153  */
154 #define RF_BITRATEMSB_1200_BPS 0x68
155 #define RF_BITRATELSB_1200_BPS 0x2B
156 #define RF_BITRATEMSB_2400_BPS 0x34
157 #define RF_BITRATELSB_2400_BPS 0x15
158 #define RF_BITRATEMSB_4800_BPS 0x1A // Default
159 #define RF_BITRATELSB_4800_BPS 0x0B // Default
160 #define RF_BITRATEMSB_9600_BPS 0x0D
161 #define RF_BITRATELSB_9600_BPS 0x05
162 #define RF_BITRATEMSB_15000_BPS 0x08
163 #define RF_BITRATELSB_15000_BPS 0x55
164 #define RF_BITRATEMSB_19200_BPS 0x06
165 #define RF_BITRATELSB_19200_BPS 0x83
166 #define RF_BITRATEMSB_38400_BPS 0x03
167 #define RF_BITRATELSB_38400_BPS 0x41
168 #define RF_BITRATEMSB_76800_BPS 0x01
169 #define RF_BITRATELSB_76800_BPS 0xA1
170 #define RF_BITRATEMSB_153600_BPS 0x00
171 #define RF_BITRATELSB_153600_BPS 0xD0
172 #define RF_BITRATEMSB_57600_BPS 0x02
173 #define RF_BITRATELSB_57600_BPS 0x2C
174 #define RF_BITRATEMSB_115200_BPS 0x01
175 #define RF_BITRATELSB_115200_BPS 0x16
176 #define RF_BITRATEMSB_12500_BPS 0x0A
177 #define RF_BITRATELSB_12500_BPS 0x00
178 #define RF_BITRATEMSB_25000_BPS 0x05
179 #define RF_BITRATELSB_25000_BPS 0x00
180 #define RF_BITRATEMSB_50000_BPS 0x02
181 #define RF_BITRATELSB_50000_BPS 0x80
182 #define RF_BITRATEMSB_100000_BPS 0x01
183 #define RF_BITRATELSB_100000_BPS 0x40
184 #define RF_BITRATEMSB_150000_BPS 0x00
185 #define RF_BITRATELSB_150000_BPS 0xD5
186 #define RF_BITRATEMSB_200000_BPS 0x00
187 #define RF_BITRATELSB_200000_BPS 0xA0
188 #define RF_BITRATEMSB_250000_BPS 0x00
189 #define RF_BITRATELSB_250000_BPS 0x80
190 #define RF_BITRATEMSB_32768_BPS 0x03
191 #define RF_BITRATELSB_32768_BPS 0xD1
192 
193 /*!
194  * RegFdev (Hz)
195  */
196 #define RF_FDEVMSB_2000_HZ 0x00
197 #define RF_FDEVLSB_2000_HZ 0x21
198 #define RF_FDEVMSB_5000_HZ 0x00 // Default
199 #define RF_FDEVLSB_5000_HZ 0x52 // Default
200 #define RF_FDEVMSB_10000_HZ 0x00
201 #define RF_FDEVLSB_10000_HZ 0xA4
202 #define RF_FDEVMSB_15000_HZ 0x00
203 #define RF_FDEVLSB_15000_HZ 0xF6
204 #define RF_FDEVMSB_20000_HZ 0x01
205 #define RF_FDEVLSB_20000_HZ 0x48
206 #define RF_FDEVMSB_25000_HZ 0x01
207 #define RF_FDEVLSB_25000_HZ 0x9A
208 #define RF_FDEVMSB_30000_HZ 0x01
209 #define RF_FDEVLSB_30000_HZ 0xEC
210 #define RF_FDEVMSB_35000_HZ 0x02
211 #define RF_FDEVLSB_35000_HZ 0x3D
212 #define RF_FDEVMSB_40000_HZ 0x02
213 #define RF_FDEVLSB_40000_HZ 0x8F
214 #define RF_FDEVMSB_45000_HZ 0x02
215 #define RF_FDEVLSB_45000_HZ 0xE1
216 #define RF_FDEVMSB_50000_HZ 0x03
217 #define RF_FDEVLSB_50000_HZ 0x33
218 #define RF_FDEVMSB_55000_HZ 0x03
219 #define RF_FDEVLSB_55000_HZ 0x85
220 #define RF_FDEVMSB_60000_HZ 0x03
221 #define RF_FDEVLSB_60000_HZ 0xD7
222 #define RF_FDEVMSB_65000_HZ 0x04
223 #define RF_FDEVLSB_65000_HZ 0x29
224 #define RF_FDEVMSB_70000_HZ 0x04
225 #define RF_FDEVLSB_70000_HZ 0x7B
226 #define RF_FDEVMSB_75000_HZ 0x04
227 #define RF_FDEVLSB_75000_HZ 0xCD
228 #define RF_FDEVMSB_80000_HZ 0x05
229 #define RF_FDEVLSB_80000_HZ 0x1F
230 #define RF_FDEVMSB_85000_HZ 0x05
231 #define RF_FDEVLSB_85000_HZ 0x71
232 #define RF_FDEVMSB_90000_HZ 0x05
233 #define RF_FDEVLSB_90000_HZ 0xC3
234 #define RF_FDEVMSB_95000_HZ 0x06
235 #define RF_FDEVLSB_95000_HZ 0x14
236 #define RF_FDEVMSB_100000_HZ 0x06
237 #define RF_FDEVLSB_100000_HZ 0x66
238 #define RF_FDEVMSB_110000_HZ 0x07
239 #define RF_FDEVLSB_110000_HZ 0x0A
240 #define RF_FDEVMSB_120000_HZ 0x07
241 #define RF_FDEVLSB_120000_HZ 0xAE
242 #define RF_FDEVMSB_130000_HZ 0x08
243 #define RF_FDEVLSB_130000_HZ 0x52
244 #define RF_FDEVMSB_140000_HZ 0x08
245 #define RF_FDEVLSB_140000_HZ 0xF6
246 #define RF_FDEVMSB_150000_HZ 0x09
247 #define RF_FDEVLSB_150000_HZ 0x9A
248 #define RF_FDEVMSB_160000_HZ 0x0A
249 #define RF_FDEVLSB_160000_HZ 0x3D
250 #define RF_FDEVMSB_170000_HZ 0x0A
251 #define RF_FDEVLSB_170000_HZ 0xE1
252 #define RF_FDEVMSB_180000_HZ 0x0B
253 #define RF_FDEVLSB_180000_HZ 0x85
254 #define RF_FDEVMSB_190000_HZ 0x0C
255 #define RF_FDEVLSB_190000_HZ 0x29
256 #define RF_FDEVMSB_200000_HZ 0x0C
257 #define RF_FDEVLSB_200000_HZ 0xCD
258 
259 /*!
260  * RegFrf (MHz)
261  */
262 #define RF_FRFMSB_863_MHZ 0xD7
263 #define RF_FRFMID_863_MHZ 0xC0
264 #define RF_FRFLSB_863_MHZ 0x00
265 #define RF_FRFMSB_864_MHZ 0xD8
266 #define RF_FRFMID_864_MHZ 0x00
267 #define RF_FRFLSB_864_MHZ 0x00
268 #define RF_FRFMSB_865_MHZ 0xD8
269 #define RF_FRFMID_865_MHZ 0x40
270 #define RF_FRFLSB_865_MHZ 0x00
271 #define RF_FRFMSB_866_MHZ 0xD8
272 #define RF_FRFMID_866_MHZ 0x80
273 #define RF_FRFLSB_866_MHZ 0x00
274 #define RF_FRFMSB_867_MHZ 0xD8
275 #define RF_FRFMID_867_MHZ 0xC0
276 #define RF_FRFLSB_867_MHZ 0x00
277 #define RF_FRFMSB_868_MHZ 0xD9
278 #define RF_FRFMID_868_MHZ 0x00
279 #define RF_FRFLSB_868_MHZ 0x00
280 #define RF_FRFMSB_869_MHZ 0xD9
281 #define RF_FRFMID_869_MHZ 0x40
282 #define RF_FRFLSB_869_MHZ 0x00
283 #define RF_FRFMSB_870_MHZ 0xD9
284 #define RF_FRFMID_870_MHZ 0x80
285 #define RF_FRFLSB_870_MHZ 0x00
286 
287 #define RF_FRFMSB_902_MHZ 0xE1
288 #define RF_FRFMID_902_MHZ 0x80
289 #define RF_FRFLSB_902_MHZ 0x00
290 #define RF_FRFMSB_903_MHZ 0xE1
291 #define RF_FRFMID_903_MHZ 0xC0
292 #define RF_FRFLSB_903_MHZ 0x00
293 #define RF_FRFMSB_904_MHZ 0xE2
294 #define RF_FRFMID_904_MHZ 0x00
295 #define RF_FRFLSB_904_MHZ 0x00
296 #define RF_FRFMSB_905_MHZ 0xE2
297 #define RF_FRFMID_905_MHZ 0x40
298 #define RF_FRFLSB_905_MHZ 0x00
299 #define RF_FRFMSB_906_MHZ 0xE2
300 #define RF_FRFMID_906_MHZ 0x80
301 #define RF_FRFLSB_906_MHZ 0x00
302 #define RF_FRFMSB_907_MHZ 0xE2
303 #define RF_FRFMID_907_MHZ 0xC0
304 #define RF_FRFLSB_907_MHZ 0x00
305 #define RF_FRFMSB_908_MHZ 0xE3
306 #define RF_FRFMID_908_MHZ 0x00
307 #define RF_FRFLSB_908_MHZ 0x00
308 #define RF_FRFMSB_909_MHZ 0xE3
309 #define RF_FRFMID_909_MHZ 0x40
310 #define RF_FRFLSB_909_MHZ 0x00
311 #define RF_FRFMSB_910_MHZ 0xE3
312 #define RF_FRFMID_910_MHZ 0x80
313 #define RF_FRFLSB_910_MHZ 0x00
314 #define RF_FRFMSB_911_MHZ 0xE3
315 #define RF_FRFMID_911_MHZ 0xC0
316 #define RF_FRFLSB_911_MHZ 0x00
317 #define RF_FRFMSB_912_MHZ 0xE4
318 #define RF_FRFMID_912_MHZ 0x00
319 #define RF_FRFLSB_912_MHZ 0x00
320 #define RF_FRFMSB_913_MHZ 0xE4
321 #define RF_FRFMID_913_MHZ 0x40
322 #define RF_FRFLSB_913_MHZ 0x00
323 #define RF_FRFMSB_914_MHZ 0xE4
324 #define RF_FRFMID_914_MHZ 0x80
325 #define RF_FRFLSB_914_MHZ 0x00
326 #define RF_FRFMSB_915_MHZ 0xE4 // Default
327 #define RF_FRFMID_915_MHZ 0xC0 // Default
328 #define RF_FRFLSB_915_MHZ 0x00 // Default
329 #define RF_FRFMSB_916_MHZ 0xE5
330 #define RF_FRFMID_916_MHZ 0x00
331 #define RF_FRFLSB_916_MHZ 0x00
332 #define RF_FRFMSB_917_MHZ 0xE5
333 #define RF_FRFMID_917_MHZ 0x40
334 #define RF_FRFLSB_917_MHZ 0x00
335 #define RF_FRFMSB_918_MHZ 0xE5
336 #define RF_FRFMID_918_MHZ 0x80
337 #define RF_FRFLSB_918_MHZ 0x00
338 #define RF_FRFMSB_919_MHZ 0xE5
339 #define RF_FRFMID_919_MHZ 0xC0
340 #define RF_FRFLSB_919_MHZ 0x00
341 #define RF_FRFMSB_920_MHZ 0xE6
342 #define RF_FRFMID_920_MHZ 0x00
343 #define RF_FRFLSB_920_MHZ 0x00
344 #define RF_FRFMSB_921_MHZ 0xE6
345 #define RF_FRFMID_921_MHZ 0x40
346 #define RF_FRFLSB_921_MHZ 0x00
347 #define RF_FRFMSB_922_MHZ 0xE6
348 #define RF_FRFMID_922_MHZ 0x80
349 #define RF_FRFLSB_922_MHZ 0x00
350 #define RF_FRFMSB_923_MHZ 0xE6
351 #define RF_FRFMID_923_MHZ 0xC0
352 #define RF_FRFLSB_923_MHZ 0x00
353 #define RF_FRFMSB_924_MHZ 0xE7
354 #define RF_FRFMID_924_MHZ 0x00
355 #define RF_FRFLSB_924_MHZ 0x00
356 #define RF_FRFMSB_925_MHZ 0xE7
357 #define RF_FRFMID_925_MHZ 0x40
358 #define RF_FRFLSB_925_MHZ 0x00
359 #define RF_FRFMSB_926_MHZ 0xE7
360 #define RF_FRFMID_926_MHZ 0x80
361 #define RF_FRFLSB_926_MHZ 0x00
362 #define RF_FRFMSB_927_MHZ 0xE7
363 #define RF_FRFMID_927_MHZ 0xC0
364 #define RF_FRFLSB_927_MHZ 0x00
365 #define RF_FRFMSB_928_MHZ 0xE8
366 #define RF_FRFMID_928_MHZ 0x00
367 #define RF_FRFLSB_928_MHZ 0x00
368 
369 /*!
370  * RegPaConfig
371  */
372 #define RF_PACONFIG_PASELECT_MASK 0x7F
373 #define RF_PACONFIG_PASELECT_PABOOST 0x80
374 #define RF_PACONFIG_PASELECT_RFO 0x00 // Default
375 
376 #define RF_PACONFIG_MAX_POWER_MASK 0x8F
377 
378 #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0
379 
380 /*!
381  * RegPaRamp
382  */
383 #define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F
384 #define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default
385 #define RF_PARAMP_MODULATIONSHAPING_01 0x20
386 #define RF_PARAMP_MODULATIONSHAPING_10 0x40
387 #define RF_PARAMP_MODULATIONSHAPING_11 0x60
388 
389 #define RF_PARAMP_LOWPNTXPLL_MASK 0xEF
390 #define RF_PARAMP_LOWPNTXPLL_OFF 0x10
391 #define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default
392 
393 #define RF_PARAMP_MASK 0xF0
394 #define RF_PARAMP_3400_US 0x00
395 #define RF_PARAMP_2000_US 0x01
396 #define RF_PARAMP_1000_US 0x02
397 #define RF_PARAMP_0500_US 0x03
398 #define RF_PARAMP_0250_US 0x04
399 #define RF_PARAMP_0125_US 0x05
400 #define RF_PARAMP_0100_US 0x06
401 #define RF_PARAMP_0062_US 0x07
402 #define RF_PARAMP_0050_US 0x08
403 #define RF_PARAMP_0040_US 0x09 // Default
404 #define RF_PARAMP_0031_US 0x0A
405 #define RF_PARAMP_0025_US 0x0B
406 #define RF_PARAMP_0020_US 0x0C
407 #define RF_PARAMP_0015_US 0x0D
408 #define RF_PARAMP_0012_US 0x0E
409 #define RF_PARAMP_0010_US 0x0F
410 
411 /*!
412  * RegOcp
413  */
414 #define RF_OCP_MASK 0xDF
415 #define RF_OCP_ON 0x20 // Default
416 #define RF_OCP_OFF 0x00
417 
418 #define RF_OCP_TRIM_MASK 0xE0
419 #define RF_OCP_TRIM_045_MA 0x00
420 #define RF_OCP_TRIM_050_MA 0x01
421 #define RF_OCP_TRIM_055_MA 0x02
422 #define RF_OCP_TRIM_060_MA 0x03
423 #define RF_OCP_TRIM_065_MA 0x04
424 #define RF_OCP_TRIM_070_MA 0x05
425 #define RF_OCP_TRIM_075_MA 0x06
426 #define RF_OCP_TRIM_080_MA 0x07
427 #define RF_OCP_TRIM_085_MA 0x08
428 #define RF_OCP_TRIM_090_MA 0x09
429 #define RF_OCP_TRIM_095_MA 0x0A
430 #define RF_OCP_TRIM_100_MA 0x0B // Default
431 #define RF_OCP_TRIM_105_MA 0x0C
432 #define RF_OCP_TRIM_110_MA 0x0D
433 #define RF_OCP_TRIM_115_MA 0x0E
434 #define RF_OCP_TRIM_120_MA 0x0F
435 #define RF_OCP_TRIM_130_MA 0x10
436 #define RF_OCP_TRIM_140_MA 0x11
437 #define RF_OCP_TRIM_150_MA 0x12
438 #define RF_OCP_TRIM_160_MA 0x13
439 #define RF_OCP_TRIM_170_MA 0x14
440 #define RF_OCP_TRIM_180_MA 0x15
441 #define RF_OCP_TRIM_190_MA 0x16
442 #define RF_OCP_TRIM_200_MA 0x17
443 #define RF_OCP_TRIM_210_MA 0x18
444 #define RF_OCP_TRIM_220_MA 0x19
445 #define RF_OCP_TRIM_230_MA 0x1A
446 #define RF_OCP_TRIM_240_MA 0x1B
447 
448 /*!
449  * RegLna
450  */
451 #define RF_LNA_GAIN_MASK 0x1F
452 #define RF_LNA_GAIN_G1 0x20 // Default
453 #define RF_LNA_GAIN_G2 0x40
454 #define RF_LNA_GAIN_G3 0x60
455 #define RF_LNA_GAIN_G4 0x80
456 #define RF_LNA_GAIN_G5 0xA0
457 #define RF_LNA_GAIN_G6 0xC0
458 
459 #define RF_LNA_BOOST_MASK 0xFC
460 #define RF_LNA_BOOST_OFF 0x00 // Default
461 #define RF_LNA_BOOST_ON 0x03
462 
463 /*!
464  * RegRxConfig
465  */
466 #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F
467 #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80
468 #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default
469 
470 #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only
471 
472 #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only
473 
474 #define RF_RXCONFIG_AFCAUTO_MASK 0xEF
475 #define RF_RXCONFIG_AFCAUTO_ON 0x10
476 #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default
477 
478 #define RF_RXCONFIG_AGCAUTO_MASK 0xF7
479 #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default
480 #define RF_RXCONFIG_AGCAUTO_OFF 0x00
481 
482 #define RF_RXCONFIG_RXTRIGER_MASK 0xF8
483 #define RF_RXCONFIG_RXTRIGER_OFF 0x00
484 #define RF_RXCONFIG_RXTRIGER_RSSI 0x01
485 #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default
486 #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07
487 
488 /*!
489  * RegRssiConfig
490  */
491 #define RF_RSSICONFIG_OFFSET_MASK 0x07
492 #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default
493 #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08
494 #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10
495 #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18
496 #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20
497 #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28
498 #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30
499 #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38
500 #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40
501 #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48
502 #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50
503 #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58
504 #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60
505 #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68
506 #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70
507 #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78
508 #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80
509 #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88
510 #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90
511 #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98
512 #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0
513 #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8
514 #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0
515 #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8
516 #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0
517 #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8
518 #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0
519 #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8
520 #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0
521 #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8
522 #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0
523 #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8
524 
525 #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8
526 #define RF_RSSICONFIG_SMOOTHING_2 0x00
527 #define RF_RSSICONFIG_SMOOTHING_4 0x01
528 #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default
529 #define RF_RSSICONFIG_SMOOTHING_16 0x03
530 #define RF_RSSICONFIG_SMOOTHING_32 0x04
531 #define RF_RSSICONFIG_SMOOTHING_64 0x05
532 #define RF_RSSICONFIG_SMOOTHING_128 0x06
533 #define RF_RSSICONFIG_SMOOTHING_256 0x07
534 
535 /*!
536  * RegRssiCollision
537  */
538 #define RF_RSSICOLISION_THRESHOLD 0x0A // Default
539 
540 /*!
541  * RegRssiThresh
542  */
543 #define RF_RSSITHRESH_THRESHOLD 0xFF // Default
544 
545 /*!
546  * RegRssiValue (Read Only)
547  */
548 
549 /*!
550  * RegRxBw
551  */
552 #define RF_RXBW_MANT_MASK 0xE7
553 #define RF_RXBW_MANT_16 0x00
554 #define RF_RXBW_MANT_20 0x08
555 #define RF_RXBW_MANT_24 0x10 // Default
556 
557 #define RF_RXBW_EXP_MASK 0xF8
558 #define RF_RXBW_EXP_0 0x00
559 #define RF_RXBW_EXP_1 0x01
560 #define RF_RXBW_EXP_2 0x02
561 #define RF_RXBW_EXP_3 0x03
562 #define RF_RXBW_EXP_4 0x04
563 #define RF_RXBW_EXP_5 0x05 // Default
564 #define RF_RXBW_EXP_6 0x06
565 #define RF_RXBW_EXP_7 0x07
566 
567 /*!
568  * RegAfcBw
569  */
570 #define RF_AFCBW_MANTAFC_MASK 0xE7
571 #define RF_AFCBW_MANTAFC_16 0x00
572 #define RF_AFCBW_MANTAFC_20 0x08 // Default
573 #define RF_AFCBW_MANTAFC_24 0x10
574 
575 #define RF_AFCBW_EXPAFC_MASK 0xF8
576 #define RF_AFCBW_EXPAFC_0 0x00
577 #define RF_AFCBW_EXPAFC_1 0x01
578 #define RF_AFCBW_EXPAFC_2 0x02
579 #define RF_AFCBW_EXPAFC_3 0x03 // Default
580 #define RF_AFCBW_EXPAFC_4 0x04
581 #define RF_AFCBW_EXPAFC_5 0x05
582 #define RF_AFCBW_EXPAFC_6 0x06
583 #define RF_AFCBW_EXPAFC_7 0x07
584 
585 /*!
586  * RegOokPeak
587  */
588 #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default
589 #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default
590 #define RF_OOKPEAK_BITSYNC_OFF 0x00
591 
592 #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7
593 #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00
594 #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default
595 #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10
596 
597 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8
598 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default
599 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01
600 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02
601 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03
602 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04
603 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05
604 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06
605 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07
606 
607 /*!
608  * RegOokFix
609  */
610 #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default
611 
612 /*!
613  * RegOokAvg
614  */
615 #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F
616 #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default
617 #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20
618 #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40
619 #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60
620 #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80
621 #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0
622 #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0
623 #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0
624 
625 #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3
626 #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default
627 #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04
628 #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08
629 #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C
630 
631 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC
632 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00
633 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01
634 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default
635 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03
636 
637 /*!
638  * RegAfcFei
639  */
640 #define RF_AFCFEI_AGCSTART 0x10
641 
642 #define RF_AFCFEI_AFCCLEAR 0x02
643 
644 #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE
645 #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01
646 #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
647 
648 /*!
649  * RegAfcMsb (Read Only)
650  */
651 
652 /*!
653  * RegAfcLsb (Read Only)
654  */
655 
656 /*!
657  * RegFeiMsb (Read Only)
658  */
659 
660 /*!
661  * RegFeiLsb (Read Only)
662  */
663 
664 /*!
665  * RegPreambleDetect
666  */
667 #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F
668 #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default
669 #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00
670 
671 #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F
672 #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00
673 #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default
674 #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40
675 #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60
676 
677 #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0
678 #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00
679 #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01
680 #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02
681 #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03
682 #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04
683 #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05
684 #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06
685 #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07
686 #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08
687 #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09
688 #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default
689 #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B
690 #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C
691 #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D
692 #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E
693 #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F
694 #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10
695 #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11
696 #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12
697 #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13
698 #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14
699 #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15
700 #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16
701 #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17
702 #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18
703 #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19
704 #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A
705 #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B
706 #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C
707 #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D
708 #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E
709 #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F
710 
711 /*!
712  * RegRxTimeout1
713  */
714 #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default
715 
716 /*!
717  * RegRxTimeout2
718  */
719 #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default
720 
721 /*!
722  * RegRxTimeout3
723  */
724 #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default
725 
726 /*!
727  * RegRxDelay
728  */
729 #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default
730 
731 /*!
732  * RegOsc
733  */
734 #define RF_OSC_RCCALSTART 0x08
735 
736 #define RF_OSC_CLKOUT_MASK 0xF8
737 #define RF_OSC_CLKOUT_32_MHZ 0x00
738 #define RF_OSC_CLKOUT_16_MHZ 0x01
739 #define RF_OSC_CLKOUT_8_MHZ 0x02
740 #define RF_OSC_CLKOUT_4_MHZ 0x03
741 #define RF_OSC_CLKOUT_2_MHZ 0x04
742 #define RF_OSC_CLKOUT_1_MHZ 0x05 // Default
743 #define RF_OSC_CLKOUT_RC 0x06
744 #define RF_OSC_CLKOUT_OFF 0x07
745 
746 /*!
747  * RegPreambleMsb/RegPreambleLsb
748  */
749 #define RF_PREAMBLEMSB_SIZE 0x00 // Default
750 #define RF_PREAMBLELSB_SIZE 0x03 // Default
751 
752 /*!
753  * RegSyncConfig
754  */
755 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F
756 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default
757 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40
758 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00
759 
760 
761 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF
762 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20
763 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default
764 
765 #define RF_SYNCCONFIG_SYNC_MASK 0xEF
766 #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default
767 #define RF_SYNCCONFIG_SYNC_OFF 0x00
768 
769 
770 #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8
771 #define RF_SYNCCONFIG_SYNCSIZE_1 0x00
772 #define RF_SYNCCONFIG_SYNCSIZE_2 0x01
773 #define RF_SYNCCONFIG_SYNCSIZE_3 0x02
774 #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default
775 #define RF_SYNCCONFIG_SYNCSIZE_5 0x04
776 #define RF_SYNCCONFIG_SYNCSIZE_6 0x05
777 #define RF_SYNCCONFIG_SYNCSIZE_7 0x06
778 #define RF_SYNCCONFIG_SYNCSIZE_8 0x07
779 
780 /*!
781  * RegSyncValue1-8
782  */
783 #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default
784 #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default
785 #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default
786 #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default
787 #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default
788 #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default
789 #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default
790 #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default
791 
792 /*!
793  * RegPacketConfig1
794  */
795 #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F
796 #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00
797 #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default
798 
799 #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F
800 #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default
801 #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20
802 #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40
803 
804 #define RF_PACKETCONFIG1_CRC_MASK 0xEF
805 #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default
806 #define RF_PACKETCONFIG1_CRC_OFF 0x00
807 
808 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7
809 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default
810 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
811 
812 #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9
813 #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default
814 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02
815 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04
816 
817 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE
818 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default
819 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01
820 
821 /*!
822  * RegPacketConfig2
823  */
824 
825 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F
826 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80
827 #define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default
828 
829 #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF
830 #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00
831 #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default
832 
833 #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF
834 #define RF_PACKETCONFIG2_IOHOME_ON 0x20
835 #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default
836 
837 #define RF_PACKETCONFIG2_BEACON_MASK 0xF7
838 #define RF_PACKETCONFIG2_BEACON_ON 0x08
839 #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default
840 
841 #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8
842 
843 /*!
844  * RegPayloadLength
845  */
846 #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default
847 
848 /*!
849  * RegNodeAdrs
850  */
851 #define RF_NODEADDRESS_ADDRESS 0x00
852 
853 /*!
854  * RegBroadcastAdrs
855  */
856 #define RF_BROADCASTADDRESS_ADDRESS 0x00
857 
858 /*!
859  * RegFifoThresh
860  */
861 #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F
862 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default
863 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80
864 
865 #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0
866 #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default
867 
868 /*!
869  * RegSeqConfig1
870  */
871 #define RF_SEQCONFIG1_SEQUENCER_START 0x80
872 
873 #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40
874 
875 #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF
876 #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20
877 #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default
878 
879 #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7
880 #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default
881 #define RF_SEQCONFIG1_FROMSTART_TORX 0x08
882 #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10
883 #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18
884 
885 #define RF_SEQCONFIG1_LPS_MASK 0xFB
886 #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default
887 #define RF_SEQCONFIG1_LPS_IDLE 0x04
888 
889 #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD
890 #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default
891 #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02
892 
893 #define RF_SEQCONFIG1_FROMTX_MASK 0xFE
894 #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default
895 #define RF_SEQCONFIG1_FROMTX_TORX 0x01
896 
897 /*!
898  * RegSeqConfig2
899  */
900 #define RF_SEQCONFIG2_FROMRX_MASK 0x1F
901 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default
902 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20
903 #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40
904 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60
905 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80
906 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0
907 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0
908 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0
909 
910 #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7
911 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default
912 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08
913 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10
914 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18
915 
916 #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8
917 #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default
918 #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01
919 #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02
920 #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03
921 #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04
922 
923 /*!
924  * RegTimerResol
925  */
926 #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3
927 #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default
928 #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04
929 #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08
930 #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C
931 
932 #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC
933 #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default
934 #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01
935 #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02
936 #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03
937 
938 /*!
939  * RegTimer1Coef
940  */
941 #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default
942 
943 /*!
944  * RegTimer2Coef
945  */
946 #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default
947 
948 /*!
949  * RegImageCal
950  */
951 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F
952 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80
953 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default
954 
955 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF
956 #define RF_IMAGECAL_IMAGECAL_START 0x40
957 
958 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20
959 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default
960 
961 #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08
962 #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00
963 
964 #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9
965 #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00
966 #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default
967 #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04
968 #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06
969 
970 #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE
971 #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default
972 #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01
973 
974 /*!
975  * RegTemp (Read Only)
976  */
977 
978 /*!
979  * RegLowBat
980  */
981 #define RF_LOWBAT_MASK 0xF7
982 #define RF_LOWBAT_ON 0x08
983 #define RF_LOWBAT_OFF 0x00 // Default
984 
985 #define RF_LOWBAT_TRIM_MASK 0xF8
986 #define RF_LOWBAT_TRIM_1695 0x00
987 #define RF_LOWBAT_TRIM_1764 0x01
988 #define RF_LOWBAT_TRIM_1835 0x02 // Default
989 #define RF_LOWBAT_TRIM_1905 0x03
990 #define RF_LOWBAT_TRIM_1976 0x04
991 #define RF_LOWBAT_TRIM_2045 0x05
992 #define RF_LOWBAT_TRIM_2116 0x06
993 #define RF_LOWBAT_TRIM_2185 0x07
994 
995 /*!
996  * RegIrqFlags1
997  */
998 #define RF_IRQFLAGS1_MODEREADY 0x80
999 
1000 #define RF_IRQFLAGS1_RXREADY 0x40
1001 
1002 #define RF_IRQFLAGS1_TXREADY 0x20
1003 
1004 #define RF_IRQFLAGS1_PLLLOCK 0x10
1005 
1006 #define RF_IRQFLAGS1_RSSI 0x08
1007 
1008 #define RF_IRQFLAGS1_TIMEOUT 0x04
1009 
1010 #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02
1011 
1012 #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01
1013 
1014 /*!
1015  * RegIrqFlags2
1016  */
1017 #define RF_IRQFLAGS2_FIFOFULL 0x80
1018 
1019 #define RF_IRQFLAGS2_FIFOEMPTY 0x40
1020 
1021 #define RF_IRQFLAGS2_FIFOLEVEL 0x20
1022 
1023 #define RF_IRQFLAGS2_FIFOOVERRUN 0x10
1024 
1025 #define RF_IRQFLAGS2_PACKETSENT 0x08
1026 
1027 #define RF_IRQFLAGS2_PAYLOADREADY 0x04
1028 
1029 #define RF_IRQFLAGS2_CRCOK 0x02
1030 
1031 #define RF_IRQFLAGS2_LOWBAT 0x01
1032 
1033 /*!
1034  * RegDioMapping1
1035  */
1036 #define RF_DIOMAPPING1_DIO0_MASK 0x3F
1037 #define RF_DIOMAPPING1_DIO0_00 0x00 // Default
1038 #define RF_DIOMAPPING1_DIO0_01 0x40
1039 #define RF_DIOMAPPING1_DIO0_10 0x80
1040 #define RF_DIOMAPPING1_DIO0_11 0xC0
1041 
1042 #define RF_DIOMAPPING1_DIO1_MASK 0xCF
1043 #define RF_DIOMAPPING1_DIO1_00 0x00 // Default
1044 #define RF_DIOMAPPING1_DIO1_01 0x10
1045 #define RF_DIOMAPPING1_DIO1_10 0x20
1046 #define RF_DIOMAPPING1_DIO1_11 0x30
1047 
1048 #define RF_DIOMAPPING1_DIO2_MASK 0xF3
1049 #define RF_DIOMAPPING1_DIO2_00 0x00 // Default
1050 #define RF_DIOMAPPING1_DIO2_01 0x04
1051 #define RF_DIOMAPPING1_DIO2_10 0x08
1052 #define RF_DIOMAPPING1_DIO2_11 0x0C
1053 
1054 #define RF_DIOMAPPING1_DIO3_MASK 0xFC
1055 #define RF_DIOMAPPING1_DIO3_00 0x00 // Default
1056 #define RF_DIOMAPPING1_DIO3_01 0x01
1057 #define RF_DIOMAPPING1_DIO3_10 0x02
1058 #define RF_DIOMAPPING1_DIO3_11 0x03
1059 
1060 /*!
1061  * RegDioMapping2
1062  */
1063 #define RF_DIOMAPPING2_DIO4_MASK 0x3F
1064 #define RF_DIOMAPPING2_DIO4_00 0x00 // Default
1065 #define RF_DIOMAPPING2_DIO4_01 0x40
1066 #define RF_DIOMAPPING2_DIO4_10 0x80
1067 #define RF_DIOMAPPING2_DIO4_11 0xC0
1068 
1069 #define RF_DIOMAPPING2_DIO5_MASK 0xCF
1070 #define RF_DIOMAPPING2_DIO5_00 0x00 // Default
1071 #define RF_DIOMAPPING2_DIO5_01 0x10
1072 #define RF_DIOMAPPING2_DIO5_10 0x20
1073 #define RF_DIOMAPPING2_DIO5_11 0x30
1074 
1075 #define RF_DIOMAPPING2_MAP_MASK 0xFE
1076 #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
1077 #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default
1078 
1079 /*!
1080  * RegVersion (Read Only)
1081  */
1082 
1083 /*!
1084  * RegPllHop
1085  */
1086 #define RF_PLLHOP_FASTHOP_MASK 0x7F
1087 #define RF_PLLHOP_FASTHOP_ON 0x80
1088 #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default
1089 
1090 /*!
1091  * RegTcxo
1092  */
1093 #define RF_TCXO_TCXOINPUT_MASK 0xEF
1094 #define RF_TCXO_TCXOINPUT_ON 0x10
1095 #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default
1096 
1097 /*!
1098  * RegPaDac
1099  */
1100 #define RF_PADAC_20DBM_MASK 0xF8
1101 #define RF_PADAC_20DBM_ON 0x07
1102 #define RF_PADAC_20DBM_OFF 0x04 // Default
1103 
1104 /*!
1105  * RegFormerTemp
1106  */
1107 
1108 /*!
1109  * RegBitrateFrac
1110  */
1111 #define RF_BITRATEFRAC_MASK 0xF0
1112 
1113 /*!
1114  * RegAgcRef
1115  */
1116 
1117 /*!
1118  * RegAgcThresh1
1119  */
1120 
1121 /*!
1122  * RegAgcThresh2
1123  */
1124 
1125 /*!
1126  * RegAgcThresh3
1127  */
1128 
1129 /*!
1130  * RegPll
1131  */
1132 #define RF_PLL_BANDWIDTH_MASK 0x3F
1133 #define RF_PLL_BANDWIDTH_75 0x00
1134 #define RF_PLL_BANDWIDTH_150 0x40
1135 #define RF_PLL_BANDWIDTH_225 0x80
1136 #define RF_PLL_BANDWIDTH_300 0xC0 // Default
1137 
1138 #endif // __SX1276_REGS_FSK_H__
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