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S25FS512S_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_S25FS512S_H
18 #define MBED_QSPI_FLASH_S25FS512S_H
19 
20 #define QSPI_FLASH_CHIP_STRING "Cypress S25FS512S"
21 #define QSPI_FLASH_CYPRESS_S25FS512S
22 
23 // Command for reading configuration register
24 #define QSPI_CMD_RDCR0 0x35 // To read Quad (QE) enable bit
25 // Command for writing status/configuration register
26 #define QSPI_CMD_WRSR 0x01 // To write Qual (QE) enable bit
27 // Command for reading status register
28 #define QSPI_CMD_RDSR 0x05 // To read WIP bit of status register 1
29 
30 
31 
32 // Command for reading security register
33 #define QSPI_CMD_RDSCUR 0x2B
34 
35 // Command for setting Reset Enable
36 #define QSPI_CMD_RSTEN 0x66
37 // Command for setting Reset
38 #define QSPI_CMD_RST 0xF0 //0x99
39 
40 // Command for setting write enable
41 #define QSPI_CMD_WREN 0x06
42 // Command for setting write disable
43 #define QSPI_CMD_WRDI 0x04
44 
45 // WRSR operations max time [us] (datasheet max time + 15%)
46 #define QSPI_WRSR_MAX_TIME 2300000 // 2.3 seconds
47 // general wait max time [us]
48 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
49 
50 
51 // Commands for writing (page programming)
52 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
53 #define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode // 1-4-4 is not supported by S25FS512S
54 
55 // write operations max time [us] (datasheet max time + 15%)
56 #define QSPI_PAGE_PROG_MAX_TIME 2300 // 2.3ms
57 
58 #define QSPI_PAGE_SIZE 256 // 256B
59 #define QSPI_SECTOR_SIZE 262144 // 256kB
60 #define QSPI_SECTOR_COUNT 256 // 64 MB
61 
62 // Commands for reading
63 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
64 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
65 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode - dual I/O
66 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode - dual output
67 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode - quad I/O
68 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode - quad output
69 
70 // Alt (mode) value for quad I/O read
71 #define QSPI_ALT_READ_4IO 0x01 // 1-4-4 mode only
72 
73 #define QSPI_READ_1IO_DUMMY_CYCLE 0
74 #define QSPI_READ_FAST_DUMMY_CYCLE 8
75 #define QSPI_READ_2IO_DUMMY_CYCLE 4 // dual I/O
76 #define QSPI_READ_1I2O_DUMMY_CYCLE 8 // dual output
77 #define QSPI_READ_4IO_DUMMY_CYCLE 6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
78 #define QSPI_READ_1I4O_DUMMY_CYCLE 8 // quad output
79 
80 // Commands for erasing
81 #define QSPI_CMD_ERASE_SECTOR 0xD8 // 256kB
82 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
83 
84 // erase operations max time [us] (datasheet max time + 15%)
85 #define QSPI_ERASE_SECTOR_MAX_TIME 850000 // 1.15*725 ~ 850 ms
86 
87 // max frequency for basic rw operation (for fast mode)
88 #define QSPI_COMMON_MAX_FREQUENCY 50000000
89 
90 #define QSPI_STATUS_REG_SIZE 1
91 #define QSPI_CONFIG_REG_0_SIZE 1
92 #define QSPI_SECURITY_REG_SIZE 1
93 #define QSPI_MAX_REG_SIZE 2
94 
95 // status register
96 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
97 #define STATUS_BIT_WEL (1 << 1) // write enable latch
98 #define STATUS_BIT_BP0 (1 << 2) //
99 #define STATUS_BIT_BP1 (1 << 3) //
100 #define STATUS_BIT_BP2 (1 << 4) //
101 #define STATUS_BIT_BP3 (1 << 5) //
102 #define STATUS_BIT_QE (1 << 1) // Quad Enable
103 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
104 
105 // configuration register 0
106 // bit 0, 1, 2, 4, 5, 7 reserved
107 #define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
108 #define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
109 
110 // configuration register 1
111 // bit 0, 2, 3, 4, 5, 6, 7 reserved
112 #define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
113 
114 
115 
116 #define EXTENDED_SPI_ENABLE() \
117  \
118  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
119  uint8_t reg_data[reg_size] = { 0 }; \
120  \
121  if (read_register(STATUS_REG, reg_data, \
122  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
123  return QSPI_STATUS_ERROR; \
124  } \
125  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
126  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
127  return QSPI_STATUS_ERROR; \
128  } \
129  \
130  if (write_enable(qspi) != QSPI_STATUS_OK) { \
131  return QSPI_STATUS_ERROR; \
132  } \
133  \
134  reg_data[1] |= STATUS_BIT_QE; \
135  if (write_register(QSPI_CMD_WRSR, reg_data, \
136  reg_size, qspi) != QSPI_STATUS_OK) { \
137  return QSPI_STATUS_ERROR; \
138  } \
139  \
140  WAIT_FOR(WRSR_MAX_TIME, qspi); \
141  \
142  memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
143  if (read_register(CONFIG_REG0, reg_data, \
144  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
145  return QSPI_STATUS_ERROR; \
146  } \
147  \
148  return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
149  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
150 
151 
152 
153 #define EXTENDED_SPI_DISABLE() \
154  \
155  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
156  uint8_t reg_data[reg_size] = { 0 }; \
157  \
158  if (read_register(STATUS_REG, reg_data, \
159  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
160  return QSPI_STATUS_ERROR; \
161  } \
162  \
163  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
164  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
165  return QSPI_STATUS_ERROR; \
166  } \
167  \
168  if (write_enable(qspi) != QSPI_STATUS_OK) { \
169  return QSPI_STATUS_ERROR; \
170  } \
171  \
172  reg_data[1] &= ~(STATUS_BIT_QE); \
173  \
174  if (write_register(QSPI_CMD_WRSR, reg_data, \
175  reg_size, qspi) != QSPI_STATUS_OK) { \
176  return QSPI_STATUS_ERROR; \
177  } \
178  \
179  WAIT_FOR(WRSR_MAX_TIME, qspi); \
180  \
181  reg_data[0] = 0; \
182  if (read_register(CONFIG_REG0, reg_data, \
183  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
184  return QSPI_STATUS_ERROR; \
185  } \
186  \
187  return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
188  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
189 
190 
191 #endif // MBED_QSPI_FLASH_S25FS512S_H
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