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N25Q128A_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_N25Q128A_H
18 #define MBED_QSPI_FLASH_N25Q128A_H
19 
20 
21 #define QSPI_FLASH_CHIP_STRING "Micron N25Q128A"
22 
23 // Command for reading status register
24 #define QSPI_CMD_RDSR 0x05
25 // Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
26 #define QSPI_CMD_RDCR0 0xB5
27 // Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
28 #define QSPI_CMD_RDCR1 0x85
29 // Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
30 #define QSPI_CMD_RDCR2 0x65
31 // Command for writing status
32 #define QSPI_CMD_WRSR 0x01
33 // Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
34 #define QSPI_CMD_WRCR0 0xB1
35 // Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
36 #define QSPI_CMD_WRCR1 0x81
37 // Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
38 #define QSPI_CMD_WRCR2 0x61
39 // Command for reading security register
40 #define QSPI_CMD_RDSCUR 0x2B
41 
42 // Command for setting Reset Enable
43 #define QSPI_CMD_RSTEN 0x66
44 // Command for setting Reset
45 #define QSPI_CMD_RST 0x99
46 
47 // Command for setting write enable
48 #define QSPI_CMD_WREN 0x06
49 // Command for setting write disable
50 #define QSPI_CMD_WRDI 0x04
51 
52 // WRSR operations max time [us] (datasheet max time + 15%)
53 #define QSPI_WRSR_MAX_TIME 9200 // 8ms
54 // general wait max time [us]
55 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
56 
57 
58 // Commands for writing (page programming)
59 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
60 #define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
61 #define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode
62 #define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
63 #define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode
64 
65 // write operations max time [us] (datasheet max time + 15%)
66 #define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms
67 
68 #define QSPI_PAGE_SIZE 256 // 256B
69 #define QSPI_SECTOR_SIZE 4096 // 4kB
70 #define QSPI_SECTOR_COUNT 4096
71 
72 // Commands for reading
73 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
74 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
75 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
76 #define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
77 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
78 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
79 #define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
80 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
81 
82 
83 #define QSPI_READ_1IO_DUMMY_CYCLE 0
84 #define QSPI_READ_FAST_DUMMY_CYCLE 8
85 // 8 dummy (10 dummy when quad SPI protocol is enabled)
86 #define QSPI_READ_2IO_DUMMY_CYCLE 8
87 #define QSPI_READ_1I2O_DUMMY_CYCLE 8
88 #define QSPI_READ_4IO_DUMMY_CYCLE 10
89 #define QSPI_READ_1I4O_DUMMY_CYCLE 8
90 
91 // Commands for erasing
92 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
93 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
94 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
95 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
96 
97 // erase operations max time [us] (datasheet max time + 15%)
98 #define QSPI_ERASE_SECTOR_MAX_TIME 920000 // 0.8s
99 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s
100 #define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s
101 
102 // max frequency for basic rw operation
103 #define QSPI_COMMON_MAX_FREQUENCY 50000000
104 
105 #define QSPI_STATUS_REG_SIZE 1
106 #define QSPI_CONFIG_REG_0_SIZE 2
107 #define QSPI_CONFIG_REG_1_SIZE 1
108 #define QSPI_CONFIG_REG_2_SIZE 1
109 #define QSPI_MAX_REG_SIZE 2
110 
111 // status register
112 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
113 #define STATUS_BIT_WEL (1 << 1) // write enable latch
114 #define STATUS_BIT_BP0 (1 << 2) // block
115 #define STATUS_BIT_BP1 (1 << 3) //
116 #define STATUS_BIT_BP2 (1 << 4) //
117 #define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
118 #define STATUS_BIT_BP3 (1 << 6) //
119 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
120 
121 // configuration register 0 (Nonvolatile Configuration Register)
122 // bit 1, 5, reserved
123 #define CONFIG0_BIT_LOCK (1 << 0) // Lock nonvolatile configuration register
124 #define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
125 #define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
126 #define CONFIG0_BIT_RH (1 << 4) // Reset/hold
127 #define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
128 #define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
129 #define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
130 #define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
131 #define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
132 #define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
133 #define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
134 #define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
135 #define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
136 #define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
137 #define CONFIG0_BITS_DEFAULT 0xFFFF // reg default state
138 
139 
140 // configuration register 1 (Volatile Configuration Register)
141 // bit 2, reserved
142 #define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
143 #define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
144 #define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
145 #define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
146 #define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
147 #define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
148 #define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
149 #define CONFIG1_BITS_DEFAULT 0xB // reg default state
150 
151 
152 // configuration register 2 (Enhanced Volatile Configuration Register)
153 // bit 5, reserved
154 #define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
155 #define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
156 #define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
157 #define CONFIG2_BIT_VPP (1 << 3) // VPP accelerator 1 = Disabled (Default)
158 #define CONFIG2_BIT_RH (1 << 4) // Reset/hold
159 #define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
160 #define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
161 #define CONFIG2_BITS_DEFAULT 0xDF // reg default state
162 
163 
164 #define DUAL_ENABLE() \
165  \
166  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
167  \
168  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
169  if (read_register(QSPI_CMD_RDCR2, reg_data, \
170  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
171  return QSPI_STATUS_ERROR; \
172  } \
173  if (write_enable(qspi) != QSPI_STATUS_OK) { \
174  return QSPI_STATUS_ERROR; \
175  } \
176  \
177  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
178  if (write_register(QSPI_CMD_WRCR2, reg_data, \
179  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
180  return QSPI_STATUS_ERROR; \
181  } \
182  qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
183  WAIT_FOR(WRSR_MAX_TIME, qspi); \
184  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
185  if (read_register(QSPI_CMD_RDCR2, reg_data, \
186  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
187  return QSPI_STATUS_ERROR; \
188  } \
189  \
190  return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
191  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
192 
193 
194 #define DUAL_DISABLE() \
195  \
196  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
197  \
198  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
199  if (read_register(QSPI_CMD_RDCR2, reg_data, \
200  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
201  return QSPI_STATUS_ERROR; \
202  } \
203  if (write_enable(qspi) != QSPI_STATUS_OK) { \
204  return QSPI_STATUS_ERROR; \
205  } \
206  \
207  reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
208  if (write_register(QSPI_CMD_WRCR2, reg_data, \
209  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
210  return QSPI_STATUS_ERROR; \
211  } \
212  WAIT_FOR(WRSR_MAX_TIME, qspi); \
213  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
214  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
215  if (read_register(QSPI_CMD_RDCR2, reg_data, \
216  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
217  return QSPI_STATUS_ERROR; \
218  } \
219  \
220  return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
221  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
222 
223 
224 #define QUAD_ENABLE() \
225  \
226  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
227  \
228  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
229  if (read_register(QSPI_CMD_RDCR2, reg_data, \
230  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
231  return QSPI_STATUS_ERROR; \
232  } \
233  if (write_enable(qspi) != QSPI_STATUS_OK) { \
234  return QSPI_STATUS_ERROR; \
235  } \
236  \
237  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
238  if (write_register(QSPI_CMD_WRCR2, reg_data, \
239  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
240  return QSPI_STATUS_ERROR; \
241  } \
242  qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
243  WAIT_FOR(WRSR_MAX_TIME, qspi); \
244  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
245  if (read_register(QSPI_CMD_RDCR2, reg_data, \
246  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
247  return QSPI_STATUS_ERROR; \
248  } \
249  \
250  return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
251  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
252 
253 
254 #define QUAD_DISABLE() \
255  \
256  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
257  \
258  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
259  if (read_register(QSPI_CMD_RDCR2, reg_data, \
260  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
261  return QSPI_STATUS_ERROR; \
262  } \
263  if (write_enable(qspi) != QSPI_STATUS_OK) { \
264  return QSPI_STATUS_ERROR; \
265  } \
266  \
267  reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
268  if (write_register(QSPI_CMD_WRCR2, reg_data, \
269  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
270  return QSPI_STATUS_ERROR; \
271  } \
272  WAIT_FOR(WRSR_MAX_TIME, qspi); \
273  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
274  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
275  if (read_register(QSPI_CMD_RDCR2, reg_data, \
276  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
277  return QSPI_STATUS_ERROR; \
278  } \
279  \
280  return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
281  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
282 
283 #endif // MBED_QSPI_FLASH_N25Q128A_H
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