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MX25RXX35F_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_MX25RXX35F_H
18 #define MBED_QSPI_FLASH_MX25RXX35F_H
19 
20 
21 #define QSPI_FLASH_CHIP_STRING "macronix MX25RXX35F"
22 
23 // Command for reading status register
24 #define QSPI_CMD_RDSR 0x05
25 // Command for reading configuration register
26 #define QSPI_CMD_RDCR0 0x15
27 // Command for writing status/configuration register
28 #define QSPI_CMD_WRSR 0x01
29 // Command for reading security register
30 #define QSPI_CMD_RDSCUR 0x2B
31 
32 // Command for setting Reset Enable
33 #define QSPI_CMD_RSTEN 0x66
34 // Command for setting Reset
35 #define QSPI_CMD_RST 0x99
36 
37 // Command for setting write enable
38 #define QSPI_CMD_WREN 0x06
39 // Command for setting write disable
40 #define QSPI_CMD_WRDI 0x04
41 
42 // WRSR operations max time [us] (datasheet max time + 15%)
43 #define QSPI_WRSR_MAX_TIME 34500 // 30ms
44 // general wait max time [us]
45 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
46 
47 
48 // Commands for writing (page programming)
49 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
50 #define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
51 
52 // write operations max time [us] (datasheet max time + 15%)
53 #define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
54 
55 #define QSPI_PAGE_SIZE 256 // 256B
56 #define QSPI_SECTOR_SIZE 4096 // 4kB
57 #define QSPI_SECTOR_COUNT 32 // adjusted to MX25R1035F smallest one from MX25RXX35F family
58 
59 // Commands for reading
60 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
61 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
62 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
63 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
64 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
65 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
66 
67 #define QSPI_READ_1IO_DUMMY_CYCLE 0
68 #define QSPI_READ_FAST_DUMMY_CYCLE 8
69 #define QSPI_READ_2IO_DUMMY_CYCLE 4
70 #define QSPI_READ_1I2O_DUMMY_CYCLE 8
71 #define QSPI_READ_4IO_DUMMY_CYCLE 6
72 #define QSPI_READ_1I4O_DUMMY_CYCLE 8
73 
74 // Commands for erasing
75 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
76 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
77 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
78 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
79 
80 // erase operations max time [us] (datasheet max time + 15%)
81 #define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
82 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
83 #define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
84 
85 // max frequency for basic rw operation (for fast mode)
86 #define QSPI_COMMON_MAX_FREQUENCY 32000000
87 
88 #define QSPI_STATUS_REG_SIZE 1
89 #define QSPI_CONFIG_REG_0_SIZE 2
90 #define QSPI_SECURITY_REG_SIZE 1
91 #define QSPI_MAX_REG_SIZE 2
92 
93 // status register
94 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
95 #define STATUS_BIT_WEL (1 << 1) // write enable latch
96 #define STATUS_BIT_BP0 (1 << 2) //
97 #define STATUS_BIT_BP1 (1 << 3) //
98 #define STATUS_BIT_BP2 (1 << 4) //
99 #define STATUS_BIT_BP3 (1 << 5) //
100 #define STATUS_BIT_QE (1 << 6) // Quad Enable
101 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
102 
103 // configuration register 0
104 // bit 0, 1, 2, 4, 5, 7 reserved
105 #define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
106 #define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
107 
108 // configuration register 1
109 // bit 0, 2, 3, 4, 5, 6, 7 reserved
110 #define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
111 
112 
113 
114 #define EXTENDED_SPI_ENABLE() \
115  \
116  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
117  uint8_t reg_data[reg_size] = { 0 }; \
118  \
119  if (read_register(STATUS_REG, reg_data, \
120  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
121  return QSPI_STATUS_ERROR; \
122  } \
123  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
124  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
125  return QSPI_STATUS_ERROR; \
126  } \
127  \
128  if (write_enable(qspi) != QSPI_STATUS_OK) { \
129  return QSPI_STATUS_ERROR; \
130  } \
131  \
132  reg_data[0] = STATUS_BIT_QE; \
133  if (write_register(QSPI_CMD_WRSR, reg_data, \
134  reg_size, qspi) != QSPI_STATUS_OK) { \
135  return QSPI_STATUS_ERROR; \
136  } \
137  WAIT_FOR(WRSR_MAX_TIME, qspi); \
138  \
139  memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
140  if (read_register(STATUS_REG, reg_data, \
141  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
142  return QSPI_STATUS_ERROR; \
143  } \
144  \
145  return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
146  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
147 
148 
149 
150 #define EXTENDED_SPI_DISABLE() \
151  \
152  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
153  uint8_t reg_data[reg_size] = { 0 }; \
154  \
155  if (read_register(STATUS_REG, reg_data, \
156  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
157  return QSPI_STATUS_ERROR; \
158  } \
159  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
160  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
161  return QSPI_STATUS_ERROR; \
162  } \
163  \
164  if (write_enable(qspi) != QSPI_STATUS_OK) { \
165  return QSPI_STATUS_ERROR; \
166  } \
167  \
168  reg_data[0] &= ~(STATUS_BIT_QE); \
169  \
170  if (write_register(QSPI_CMD_WRSR, reg_data, \
171  reg_size, qspi) != QSPI_STATUS_OK) { \
172  return QSPI_STATUS_ERROR; \
173  } \
174  WAIT_FOR(WRSR_MAX_TIME, qspi); \
175  \
176  reg_data[0] = 0; \
177  if (read_register(STATUS_REG, reg_data, \
178  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
179  return QSPI_STATUS_ERROR; \
180  } \
181  \
182  return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
183  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
184 
185 
186 
187 #define FAST_MODE_ENABLE() \
188  \
189  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
190  uint8_t reg_data[reg_size]; \
191  \
192  if (read_register(STATUS_REG, reg_data, \
193  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
194  return QSPI_STATUS_ERROR; \
195  } \
196  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
197  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
198  return QSPI_STATUS_ERROR; \
199  } \
200  \
201  if (write_enable(qspi) != QSPI_STATUS_OK) { \
202  return QSPI_STATUS_ERROR; \
203  } \
204  \
205  reg_data[2] |= CONFIG1_BIT_LH; \
206  if (write_register(QSPI_CMD_WRSR, reg_data, \
207  reg_size, qspi) != QSPI_STATUS_OK) { \
208  return QSPI_STATUS_ERROR; \
209  } \
210  WAIT_FOR(WRSR_MAX_TIME, qspi); \
211  \
212  if (read_register(CONFIG_REG0, reg_data, \
213  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
214  return QSPI_STATUS_ERROR; \
215  } \
216  \
217  return ((reg_data[1] & CONFIG1_BIT_LH) != 0 ? \
218  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
219 
220 
221 #define FAST_MODE_DISABLE() \
222  \
223  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
224  uint8_t reg_data[reg_size]; \
225  \
226  if (read_register(STATUS_REG, reg_data, \
227  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
228  return QSPI_STATUS_ERROR; \
229  } \
230  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
231  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
232  return QSPI_STATUS_ERROR; \
233  } \
234  \
235  if (write_enable(qspi) != QSPI_STATUS_OK) { \
236  return QSPI_STATUS_ERROR; \
237  } \
238  \
239  reg_data[2] &= ~(CONFIG1_BIT_LH); \
240  if (write_register(QSPI_CMD_WRSR, reg_data, \
241  reg_size, qspi) != QSPI_STATUS_OK) { \
242  return QSPI_STATUS_ERROR; \
243  } \
244  WAIT_FOR(WRSR_MAX_TIME, qspi); \
245  \
246  if (read_register(CONFIG_REG0, reg_data, \
247  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
248  return QSPI_STATUS_ERROR; \
249  } \
250  \
251  return ((reg_data[1] & CONFIG1_BIT_LH) == 0 ? \
252  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
253 
254 
255 #endif // MBED_QSPI_FLASH_MX25RXX35F_H
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