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fpga_config.h
1 /*
2  * Copyright (c) 2019, Arm Limited and affiliates.
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 
18 #define TESTER_CLOCK_FREQUENCY_HZ 100000000
19 #define TESTER_CLOCK_PERIOD_NS 10
20 #define TESTER_CONTROL 0x00000000
21 #define TESTER_CONTROL_RESET 0x00000000
22 #define TESTER_CONTROL_RESET_PERIPHERALS (1 << 0)
23 #define TESTER_CONTROL_RESET_ALL (1 << 1)
24 #define TESTER_CONTROL_REPROGRAM (1 << 2)
25 #define TESTER_CONTROL_VERSION 0x00000010
26 #define TESTER_CONTROL_VERSION_SIZE 4
27 #define TESTER_REMAP 0x00001000
28 #define TESTER_SYS_IO 0x00002000
29 #define TESTER_SYS_IO_MODE (0x000 + 0x00002C00)
30 #define TESTER_SYS_IO_MODE_DISABLED 0
31 #define TESTER_SYS_IO_MODE_SPI_SERIAL_FLASH 1
32 #define TESTER_SYS_IO_MODE_I2C_IO_EXPANDER0 2
33 #define TESTER_SYS_IO_MODE_I2C_IO_EXPANDER1 3
34 #define TESTER_SYS_IO_MODE_I2C_IO_EXPANDER2 4
35 #define TESTER_SYS_IO_PWM_ENABLE (0x001 + 0x00002C00)
36 #define TESTER_SYS_IO_PWM_PERIOD (0x002 + 0x00002C00)
37 #define TESTER_SYS_IO_PWM_CYCLES_HIGH (0x006 + 0x00002C00)
38 #define TESTER_SYS_IO_AN_MUX_ANALOGIN_MEASUREMENT (0x00A + 0x00002C00)
39 #define TESTER_SYS_IO_NUM_POWER_SAMPLES (0x00C + 0x00002C00)
40 #define TESTER_SYS_IO_NUM_POWER_CYCLES (0x010 + 0x00002C00)
41 #define TESTER_SYS_IO_ADC_SNAPSHOT (0x018 + 0x00002C00)
42 #define TESTER_SYS_IO_SAMPLE_ADC (0x019 + 0x00002C00)
43 #define TESTER_SYS_IO_ANIN0_MEASUREMENT (0x030 + 0x00002C00)
44 #define TESTER_SYS_IO_ANIN0_MEASUREMENTS_SUM (0x032 + 0x00002C00)
45 #define TESTER_SYS_IO_ANIN1_MEASUREMENT (0x03A + 0x00002C00)
46 #define TESTER_SYS_IO_ANIN1_MEASUREMENTS_SUM (0x03C + 0x00002C00)
47 #define TESTER_SYS_IO_ANIN2_MEASUREMENT (0x044 + 0x00002C00)
48 #define TESTER_SYS_IO_ANIN2_MEASUREMENTS_SUM (0x046 + 0x00002C00)
49 #define TESTER_SYS_IO_ANIN3_MEASUREMENT (0x04E + 0x00002C00)
50 #define TESTER_SYS_IO_ANIN3_MEASUREMENTS_SUM (0x050 + 0x00002C00)
51 #define TESTER_PERIPHERAL 0x00100000
52 #define TESTER_PERIPHERAL_SELECT 0x00100000
53 #define TESTER_GPIO 0x00101000
54 #define TESTER_SPI_MASTER 0x00102000
55 #define TESTER_SPI_MASTER_STARTS 0x00102008
56 #define TESTER_SPI_MASTER_STOPS 0x00102009
57 #define TESTER_SPI_MASTER_TRANSFERS 0x0010200A
58 #define TESTER_SPI_MASTER_TRANSFERS_SIZE 2
59 #define TESTER_SPI_MASTER_START_STOP_STATS 0x0010200C
60 #define TESTER_SPI_MASTER_START_STOP_STATS_SIZE 1
61 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM 0x00102012
62 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM_SIZE 4
63 #define TESTER_SPI_MASTER_CTRL 0x00102016
64 #define TESTER_SPI_MASTER_CTRL_SIZE 2
65 #define TESTER_SPI_MASTER_HD_TX_CNT 0x00102018
66 #define TESTER_SPI_MASTER_HD_TX_CNT_SIZE 2
67 #define TESTER_SPI_MASTER_HD_RX_CNT 0x0010201A
68 #define TESTER_SPI_MASTER_HD_RX_CNT_SIZE 2
69 #define TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT 0x0010201C
70 #define TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT_SIZE 4
71 #define TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT 0x00102020
72 #define TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT_SIZE 4
73 #define TESTER_SPI_MASTER_CLK_MODE_OFFSET 0
74 #define TESTER_SPI_MASTER_CLK_MODE_SIZE 2
75 #define TESTER_SPI_MASTER_BIT_ORDER_OFFSET 2
76 #define TESTER_SPI_MASTER_BIT_ORDER_SIZE 1
77 #define TESTER_SPI_MASTER_DUPLEX_OFFSET 3
78 #define TESTER_SPI_MASTER_DUPLEX_SIZE 1
79 #define TESTER_SPI_MASTER_SYM_SIZE_OFFSET 4
80 #define TESTER_SPI_MASTER_SYM_SIZE_SIZE 6
81 #define TESTER_SPI_SLAVE 0x00106000
82 #define TESTER_SPI_SLAVE_STARTS 0x00106008
83 #define TESTER_SPI_SLAVE_STOPS 0x00106009
84 #define TESTER_SPI_SLAVE_TRANSFERS 0x0010600A
85 #define TESTER_SPI_SLAVE_TRANSFERS_SIZE 2
86 #define TESTER_SPI_SLAVE_TO_MASTER_CHECKSUM 0x00106015
87 #define TESTER_SPI_SLAVE_TO_MASTER_CHECKSUM_SIZE 4
88 #define TESTER_SPI_SLAVE_CTRL 0x00106019
89 #define TESTER_SPI_SLAVE_CTRL_SIZE 2
90 #define TESTER_SPI_SLAVE_HD_TX_CNT 0x0010601B
91 #define TESTER_SPI_SLAVE_HD_TX_CNT_SIZE 2
92 #define TESTER_SPI_SLAVE_HD_RX_CNT 0x0010601D
93 #define TESTER_SPI_SLAVE_HD_RX_CNT_SIZE 2
94 #define TESTER_SPI_SLAVE_CLK_DIV 0x0010601F
95 #define TESTER_SPI_SLAVE_CLK_DIV_SIZE 2
96 #define TESTER_SPI_SLAVE_NUM_OF_SYMBOLS 0x00106021
97 #define TESTER_SPI_SLAVE_NUM_OF_SYMBOLS_SIZE 2
98 #define TESTER_SPI_SLAVE_START_DELAY_US 0x00106023
99 #define TESTER_SPI_SLAVE_START_DELAY_US_SIZE 1
100 #define TESTER_SPI_SLAVE_SYM_DELAY_TICKS 0x00106024
101 #define TESTER_SPI_SLAVE_SYM_DELAY_TICKS_SIZE 2
102 #define TESTER_SPI_SLAVE_CLK_MODE_OFFSET 0
103 #define TESTER_SPI_SLAVE_CLK_MODE_SIZE 2
104 #define TESTER_SPI_SLAVE_BIT_ORDER_OFFSET 2
105 #define TESTER_SPI_SLAVE_BIT_ORDER_SIZE 1
106 #define TESTER_SPI_SLAVE_DUPLEX_OFFSET 3
107 #define TESTER_SPI_SLAVE_DUPLEX_SIZE 1
108 #define TESTER_SPI_SLAVE_SYM_SIZE_OFFSET 4
109 #define TESTER_SPI_SLAVE_SYM_SIZE_SIZE 6
110 #define TESTER_SPI_SLAVE_START_REQUEST_OFFSET 10
111 #define TESTER_SPI_SLAVE_START_REQUEST_SIZE 1
112 #define TESTER_IO_METRICS 0x00103000
113 #define TESTER_IO_METRICS_CTRL 0x00103000
114 #define TESTER_IO_METRICS_CTRL_ACTIVE_BIT (1 << 0)
115 #define TESTER_IO_METRICS_CTRL_RESET_BIT (1 << 1)
116 #define TESTER_IO_METRICS_BASE(i) (0x00103040 + 0x40 * (i))
117 #define TESTER_IO_METRICS_MIN_PULSE_LOW(i) (TESTER_IO_METRICS_BASE(i) + 0x00)
118 #define TESTER_IO_METRICS_MIN_PULSE_LOW_SIZE 4
119 #define TESTER_IO_METRICS_MIN_PULSE_HIGH(i) (TESTER_IO_METRICS_BASE(i) + 0x04)
120 #define TESTER_IO_METRICS_MIN_PULSE_HIGH_SIZE 4
121 #define TESTER_IO_METRICS_MAX_PULSE_LOW(i) (TESTER_IO_METRICS_BASE(i) + 0x08)
122 #define TESTER_IO_METRICS_MAX_PULSE_LOW_SIZE 4
123 #define TESTER_IO_METRICS_MAX_PULSE_HIGH(i) (TESTER_IO_METRICS_BASE(i) + 0x0C)
124 #define TESTER_IO_METRICS_MAX_PULSE_HIGH_SIZE 4
125 #define TESTER_IO_METRICS_RISING_EDGES(i) (TESTER_IO_METRICS_BASE(i) + 0x10)
126 #define TESTER_IO_METRICS_RISING_EDGES_SIZE 4
127 #define TESTER_IO_METRICS_FALLING_EDGES(i) (TESTER_IO_METRICS_BASE(i) + 0x14)
128 #define TESTER_IO_METRICS_FALLING_EDGES_SIZE 4
129 #define TESTER_UART_CONTROL (0x000 + 0x00104000)
130 #define TESTER_UART_CONTROL_SIZE 4
131 #define TESTER_UART_BAUD_DIVISOR (0x004 + 0x00104000)
132 #define TESTER_UART_BAUD_DIVISOR_SIZE 2
133 #define TESTER_UART_BIT_COUNT (0x010 + 0x00104000)
134 #define TESTER_UART_BIT_COUNT_SIZE 1
135 #define TESTER_UART_STOP_COUNT (0x011 + 0x00104000)
136 #define TESTER_UART_STOP_COUNT_SIZE 1
137 #define TESTER_UART_PARITY (0x012 + 0x00104000)
138 #define TESTER_UART_PARITY_SIZE 1
139 #define TESTER_UART_PARITY_ENABLE (1 << 0)
140 #define TESTER_UART_PARITY_ODD_N_EVEN (1 << 1)
141 #define TESTER_UART_RX_CONTROL (0x100 + 0x00104000)
142 #define TESTER_UART_RX_CONTROL_SIZE 4
143 #define TESTER_UART_RX_CONTROL_ENABLE (1 << 0)
144 #define TESTER_UART_RX_CONTROL_RESET (1 << 1)
145 #define TESTER_UART_RX_CHECKSUM (0x104 + 0x00104000)
146 #define TESTER_UART_RX_CHECKSUM_SIZE 4
147 #define TESTER_UART_RX_COUNT (0x108 + 0x00104000)
148 #define TESTER_UART_RX_COUNT_SIZE 4
149 #define TESTER_UART_RX_PARITY_ERRORS (0x10C + 0x00104000)
150 #define TESTER_UART_RX_PARITY_ERRORS_SIZE 4
151 #define TESTER_UART_RX_STOP_ERRORS (0x110 + 0x00104000)
152 #define TESTER_UART_RX_STOP_ERRORS_SIZE 4
153 #define TESTER_UART_RX_FRAMING_ERRORS (0x114 + 0x00104000)
154 #define TESTER_UART_RX_FRAMING_ERRORS_SIZE 4
155 #define TESTER_UART_RX_PREV_4 (0x118 + 0x00104000)
156 #define TESTER_UART_RX_PREV_4_SIZE 2
157 #define TESTER_UART_RX_PREV_3 (0x11A + 0x00104000)
158 #define TESTER_UART_RX_PREV_3_SIZE 2
159 #define TESTER_UART_RX_PREV_2 (0x11C + 0x00104000)
160 #define TESTER_UART_RX_PREV_2_SIZE 2
161 #define TESTER_UART_RX_PREV_1 (0x11E + 0x00104000)
162 #define TESTER_UART_RX_PREV_1_SIZE 2
163 #define TESTER_UART_TX_CONTROL (0x200 + 0x00104000)
164 #define TESTER_UART_TX_CONTROL_SIZE 4
165 #define TESTER_UART_TX_CONTROL_ENABLE (1 << 0)
166 #define TESTER_UART_TX_CONTROL_RESET (1 << 1)
167 #define TESTER_UART_TX_CONTROL_ENABLE_CTS (1 << 2)
168 #define TESTER_UART_TX_COUNT (0x204 + 0x00104000)
169 #define TESTER_UART_TX_COUNT_SIZE 4
170 #define TESTER_UART_TX_NEXT (0x208 + 0x00104000)
171 #define TESTER_UART_TX_NEXT_SIZE 2
172 #define TESTER_UART_CTS_DEACTIVATE_DELAY (0x210 + 0x00104000)
173 #define TESTER_UART_CTS_DEACTIVATE_DELAY_SIZE 4
174 #define TESTER_UART_TX_DELAY (0x214 + 0x00104000)
175 #define TESTER_UART_TX_DELAY_SIZE 4
176 #define TESTER_I2C_STARTS (0x000 + 0x00105000)
177 #define TESTER_I2C_STOPS (0x001 + 0x00105000)
178 #define TESTER_I2C_ACKS (0x002 + 0x00105000)
179 #define TESTER_I2C_NACKS (0x004 + 0x00105000)
180 #define TESTER_I2C_TRANSFERS (0x006 + 0x00105000)
181 #define TESTER_I2C_TRANSFERS_SIZE 2
182 #define TESTER_I2C_TO_SLAVE_CHECKSUM (0x008 + 0x00105000)
183 #define TESTER_I2C_TO_SLAVE_CHECKSUM_SIZE 4
184 #define TESTER_I2C_STATE_NUM (0x00C + 0x00105000)
185 #define TESTER_I2C_NUMBER_DEV_ADDR_MATCHES (0x00D + 0x00105000)
186 #define TESTER_I2C_DEVICE_ADDRESS (0x00E + 0x00105000)
187 #define TESTER_I2C_SET_SDA (0x010 + 0x00105000)
188 #define TESTER_I2C_PREV_TO_SLAVE_4 (0x011 + 0x00105000)
189 #define TESTER_I2C_PREV_TO_SLAVE_3 (0x012 + 0x00105000)
190 #define TESTER_I2C_PREV_TO_SLAVE_2 (0x013 + 0x00105000)
191 #define TESTER_I2C_PREV_TO_SLAVE_1 (0x014 + 0x00105000)
192 #define TESTER_I2C_NEXT_FROM_SLAVE (0x015 + 0x00105000)
193 #define TESTER_I2C_NUM_WRITES (0x016 + 0x00105000)
194 #define TESTER_I2C_NUM_READS (0x018 + 0x00105000)
195 #define TESTER_I2C_FROM_SLAVE_CHECKSUM (0x01A + 0x00105000)
196 #define TESTER_I2C_FROM_SLAVE_CHECKSUM_SIZE 4
197 #define TESTER_I2C_NUMBER_DEV_ADDR_MISMATCHES (0x01E + 0x00105000)
198 #define TESTER_I2C_NUMBER_DEV_ADDR_MISMATCHES_SIZE 1
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