Lee Kai Xuan / mbed-os

mbed-os

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targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file rfAna.c
elessair 0:f269e3021894 4 * @brief Implementation of rfAna hw module functions
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 3445 $
elessair 0:f269e3021894 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup rfAna
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 *
elessair 0:f269e3021894 31 * <h1> Reference document(s) </h1>
elessair 0:f269e3021894 32 */
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 /*************************************************************************************************
elessair 0:f269e3021894 35 * *
elessair 0:f269e3021894 36 * Header files *
elessair 0:f269e3021894 37 * *
elessair 0:f269e3021894 38 *************************************************************************************************/
elessair 0:f269e3021894 39
elessair 0:f269e3021894 40 #include "memory_map.h"
elessair 0:f269e3021894 41 #include "rfAna.h"
elessair 0:f269e3021894 42 #include "clock.h"
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #ifdef REVA
elessair 0:f269e3021894 45 #include "test.h"
elessair 0:f269e3021894 46 #endif
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 /*************************************************************************************************
elessair 0:f269e3021894 49 * *
elessair 0:f269e3021894 50 * Global variables *
elessair 0:f269e3021894 51 * *
elessair 0:f269e3021894 52 *************************************************************************************************/
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 /** Rf channel and tx power lookup tables (constant)
elessair 0:f269e3021894 55 * @details
elessair 0:f269e3021894 56 *
elessair 0:f269e3021894 57 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
elessair 0:f269e3021894 58 * It has 16 entries corresponding to 16 15.4 channels.
elessair 0:f269e3021894 59 * Entry 1 <-> Channel 11
elessair 0:f269e3021894 60 * ...
elessair 0:f269e3021894 61 * Entry 16 <-> Channel 26
elessair 0:f269e3021894 62 *
elessair 0:f269e3021894 63 * Each entry is compound of 4 items.
elessair 0:f269e3021894 64 * Item 0: Rx Frequency integer divide portion
elessair 0:f269e3021894 65 * Item 1: Rx Frequency fractional divide portion
elessair 0:f269e3021894 66 * Item 2: Tx Frequency integer divide portion
elessair 0:f269e3021894 67 * Item 3: Tx Frequency fractional divide portion
elessair 0:f269e3021894 68 *
elessair 0:f269e3021894 69 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
elessair 0:f269e3021894 70 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
elessair 0:f269e3021894 71 * Entry 1 <-> -32dB
elessair 0:f269e3021894 72 * Entry 2 <-> -31dB
elessair 0:f269e3021894 73 * ...
elessair 0:f269e3021894 74 * Entry 2 <-> 9dB
elessair 0:f269e3021894 75 * Entry 43 <-> +10dB
elessair 0:f269e3021894 76 *
elessair 0:f269e3021894 77 * Each entry is compound of 1 byte.
elessair 0:f269e3021894 78 */
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 // RR: Making high side injection changes to RevD
elessair 0:f269e3021894 81 #ifdef REVD
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83 /** This rf LUT is built for high side injection, using low side injection
elessair 0:f269e3021894 84 * would requiere to change this LUT. */
elessair 0:f269e3021894 85 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
elessair 0:f269e3021894 86 {0x50,0x017F52,0x4B,0x014001},
elessair 0:f269e3021894 87 {0x51,0xFE29FB,0x4B,0x01E001},
elessair 0:f269e3021894 88 {0x51,0xFED4A6,0x4C,0xFE7FFF},
elessair 0:f269e3021894 89 {0x51,0xFF7F51,0x4C,0xFF1FFF},
elessair 0:f269e3021894 90 {0x51,0x0029FC,0x4C,0xFFC000},
elessair 0:f269e3021894 91 {0x51,0x00D4A7,0x4C,0x006000},
elessair 0:f269e3021894 92 {0x51,0x017F52,0x4C,0x010001},
elessair 0:f269e3021894 93 {0x52,0xFE29FB,0x4C,0x01A001},
elessair 0:f269e3021894 94 {0x52,0xFED4A6,0x4D,0xFE3FFF},
elessair 0:f269e3021894 95 {0x52,0xFF7F51,0x4D,0xFEDFFF},
elessair 0:f269e3021894 96 {0x52,0x0029FC,0x4D,0xFF8000},
elessair 0:f269e3021894 97 {0x52,0x00D4A7,0x4D,0x002000},
elessair 0:f269e3021894 98 {0x52,0x017F52,0x4D,0x00C001},
elessair 0:f269e3021894 99 {0x53,0xFE29FB,0x4D,0x016001},
elessair 0:f269e3021894 100 {0x53,0xFED4A6,0x4E,0xFDFFFE}
elessair 0:f269e3021894 101 };
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
elessair 0:f269e3021894 104 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
elessair 0:f269e3021894 105 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
elessair 0:f269e3021894 106 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
elessair 0:f269e3021894 107 13,14,15,16,17,18,19,20,20,20
elessair 0:f269e3021894 108 }; // +1dBm to +10 dBm
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 #endif /* REVD */
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 #ifdef REVC
elessair 0:f269e3021894 113 /** This rf LUT is built for low side injection, using high side injection
elessair 0:f269e3021894 114 * would requiere to change this LUT. */
elessair 0:f269e3021894 115 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
elessair 0:f269e3021894 116 {0x47,0xFFAC93,0x4B,0x014001},
elessair 0:f269e3021894 117 {0x47,0x00432A,0x4B,0x01E001},
elessair 0:f269e3021894 118 {0x47,0x00D9C1,0x4C,0xFE7FFF},
elessair 0:f269e3021894 119 {0x47,0x017058,0x4C,0xFF1FFF},
elessair 0:f269e3021894 120 {0x48,0xFE06EC,0x4C,0xFFC000},
elessair 0:f269e3021894 121 {0x48,0xFE9D83,0x4C,0x006000},
elessair 0:f269e3021894 122 {0x48,0xFF341A,0x4C,0x010001},
elessair 0:f269e3021894 123 {0x48,0xFFCAB1,0x4C,0x01A001},
elessair 0:f269e3021894 124 {0x48,0x006148,0x4D,0xFE3FFF},
elessair 0:f269e3021894 125 {0x48,0x00F7DF,0x4D,0xFEDFFF},
elessair 0:f269e3021894 126 {0x48,0x018E76,0x4D,0xFF8000},
elessair 0:f269e3021894 127 {0x49,0xFE250A,0x4D,0x002000},
elessair 0:f269e3021894 128 {0x49,0xFEBBA1,0x4D,0x00C001},
elessair 0:f269e3021894 129 {0x49,0xFF5238,0x4D,0x016001},
elessair 0:f269e3021894 130 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
elessair 0:f269e3021894 131 };
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
elessair 0:f269e3021894 134 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
elessair 0:f269e3021894 135 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
elessair 0:f269e3021894 136 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
elessair 0:f269e3021894 137 17,19,20,20,20,20,20,20,20,20
elessair 0:f269e3021894 138 }; // +1dBm to +10 dBm (clamp high at +3dB)
elessair 0:f269e3021894 139 #endif /* REVC */
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 #ifdef REVB
elessair 0:f269e3021894 142 /** This rf LUT is built for low side injection, using high side injection
elessair 0:f269e3021894 143 * would requiere to change this LUT. */
elessair 0:f269e3021894 144 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
elessair 0:f269e3021894 145 {0x47,0xFFAC93,0x4B,0x014001},
elessair 0:f269e3021894 146 {0x47,0x00432A,0x4B,0x01E001},
elessair 0:f269e3021894 147 {0x47,0x00D9C1,0x4C,0xFE7FFF},
elessair 0:f269e3021894 148 {0x47,0x017058,0x4C,0xFF1FFF},
elessair 0:f269e3021894 149 {0x48,0xFE06EC,0x4C,0xFFC000},
elessair 0:f269e3021894 150 {0x48,0xFE9D83,0x4C,0x006000},
elessair 0:f269e3021894 151 {0x48,0xFF341A,0x4C,0x010001},
elessair 0:f269e3021894 152 {0x48,0xFFCAB1,0x4C,0x01A001},
elessair 0:f269e3021894 153 {0x48,0x006148,0x4D,0xFE3FFF},
elessair 0:f269e3021894 154 {0x48,0x00F7DF,0x4D,0xFEDFFF},
elessair 0:f269e3021894 155 {0x48,0x018E76,0x4D,0xFF8000},
elessair 0:f269e3021894 156 {0x49,0xFE250A,0x4D,0x002000},
elessair 0:f269e3021894 157 {0x49,0xFEBBA1,0x4D,0x00C001},
elessair 0:f269e3021894 158 {0x49,0xFF5238,0x4D,0x016001},
elessair 0:f269e3021894 159 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
elessair 0:f269e3021894 160 };
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
elessair 0:f269e3021894 163 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
elessair 0:f269e3021894 164 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
elessair 0:f269e3021894 165 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
elessair 0:f269e3021894 166 17,19,20,20,20,20,20,20,20,20
elessair 0:f269e3021894 167 }; // +1dBm to +10 dBm (clamp high at +3dB)
elessair 0:f269e3021894 168 #endif
elessair 0:f269e3021894 169
elessair 0:f269e3021894 170 #ifdef REVA
elessair 0:f269e3021894 171 const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
elessair 0:f269e3021894 172 {0x57,0x0007DA,0x52,0xFE1FFF},
elessair 0:f269e3021894 173 {0x57,0x00B285,0x52,0xFEBFFF},
elessair 0:f269e3021894 174 {0x57,0x015D30,0x52,0xFF6000},
elessair 0:f269e3021894 175 {0x58,0xFE07D8,0x52,0x000000},
elessair 0:f269e3021894 176 {0x58,0xFEB283,0x52,0x00A000},
elessair 0:f269e3021894 177 {0x58,0xFF5D2F,0x52,0x014001},
elessair 0:f269e3021894 178 {0x58,0x0007DA,0x52,0x01E001},
elessair 0:f269e3021894 179 {0x58,0x00B285,0x53,0xFE7FFF},
elessair 0:f269e3021894 180 {0x58,0x015D30,0x53,0xFF1FFF},
elessair 0:f269e3021894 181 {0x59,0xFE07D8,0x53,0xFFC000},
elessair 0:f269e3021894 182 {0x59,0xFEB283,0x53,0x006000},
elessair 0:f269e3021894 183 {0x59,0xFF5D2F,0x53,0x010001},
elessair 0:f269e3021894 184 {0x59,0x0007DA,0x53,0x01A001},
elessair 0:f269e3021894 185 {0x59,0x00B285,0x53,0xFE3FFF},
elessair 0:f269e3021894 186 {0x59,0x015D30,0x53,0xFEDFFF}
elessair 0:f269e3021894 187 };
elessair 0:f269e3021894 188
elessair 0:f269e3021894 189 const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
elessair 0:f269e3021894 190 4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
elessair 0:f269e3021894 191 5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
elessair 0:f269e3021894 192 5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
elessair 0:f269e3021894 193 5,5,5,5,5,5,5,5,5,5
elessair 0:f269e3021894 194 }; // +1dBm to +10 dBm
elessair 0:f269e3021894 195 #endif
elessair 0:f269e3021894 196
elessair 0:f269e3021894 197 /*************************************************************************************************
elessair 0:f269e3021894 198 * *
elessair 0:f269e3021894 199 * Functions *
elessair 0:f269e3021894 200 * *
elessair 0:f269e3021894 201 *************************************************************************************************/
elessair 0:f269e3021894 202
elessair 0:f269e3021894 203 void fRfAnaInit()
elessair 0:f269e3021894 204 {
elessair 0:f269e3021894 205 // Enable rfana clock
elessair 0:f269e3021894 206 CLOCK_ENABLE(CLOCK_RFANA);
elessair 0:f269e3021894 207
elessair 0:f269e3021894 208 #ifdef REVA
elessair 0:f269e3021894 209 // Force Pll lock (it shouldn't be needed for either silicon if the part is configured/trimmed properly)
elessair 0:f269e3021894 210 fTestForcePllLock();
elessair 0:f269e3021894 211 // Bypass Pll regulator
elessair 0:f269e3021894 212 fTestBypassPllReg();
elessair 0:f269e3021894 213 #endif
elessair 0:f269e3021894 214
elessair 0:f269e3021894 215 // Set PLL timing
elessair 0:f269e3021894 216 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
elessair 0:f269e3021894 217 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 // Set other parameters
elessair 0:f269e3021894 220 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
elessair 0:f269e3021894 221 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
elessair 0:f269e3021894 222 }
elessair 0:f269e3021894 223
elessair 0:f269e3021894 224 boolean fRfAnaIoctl (uint32_t request, void *argument)
elessair 0:f269e3021894 225 {
elessair 0:f269e3021894 226 uint8_t channel, txPower;
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
elessair 0:f269e3021894 229 CLOCK_ENABLE(CLOCK_RFANA);
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 switch(request) {
elessair 0:f269e3021894 232 case SET_RF_CHANNEL:
elessair 0:f269e3021894 233 channel = *(uint8_t*)argument;
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 // Set tx/rx integer/fractional divide portions
elessair 0:f269e3021894 236 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
elessair 0:f269e3021894 237 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
elessair 0:f269e3021894 238 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
elessair 0:f269e3021894 239 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
elessair 0:f269e3021894 240
elessair 0:f269e3021894 241 // Set tx/rx vco trims
elessair 0:f269e3021894 242 #ifdef REVB
elessair 0:f269e3021894 243 /** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
elessair 0:f269e3021894 244 * from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
elessair 0:f269e3021894 245 if (channel < 19) {
elessair 0:f269e3021894 246 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
elessair 0:f269e3021894 247 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
elessair 0:f269e3021894 248 } else {
elessair 0:f269e3021894 249 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
elessair 0:f269e3021894 250 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
elessair 0:f269e3021894 251 }
elessair 0:f269e3021894 252 #endif /* REVB */
elessair 0:f269e3021894 253 #ifdef REVC
elessair 0:f269e3021894 254 /** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
elessair 0:f269e3021894 255 * from trims stored in dedicated registers available in digital.*/
elessair 0:f269e3021894 256 if (channel < 19) {
elessair 0:f269e3021894 257 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
elessair 0:f269e3021894 258 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
elessair 0:f269e3021894 259 } else {
elessair 0:f269e3021894 260 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
elessair 0:f269e3021894 261 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
elessair 0:f269e3021894 262 }
elessair 0:f269e3021894 263 #endif /* REVC */
elessair 0:f269e3021894 264 #ifdef REVD
elessair 0:f269e3021894 265 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
elessair 0:f269e3021894 266 * from trims stored in dedicated registers available in digital.*/
elessair 0:f269e3021894 267 if (channel < 19) {
elessair 0:f269e3021894 268 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
elessair 0:f269e3021894 269 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
elessair 0:f269e3021894 270 } else {
elessair 0:f269e3021894 271 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
elessair 0:f269e3021894 272 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
elessair 0:f269e3021894 273 }
elessair 0:f269e3021894 274 #endif /* REVD */
elessair 0:f269e3021894 275 break;
elessair 0:f269e3021894 276 case SET_TX_POWER:
elessair 0:f269e3021894 277 txPower = *(uint8_t*)argument;
elessair 0:f269e3021894 278
elessair 0:f269e3021894 279 // Set tx power register
elessair 0:f269e3021894 280 if ((txPower & 0x20) == 0) {
elessair 0:f269e3021894 281 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
elessair 0:f269e3021894 282 } else {
elessair 0:f269e3021894 283 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
elessair 0:f269e3021894 284 }
elessair 0:f269e3021894 285
elessair 0:f269e3021894 286 break;
elessair 0:f269e3021894 287 default:
elessair 0:f269e3021894 288 return False;
elessair 0:f269e3021894 289 }
elessair 0:f269e3021894 290 return True;
elessair 0:f269e3021894 291 }