Lee Kai Xuan / mbed-os

mbed-os

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targets/TARGET_NXP/TARGET_LPC43XX/README.txt@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 mbed port to NXP LPC43xx
elessair 0:f269e3021894 2 ========================
elessair 0:f269e3021894 3 Updated: 07/11/14
elessair 0:f269e3021894 4
elessair 0:f269e3021894 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
elessair 0:f269e3021894 6 microcontroller package. This port allows mbed developers to take advantage
elessair 0:f269e3021894 7 of the LPC43xx in their application using APIs that they are familiar with.
elessair 0:f269e3021894 8 Some of the key features of the LPC43xx include:
elessair 0:f269e3021894 9
elessair 0:f269e3021894 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
elessair 0:f269e3021894 11 * Up to 264 KB SRAM, 1 MB internal flash
elessair 0:f269e3021894 12 * Two High-speed USB 2.0 interfaces
elessair 0:f269e3021894 13 * Ethernet MAC
elessair 0:f269e3021894 14 * LCD interface
elessair 0:f269e3021894 15 * Quad-SPI Flash Interface (SPIFI)
elessair 0:f269e3021894 16 * State Configurable Timer (SCT)
elessair 0:f269e3021894 17 * Serial GPIO (SGPIO)
elessair 0:f269e3021894 18 * Up to 164 GPIO
elessair 0:f269e3021894 19
elessair 0:f269e3021894 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
elessair 0:f269e3021894 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
elessair 0:f269e3021894 22
elessair 0:f269e3021894 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
elessair 0:f269e3021894 24
elessair 0:f269e3021894 25 Compatibility
elessair 0:f269e3021894 26 -------------
elessair 0:f269e3021894 27 * This port has been tested with the following boards:
elessair 0:f269e3021894 28 Board MCU RAM/Flash
elessair 0:f269e3021894 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
elessair 0:f269e3021894 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
elessair 0:f269e3021894 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
elessair 0:f269e3021894 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
elessair 0:f269e3021894 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
elessair 0:f269e3021894 36 for flash programming.
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
elessair 0:f269e3021894 39 codebase. The core declaration specifies the binaries to be built:
elessair 0:f269e3021894 40 mbed define CMSIS define MCU Target
elessair 0:f269e3021894 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
elessair 0:f269e3021894 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
elessair 0:f269e3021894 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
elessair 0:f269e3021894 44 These MCUs all share the peripheral IP, common driver code is feasible.
elessair 0:f269e3021894 45 Yet each variant can have different memory segments, peripherals, etc.
elessair 0:f269e3021894 46 Plus, each board design can integrate different external peripherals
elessair 0:f269e3021894 47 or interfaces. A future release of the mbed SDK and its build tools will
elessair 0:f269e3021894 48 support specifying the target board when building binaries. At this time
elessair 0:f269e3021894 49 building binaries for different targets requires an external project or
elessair 0:f269e3021894 50 Makefile.
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 * No testing has been done with LPC18xx hardware.
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 Notes
elessair 0:f269e3021894 55 -----
elessair 0:f269e3021894 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
elessair 0:f269e3021894 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
elessair 0:f269e3021894 58 the pin identifier encodes the offsets. Macros are used for decoding.
elessair 0:f269e3021894 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
elessair 0:f269e3021894 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
elessair 0:f269e3021894 65
elessair 0:f269e3021894 66 * Pin names use multiple aliases to support Arduino naming conventions as well
elessair 0:f269e3021894 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
elessair 0:f269e3021894 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
elessair 0:f269e3021894 69 See the board pinout graphic and the PinNames.h for available aliases.
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
elessair 0:f269e3021894 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
elessair 0:f269e3021894 73 pin can only interrupt on the rising or falling edge, not both as required
elessair 0:f269e3021894 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
elessair 0:f269e3021894 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
elessair 0:f269e3021894 76 A future implementation may provide group interrupt support.
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
elessair 0:f269e3021894 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
elessair 0:f269e3021894 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
elessair 0:f269e3021894 81 when building the library.