Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NXP/TARGET_LPC176X/serial_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 // math.h required for floating point operations for baud rate calculation
elessair 0:f269e3021894 17 #include "mbed_assert.h"
elessair 0:f269e3021894 18 #include <math.h>
elessair 0:f269e3021894 19 #include <string.h>
elessair 0:f269e3021894 20 #include <stdlib.h>
elessair 0:f269e3021894 21
elessair 0:f269e3021894 22 #include "serial_api.h"
elessair 0:f269e3021894 23 #include "cmsis.h"
elessair 0:f269e3021894 24 #include "pinmap.h"
elessair 0:f269e3021894 25 #include "gpio_api.h"
elessair 0:f269e3021894 26
elessair 0:f269e3021894 27 /******************************************************************************
elessair 0:f269e3021894 28 * INITIALIZATION
elessair 0:f269e3021894 29 ******************************************************************************/
elessair 0:f269e3021894 30 #define UART_NUM 4
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 static const PinMap PinMap_UART_TX[] = {
elessair 0:f269e3021894 33 {P0_0, UART_3, 2},
elessair 0:f269e3021894 34 {P0_2, UART_0, 1},
elessair 0:f269e3021894 35 {P0_10, UART_2, 1},
elessair 0:f269e3021894 36 {P0_15, UART_1, 1},
elessair 0:f269e3021894 37 {P0_25, UART_3, 3},
elessair 0:f269e3021894 38 {P2_0 , UART_1, 2},
elessair 0:f269e3021894 39 {P2_8 , UART_2, 2},
elessair 0:f269e3021894 40 {P4_28, UART_3, 3},
elessair 0:f269e3021894 41 {NC , NC , 0}
elessair 0:f269e3021894 42 };
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 static const PinMap PinMap_UART_RX[] = {
elessair 0:f269e3021894 45 {P0_1 , UART_3, 2},
elessair 0:f269e3021894 46 {P0_3 , UART_0, 1},
elessair 0:f269e3021894 47 {P0_11, UART_2, 1},
elessair 0:f269e3021894 48 {P0_16, UART_1, 1},
elessair 0:f269e3021894 49 {P0_26, UART_3, 3},
elessair 0:f269e3021894 50 {P2_1 , UART_1, 2},
elessair 0:f269e3021894 51 {P2_9 , UART_2, 2},
elessair 0:f269e3021894 52 {P4_29, UART_3, 3},
elessair 0:f269e3021894 53 {NC , NC , 0}
elessair 0:f269e3021894 54 };
elessair 0:f269e3021894 55
elessair 0:f269e3021894 56 static const PinMap PinMap_UART_RTS[] = {
elessair 0:f269e3021894 57 {P0_22, UART_1, 1},
elessair 0:f269e3021894 58 {P2_7, UART_1, 2},
elessair 0:f269e3021894 59 {NC, NC, 0}
elessair 0:f269e3021894 60 };
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 static const PinMap PinMap_UART_CTS[] = {
elessair 0:f269e3021894 63 {P0_17, UART_1, 1},
elessair 0:f269e3021894 64 {P2_2, UART_1, 2},
elessair 0:f269e3021894 65 {NC, NC, 0}
elessair 0:f269e3021894 66 };
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 #define UART_MCR_RTSEN_MASK (1 << 6)
elessair 0:f269e3021894 69 #define UART_MCR_CTSEN_MASK (1 << 7)
elessair 0:f269e3021894 70 #define UART_MCR_FLOWCTRL_MASK (UART_MCR_RTSEN_MASK | UART_MCR_CTSEN_MASK)
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 static uart_irq_handler irq_handler;
elessair 0:f269e3021894 73
elessair 0:f269e3021894 74 int stdio_uart_inited = 0;
elessair 0:f269e3021894 75 serial_t stdio_uart;
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 struct serial_global_data_s {
elessair 0:f269e3021894 78 uint32_t serial_irq_id;
elessair 0:f269e3021894 79 gpio_t sw_rts, sw_cts;
elessair 0:f269e3021894 80 uint8_t count, rx_irq_set_flow, rx_irq_set_api;
elessair 0:f269e3021894 81 };
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83 static struct serial_global_data_s uart_data[UART_NUM];
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 void serial_init(serial_t *obj, PinName tx, PinName rx) {
elessair 0:f269e3021894 86 int is_stdio_uart = 0;
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 // determine the UART to use
elessair 0:f269e3021894 89 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
elessair 0:f269e3021894 90 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
elessair 0:f269e3021894 91 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
elessair 0:f269e3021894 92 MBED_ASSERT((int)uart != NC);
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 obj->uart = (LPC_UART_TypeDef *)uart;
elessair 0:f269e3021894 95 // enable power
elessair 0:f269e3021894 96 switch (uart) {
elessair 0:f269e3021894 97 case UART_0: LPC_SC->PCONP |= 1 << 3; break;
elessair 0:f269e3021894 98 case UART_1: LPC_SC->PCONP |= 1 << 4; break;
elessair 0:f269e3021894 99 case UART_2: LPC_SC->PCONP |= 1 << 24; break;
elessair 0:f269e3021894 100 case UART_3: LPC_SC->PCONP |= 1 << 25; break;
elessair 0:f269e3021894 101 }
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 // enable fifos and default rx trigger level
elessair 0:f269e3021894 104 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
elessair 0:f269e3021894 105 | 0 << 1 // Rx Fifo Reset
elessair 0:f269e3021894 106 | 0 << 2 // Tx Fifo Reset
elessair 0:f269e3021894 107 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 // disable irqs
elessair 0:f269e3021894 110 obj->uart->IER = 0 << 0 // Rx Data available irq enable
elessair 0:f269e3021894 111 | 0 << 1 // Tx Fifo empty irq enable
elessair 0:f269e3021894 112 | 0 << 2; // Rx Line Status irq enable
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 // set default baud rate and format
elessair 0:f269e3021894 115 serial_baud (obj, 9600);
elessair 0:f269e3021894 116 serial_format(obj, 8, ParityNone, 1);
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 // pinout the chosen uart
elessair 0:f269e3021894 119 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 120 pinmap_pinout(rx, PinMap_UART_RX);
elessair 0:f269e3021894 121
elessair 0:f269e3021894 122 // set rx/tx pins in PullUp mode
elessair 0:f269e3021894 123 if (tx != NC) {
elessair 0:f269e3021894 124 pin_mode(tx, PullUp);
elessair 0:f269e3021894 125 }
elessair 0:f269e3021894 126 if (rx != NC) {
elessair 0:f269e3021894 127 pin_mode(rx, PullUp);
elessair 0:f269e3021894 128 }
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 switch (uart) {
elessair 0:f269e3021894 131 case UART_0: obj->index = 0; break;
elessair 0:f269e3021894 132 case UART_1: obj->index = 1; break;
elessair 0:f269e3021894 133 case UART_2: obj->index = 2; break;
elessair 0:f269e3021894 134 case UART_3: obj->index = 3; break;
elessair 0:f269e3021894 135 }
elessair 0:f269e3021894 136 uart_data[obj->index].sw_rts.pin = NC;
elessair 0:f269e3021894 137 uart_data[obj->index].sw_cts.pin = NC;
elessair 0:f269e3021894 138 serial_set_flow_control(obj, FlowControlNone, NC, NC);
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
elessair 0:f269e3021894 141
elessair 0:f269e3021894 142 if (is_stdio_uart) {
elessair 0:f269e3021894 143 stdio_uart_inited = 1;
elessair 0:f269e3021894 144 memcpy(&stdio_uart, obj, sizeof(serial_t));
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146 }
elessair 0:f269e3021894 147
elessair 0:f269e3021894 148 void serial_free(serial_t *obj) {
elessair 0:f269e3021894 149 uart_data[obj->index].serial_irq_id = 0;
elessair 0:f269e3021894 150 }
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 // serial_baud
elessair 0:f269e3021894 153 // set the baud rate, taking in to account the current SystemFrequency
elessair 0:f269e3021894 154 void serial_baud(serial_t *obj, int baudrate) {
elessair 0:f269e3021894 155 MBED_ASSERT((int)obj->uart <= UART_3);
elessair 0:f269e3021894 156 // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
elessair 0:f269e3021894 157 // baud rate. The formula is:
elessair 0:f269e3021894 158 //
elessair 0:f269e3021894 159 // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
elessair 0:f269e3021894 160 // where:
elessair 0:f269e3021894 161 // 1 < MulVal <= 15
elessair 0:f269e3021894 162 // 0 <= DivAddVal < 14
elessair 0:f269e3021894 163 // DivAddVal < MulVal
elessair 0:f269e3021894 164 //
elessair 0:f269e3021894 165 // set pclk to /1
elessair 0:f269e3021894 166 switch ((int)obj->uart) {
elessair 0:f269e3021894 167 case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 << 6); LPC_SC->PCLKSEL0 |= (0x1 << 6); break;
elessair 0:f269e3021894 168 case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 << 8); LPC_SC->PCLKSEL0 |= (0x1 << 8); break;
elessair 0:f269e3021894 169 case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
elessair 0:f269e3021894 170 case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
elessair 0:f269e3021894 171 default: break;
elessair 0:f269e3021894 172 }
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174 uint32_t PCLK = SystemCoreClock;
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 // First we check to see if the basic divide with no DivAddVal/MulVal
elessair 0:f269e3021894 177 // ratio gives us an integer result. If it does, we set DivAddVal = 0,
elessair 0:f269e3021894 178 // MulVal = 1. Otherwise, we search the valid ratio value range to find
elessair 0:f269e3021894 179 // the closest match. This could be more elegant, using search methods
elessair 0:f269e3021894 180 // and/or lookup tables, but the brute force method is not that much
elessair 0:f269e3021894 181 // slower, and is more maintainable.
elessair 0:f269e3021894 182 uint16_t DL = PCLK / (16 * baudrate);
elessair 0:f269e3021894 183
elessair 0:f269e3021894 184 uint8_t DivAddVal = 0;
elessair 0:f269e3021894 185 uint8_t MulVal = 1;
elessair 0:f269e3021894 186 int hit = 0;
elessair 0:f269e3021894 187 uint16_t dlv;
elessair 0:f269e3021894 188 uint8_t mv, dav;
elessair 0:f269e3021894 189 if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
elessair 0:f269e3021894 190 int err_best = baudrate, b;
elessair 0:f269e3021894 191 for (mv = 1; mv < 16 && !hit; mv++)
elessair 0:f269e3021894 192 {
elessair 0:f269e3021894 193 for (dav = 0; dav < mv; dav++)
elessair 0:f269e3021894 194 {
elessair 0:f269e3021894 195 // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
elessair 0:f269e3021894 196 // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
elessair 0:f269e3021894 197 // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
elessair 0:f269e3021894 198 // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
elessair 0:f269e3021894 199 // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
elessair 0:f269e3021894 200
elessair 0:f269e3021894 201 if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
elessair 0:f269e3021894 202 dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
elessair 0:f269e3021894 203 else // 2 bits headroom, use more precision
elessair 0:f269e3021894 204 dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206 // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
elessair 0:f269e3021894 207 if (dlv == 0)
elessair 0:f269e3021894 208 dlv = 1;
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 // datasheet says if dav > 0 then DL must be >= 2
elessair 0:f269e3021894 211 if ((dav > 0) && (dlv < 2))
elessair 0:f269e3021894 212 dlv = 2;
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 // integer rearrangement of the baudrate equation (with rounding)
elessair 0:f269e3021894 215 b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
elessair 0:f269e3021894 216
elessair 0:f269e3021894 217 // check to see how we went
elessair 0:f269e3021894 218 b = abs(b - baudrate);
elessair 0:f269e3021894 219 if (b < err_best)
elessair 0:f269e3021894 220 {
elessair 0:f269e3021894 221 err_best = b;
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 DL = dlv;
elessair 0:f269e3021894 224 MulVal = mv;
elessair 0:f269e3021894 225 DivAddVal = dav;
elessair 0:f269e3021894 226
elessair 0:f269e3021894 227 if (b == baudrate)
elessair 0:f269e3021894 228 {
elessair 0:f269e3021894 229 hit = 1;
elessair 0:f269e3021894 230 break;
elessair 0:f269e3021894 231 }
elessair 0:f269e3021894 232 }
elessair 0:f269e3021894 233 }
elessair 0:f269e3021894 234 }
elessair 0:f269e3021894 235 }
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 // set LCR[DLAB] to enable writing to divider registers
elessair 0:f269e3021894 238 obj->uart->LCR |= (1 << 7);
elessair 0:f269e3021894 239
elessair 0:f269e3021894 240 // set divider values
elessair 0:f269e3021894 241 obj->uart->DLM = (DL >> 8) & 0xFF;
elessair 0:f269e3021894 242 obj->uart->DLL = (DL >> 0) & 0xFF;
elessair 0:f269e3021894 243 obj->uart->FDR = (uint32_t) DivAddVal << 0
elessair 0:f269e3021894 244 | (uint32_t) MulVal << 4;
elessair 0:f269e3021894 245
elessair 0:f269e3021894 246 // clear LCR[DLAB]
elessair 0:f269e3021894 247 obj->uart->LCR &= ~(1 << 7);
elessair 0:f269e3021894 248 }
elessair 0:f269e3021894 249
elessair 0:f269e3021894 250 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
elessair 0:f269e3021894 251 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
elessair 0:f269e3021894 252 MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
elessair 0:f269e3021894 253 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
elessair 0:f269e3021894 254 (parity == ParityForced1) || (parity == ParityForced0));
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 stop_bits -= 1;
elessair 0:f269e3021894 257 data_bits -= 5;
elessair 0:f269e3021894 258
elessair 0:f269e3021894 259 int parity_enable, parity_select;
elessair 0:f269e3021894 260 switch (parity) {
elessair 0:f269e3021894 261 case ParityNone: parity_enable = 0; parity_select = 0; break;
elessair 0:f269e3021894 262 case ParityOdd : parity_enable = 1; parity_select = 0; break;
elessair 0:f269e3021894 263 case ParityEven: parity_enable = 1; parity_select = 1; break;
elessair 0:f269e3021894 264 case ParityForced1: parity_enable = 1; parity_select = 2; break;
elessair 0:f269e3021894 265 case ParityForced0: parity_enable = 1; parity_select = 3; break;
elessair 0:f269e3021894 266 default:
elessair 0:f269e3021894 267 parity_enable = 0, parity_select = 0;
elessair 0:f269e3021894 268 break;
elessair 0:f269e3021894 269 }
elessair 0:f269e3021894 270
elessair 0:f269e3021894 271 obj->uart->LCR = data_bits << 0
elessair 0:f269e3021894 272 | stop_bits << 2
elessair 0:f269e3021894 273 | parity_enable << 3
elessair 0:f269e3021894 274 | parity_select << 4;
elessair 0:f269e3021894 275 }
elessair 0:f269e3021894 276
elessair 0:f269e3021894 277 /******************************************************************************
elessair 0:f269e3021894 278 * INTERRUPTS HANDLING
elessair 0:f269e3021894 279 ******************************************************************************/
elessair 0:f269e3021894 280 static inline void uart_irq(uint32_t iir, uint32_t index, LPC_UART_TypeDef *puart) {
elessair 0:f269e3021894 281 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
elessair 0:f269e3021894 282 SerialIrq irq_type;
elessair 0:f269e3021894 283 switch (iir) {
elessair 0:f269e3021894 284 case 1: irq_type = TxIrq; break;
elessair 0:f269e3021894 285 case 2: irq_type = RxIrq; break;
elessair 0:f269e3021894 286 default: return;
elessair 0:f269e3021894 287 }
elessair 0:f269e3021894 288 if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
elessair 0:f269e3021894 289 gpio_write(&uart_data[index].sw_rts, 1);
elessair 0:f269e3021894 290 // Disable interrupt if it wasn't enabled by other part of the application
elessair 0:f269e3021894 291 if (!uart_data[index].rx_irq_set_api)
elessair 0:f269e3021894 292 puart->IER &= ~(1 << RxIrq);
elessair 0:f269e3021894 293 }
elessair 0:f269e3021894 294 if (uart_data[index].serial_irq_id != 0)
elessair 0:f269e3021894 295 if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
elessair 0:f269e3021894 296 irq_handler(uart_data[index].serial_irq_id, irq_type);
elessair 0:f269e3021894 297 }
elessair 0:f269e3021894 298
elessair 0:f269e3021894 299 void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0, (LPC_UART_TypeDef*)LPC_UART0);}
elessair 0:f269e3021894 300 void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);}
elessair 0:f269e3021894 301 void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);}
elessair 0:f269e3021894 302 void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);}
elessair 0:f269e3021894 303
elessair 0:f269e3021894 304 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
elessair 0:f269e3021894 305 irq_handler = handler;
elessair 0:f269e3021894 306 uart_data[obj->index].serial_irq_id = id;
elessair 0:f269e3021894 307 }
elessair 0:f269e3021894 308
elessair 0:f269e3021894 309 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
elessair 0:f269e3021894 310 IRQn_Type irq_n = (IRQn_Type)0;
elessair 0:f269e3021894 311 uint32_t vector = 0;
elessair 0:f269e3021894 312 switch ((int)obj->uart) {
elessair 0:f269e3021894 313 case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
elessair 0:f269e3021894 314 case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
elessair 0:f269e3021894 315 case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
elessair 0:f269e3021894 316 case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
elessair 0:f269e3021894 317 }
elessair 0:f269e3021894 318
elessair 0:f269e3021894 319 if (enable) {
elessair 0:f269e3021894 320 obj->uart->IER |= 1 << irq;
elessair 0:f269e3021894 321 NVIC_SetVector(irq_n, vector);
elessair 0:f269e3021894 322 NVIC_EnableIRQ(irq_n);
elessair 0:f269e3021894 323 } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
elessair 0:f269e3021894 324 int all_disabled = 0;
elessair 0:f269e3021894 325 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
elessair 0:f269e3021894 326 obj->uart->IER &= ~(1 << irq);
elessair 0:f269e3021894 327 all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
elessair 0:f269e3021894 328 if (all_disabled)
elessair 0:f269e3021894 329 NVIC_DisableIRQ(irq_n);
elessair 0:f269e3021894 330 }
elessair 0:f269e3021894 331 }
elessair 0:f269e3021894 332
elessair 0:f269e3021894 333 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
elessair 0:f269e3021894 334 if (RxIrq == irq)
elessair 0:f269e3021894 335 uart_data[obj->index].rx_irq_set_api = enable;
elessair 0:f269e3021894 336 serial_irq_set_internal(obj, irq, enable);
elessair 0:f269e3021894 337 }
elessair 0:f269e3021894 338
elessair 0:f269e3021894 339 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
elessair 0:f269e3021894 340 uart_data[obj->index].rx_irq_set_flow = enable;
elessair 0:f269e3021894 341 serial_irq_set_internal(obj, RxIrq, enable);
elessair 0:f269e3021894 342 }
elessair 0:f269e3021894 343
elessair 0:f269e3021894 344 /******************************************************************************
elessair 0:f269e3021894 345 * READ/WRITE
elessair 0:f269e3021894 346 ******************************************************************************/
elessair 0:f269e3021894 347 int serial_getc(serial_t *obj) {
elessair 0:f269e3021894 348 while (!serial_readable(obj));
elessair 0:f269e3021894 349 int data = obj->uart->RBR;
elessair 0:f269e3021894 350 if (NC != uart_data[obj->index].sw_rts.pin) {
elessair 0:f269e3021894 351 gpio_write(&uart_data[obj->index].sw_rts, 0);
elessair 0:f269e3021894 352 obj->uart->IER |= 1 << RxIrq;
elessair 0:f269e3021894 353 }
elessair 0:f269e3021894 354 return data;
elessair 0:f269e3021894 355 }
elessair 0:f269e3021894 356
elessair 0:f269e3021894 357 void serial_putc(serial_t *obj, int c) {
elessair 0:f269e3021894 358 while (!serial_writable(obj));
elessair 0:f269e3021894 359 obj->uart->THR = c;
elessair 0:f269e3021894 360 uart_data[obj->index].count++;
elessair 0:f269e3021894 361 }
elessair 0:f269e3021894 362
elessair 0:f269e3021894 363 int serial_readable(serial_t *obj) {
elessair 0:f269e3021894 364 return obj->uart->LSR & 0x01;
elessair 0:f269e3021894 365 }
elessair 0:f269e3021894 366
elessair 0:f269e3021894 367 int serial_writable(serial_t *obj) {
elessair 0:f269e3021894 368 int isWritable = 1;
elessair 0:f269e3021894 369 if (NC != uart_data[obj->index].sw_cts.pin)
elessair 0:f269e3021894 370 isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
elessair 0:f269e3021894 371 else {
elessair 0:f269e3021894 372 if (obj->uart->LSR & 0x20)
elessair 0:f269e3021894 373 uart_data[obj->index].count = 0;
elessair 0:f269e3021894 374 else if (uart_data[obj->index].count >= 16)
elessair 0:f269e3021894 375 isWritable = 0;
elessair 0:f269e3021894 376 }
elessair 0:f269e3021894 377 return isWritable;
elessair 0:f269e3021894 378 }
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380 void serial_clear(serial_t *obj) {
elessair 0:f269e3021894 381 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
elessair 0:f269e3021894 382 | 1 << 1 // rx FIFO reset
elessair 0:f269e3021894 383 | 1 << 2 // tx FIFO reset
elessair 0:f269e3021894 384 | 0 << 6; // interrupt depth
elessair 0:f269e3021894 385 }
elessair 0:f269e3021894 386
elessair 0:f269e3021894 387 void serial_pinout_tx(PinName tx) {
elessair 0:f269e3021894 388 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 389 }
elessair 0:f269e3021894 390
elessair 0:f269e3021894 391 void serial_break_set(serial_t *obj) {
elessair 0:f269e3021894 392 obj->uart->LCR |= (1 << 6);
elessair 0:f269e3021894 393 }
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 void serial_break_clear(serial_t *obj) {
elessair 0:f269e3021894 396 obj->uart->LCR &= ~(1 << 6);
elessair 0:f269e3021894 397 }
elessair 0:f269e3021894 398
elessair 0:f269e3021894 399 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
elessair 0:f269e3021894 400 // Only UART1 has hardware flow control on LPC176x
elessair 0:f269e3021894 401 LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
elessair 0:f269e3021894 402 int index = obj->index;
elessair 0:f269e3021894 403
elessair 0:f269e3021894 404 // First, disable flow control completely
elessair 0:f269e3021894 405 if (uart1)
elessair 0:f269e3021894 406 uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
elessair 0:f269e3021894 407 uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
elessair 0:f269e3021894 408 serial_flow_irq_set(obj, 0);
elessair 0:f269e3021894 409 if (FlowControlNone == type)
elessair 0:f269e3021894 410 return;
elessair 0:f269e3021894 411 // Check type(s) of flow control to use
elessair 0:f269e3021894 412 UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 413 UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 414 if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
elessair 0:f269e3021894 415 // Can this be enabled in hardware?
elessair 0:f269e3021894 416 if ((UART_1 == uart_cts) && (NULL != uart1)) {
elessair 0:f269e3021894 417 // Enable auto-CTS mode
elessair 0:f269e3021894 418 uart1->MCR |= UART_MCR_CTSEN_MASK;
elessair 0:f269e3021894 419 pinmap_pinout(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 420 } else {
elessair 0:f269e3021894 421 // Can't enable in hardware, use software emulation
elessair 0:f269e3021894 422 gpio_init_in(&uart_data[index].sw_cts, txflow);
elessair 0:f269e3021894 423 }
elessair 0:f269e3021894 424 }
elessair 0:f269e3021894 425 if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
elessair 0:f269e3021894 426 // Enable FIFOs, trigger level of 1 char on RX FIFO
elessair 0:f269e3021894 427 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
elessair 0:f269e3021894 428 | 1 << 1 // Rx Fifo Reset
elessair 0:f269e3021894 429 | 1 << 2 // Tx Fifo Reset
elessair 0:f269e3021894 430 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
elessair 0:f269e3021894 431 // Can this be enabled in hardware?
elessair 0:f269e3021894 432 if ((UART_1 == uart_rts) && (NULL != uart1)) {
elessair 0:f269e3021894 433 // Enable auto-RTS mode
elessair 0:f269e3021894 434 uart1->MCR |= UART_MCR_RTSEN_MASK;
elessair 0:f269e3021894 435 pinmap_pinout(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 436 } else { // can't enable in hardware, use software emulation
elessair 0:f269e3021894 437 gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0);
elessair 0:f269e3021894 438 // Enable RX interrupt
elessair 0:f269e3021894 439 serial_flow_irq_set(obj, 1);
elessair 0:f269e3021894 440 }
elessair 0:f269e3021894 441 }
elessair 0:f269e3021894 442 }
elessair 0:f269e3021894 443