Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NXP/TARGET_LPC2460/device/LPC24xx.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library - LPC24xx CMSIS-like structs
elessair 0:f269e3021894 2 * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * An LPC24xx header file, based on LPC23xx.h
elessair 0:f269e3021894 5 */
elessair 0:f269e3021894 6
elessair 0:f269e3021894 7 #ifndef __LPC24xx_H
elessair 0:f269e3021894 8 #define __LPC24xx_H
elessair 0:f269e3021894 9
elessair 0:f269e3021894 10 #ifdef __cplusplus
elessair 0:f269e3021894 11 extern "C" {
elessair 0:f269e3021894 12 #endif
elessair 0:f269e3021894 13
elessair 0:f269e3021894 14 /*
elessair 0:f269e3021894 15 * ==========================================================================
elessair 0:f269e3021894 16 * ---------- Interrupt Number Definition -----------------------------------
elessair 0:f269e3021894 17 * ==========================================================================
elessair 0:f269e3021894 18 */
elessair 0:f269e3021894 19
elessair 0:f269e3021894 20 typedef enum IRQn
elessair 0:f269e3021894 21 {
elessair 0:f269e3021894 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
elessair 0:f269e3021894 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
elessair 0:f269e3021894 24
elessair 0:f269e3021894 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
elessair 0:f269e3021894 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
elessair 0:f269e3021894 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
elessair 0:f269e3021894 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
elessair 0:f269e3021894 29 PWM0_IRQn = 8, /*!< PWM0 Interrupt */
elessair 0:f269e3021894 30 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
elessair 0:f269e3021894 31 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
elessair 0:f269e3021894 32 SPI_IRQn = 10, /*!< SPI Interrupt */
elessair 0:f269e3021894 33 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
elessair 0:f269e3021894 34 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
elessair 0:f269e3021894 35 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
elessair 0:f269e3021894 36 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
elessair 0:f269e3021894 37 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
elessair 0:f269e3021894 38 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
elessair 0:f269e3021894 39 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
elessair 0:f269e3021894 40 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
elessair 0:f269e3021894 41 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
elessair 0:f269e3021894 42 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
elessair 0:f269e3021894 43 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
elessair 0:f269e3021894 44 ENET_IRQn = 21, /*!< Ethernet Interrupt */
elessair 0:f269e3021894 45 USB_IRQn = 22, /*!< USB Interrupt */
elessair 0:f269e3021894 46 CAN_IRQn = 23, /*!< CAN Interrupt */
elessair 0:f269e3021894 47 SDMMC_IRQn = 24, /*!< SD/MMC Interrupt */
elessair 0:f269e3021894 48 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
elessair 0:f269e3021894 49 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
elessair 0:f269e3021894 50 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
elessair 0:f269e3021894 51 UART2_IRQn = 28, /*!< UART2 Interrupt */
elessair 0:f269e3021894 52 UART3_IRQn = 29, /*!< UART3 Interrupt */
elessair 0:f269e3021894 53 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
elessair 0:f269e3021894 54 I2S_IRQn = 31, /*!< I2S Interrupt */
elessair 0:f269e3021894 55 } IRQn_Type;
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 /*
elessair 0:f269e3021894 58 * ==========================================================================
elessair 0:f269e3021894 59 * ----------- Processor and Core Peripheral Section ------------------------
elessair 0:f269e3021894 60 * ==========================================================================
elessair 0:f269e3021894 61 */
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 /* Configuration of the ARM7 Processor and Core Peripherals */
elessair 0:f269e3021894 64 #define __MPU_PRESENT 0 /*!< MPU present or not */
elessair 0:f269e3021894 65 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
elessair 0:f269e3021894 66 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68
elessair 0:f269e3021894 69 #include <core_arm7.h>
elessair 0:f269e3021894 70 #include "system_LPC24xx.h" /* System Header */
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 /******************************************************************************/
elessair 0:f269e3021894 74 /* Device Specific Peripheral registers structures */
elessair 0:f269e3021894 75 /******************************************************************************/
elessair 0:f269e3021894 76 #if defined ( __CC_ARM )
elessair 0:f269e3021894 77 #pragma anon_unions
elessair 0:f269e3021894 78 #endif
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
elessair 0:f269e3021894 81 typedef struct
elessair 0:f269e3021894 82 {
elessair 0:f269e3021894 83 __I uint32_t IRQStatus;
elessair 0:f269e3021894 84 __I uint32_t FIQStatus;
elessair 0:f269e3021894 85 __I uint32_t RawIntr;
elessair 0:f269e3021894 86 __IO uint32_t IntSelect;
elessair 0:f269e3021894 87 __IO uint32_t IntEnable;
elessair 0:f269e3021894 88 __O uint32_t IntEnClr;
elessair 0:f269e3021894 89 __IO uint32_t SoftInt;
elessair 0:f269e3021894 90 __O uint32_t SoftIntClr;
elessair 0:f269e3021894 91 __IO uint32_t Protection;
elessair 0:f269e3021894 92 __IO uint32_t SWPriorityMask;
elessair 0:f269e3021894 93 __IO uint32_t RESERVED0[54];
elessair 0:f269e3021894 94 __IO uint32_t VectAddr[32];
elessair 0:f269e3021894 95 __IO uint32_t RESERVED1[32];
elessair 0:f269e3021894 96 __IO uint32_t VectPriority[32];
elessair 0:f269e3021894 97 __IO uint32_t RESERVED2[800];
elessair 0:f269e3021894 98 __IO uint32_t Address;
elessair 0:f269e3021894 99 } LPC_VIC_TypeDef;
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 /*------------- System Control (SC) ------------------------------------------*/
elessair 0:f269e3021894 102 typedef struct
elessair 0:f269e3021894 103 {
elessair 0:f269e3021894 104 __IO uint32_t MAMCR;
elessair 0:f269e3021894 105 __IO uint32_t MAMTIM;
elessair 0:f269e3021894 106 uint32_t RESERVED0[14];
elessair 0:f269e3021894 107 __IO uint32_t MEMMAP;
elessair 0:f269e3021894 108 uint32_t RESERVED1[15];
elessair 0:f269e3021894 109 __IO uint32_t PLL0CON; /* Clocking and Power Control */
elessair 0:f269e3021894 110 __IO uint32_t PLL0CFG;
elessair 0:f269e3021894 111 __I uint32_t PLL0STAT;
elessair 0:f269e3021894 112 __O uint32_t PLL0FEED;
elessair 0:f269e3021894 113 uint32_t RESERVED2[12];
elessair 0:f269e3021894 114 __IO uint32_t PCON;
elessair 0:f269e3021894 115 __IO uint32_t PCONP;
elessair 0:f269e3021894 116 uint32_t RESERVED3[15];
elessair 0:f269e3021894 117 __IO uint32_t CCLKCFG;
elessair 0:f269e3021894 118 __IO uint32_t USBCLKCFG;
elessair 0:f269e3021894 119 __IO uint32_t CLKSRCSEL;
elessair 0:f269e3021894 120 uint32_t RESERVED4[12];
elessair 0:f269e3021894 121 __IO uint32_t EXTINT; /* External Interrupts */
elessair 0:f269e3021894 122 __IO uint32_t INTWAKE;
elessair 0:f269e3021894 123 __IO uint32_t EXTMODE;
elessair 0:f269e3021894 124 __IO uint32_t EXTPOLAR;
elessair 0:f269e3021894 125 uint32_t RESERVED6[12];
elessair 0:f269e3021894 126 __IO uint32_t RSID; /* Reset */
elessair 0:f269e3021894 127 __IO uint32_t CSPR;
elessair 0:f269e3021894 128 __IO uint32_t AHBCFG1;
elessair 0:f269e3021894 129 __IO uint32_t AHBCFG2;
elessair 0:f269e3021894 130 uint32_t RESERVED7[4];
elessair 0:f269e3021894 131 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
elessair 0:f269e3021894 132 __IO uint32_t IRCTRIM; /* Clock Dividers */
elessair 0:f269e3021894 133 __IO uint32_t PCLKSEL0;
elessair 0:f269e3021894 134 __IO uint32_t PCLKSEL1;
elessair 0:f269e3021894 135 uint32_t RESERVED8[4];
elessair 0:f269e3021894 136 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
elessair 0:f269e3021894 137 uint32_t RESERVED9;
elessair 0:f269e3021894 138 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
elessair 0:f269e3021894 139 } LPC_SC_TypeDef;
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
elessair 0:f269e3021894 142 typedef struct
elessair 0:f269e3021894 143 {
elessair 0:f269e3021894 144 __IO uint32_t PINSEL0;
elessair 0:f269e3021894 145 __IO uint32_t PINSEL1;
elessair 0:f269e3021894 146 __IO uint32_t PINSEL2;
elessair 0:f269e3021894 147 __IO uint32_t PINSEL3;
elessair 0:f269e3021894 148 __IO uint32_t PINSEL4;
elessair 0:f269e3021894 149 __IO uint32_t PINSEL5;
elessair 0:f269e3021894 150 __IO uint32_t PINSEL6;
elessair 0:f269e3021894 151 __IO uint32_t PINSEL7;
elessair 0:f269e3021894 152 __IO uint32_t PINSEL8;
elessair 0:f269e3021894 153 __IO uint32_t PINSEL9;
elessair 0:f269e3021894 154 __IO uint32_t PINSEL10;
elessair 0:f269e3021894 155 uint32_t RESERVED0[5];
elessair 0:f269e3021894 156 __IO uint32_t PINMODE0;
elessair 0:f269e3021894 157 __IO uint32_t PINMODE1;
elessair 0:f269e3021894 158 __IO uint32_t PINMODE2;
elessair 0:f269e3021894 159 __IO uint32_t PINMODE3;
elessair 0:f269e3021894 160 __IO uint32_t PINMODE4;
elessair 0:f269e3021894 161 __IO uint32_t PINMODE5;
elessair 0:f269e3021894 162 __IO uint32_t PINMODE6;
elessair 0:f269e3021894 163 __IO uint32_t PINMODE7;
elessair 0:f269e3021894 164 __IO uint32_t PINMODE8;
elessair 0:f269e3021894 165 __IO uint32_t PINMODE9;
elessair 0:f269e3021894 166 __IO uint32_t PINMODE_OD0;
elessair 0:f269e3021894 167 __IO uint32_t PINMODE_OD1;
elessair 0:f269e3021894 168 __IO uint32_t PINMODE_OD2;
elessair 0:f269e3021894 169 __IO uint32_t PINMODE_OD3;
elessair 0:f269e3021894 170 __IO uint32_t PINMODE_OD4;
elessair 0:f269e3021894 171 } LPC_PINCON_TypeDef;
elessair 0:f269e3021894 172
elessair 0:f269e3021894 173 #define PCTIM0 1
elessair 0:f269e3021894 174 #define PCTIM1 2
elessair 0:f269e3021894 175 #define PCUART0 3
elessair 0:f269e3021894 176 #define PCUART1 4
elessair 0:f269e3021894 177 #define PCPWM1 6
elessair 0:f269e3021894 178 #define PCI2C0 7
elessair 0:f269e3021894 179 #define PCSPI 8
elessair 0:f269e3021894 180 #define PCRTC 9
elessair 0:f269e3021894 181 #define PCSSP1 10
elessair 0:f269e3021894 182 #define PCEMC 11
elessair 0:f269e3021894 183 #define PCADC 12
elessair 0:f269e3021894 184 #define PCAN1 13
elessair 0:f269e3021894 185 #define PCAN2 14
elessair 0:f269e3021894 186 #define PCI2C1 19
elessair 0:f269e3021894 187 #define PCSSP0 21
elessair 0:f269e3021894 188 #define PCTIM2 22
elessair 0:f269e3021894 189 #define PCTIM3 23
elessair 0:f269e3021894 190 #define PCUART2 24
elessair 0:f269e3021894 191 #define PCUART3 25
elessair 0:f269e3021894 192 #define PCI2C2 26
elessair 0:f269e3021894 193 #define PCI2S 27
elessair 0:f269e3021894 194 #define PCSDC 28
elessair 0:f269e3021894 195 #define PCGPDMA 29
elessair 0:f269e3021894 196 #define PCENET 30
elessair 0:f269e3021894 197 #define PCUSB 31
elessair 0:f269e3021894 198
elessair 0:f269e3021894 199 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
elessair 0:f269e3021894 200 typedef struct
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 __IO uint32_t FIODIR;
elessair 0:f269e3021894 203 uint32_t RESERVED0[3];
elessair 0:f269e3021894 204 __IO uint32_t FIOMASK;
elessair 0:f269e3021894 205 __IO uint32_t FIOPIN;
elessair 0:f269e3021894 206 __IO uint32_t FIOSET;
elessair 0:f269e3021894 207 __O uint32_t FIOCLR;
elessair 0:f269e3021894 208 } LPC_GPIO_TypeDef;
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 typedef struct
elessair 0:f269e3021894 211 {
elessair 0:f269e3021894 212 __I uint32_t IntStatus;
elessair 0:f269e3021894 213 __I uint32_t IO0IntStatR;
elessair 0:f269e3021894 214 __I uint32_t IO0IntStatF;
elessair 0:f269e3021894 215 __O uint32_t IO0IntClr;
elessair 0:f269e3021894 216 __IO uint32_t IO0IntEnR;
elessair 0:f269e3021894 217 __IO uint32_t IO0IntEnF;
elessair 0:f269e3021894 218 uint32_t RESERVED0[3];
elessair 0:f269e3021894 219 __I uint32_t IO2IntStatR;
elessair 0:f269e3021894 220 __I uint32_t IO2IntStatF;
elessair 0:f269e3021894 221 __O uint32_t IO2IntClr;
elessair 0:f269e3021894 222 __IO uint32_t IO2IntEnR;
elessair 0:f269e3021894 223 __IO uint32_t IO2IntEnF;
elessair 0:f269e3021894 224 } LPC_GPIOINT_TypeDef;
elessair 0:f269e3021894 225
elessair 0:f269e3021894 226 /*------------- Timer (TIM) --------------------------------------------------*/
elessair 0:f269e3021894 227 typedef struct
elessair 0:f269e3021894 228 {
elessair 0:f269e3021894 229 __IO uint32_t IR;
elessair 0:f269e3021894 230 __IO uint32_t TCR;
elessair 0:f269e3021894 231 __IO uint32_t TC;
elessair 0:f269e3021894 232 __IO uint32_t PR;
elessair 0:f269e3021894 233 __IO uint32_t PC;
elessair 0:f269e3021894 234 __IO uint32_t MCR;
elessair 0:f269e3021894 235 __IO uint32_t MR0;
elessair 0:f269e3021894 236 __IO uint32_t MR1;
elessair 0:f269e3021894 237 __IO uint32_t MR2;
elessair 0:f269e3021894 238 __IO uint32_t MR3;
elessair 0:f269e3021894 239 __IO uint32_t CCR;
elessair 0:f269e3021894 240 __I uint32_t CR0;
elessair 0:f269e3021894 241 __I uint32_t CR1;
elessair 0:f269e3021894 242 uint32_t RESERVED0[2];
elessair 0:f269e3021894 243 __IO uint32_t EMR;
elessair 0:f269e3021894 244 uint32_t RESERVED1[12];
elessair 0:f269e3021894 245 __IO uint32_t CTCR;
elessair 0:f269e3021894 246 } LPC_TIM_TypeDef;
elessair 0:f269e3021894 247
elessair 0:f269e3021894 248 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
elessair 0:f269e3021894 249 typedef struct
elessair 0:f269e3021894 250 {
elessair 0:f269e3021894 251 __IO uint32_t IR;
elessair 0:f269e3021894 252 __IO uint32_t TCR;
elessair 0:f269e3021894 253 __IO uint32_t TC;
elessair 0:f269e3021894 254 __IO uint32_t PR;
elessair 0:f269e3021894 255 __IO uint32_t PC;
elessair 0:f269e3021894 256 __IO uint32_t MCR;
elessair 0:f269e3021894 257 __IO uint32_t MR0;
elessair 0:f269e3021894 258 __IO uint32_t MR1;
elessair 0:f269e3021894 259 __IO uint32_t MR2;
elessair 0:f269e3021894 260 __IO uint32_t MR3;
elessair 0:f269e3021894 261 __IO uint32_t CCR;
elessair 0:f269e3021894 262 __I uint32_t CR0;
elessair 0:f269e3021894 263 __I uint32_t CR1;
elessair 0:f269e3021894 264 __I uint32_t CR2;
elessair 0:f269e3021894 265 __I uint32_t CR3;
elessair 0:f269e3021894 266 uint32_t RESERVED0;
elessair 0:f269e3021894 267 __IO uint32_t MR4;
elessair 0:f269e3021894 268 __IO uint32_t MR5;
elessair 0:f269e3021894 269 __IO uint32_t MR6;
elessair 0:f269e3021894 270 __IO uint32_t PCR;
elessair 0:f269e3021894 271 __IO uint32_t LER;
elessair 0:f269e3021894 272 uint32_t RESERVED1[7];
elessair 0:f269e3021894 273 __IO uint32_t CTCR;
elessair 0:f269e3021894 274 } LPC_PWM_TypeDef;
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
elessair 0:f269e3021894 277 typedef struct
elessair 0:f269e3021894 278 {
elessair 0:f269e3021894 279 union {
elessair 0:f269e3021894 280 __I uint8_t RBR;
elessair 0:f269e3021894 281 __O uint8_t THR;
elessair 0:f269e3021894 282 __IO uint8_t DLL;
elessair 0:f269e3021894 283 uint32_t RESERVED0;
elessair 0:f269e3021894 284 };
elessair 0:f269e3021894 285 union {
elessair 0:f269e3021894 286 __IO uint8_t DLM;
elessair 0:f269e3021894 287 __IO uint32_t IER;
elessair 0:f269e3021894 288 };
elessair 0:f269e3021894 289 union {
elessair 0:f269e3021894 290 __I uint32_t IIR;
elessair 0:f269e3021894 291 __O uint8_t FCR;
elessair 0:f269e3021894 292 };
elessair 0:f269e3021894 293 __IO uint8_t LCR;
elessair 0:f269e3021894 294 uint8_t RESERVED1[7];
elessair 0:f269e3021894 295 __IO uint8_t LSR;
elessair 0:f269e3021894 296 uint8_t RESERVED2[7];
elessair 0:f269e3021894 297 __IO uint8_t SCR;
elessair 0:f269e3021894 298 uint8_t RESERVED3[3];
elessair 0:f269e3021894 299 __IO uint32_t ACR;
elessair 0:f269e3021894 300 __IO uint8_t ICR;
elessair 0:f269e3021894 301 uint8_t RESERVED4[3];
elessair 0:f269e3021894 302 __IO uint8_t FDR;
elessair 0:f269e3021894 303 uint8_t RESERVED5[7];
elessair 0:f269e3021894 304 __IO uint8_t TER;
elessair 0:f269e3021894 305 uint8_t RESERVED6[27];
elessair 0:f269e3021894 306 __IO uint8_t RS485CTRL;
elessair 0:f269e3021894 307 uint8_t RESERVED7[3];
elessair 0:f269e3021894 308 __IO uint8_t ADRMATCH;
elessair 0:f269e3021894 309 } LPC_UART_TypeDef;
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 typedef struct
elessair 0:f269e3021894 312 {
elessair 0:f269e3021894 313 union {
elessair 0:f269e3021894 314 __I uint8_t RBR;
elessair 0:f269e3021894 315 __O uint8_t THR;
elessair 0:f269e3021894 316 __IO uint8_t DLL;
elessair 0:f269e3021894 317 uint32_t RESERVED0;
elessair 0:f269e3021894 318 };
elessair 0:f269e3021894 319 union {
elessair 0:f269e3021894 320 __IO uint8_t DLM;
elessair 0:f269e3021894 321 __IO uint32_t IER;
elessair 0:f269e3021894 322 };
elessair 0:f269e3021894 323 union {
elessair 0:f269e3021894 324 __I uint32_t IIR;
elessair 0:f269e3021894 325 __O uint8_t FCR;
elessair 0:f269e3021894 326 };
elessair 0:f269e3021894 327 __IO uint8_t LCR;
elessair 0:f269e3021894 328 uint8_t RESERVED1[3];
elessair 0:f269e3021894 329 __IO uint8_t MCR;
elessair 0:f269e3021894 330 uint8_t RESERVED2[3];
elessair 0:f269e3021894 331 __IO uint8_t LSR;
elessair 0:f269e3021894 332 uint8_t RESERVED3[3];
elessair 0:f269e3021894 333 __IO uint8_t MSR;
elessair 0:f269e3021894 334 uint8_t RESERVED4[3];
elessair 0:f269e3021894 335 __IO uint8_t SCR;
elessair 0:f269e3021894 336 uint8_t RESERVED5[3];
elessair 0:f269e3021894 337 __IO uint32_t ACR;
elessair 0:f269e3021894 338 uint32_t RESERVED6;
elessair 0:f269e3021894 339 __IO uint32_t FDR;
elessair 0:f269e3021894 340 uint32_t RESERVED7;
elessair 0:f269e3021894 341 __IO uint8_t TER;
elessair 0:f269e3021894 342 uint8_t RESERVED8[27];
elessair 0:f269e3021894 343 __IO uint8_t RS485CTRL;
elessair 0:f269e3021894 344 uint8_t RESERVED9[3];
elessair 0:f269e3021894 345 __IO uint8_t ADRMATCH;
elessair 0:f269e3021894 346 uint8_t RESERVED10[3];
elessair 0:f269e3021894 347 __IO uint8_t RS485DLY;
elessair 0:f269e3021894 348 } LPC_UART1_TypeDef;
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
elessair 0:f269e3021894 351 typedef struct
elessair 0:f269e3021894 352 {
elessair 0:f269e3021894 353 __IO uint32_t SPCR;
elessair 0:f269e3021894 354 __I uint32_t SPSR;
elessair 0:f269e3021894 355 __IO uint32_t SPDR;
elessair 0:f269e3021894 356 __IO uint32_t SPCCR;
elessair 0:f269e3021894 357 uint32_t RESERVED0[3];
elessair 0:f269e3021894 358 __IO uint32_t SPINT;
elessair 0:f269e3021894 359 } LPC_SPI_TypeDef;
elessair 0:f269e3021894 360
elessair 0:f269e3021894 361 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
elessair 0:f269e3021894 362 typedef struct
elessair 0:f269e3021894 363 {
elessair 0:f269e3021894 364 __IO uint32_t CR0;
elessair 0:f269e3021894 365 __IO uint32_t CR1;
elessair 0:f269e3021894 366 __IO uint32_t DR;
elessair 0:f269e3021894 367 __I uint32_t SR;
elessair 0:f269e3021894 368 __IO uint32_t CPSR;
elessair 0:f269e3021894 369 __IO uint32_t IMSC;
elessair 0:f269e3021894 370 __IO uint32_t RIS;
elessair 0:f269e3021894 371 __IO uint32_t MIS;
elessair 0:f269e3021894 372 __IO uint32_t ICR;
elessair 0:f269e3021894 373 __IO uint32_t DMACR;
elessair 0:f269e3021894 374 } LPC_SSP_TypeDef;
elessair 0:f269e3021894 375
elessair 0:f269e3021894 376 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
elessair 0:f269e3021894 377 typedef struct
elessair 0:f269e3021894 378 {
elessair 0:f269e3021894 379 __IO uint32_t I2CONSET;
elessair 0:f269e3021894 380 __I uint32_t I2STAT;
elessair 0:f269e3021894 381 __IO uint32_t I2DAT;
elessair 0:f269e3021894 382 __IO uint32_t I2ADR0;
elessair 0:f269e3021894 383 __IO uint32_t I2SCLH;
elessair 0:f269e3021894 384 __IO uint32_t I2SCLL;
elessair 0:f269e3021894 385 __O uint32_t I2CONCLR;
elessair 0:f269e3021894 386 __IO uint32_t MMCTRL;
elessair 0:f269e3021894 387 __IO uint32_t I2ADR1;
elessair 0:f269e3021894 388 __IO uint32_t I2ADR2;
elessair 0:f269e3021894 389 __IO uint32_t I2ADR3;
elessair 0:f269e3021894 390 __I uint32_t I2DATA_BUFFER;
elessair 0:f269e3021894 391 __IO uint32_t I2MASK0;
elessair 0:f269e3021894 392 __IO uint32_t I2MASK1;
elessair 0:f269e3021894 393 __IO uint32_t I2MASK2;
elessair 0:f269e3021894 394 __IO uint32_t I2MASK3;
elessair 0:f269e3021894 395 } LPC_I2C_TypeDef;
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
elessair 0:f269e3021894 398 typedef struct
elessair 0:f269e3021894 399 {
elessair 0:f269e3021894 400 __IO uint32_t I2SDAO;
elessair 0:f269e3021894 401 __I uint32_t I2SDAI;
elessair 0:f269e3021894 402 __O uint32_t I2STXFIFO;
elessair 0:f269e3021894 403 __I uint32_t I2SRXFIFO;
elessair 0:f269e3021894 404 __I uint32_t I2SSTATE;
elessair 0:f269e3021894 405 __IO uint32_t I2SDMA1;
elessair 0:f269e3021894 406 __IO uint32_t I2SDMA2;
elessair 0:f269e3021894 407 __IO uint32_t I2SIRQ;
elessair 0:f269e3021894 408 __IO uint32_t I2STXRATE;
elessair 0:f269e3021894 409 __IO uint32_t I2SRXRATE;
elessair 0:f269e3021894 410 __IO uint32_t I2STXBITRATE;
elessair 0:f269e3021894 411 __IO uint32_t I2SRXBITRATE;
elessair 0:f269e3021894 412 __IO uint32_t I2STXMODE;
elessair 0:f269e3021894 413 __IO uint32_t I2SRXMODE;
elessair 0:f269e3021894 414 } LPC_I2S_TypeDef;
elessair 0:f269e3021894 415
elessair 0:f269e3021894 416 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
elessair 0:f269e3021894 417 typedef struct
elessair 0:f269e3021894 418 {
elessair 0:f269e3021894 419 __IO uint8_t ILR;
elessair 0:f269e3021894 420 uint8_t RESERVED0[3];
elessair 0:f269e3021894 421 __IO uint8_t CTC;
elessair 0:f269e3021894 422 uint8_t RESERVED1[3];
elessair 0:f269e3021894 423 __IO uint8_t CCR;
elessair 0:f269e3021894 424 uint8_t RESERVED2[3];
elessair 0:f269e3021894 425 __IO uint8_t CIIR;
elessair 0:f269e3021894 426 uint8_t RESERVED3[3];
elessair 0:f269e3021894 427 __IO uint8_t AMR;
elessair 0:f269e3021894 428 uint8_t RESERVED4[3];
elessair 0:f269e3021894 429 __I uint32_t CTIME0;
elessair 0:f269e3021894 430 __I uint32_t CTIME1;
elessair 0:f269e3021894 431 __I uint32_t CTIME2;
elessair 0:f269e3021894 432 __IO uint8_t SEC;
elessair 0:f269e3021894 433 uint8_t RESERVED5[3];
elessair 0:f269e3021894 434 __IO uint8_t MIN;
elessair 0:f269e3021894 435 uint8_t RESERVED6[3];
elessair 0:f269e3021894 436 __IO uint8_t HOUR;
elessair 0:f269e3021894 437 uint8_t RESERVED7[3];
elessair 0:f269e3021894 438 __IO uint8_t DOM;
elessair 0:f269e3021894 439 uint8_t RESERVED8[3];
elessair 0:f269e3021894 440 __IO uint8_t DOW;
elessair 0:f269e3021894 441 uint8_t RESERVED9[3];
elessair 0:f269e3021894 442 __IO uint16_t DOY;
elessair 0:f269e3021894 443 uint16_t RESERVED10;
elessair 0:f269e3021894 444 __IO uint8_t MONTH;
elessair 0:f269e3021894 445 uint8_t RESERVED11[3];
elessair 0:f269e3021894 446 __IO uint16_t YEAR;
elessair 0:f269e3021894 447 uint16_t RESERVED12;
elessair 0:f269e3021894 448 __IO uint32_t CALIBRATION;
elessair 0:f269e3021894 449 __IO uint32_t GPREG0;
elessair 0:f269e3021894 450 __IO uint32_t GPREG1;
elessair 0:f269e3021894 451 __IO uint32_t GPREG2;
elessair 0:f269e3021894 452 __IO uint32_t GPREG3;
elessair 0:f269e3021894 453 __IO uint32_t GPREG4;
elessair 0:f269e3021894 454 __IO uint8_t WAKEUPDIS;
elessair 0:f269e3021894 455 uint8_t RESERVED13[3];
elessair 0:f269e3021894 456 __IO uint8_t PWRCTRL;
elessair 0:f269e3021894 457 uint8_t RESERVED14[3];
elessair 0:f269e3021894 458 __IO uint8_t ALSEC;
elessair 0:f269e3021894 459 uint8_t RESERVED15[3];
elessair 0:f269e3021894 460 __IO uint8_t ALMIN;
elessair 0:f269e3021894 461 uint8_t RESERVED16[3];
elessair 0:f269e3021894 462 __IO uint8_t ALHOUR;
elessair 0:f269e3021894 463 uint8_t RESERVED17[3];
elessair 0:f269e3021894 464 __IO uint8_t ALDOM;
elessair 0:f269e3021894 465 uint8_t RESERVED18[3];
elessair 0:f269e3021894 466 __IO uint8_t ALDOW;
elessair 0:f269e3021894 467 uint8_t RESERVED19[3];
elessair 0:f269e3021894 468 __IO uint16_t ALDOY;
elessair 0:f269e3021894 469 uint16_t RESERVED20;
elessair 0:f269e3021894 470 __IO uint8_t ALMON;
elessair 0:f269e3021894 471 uint8_t RESERVED21[3];
elessair 0:f269e3021894 472 __IO uint16_t ALYEAR;
elessair 0:f269e3021894 473 uint16_t RESERVED22;
elessair 0:f269e3021894 474 } LPC_RTC_TypeDef;
elessair 0:f269e3021894 475
elessair 0:f269e3021894 476 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
elessair 0:f269e3021894 477 typedef struct
elessair 0:f269e3021894 478 {
elessair 0:f269e3021894 479 __IO uint8_t WDMOD;
elessair 0:f269e3021894 480 uint8_t RESERVED0[3];
elessair 0:f269e3021894 481 __IO uint32_t WDTC;
elessair 0:f269e3021894 482 __O uint8_t WDFEED;
elessair 0:f269e3021894 483 uint8_t RESERVED1[3];
elessair 0:f269e3021894 484 __I uint32_t WDTV;
elessair 0:f269e3021894 485 __IO uint32_t WDCLKSEL;
elessair 0:f269e3021894 486 } LPC_WDT_TypeDef;
elessair 0:f269e3021894 487
elessair 0:f269e3021894 488 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
elessair 0:f269e3021894 489 typedef struct
elessair 0:f269e3021894 490 {
elessair 0:f269e3021894 491 __IO uint32_t ADCR;
elessair 0:f269e3021894 492 __IO uint32_t ADGDR;
elessair 0:f269e3021894 493 uint32_t RESERVED0;
elessair 0:f269e3021894 494 __IO uint32_t ADINTEN;
elessair 0:f269e3021894 495 __I uint32_t ADDR0;
elessair 0:f269e3021894 496 __I uint32_t ADDR1;
elessair 0:f269e3021894 497 __I uint32_t ADDR2;
elessair 0:f269e3021894 498 __I uint32_t ADDR3;
elessair 0:f269e3021894 499 __I uint32_t ADDR4;
elessair 0:f269e3021894 500 __I uint32_t ADDR5;
elessair 0:f269e3021894 501 __I uint32_t ADDR6;
elessair 0:f269e3021894 502 __I uint32_t ADDR7;
elessair 0:f269e3021894 503 __I uint32_t ADSTAT;
elessair 0:f269e3021894 504 __IO uint32_t ADTRM;
elessair 0:f269e3021894 505 } LPC_ADC_TypeDef;
elessair 0:f269e3021894 506
elessair 0:f269e3021894 507 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
elessair 0:f269e3021894 508 typedef struct
elessair 0:f269e3021894 509 {
elessair 0:f269e3021894 510 __IO uint32_t DACR;
elessair 0:f269e3021894 511 __IO uint32_t DACCTRL;
elessair 0:f269e3021894 512 __IO uint16_t DACCNTVAL;
elessair 0:f269e3021894 513 } LPC_DAC_TypeDef;
elessair 0:f269e3021894 514
elessair 0:f269e3021894 515 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
elessair 0:f269e3021894 516 typedef struct
elessair 0:f269e3021894 517 {
elessair 0:f269e3021894 518 __IO uint32_t MCIPower; /* Power control */
elessair 0:f269e3021894 519 __IO uint32_t MCIClock; /* Clock control */
elessair 0:f269e3021894 520 __IO uint32_t MCIArgument;
elessair 0:f269e3021894 521 __IO uint32_t MMCCommand;
elessair 0:f269e3021894 522 __I uint32_t MCIRespCmd;
elessair 0:f269e3021894 523 __I uint32_t MCIResponse0;
elessair 0:f269e3021894 524 __I uint32_t MCIResponse1;
elessair 0:f269e3021894 525 __I uint32_t MCIResponse2;
elessair 0:f269e3021894 526 __I uint32_t MCIResponse3;
elessair 0:f269e3021894 527 __IO uint32_t MCIDataTimer;
elessair 0:f269e3021894 528 __IO uint32_t MCIDataLength;
elessair 0:f269e3021894 529 __IO uint32_t MCIDataCtrl;
elessair 0:f269e3021894 530 __I uint32_t MCIDataCnt;
elessair 0:f269e3021894 531 __I uint32_t MCIStatus;
elessair 0:f269e3021894 532 __O uint32_t MCIClear;
elessair 0:f269e3021894 533 __IO uint32_t MCIMask0;
elessair 0:f269e3021894 534 uint32_t RESERVED1[2];
elessair 0:f269e3021894 535 __I uint32_t MCIFifoCnt;
elessair 0:f269e3021894 536 uint32_t RESERVED2[13];
elessair 0:f269e3021894 537 __IO uint32_t MCIFIFO[16];
elessair 0:f269e3021894 538 } LPC_MCI_TypeDef;
elessair 0:f269e3021894 539
elessair 0:f269e3021894 540 /*------------- Controller Area Network (CAN) --------------------------------*/
elessair 0:f269e3021894 541 typedef struct
elessair 0:f269e3021894 542 {
elessair 0:f269e3021894 543 __IO uint32_t mask[512]; /* ID Masks */
elessair 0:f269e3021894 544 } LPC_CANAF_RAM_TypeDef;
elessair 0:f269e3021894 545
elessair 0:f269e3021894 546 typedef struct /* Acceptance Filter Registers */
elessair 0:f269e3021894 547 {
elessair 0:f269e3021894 548 __IO uint32_t AFMR;
elessair 0:f269e3021894 549 __IO uint32_t SFF_sa;
elessair 0:f269e3021894 550 __IO uint32_t SFF_GRP_sa;
elessair 0:f269e3021894 551 __IO uint32_t EFF_sa;
elessair 0:f269e3021894 552 __IO uint32_t EFF_GRP_sa;
elessair 0:f269e3021894 553 __IO uint32_t ENDofTable;
elessair 0:f269e3021894 554 __I uint32_t LUTerrAd;
elessair 0:f269e3021894 555 __I uint32_t LUTerr;
elessair 0:f269e3021894 556 __IO uint32_t FCANIE;
elessair 0:f269e3021894 557 __IO uint32_t FCANIC0;
elessair 0:f269e3021894 558 __IO uint32_t FCANIC1;
elessair 0:f269e3021894 559 } LPC_CANAF_TypeDef;
elessair 0:f269e3021894 560
elessair 0:f269e3021894 561 typedef struct /* Central Registers */
elessair 0:f269e3021894 562 {
elessair 0:f269e3021894 563 __I uint32_t CANTxSR;
elessair 0:f269e3021894 564 __I uint32_t CANRxSR;
elessair 0:f269e3021894 565 __I uint32_t CANMSR;
elessair 0:f269e3021894 566 } LPC_CANCR_TypeDef;
elessair 0:f269e3021894 567
elessair 0:f269e3021894 568 typedef struct /* Controller Registers */
elessair 0:f269e3021894 569 {
elessair 0:f269e3021894 570 __IO uint32_t MOD;
elessair 0:f269e3021894 571 __O uint32_t CMR;
elessair 0:f269e3021894 572 __IO uint32_t GSR;
elessair 0:f269e3021894 573 __I uint32_t ICR;
elessair 0:f269e3021894 574 __IO uint32_t IER;
elessair 0:f269e3021894 575 __IO uint32_t BTR;
elessair 0:f269e3021894 576 __IO uint32_t EWL;
elessair 0:f269e3021894 577 __I uint32_t SR;
elessair 0:f269e3021894 578 __IO uint32_t RFS;
elessair 0:f269e3021894 579 __IO uint32_t RID;
elessair 0:f269e3021894 580 __IO uint32_t RDA;
elessair 0:f269e3021894 581 __IO uint32_t RDB;
elessair 0:f269e3021894 582 __IO uint32_t TFI1;
elessair 0:f269e3021894 583 __IO uint32_t TID1;
elessair 0:f269e3021894 584 __IO uint32_t TDA1;
elessair 0:f269e3021894 585 __IO uint32_t TDB1;
elessair 0:f269e3021894 586 __IO uint32_t TFI2;
elessair 0:f269e3021894 587 __IO uint32_t TID2;
elessair 0:f269e3021894 588 __IO uint32_t TDA2;
elessair 0:f269e3021894 589 __IO uint32_t TDB2;
elessair 0:f269e3021894 590 __IO uint32_t TFI3;
elessair 0:f269e3021894 591 __IO uint32_t TID3;
elessair 0:f269e3021894 592 __IO uint32_t TDA3;
elessair 0:f269e3021894 593 __IO uint32_t TDB3;
elessair 0:f269e3021894 594 } LPC_CAN_TypeDef;
elessair 0:f269e3021894 595
elessair 0:f269e3021894 596 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
elessair 0:f269e3021894 597 typedef struct /* Common Registers */
elessair 0:f269e3021894 598 {
elessair 0:f269e3021894 599 __I uint32_t DMACIntStat;
elessair 0:f269e3021894 600 __I uint32_t DMACIntTCStat;
elessair 0:f269e3021894 601 __O uint32_t DMACIntTCClear;
elessair 0:f269e3021894 602 __I uint32_t DMACIntErrStat;
elessair 0:f269e3021894 603 __O uint32_t DMACIntErrClr;
elessair 0:f269e3021894 604 __I uint32_t DMACRawIntTCStat;
elessair 0:f269e3021894 605 __I uint32_t DMACRawIntErrStat;
elessair 0:f269e3021894 606 __I uint32_t DMACEnbldChns;
elessair 0:f269e3021894 607 __IO uint32_t DMACSoftBReq;
elessair 0:f269e3021894 608 __IO uint32_t DMACSoftSReq;
elessair 0:f269e3021894 609 __IO uint32_t DMACSoftLBReq;
elessair 0:f269e3021894 610 __IO uint32_t DMACSoftLSReq;
elessair 0:f269e3021894 611 __IO uint32_t DMACConfig;
elessair 0:f269e3021894 612 __IO uint32_t DMACSync;
elessair 0:f269e3021894 613 } LPC_GPDMA_TypeDef;
elessair 0:f269e3021894 614
elessair 0:f269e3021894 615 typedef struct /* Channel Registers */
elessair 0:f269e3021894 616 {
elessair 0:f269e3021894 617 __IO uint32_t DMACCSrcAddr;
elessair 0:f269e3021894 618 __IO uint32_t DMACCDestAddr;
elessair 0:f269e3021894 619 __IO uint32_t DMACCLLI;
elessair 0:f269e3021894 620 __IO uint32_t DMACCControl;
elessair 0:f269e3021894 621 __IO uint32_t DMACCConfig;
elessair 0:f269e3021894 622 } LPC_GPDMACH_TypeDef;
elessair 0:f269e3021894 623
elessair 0:f269e3021894 624 /*------------- Universal Serial Bus (USB) -----------------------------------*/
elessair 0:f269e3021894 625 typedef struct
elessair 0:f269e3021894 626 {
elessair 0:f269e3021894 627 __I uint32_t HcRevision; /* USB Host Registers */
elessair 0:f269e3021894 628 __IO uint32_t HcControl;
elessair 0:f269e3021894 629 __IO uint32_t HcCommandStatus;
elessair 0:f269e3021894 630 __IO uint32_t HcInterruptStatus;
elessair 0:f269e3021894 631 __IO uint32_t HcInterruptEnable;
elessair 0:f269e3021894 632 __IO uint32_t HcInterruptDisable;
elessair 0:f269e3021894 633 __IO uint32_t HcHCCA;
elessair 0:f269e3021894 634 __I uint32_t HcPeriodCurrentED;
elessair 0:f269e3021894 635 __IO uint32_t HcControlHeadED;
elessair 0:f269e3021894 636 __IO uint32_t HcControlCurrentED;
elessair 0:f269e3021894 637 __IO uint32_t HcBulkHeadED;
elessair 0:f269e3021894 638 __IO uint32_t HcBulkCurrentED;
elessair 0:f269e3021894 639 __I uint32_t HcDoneHead;
elessair 0:f269e3021894 640 __IO uint32_t HcFmInterval;
elessair 0:f269e3021894 641 __I uint32_t HcFmRemaining;
elessair 0:f269e3021894 642 __I uint32_t HcFmNumber;
elessair 0:f269e3021894 643 __IO uint32_t HcPeriodicStart;
elessair 0:f269e3021894 644 __IO uint32_t HcLSTreshold;
elessair 0:f269e3021894 645 __IO uint32_t HcRhDescriptorA;
elessair 0:f269e3021894 646 __IO uint32_t HcRhDescriptorB;
elessair 0:f269e3021894 647 __IO uint32_t HcRhStatus;
elessair 0:f269e3021894 648 __IO uint32_t HcRhPortStatus1;
elessair 0:f269e3021894 649 __IO uint32_t HcRhPortStatus2;
elessair 0:f269e3021894 650 uint32_t RESERVED0[40];
elessair 0:f269e3021894 651 __I uint32_t Module_ID;
elessair 0:f269e3021894 652
elessair 0:f269e3021894 653 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
elessair 0:f269e3021894 654 __IO uint32_t OTGIntEn;
elessair 0:f269e3021894 655 __O uint32_t OTGIntSet;
elessair 0:f269e3021894 656 __O uint32_t OTGIntClr;
elessair 0:f269e3021894 657 __IO uint32_t OTGStCtrl;
elessair 0:f269e3021894 658 __IO uint32_t OTGTmr;
elessair 0:f269e3021894 659 uint32_t RESERVED1[58];
elessair 0:f269e3021894 660
elessair 0:f269e3021894 661 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
elessair 0:f269e3021894 662 __IO uint32_t USBDevIntEn;
elessair 0:f269e3021894 663 __O uint32_t USBDevIntClr;
elessair 0:f269e3021894 664 __O uint32_t USBDevIntSet;
elessair 0:f269e3021894 665
elessair 0:f269e3021894 666 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
elessair 0:f269e3021894 667 __I uint32_t USBCmdData;
elessair 0:f269e3021894 668
elessair 0:f269e3021894 669 __I uint32_t USBRxData; /* USB Device Transfer Registers */
elessair 0:f269e3021894 670 __O uint32_t USBTxData;
elessair 0:f269e3021894 671 __I uint32_t USBRxPLen;
elessair 0:f269e3021894 672 __O uint32_t USBTxPLen;
elessair 0:f269e3021894 673 __IO uint32_t USBCtrl;
elessair 0:f269e3021894 674 __O uint32_t USBDevIntPri;
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
elessair 0:f269e3021894 677 __IO uint32_t USBEpIntEn;
elessair 0:f269e3021894 678 __O uint32_t USBEpIntClr;
elessair 0:f269e3021894 679 __O uint32_t USBEpIntSet;
elessair 0:f269e3021894 680 __O uint32_t USBEpIntPri;
elessair 0:f269e3021894 681
elessair 0:f269e3021894 682 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
elessair 0:f269e3021894 683 __O uint32_t USBEpInd;
elessair 0:f269e3021894 684 __IO uint32_t USBMaxPSize;
elessair 0:f269e3021894 685
elessair 0:f269e3021894 686 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
elessair 0:f269e3021894 687 __O uint32_t USBDMARClr;
elessair 0:f269e3021894 688 __O uint32_t USBDMARSet;
elessair 0:f269e3021894 689 uint32_t RESERVED2[9];
elessair 0:f269e3021894 690 __IO uint32_t USBUDCAH;
elessair 0:f269e3021894 691 __I uint32_t USBEpDMASt;
elessair 0:f269e3021894 692 __O uint32_t USBEpDMAEn;
elessair 0:f269e3021894 693 __O uint32_t USBEpDMADis;
elessair 0:f269e3021894 694 __I uint32_t USBDMAIntSt;
elessair 0:f269e3021894 695 __IO uint32_t USBDMAIntEn;
elessair 0:f269e3021894 696 uint32_t RESERVED3[2];
elessair 0:f269e3021894 697 __I uint32_t USBEoTIntSt;
elessair 0:f269e3021894 698 __O uint32_t USBEoTIntClr;
elessair 0:f269e3021894 699 __O uint32_t USBEoTIntSet;
elessair 0:f269e3021894 700 __I uint32_t USBNDDRIntSt;
elessair 0:f269e3021894 701 __O uint32_t USBNDDRIntClr;
elessair 0:f269e3021894 702 __O uint32_t USBNDDRIntSet;
elessair 0:f269e3021894 703 __I uint32_t USBSysErrIntSt;
elessair 0:f269e3021894 704 __O uint32_t USBSysErrIntClr;
elessair 0:f269e3021894 705 __O uint32_t USBSysErrIntSet;
elessair 0:f269e3021894 706 uint32_t RESERVED4[15];
elessair 0:f269e3021894 707
elessair 0:f269e3021894 708 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
elessair 0:f269e3021894 709 __O uint32_t I2C_WO;
elessair 0:f269e3021894 710 __I uint32_t I2C_STS;
elessair 0:f269e3021894 711 __IO uint32_t I2C_CTL;
elessair 0:f269e3021894 712 __IO uint32_t I2C_CLKHI;
elessair 0:f269e3021894 713 __O uint32_t I2C_CLKLO;
elessair 0:f269e3021894 714 uint32_t RESERVED5[823];
elessair 0:f269e3021894 715
elessair 0:f269e3021894 716 union {
elessair 0:f269e3021894 717 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
elessair 0:f269e3021894 718 __IO uint32_t OTGClkCtrl;
elessair 0:f269e3021894 719 };
elessair 0:f269e3021894 720 union {
elessair 0:f269e3021894 721 __I uint32_t USBClkSt;
elessair 0:f269e3021894 722 __I uint32_t OTGClkSt;
elessair 0:f269e3021894 723 };
elessair 0:f269e3021894 724 } LPC_USB_TypeDef;
elessair 0:f269e3021894 725
elessair 0:f269e3021894 726 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
elessair 0:f269e3021894 727 typedef struct
elessair 0:f269e3021894 728 {
elessair 0:f269e3021894 729 __IO uint32_t MAC1; /* MAC Registers */
elessair 0:f269e3021894 730 __IO uint32_t MAC2;
elessair 0:f269e3021894 731 __IO uint32_t IPGT;
elessair 0:f269e3021894 732 __IO uint32_t IPGR;
elessair 0:f269e3021894 733 __IO uint32_t CLRT;
elessair 0:f269e3021894 734 __IO uint32_t MAXF;
elessair 0:f269e3021894 735 __IO uint32_t SUPP;
elessair 0:f269e3021894 736 __IO uint32_t TEST;
elessair 0:f269e3021894 737 __IO uint32_t MCFG;
elessair 0:f269e3021894 738 __IO uint32_t MCMD;
elessair 0:f269e3021894 739 __IO uint32_t MADR;
elessair 0:f269e3021894 740 __O uint32_t MWTD;
elessair 0:f269e3021894 741 __I uint32_t MRDD;
elessair 0:f269e3021894 742 __I uint32_t MIND;
elessair 0:f269e3021894 743 uint32_t RESERVED0[2];
elessair 0:f269e3021894 744 __IO uint32_t SA0;
elessair 0:f269e3021894 745 __IO uint32_t SA1;
elessair 0:f269e3021894 746 __IO uint32_t SA2;
elessair 0:f269e3021894 747 uint32_t RESERVED1[45];
elessair 0:f269e3021894 748 __IO uint32_t Command; /* Control Registers */
elessair 0:f269e3021894 749 __I uint32_t Status;
elessair 0:f269e3021894 750 __IO uint32_t RxDescriptor;
elessair 0:f269e3021894 751 __IO uint32_t RxStatus;
elessair 0:f269e3021894 752 __IO uint32_t RxDescriptorNumber;
elessair 0:f269e3021894 753 __I uint32_t RxProduceIndex;
elessair 0:f269e3021894 754 __IO uint32_t RxConsumeIndex;
elessair 0:f269e3021894 755 __IO uint32_t TxDescriptor;
elessair 0:f269e3021894 756 __IO uint32_t TxStatus;
elessair 0:f269e3021894 757 __IO uint32_t TxDescriptorNumber;
elessair 0:f269e3021894 758 __IO uint32_t TxProduceIndex;
elessair 0:f269e3021894 759 __I uint32_t TxConsumeIndex;
elessair 0:f269e3021894 760 uint32_t RESERVED2[10];
elessair 0:f269e3021894 761 __I uint32_t TSV0;
elessair 0:f269e3021894 762 __I uint32_t TSV1;
elessair 0:f269e3021894 763 __I uint32_t RSV;
elessair 0:f269e3021894 764 uint32_t RESERVED3[3];
elessair 0:f269e3021894 765 __IO uint32_t FlowControlCounter;
elessair 0:f269e3021894 766 __I uint32_t FlowControlStatus;
elessair 0:f269e3021894 767 uint32_t RESERVED4[34];
elessair 0:f269e3021894 768 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
elessair 0:f269e3021894 769 __IO uint32_t RxFilterWoLStatus;
elessair 0:f269e3021894 770 __IO uint32_t RxFilterWoLClear;
elessair 0:f269e3021894 771 uint32_t RESERVED5;
elessair 0:f269e3021894 772 __IO uint32_t HashFilterL;
elessair 0:f269e3021894 773 __IO uint32_t HashFilterH;
elessair 0:f269e3021894 774 uint32_t RESERVED6[882];
elessair 0:f269e3021894 775 __I uint32_t IntStatus; /* Module Control Registers */
elessair 0:f269e3021894 776 __IO uint32_t IntEnable;
elessair 0:f269e3021894 777 __O uint32_t IntClear;
elessair 0:f269e3021894 778 __O uint32_t IntSet;
elessair 0:f269e3021894 779 uint32_t RESERVED7;
elessair 0:f269e3021894 780 __IO uint32_t PowerDown;
elessair 0:f269e3021894 781 uint32_t RESERVED8;
elessair 0:f269e3021894 782 __IO uint32_t Module_ID;
elessair 0:f269e3021894 783 } LPC_EMAC_TypeDef;
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785 /*-------------------- External Memory Controller (EMC) ----------------------*/
elessair 0:f269e3021894 786 typedef struct
elessair 0:f269e3021894 787 {
elessair 0:f269e3021894 788 __IO uint32_t EMCControl;
elessair 0:f269e3021894 789 __I uint32_t EMCStatus;
elessair 0:f269e3021894 790 __IO uint32_t EMCConfig;
elessair 0:f269e3021894 791 uint32_t RESERVED1[5];
elessair 0:f269e3021894 792 __IO uint32_t EMCDynamicControl;
elessair 0:f269e3021894 793 __IO uint32_t EMCDynamicRefresh;
elessair 0:f269e3021894 794 __IO uint32_t EMCDynamicReadConfig;
elessair 0:f269e3021894 795 uint32_t RESERVED2;
elessair 0:f269e3021894 796 __IO uint32_t EMCDynamicRP;
elessair 0:f269e3021894 797 __IO uint32_t EMCDynamicRAS;
elessair 0:f269e3021894 798 __IO uint32_t EMCDynamicSREX;
elessair 0:f269e3021894 799 __IO uint32_t EMCDynamicAPR;
elessair 0:f269e3021894 800 __IO uint32_t EMCDynamicDAL;
elessair 0:f269e3021894 801 __IO uint32_t EMCDynamicWR;
elessair 0:f269e3021894 802 __IO uint32_t EMCDynamicRC;
elessair 0:f269e3021894 803 __IO uint32_t EMCDynamicRFC;
elessair 0:f269e3021894 804 __IO uint32_t EMCDynamicXSR;
elessair 0:f269e3021894 805 __IO uint32_t EMCDynamicRRD;
elessair 0:f269e3021894 806 __IO uint32_t EMCDynamicMRD;
elessair 0:f269e3021894 807 uint32_t RESERVED3[9];
elessair 0:f269e3021894 808 __IO uint32_t EMCStaticExtendedWait;
elessair 0:f269e3021894 809 uint32_t RESERVED4[31];
elessair 0:f269e3021894 810 __IO uint32_t EMCDynamicConfig0;
elessair 0:f269e3021894 811 __IO uint32_t EMCDynamicRasCas0;
elessair 0:f269e3021894 812 uint32_t RESERVED5[6];
elessair 0:f269e3021894 813 __IO uint32_t EMCDynamicConfig1;
elessair 0:f269e3021894 814 __IO uint32_t EMCDynamicRasCas1;
elessair 0:f269e3021894 815 uint32_t RESERVED6[6];
elessair 0:f269e3021894 816 __IO uint32_t EMCDynamicConfic2;
elessair 0:f269e3021894 817 __IO uint32_t EMCDynamicRasCas2;
elessair 0:f269e3021894 818 uint32_t RESERVED7[6];
elessair 0:f269e3021894 819 __IO uint32_t EMCDynamicConfig3;
elessair 0:f269e3021894 820 __IO uint32_t EMCDynamicRasCas3;
elessair 0:f269e3021894 821 uint32_t RESERVED8[38];
elessair 0:f269e3021894 822 __IO uint32_t EMCStaticConfig0;
elessair 0:f269e3021894 823 __IO uint32_t EMCStaticWaitWen0;
elessair 0:f269e3021894 824 __IO uint32_t EMCStaticWaitOen0;
elessair 0:f269e3021894 825 __IO uint32_t EMCStaticWaitRd0;
elessair 0:f269e3021894 826 __IO uint32_t EMCStaticWaitPage0;
elessair 0:f269e3021894 827 __IO uint32_t EMCStaticWaitWr0;
elessair 0:f269e3021894 828 __IO uint32_t EMCStaticWaitTurn0;
elessair 0:f269e3021894 829 uint32_t RESERVED9;
elessair 0:f269e3021894 830 __IO uint32_t EMCStaticConfig1;
elessair 0:f269e3021894 831 __IO uint32_t EMCStaticWaitWen1;
elessair 0:f269e3021894 832 __IO uint32_t EMCStaticWaitOen1;
elessair 0:f269e3021894 833 __IO uint32_t EMCStaticWaitRd1;
elessair 0:f269e3021894 834 __IO uint32_t EMCStaticWaitPage1;
elessair 0:f269e3021894 835 __IO uint32_t EMCStaticWaitWr1;
elessair 0:f269e3021894 836 __IO uint32_t EMCStaticWaitTurn1;
elessair 0:f269e3021894 837 uint32_t RESERVED10;
elessair 0:f269e3021894 838 __IO uint32_t EMCStaticConfig2;
elessair 0:f269e3021894 839 __IO uint32_t EMCStaticWaitWen2;
elessair 0:f269e3021894 840 __IO uint32_t EMCStaticWaitOen2;
elessair 0:f269e3021894 841 __IO uint32_t EMCStaticWaitRd2;
elessair 0:f269e3021894 842 __IO uint32_t EMCStaticWaitPage2;
elessair 0:f269e3021894 843 __IO uint32_t EMCStaticWaitWr2;
elessair 0:f269e3021894 844 __IO uint32_t EMCStaticWaitTurn2;
elessair 0:f269e3021894 845 uint32_t RESERVED11;
elessair 0:f269e3021894 846 __IO uint32_t EMCStaticConfig3;
elessair 0:f269e3021894 847 __IO uint32_t EMCStaticWaitWen3;
elessair 0:f269e3021894 848 __IO uint32_t EMCStaticWaitOen3;
elessair 0:f269e3021894 849 __IO uint32_t EMCStaticWaitRd3;
elessair 0:f269e3021894 850 __IO uint32_t EMCStaticWaitPage3;
elessair 0:f269e3021894 851 __IO uint32_t EMCStaticWaitWr3;
elessair 0:f269e3021894 852 __IO uint32_t EMCStaticWaitTurn3;
elessair 0:f269e3021894 853 } LPC_EMC_TypeDef;
elessair 0:f269e3021894 854 #if defined ( __CC_ARM )
elessair 0:f269e3021894 855 #pragma no_anon_unions
elessair 0:f269e3021894 856 #endif
elessair 0:f269e3021894 857
elessair 0:f269e3021894 858 /******************************************************************************/
elessair 0:f269e3021894 859 /* Peripheral memory map */
elessair 0:f269e3021894 860 /******************************************************************************/
elessair 0:f269e3021894 861 /* Base addresses */
elessair 0:f269e3021894 862
elessair 0:f269e3021894 863 /* AHB Peripheral # 0 */
elessair 0:f269e3021894 864
elessair 0:f269e3021894 865 /*
elessair 0:f269e3021894 866 #define FLASH_BASE (0x00000000UL)
elessair 0:f269e3021894 867 #define RAM_BASE (0x10000000UL)
elessair 0:f269e3021894 868 #define GPIO_BASE (0x2009C000UL)
elessair 0:f269e3021894 869 #define APB0_BASE (0x40000000UL)
elessair 0:f269e3021894 870 #define APB1_BASE (0x40080000UL)
elessair 0:f269e3021894 871 #define AHB_BASE (0x50000000UL)
elessair 0:f269e3021894 872 #define CM3_BASE (0xE0000000UL)
elessair 0:f269e3021894 873 */
elessair 0:f269e3021894 874
elessair 0:f269e3021894 875 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
elessair 0:f269e3021894 876
elessair 0:f269e3021894 877 #define LPC_WDT_BASE (0xE0000000)
elessair 0:f269e3021894 878 #define LPC_TIM0_BASE (0xE0004000)
elessair 0:f269e3021894 879 #define LPC_TIM1_BASE (0xE0008000)
elessair 0:f269e3021894 880 #define LPC_UART0_BASE (0xE000C000)
elessair 0:f269e3021894 881 #define LPC_UART1_BASE (0xE0010000)
elessair 0:f269e3021894 882 #define LPC_PWM1_BASE (0xE0018000)
elessair 0:f269e3021894 883 #define LPC_I2C0_BASE (0xE001C000)
elessair 0:f269e3021894 884 #define LPC_SPI_BASE (0xE0020000)
elessair 0:f269e3021894 885 #define LPC_RTC_BASE (0xE0024000)
elessair 0:f269e3021894 886 #define LPC_GPIOINT_BASE (0xE0028080)
elessair 0:f269e3021894 887 #define LPC_PINCON_BASE (0xE002C000)
elessair 0:f269e3021894 888 #define LPC_SSP1_BASE (0xE0030000)
elessair 0:f269e3021894 889 #define LPC_ADC_BASE (0xE0034000)
elessair 0:f269e3021894 890 #define LPC_CANAF_RAM_BASE (0xE0038000)
elessair 0:f269e3021894 891 #define LPC_CANAF_BASE (0xE003C000)
elessair 0:f269e3021894 892 #define LPC_CANCR_BASE (0xE0040000)
elessair 0:f269e3021894 893 #define LPC_CAN1_BASE (0xE0044000)
elessair 0:f269e3021894 894 #define LPC_CAN2_BASE (0xE0048000)
elessair 0:f269e3021894 895 #define LPC_I2C1_BASE (0xE005C000)
elessair 0:f269e3021894 896 #define LPC_SSP0_BASE (0xE0068000)
elessair 0:f269e3021894 897 #define LPC_DAC_BASE (0xE006C000)
elessair 0:f269e3021894 898 #define LPC_TIM2_BASE (0xE0070000)
elessair 0:f269e3021894 899 #define LPC_TIM3_BASE (0xE0074000)
elessair 0:f269e3021894 900 #define LPC_UART2_BASE (0xE0078000)
elessair 0:f269e3021894 901 #define LPC_UART3_BASE (0xE007C000)
elessair 0:f269e3021894 902 #define LPC_I2C2_BASE (0xE0080000)
elessair 0:f269e3021894 903 #define LPC_I2S_BASE (0xE0088000)
elessair 0:f269e3021894 904 #define LPC_MCI_BASE (0xE008C000)
elessair 0:f269e3021894 905 #define LPC_SC_BASE (0xE01FC000)
elessair 0:f269e3021894 906 #define LPC_EMAC_BASE (0xFFE00000)
elessair 0:f269e3021894 907 #define LPC_GPDMA_BASE (0xFFE04000)
elessair 0:f269e3021894 908 #define LPC_GPDMACH0_BASE (0xFFE04100)
elessair 0:f269e3021894 909 #define LPC_GPDMACH1_BASE (0xFFE04120)
elessair 0:f269e3021894 910 #define LPC_EMC_BASE (0xFFE08000)
elessair 0:f269e3021894 911 #define LPC_USB_BASE (0xFFE0C000)
elessair 0:f269e3021894 912 #define LPC_VIC_BASE (0xFFFFF000)
elessair 0:f269e3021894 913
elessair 0:f269e3021894 914 /* GPIOs */
elessair 0:f269e3021894 915 #define LPC_GPIO0_BASE (0x3FFFC000)
elessair 0:f269e3021894 916 #define LPC_GPIO1_BASE (0x3FFFC020)
elessair 0:f269e3021894 917 #define LPC_GPIO2_BASE (0x3FFFC040)
elessair 0:f269e3021894 918 #define LPC_GPIO3_BASE (0x3FFFC060)
elessair 0:f269e3021894 919 #define LPC_GPIO4_BASE (0x3FFFC080)
elessair 0:f269e3021894 920
elessair 0:f269e3021894 921
elessair 0:f269e3021894 922 /******************************************************************************/
elessair 0:f269e3021894 923 /* Peripheral declaration */
elessair 0:f269e3021894 924 /******************************************************************************/
elessair 0:f269e3021894 925 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
elessair 0:f269e3021894 926 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
elessair 0:f269e3021894 927 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
elessair 0:f269e3021894 928 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
elessair 0:f269e3021894 929 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
elessair 0:f269e3021894 930 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
elessair 0:f269e3021894 931 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
elessair 0:f269e3021894 932 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
elessair 0:f269e3021894 933 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
elessair 0:f269e3021894 934 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
elessair 0:f269e3021894 935 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
elessair 0:f269e3021894 936 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
elessair 0:f269e3021894 937 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
elessair 0:f269e3021894 938 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
elessair 0:f269e3021894 939 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
elessair 0:f269e3021894 940 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
elessair 0:f269e3021894 941 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
elessair 0:f269e3021894 942 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
elessair 0:f269e3021894 943 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
elessair 0:f269e3021894 944 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
elessair 0:f269e3021894 945 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
elessair 0:f269e3021894 946 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
elessair 0:f269e3021894 947 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
elessair 0:f269e3021894 948 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
elessair 0:f269e3021894 949 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
elessair 0:f269e3021894 950 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
elessair 0:f269e3021894 951 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
elessair 0:f269e3021894 952 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
elessair 0:f269e3021894 953 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
elessair 0:f269e3021894 954 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
elessair 0:f269e3021894 955 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
elessair 0:f269e3021894 956 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
elessair 0:f269e3021894 957 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
elessair 0:f269e3021894 958 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
elessair 0:f269e3021894 959 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
elessair 0:f269e3021894 960 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
elessair 0:f269e3021894 961 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
elessair 0:f269e3021894 962 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
elessair 0:f269e3021894 963 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
elessair 0:f269e3021894 964 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
elessair 0:f269e3021894 965 #define LPC_EMC (( LPC_EMC_TypeDef *) LPC_EMC_BASE)
elessair 0:f269e3021894 966
elessair 0:f269e3021894 967 #ifdef __cplusplus
elessair 0:f269e3021894 968 }
elessair 0:f269e3021894 969 #endif
elessair 0:f269e3021894 970
elessair 0:f269e3021894 971 #endif // __LPC24xx_H
elessair 0:f269e3021894 972