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mbed-os

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cmsis/core_cmInstr.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cmInstr.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
elessair 0:f269e3021894 4 * @version V4.10
elessair 0:f269e3021894 5 * @date 18. March 2015
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #ifndef __CORE_CMINSTR_H
elessair 0:f269e3021894 39 #define __CORE_CMINSTR_H
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 /* ########################## Core Instruction Access ######################### */
elessair 0:f269e3021894 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
elessair 0:f269e3021894 44 Access to dedicated instructions
elessair 0:f269e3021894 45 @{
elessair 0:f269e3021894 46 */
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
elessair 0:f269e3021894 49 /* ARM armcc specific functions */
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 #if (__ARMCC_VERSION < 400677)
elessair 0:f269e3021894 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
elessair 0:f269e3021894 53 #endif
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55
elessair 0:f269e3021894 56 /** \brief No Operation
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 No Operation does nothing. This instruction can be used for code alignment purposes.
elessair 0:f269e3021894 59 */
elessair 0:f269e3021894 60 #define __NOP __nop
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 /** \brief Wait For Interrupt
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 Wait For Interrupt is a hint instruction that suspends execution
elessair 0:f269e3021894 66 until one of a number of events occurs.
elessair 0:f269e3021894 67 */
elessair 0:f269e3021894 68 #define __WFI __wfi
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 /** \brief Wait For Event
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 Wait For Event is a hint instruction that permits the processor to enter
elessair 0:f269e3021894 74 a low-power state until one of a number of events occurs.
elessair 0:f269e3021894 75 */
elessair 0:f269e3021894 76 #define __WFE __wfe
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 /** \brief Send Event
elessair 0:f269e3021894 80
elessair 0:f269e3021894 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
elessair 0:f269e3021894 82 */
elessair 0:f269e3021894 83 #define __SEV __sev
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 /** \brief Instruction Synchronization Barrier
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
elessair 0:f269e3021894 89 so that all instructions following the ISB are fetched from cache or
elessair 0:f269e3021894 90 memory, after the instruction has been completed.
elessair 0:f269e3021894 91 */
elessair 0:f269e3021894 92 #define __ISB() do {\
elessair 0:f269e3021894 93 __schedule_barrier();\
elessair 0:f269e3021894 94 __isb(0xF);\
elessair 0:f269e3021894 95 __schedule_barrier();\
elessair 0:f269e3021894 96 } while (0)
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 /** \brief Data Synchronization Barrier
elessair 0:f269e3021894 99
elessair 0:f269e3021894 100 This function acts as a special kind of Data Memory Barrier.
elessair 0:f269e3021894 101 It completes when all explicit memory accesses before this instruction complete.
elessair 0:f269e3021894 102 */
elessair 0:f269e3021894 103 #define __DSB() do {\
elessair 0:f269e3021894 104 __schedule_barrier();\
elessair 0:f269e3021894 105 __dsb(0xF);\
elessair 0:f269e3021894 106 __schedule_barrier();\
elessair 0:f269e3021894 107 } while (0)
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 /** \brief Data Memory Barrier
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 This function ensures the apparent order of the explicit memory operations before
elessair 0:f269e3021894 112 and after the instruction, without ensuring their completion.
elessair 0:f269e3021894 113 */
elessair 0:f269e3021894 114 #define __DMB() do {\
elessair 0:f269e3021894 115 __schedule_barrier();\
elessair 0:f269e3021894 116 __dmb(0xF);\
elessair 0:f269e3021894 117 __schedule_barrier();\
elessair 0:f269e3021894 118 } while (0)
elessair 0:f269e3021894 119
elessair 0:f269e3021894 120 /** \brief Reverse byte order (32 bit)
elessair 0:f269e3021894 121
elessair 0:f269e3021894 122 This function reverses the byte order in integer value.
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 \param [in] value Value to reverse
elessair 0:f269e3021894 125 \return Reversed value
elessair 0:f269e3021894 126 */
elessair 0:f269e3021894 127 #define __REV __rev
elessair 0:f269e3021894 128
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 /** \brief Reverse byte order (16 bit)
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 This function reverses the byte order in two unsigned short values.
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 \param [in] value Value to reverse
elessair 0:f269e3021894 135 \return Reversed value
elessair 0:f269e3021894 136 */
elessair 0:f269e3021894 137 #ifndef __NO_EMBEDDED_ASM
elessair 0:f269e3021894 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
elessair 0:f269e3021894 139 {
elessair 0:f269e3021894 140 rev16 r0, r0
elessair 0:f269e3021894 141 bx lr
elessair 0:f269e3021894 142 }
elessair 0:f269e3021894 143 #endif
elessair 0:f269e3021894 144
elessair 0:f269e3021894 145 /** \brief Reverse byte order in signed short value
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 This function reverses the byte order in a signed short value with sign extension to integer.
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 \param [in] value Value to reverse
elessair 0:f269e3021894 150 \return Reversed value
elessair 0:f269e3021894 151 */
elessair 0:f269e3021894 152 #ifndef __NO_EMBEDDED_ASM
elessair 0:f269e3021894 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
elessair 0:f269e3021894 154 {
elessair 0:f269e3021894 155 revsh r0, r0
elessair 0:f269e3021894 156 bx lr
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158 #endif
elessair 0:f269e3021894 159
elessair 0:f269e3021894 160
elessair 0:f269e3021894 161 /** \brief Rotate Right in unsigned value (32 bit)
elessair 0:f269e3021894 162
elessair 0:f269e3021894 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
elessair 0:f269e3021894 164
elessair 0:f269e3021894 165 \param [in] value Value to rotate
elessair 0:f269e3021894 166 \param [in] value Number of Bits to rotate
elessair 0:f269e3021894 167 \return Rotated value
elessair 0:f269e3021894 168 */
elessair 0:f269e3021894 169 #define __ROR __ror
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 /** \brief Breakpoint
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174 This function causes the processor to enter Debug state.
elessair 0:f269e3021894 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
elessair 0:f269e3021894 176
elessair 0:f269e3021894 177 \param [in] value is ignored by the processor.
elessair 0:f269e3021894 178 If required, a debugger can use it to store additional information about the breakpoint.
elessair 0:f269e3021894 179 */
elessair 0:f269e3021894 180 #define __BKPT(value) __breakpoint(value)
elessair 0:f269e3021894 181
elessair 0:f269e3021894 182
elessair 0:f269e3021894 183 /** \brief Reverse bit order of value
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 This function reverses the bit order of the given value.
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187 \param [in] value Value to reverse
elessair 0:f269e3021894 188 \return Reversed value
elessair 0:f269e3021894 189 */
elessair 0:f269e3021894 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
elessair 0:f269e3021894 191 #define __RBIT __rbit
elessair 0:f269e3021894 192 #else
elessair 0:f269e3021894 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
elessair 0:f269e3021894 194 {
elessair 0:f269e3021894 195 uint32_t result;
elessair 0:f269e3021894 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
elessair 0:f269e3021894 197
elessair 0:f269e3021894 198 result = value; // r will be reversed bits of v; first get LSB of v
elessair 0:f269e3021894 199 for (value >>= 1; value; value >>= 1)
elessair 0:f269e3021894 200 {
elessair 0:f269e3021894 201 result <<= 1;
elessair 0:f269e3021894 202 result |= value & 1;
elessair 0:f269e3021894 203 s--;
elessair 0:f269e3021894 204 }
elessair 0:f269e3021894 205 result <<= s; // shift when v's highest bits are zero
elessair 0:f269e3021894 206 return(result);
elessair 0:f269e3021894 207 }
elessair 0:f269e3021894 208 #endif
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210
elessair 0:f269e3021894 211 /** \brief Count leading zeros
elessair 0:f269e3021894 212
elessair 0:f269e3021894 213 This function counts the number of leading zeros of a data value.
elessair 0:f269e3021894 214
elessair 0:f269e3021894 215 \param [in] value Value to count the leading zeros
elessair 0:f269e3021894 216 \return number of leading zeros in value
elessair 0:f269e3021894 217 */
elessair 0:f269e3021894 218 #define __CLZ __clz
elessair 0:f269e3021894 219
elessair 0:f269e3021894 220
elessair 0:f269e3021894 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 /** \brief LDR Exclusive (8 bit)
elessair 0:f269e3021894 224
elessair 0:f269e3021894 225 This function executes a exclusive LDR instruction for 8 bit value.
elessair 0:f269e3021894 226
elessair 0:f269e3021894 227 \param [in] ptr Pointer to data
elessair 0:f269e3021894 228 \return value of type uint8_t at (*ptr)
elessair 0:f269e3021894 229 */
elessair 0:f269e3021894 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
elessair 0:f269e3021894 231
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 /** \brief LDR Exclusive (16 bit)
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 This function executes a exclusive LDR instruction for 16 bit values.
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 \param [in] ptr Pointer to data
elessair 0:f269e3021894 238 \return value of type uint16_t at (*ptr)
elessair 0:f269e3021894 239 */
elessair 0:f269e3021894 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
elessair 0:f269e3021894 241
elessair 0:f269e3021894 242
elessair 0:f269e3021894 243 /** \brief LDR Exclusive (32 bit)
elessair 0:f269e3021894 244
elessair 0:f269e3021894 245 This function executes a exclusive LDR instruction for 32 bit values.
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 \param [in] ptr Pointer to data
elessair 0:f269e3021894 248 \return value of type uint32_t at (*ptr)
elessair 0:f269e3021894 249 */
elessair 0:f269e3021894 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253 /** \brief STR Exclusive (8 bit)
elessair 0:f269e3021894 254
elessair 0:f269e3021894 255 This function executes a exclusive STR instruction for 8 bit values.
elessair 0:f269e3021894 256
elessair 0:f269e3021894 257 \param [in] value Value to store
elessair 0:f269e3021894 258 \param [in] ptr Pointer to location
elessair 0:f269e3021894 259 \return 0 Function succeeded
elessair 0:f269e3021894 260 \return 1 Function failed
elessair 0:f269e3021894 261 */
elessair 0:f269e3021894 262 #define __STREXB(value, ptr) __strex(value, ptr)
elessair 0:f269e3021894 263
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 /** \brief STR Exclusive (16 bit)
elessair 0:f269e3021894 266
elessair 0:f269e3021894 267 This function executes a exclusive STR instruction for 16 bit values.
elessair 0:f269e3021894 268
elessair 0:f269e3021894 269 \param [in] value Value to store
elessair 0:f269e3021894 270 \param [in] ptr Pointer to location
elessair 0:f269e3021894 271 \return 0 Function succeeded
elessair 0:f269e3021894 272 \return 1 Function failed
elessair 0:f269e3021894 273 */
elessair 0:f269e3021894 274 #define __STREXH(value, ptr) __strex(value, ptr)
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276
elessair 0:f269e3021894 277 /** \brief STR Exclusive (32 bit)
elessair 0:f269e3021894 278
elessair 0:f269e3021894 279 This function executes a exclusive STR instruction for 32 bit values.
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 \param [in] value Value to store
elessair 0:f269e3021894 282 \param [in] ptr Pointer to location
elessair 0:f269e3021894 283 \return 0 Function succeeded
elessair 0:f269e3021894 284 \return 1 Function failed
elessair 0:f269e3021894 285 */
elessair 0:f269e3021894 286 #define __STREXW(value, ptr) __strex(value, ptr)
elessair 0:f269e3021894 287
elessair 0:f269e3021894 288
elessair 0:f269e3021894 289 /** \brief Remove the exclusive lock
elessair 0:f269e3021894 290
elessair 0:f269e3021894 291 This function removes the exclusive lock which is created by LDREX.
elessair 0:f269e3021894 292
elessair 0:f269e3021894 293 */
elessair 0:f269e3021894 294 #define __CLREX __clrex
elessair 0:f269e3021894 295
elessair 0:f269e3021894 296
elessair 0:f269e3021894 297 /** \brief Signed Saturate
elessair 0:f269e3021894 298
elessair 0:f269e3021894 299 This function saturates a signed value.
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 \param [in] value Value to be saturated
elessair 0:f269e3021894 302 \param [in] sat Bit position to saturate to (1..32)
elessair 0:f269e3021894 303 \return Saturated value
elessair 0:f269e3021894 304 */
elessair 0:f269e3021894 305 #define __SSAT __ssat
elessair 0:f269e3021894 306
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 /** \brief Unsigned Saturate
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 This function saturates an unsigned value.
elessair 0:f269e3021894 311
elessair 0:f269e3021894 312 \param [in] value Value to be saturated
elessair 0:f269e3021894 313 \param [in] sat Bit position to saturate to (0..31)
elessair 0:f269e3021894 314 \return Saturated value
elessair 0:f269e3021894 315 */
elessair 0:f269e3021894 316 #define __USAT __usat
elessair 0:f269e3021894 317
elessair 0:f269e3021894 318
elessair 0:f269e3021894 319 /** \brief Rotate Right with Extend (32 bit)
elessair 0:f269e3021894 320
elessair 0:f269e3021894 321 This function moves each bit of a bitstring right by one bit.
elessair 0:f269e3021894 322 The carry input is shifted in at the left end of the bitstring.
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 \param [in] value Value to rotate
elessair 0:f269e3021894 325 \return Rotated value
elessair 0:f269e3021894 326 */
elessair 0:f269e3021894 327 #ifndef __NO_EMBEDDED_ASM
elessair 0:f269e3021894 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
elessair 0:f269e3021894 329 {
elessair 0:f269e3021894 330 rrx r0, r0
elessair 0:f269e3021894 331 bx lr
elessair 0:f269e3021894 332 }
elessair 0:f269e3021894 333 #endif
elessair 0:f269e3021894 334
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336 /** \brief LDRT Unprivileged (8 bit)
elessair 0:f269e3021894 337
elessair 0:f269e3021894 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
elessair 0:f269e3021894 339
elessair 0:f269e3021894 340 \param [in] ptr Pointer to data
elessair 0:f269e3021894 341 \return value of type uint8_t at (*ptr)
elessair 0:f269e3021894 342 */
elessair 0:f269e3021894 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
elessair 0:f269e3021894 344
elessair 0:f269e3021894 345
elessair 0:f269e3021894 346 /** \brief LDRT Unprivileged (16 bit)
elessair 0:f269e3021894 347
elessair 0:f269e3021894 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 \param [in] ptr Pointer to data
elessair 0:f269e3021894 351 \return value of type uint16_t at (*ptr)
elessair 0:f269e3021894 352 */
elessair 0:f269e3021894 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
elessair 0:f269e3021894 354
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 /** \brief LDRT Unprivileged (32 bit)
elessair 0:f269e3021894 357
elessair 0:f269e3021894 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
elessair 0:f269e3021894 359
elessair 0:f269e3021894 360 \param [in] ptr Pointer to data
elessair 0:f269e3021894 361 \return value of type uint32_t at (*ptr)
elessair 0:f269e3021894 362 */
elessair 0:f269e3021894 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365
elessair 0:f269e3021894 366 /** \brief STRT Unprivileged (8 bit)
elessair 0:f269e3021894 367
elessair 0:f269e3021894 368 This function executes a Unprivileged STRT instruction for 8 bit values.
elessair 0:f269e3021894 369
elessair 0:f269e3021894 370 \param [in] value Value to store
elessair 0:f269e3021894 371 \param [in] ptr Pointer to location
elessair 0:f269e3021894 372 */
elessair 0:f269e3021894 373 #define __STRBT(value, ptr) __strt(value, ptr)
elessair 0:f269e3021894 374
elessair 0:f269e3021894 375
elessair 0:f269e3021894 376 /** \brief STRT Unprivileged (16 bit)
elessair 0:f269e3021894 377
elessair 0:f269e3021894 378 This function executes a Unprivileged STRT instruction for 16 bit values.
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380 \param [in] value Value to store
elessair 0:f269e3021894 381 \param [in] ptr Pointer to location
elessair 0:f269e3021894 382 */
elessair 0:f269e3021894 383 #define __STRHT(value, ptr) __strt(value, ptr)
elessair 0:f269e3021894 384
elessair 0:f269e3021894 385
elessair 0:f269e3021894 386 /** \brief STRT Unprivileged (32 bit)
elessair 0:f269e3021894 387
elessair 0:f269e3021894 388 This function executes a Unprivileged STRT instruction for 32 bit values.
elessair 0:f269e3021894 389
elessair 0:f269e3021894 390 \param [in] value Value to store
elessair 0:f269e3021894 391 \param [in] ptr Pointer to location
elessair 0:f269e3021894 392 */
elessair 0:f269e3021894 393 #define __STRT(value, ptr) __strt(value, ptr)
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397
elessair 0:f269e3021894 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
elessair 0:f269e3021894 399 /* GNU gcc specific functions */
elessair 0:f269e3021894 400
elessair 0:f269e3021894 401 /* Define macros for porting to both thumb1 and thumb2.
elessair 0:f269e3021894 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
elessair 0:f269e3021894 403 * Otherwise, use general registers, specified by constrant "r" */
elessair 0:f269e3021894 404 #if defined (__thumb__) && !defined (__thumb2__)
elessair 0:f269e3021894 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
elessair 0:f269e3021894 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
elessair 0:f269e3021894 407 #else
elessair 0:f269e3021894 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
elessair 0:f269e3021894 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
elessair 0:f269e3021894 410 #endif
elessair 0:f269e3021894 411
elessair 0:f269e3021894 412 /** \brief No Operation
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414 No Operation does nothing. This instruction can be used for code alignment purposes.
elessair 0:f269e3021894 415 */
elessair 0:f269e3021894 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
elessair 0:f269e3021894 417 {
elessair 0:f269e3021894 418 __ASM volatile ("nop");
elessair 0:f269e3021894 419 }
elessair 0:f269e3021894 420
elessair 0:f269e3021894 421
elessair 0:f269e3021894 422 /** \brief Wait For Interrupt
elessair 0:f269e3021894 423
elessair 0:f269e3021894 424 Wait For Interrupt is a hint instruction that suspends execution
elessair 0:f269e3021894 425 until one of a number of events occurs.
elessair 0:f269e3021894 426 */
elessair 0:f269e3021894 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
elessair 0:f269e3021894 428 {
elessair 0:f269e3021894 429 __ASM volatile ("wfi");
elessair 0:f269e3021894 430 }
elessair 0:f269e3021894 431
elessair 0:f269e3021894 432
elessair 0:f269e3021894 433 /** \brief Wait For Event
elessair 0:f269e3021894 434
elessair 0:f269e3021894 435 Wait For Event is a hint instruction that permits the processor to enter
elessair 0:f269e3021894 436 a low-power state until one of a number of events occurs.
elessair 0:f269e3021894 437 */
elessair 0:f269e3021894 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
elessair 0:f269e3021894 439 {
elessair 0:f269e3021894 440 __ASM volatile ("wfe");
elessair 0:f269e3021894 441 }
elessair 0:f269e3021894 442
elessair 0:f269e3021894 443
elessair 0:f269e3021894 444 /** \brief Send Event
elessair 0:f269e3021894 445
elessair 0:f269e3021894 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
elessair 0:f269e3021894 447 */
elessair 0:f269e3021894 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
elessair 0:f269e3021894 449 {
elessair 0:f269e3021894 450 __ASM volatile ("sev");
elessair 0:f269e3021894 451 }
elessair 0:f269e3021894 452
elessair 0:f269e3021894 453
elessair 0:f269e3021894 454 /** \brief Instruction Synchronization Barrier
elessair 0:f269e3021894 455
elessair 0:f269e3021894 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
elessair 0:f269e3021894 457 so that all instructions following the ISB are fetched from cache or
elessair 0:f269e3021894 458 memory, after the instruction has been completed.
elessair 0:f269e3021894 459 */
elessair 0:f269e3021894 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
elessair 0:f269e3021894 461 {
elessair 0:f269e3021894 462 __ASM volatile ("isb 0xF":::"memory");
elessair 0:f269e3021894 463 }
elessair 0:f269e3021894 464
elessair 0:f269e3021894 465
elessair 0:f269e3021894 466 /** \brief Data Synchronization Barrier
elessair 0:f269e3021894 467
elessair 0:f269e3021894 468 This function acts as a special kind of Data Memory Barrier.
elessair 0:f269e3021894 469 It completes when all explicit memory accesses before this instruction complete.
elessair 0:f269e3021894 470 */
elessair 0:f269e3021894 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
elessair 0:f269e3021894 472 {
elessair 0:f269e3021894 473 __ASM volatile ("dsb 0xF":::"memory");
elessair 0:f269e3021894 474 }
elessair 0:f269e3021894 475
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 /** \brief Data Memory Barrier
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479 This function ensures the apparent order of the explicit memory operations before
elessair 0:f269e3021894 480 and after the instruction, without ensuring their completion.
elessair 0:f269e3021894 481 */
elessair 0:f269e3021894 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
elessair 0:f269e3021894 483 {
elessair 0:f269e3021894 484 __ASM volatile ("dmb 0xF":::"memory");
elessair 0:f269e3021894 485 }
elessair 0:f269e3021894 486
elessair 0:f269e3021894 487
elessair 0:f269e3021894 488 /** \brief Reverse byte order (32 bit)
elessair 0:f269e3021894 489
elessair 0:f269e3021894 490 This function reverses the byte order in integer value.
elessair 0:f269e3021894 491
elessair 0:f269e3021894 492 \param [in] value Value to reverse
elessair 0:f269e3021894 493 \return Reversed value
elessair 0:f269e3021894 494 */
elessair 0:f269e3021894 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
elessair 0:f269e3021894 496 {
elessair 0:f269e3021894 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
elessair 0:f269e3021894 498 return __builtin_bswap32(value);
elessair 0:f269e3021894 499 #else
elessair 0:f269e3021894 500 uint32_t result;
elessair 0:f269e3021894 501
elessair 0:f269e3021894 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
elessair 0:f269e3021894 503 return(result);
elessair 0:f269e3021894 504 #endif
elessair 0:f269e3021894 505 }
elessair 0:f269e3021894 506
elessair 0:f269e3021894 507
elessair 0:f269e3021894 508 /** \brief Reverse byte order (16 bit)
elessair 0:f269e3021894 509
elessair 0:f269e3021894 510 This function reverses the byte order in two unsigned short values.
elessair 0:f269e3021894 511
elessair 0:f269e3021894 512 \param [in] value Value to reverse
elessair 0:f269e3021894 513 \return Reversed value
elessair 0:f269e3021894 514 */
elessair 0:f269e3021894 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
elessair 0:f269e3021894 516 {
elessair 0:f269e3021894 517 uint32_t result;
elessair 0:f269e3021894 518
elessair 0:f269e3021894 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
elessair 0:f269e3021894 520 return(result);
elessair 0:f269e3021894 521 }
elessair 0:f269e3021894 522
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 /** \brief Reverse byte order in signed short value
elessair 0:f269e3021894 525
elessair 0:f269e3021894 526 This function reverses the byte order in a signed short value with sign extension to integer.
elessair 0:f269e3021894 527
elessair 0:f269e3021894 528 \param [in] value Value to reverse
elessair 0:f269e3021894 529 \return Reversed value
elessair 0:f269e3021894 530 */
elessair 0:f269e3021894 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
elessair 0:f269e3021894 532 {
elessair 0:f269e3021894 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
elessair 0:f269e3021894 534 return (short)__builtin_bswap16(value);
elessair 0:f269e3021894 535 #else
elessair 0:f269e3021894 536 uint32_t result;
elessair 0:f269e3021894 537
elessair 0:f269e3021894 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
elessair 0:f269e3021894 539 return(result);
elessair 0:f269e3021894 540 #endif
elessair 0:f269e3021894 541 }
elessair 0:f269e3021894 542
elessair 0:f269e3021894 543
elessair 0:f269e3021894 544 /** \brief Rotate Right in unsigned value (32 bit)
elessair 0:f269e3021894 545
elessair 0:f269e3021894 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
elessair 0:f269e3021894 547
elessair 0:f269e3021894 548 \param [in] value Value to rotate
elessair 0:f269e3021894 549 \param [in] value Number of Bits to rotate
elessair 0:f269e3021894 550 \return Rotated value
elessair 0:f269e3021894 551 */
elessair 0:f269e3021894 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
elessair 0:f269e3021894 553 {
elessair 0:f269e3021894 554 return (op1 >> op2) | (op1 << (32 - op2));
elessair 0:f269e3021894 555 }
elessair 0:f269e3021894 556
elessair 0:f269e3021894 557
elessair 0:f269e3021894 558 /** \brief Breakpoint
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 This function causes the processor to enter Debug state.
elessair 0:f269e3021894 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
elessair 0:f269e3021894 562
elessair 0:f269e3021894 563 \param [in] value is ignored by the processor.
elessair 0:f269e3021894 564 If required, a debugger can use it to store additional information about the breakpoint.
elessair 0:f269e3021894 565 */
elessair 0:f269e3021894 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
elessair 0:f269e3021894 567
elessair 0:f269e3021894 568
elessair 0:f269e3021894 569 /** \brief Reverse bit order of value
elessair 0:f269e3021894 570
elessair 0:f269e3021894 571 This function reverses the bit order of the given value.
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 \param [in] value Value to reverse
elessair 0:f269e3021894 574 \return Reversed value
elessair 0:f269e3021894 575 */
elessair 0:f269e3021894 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
elessair 0:f269e3021894 577 {
elessair 0:f269e3021894 578 uint32_t result;
elessair 0:f269e3021894 579
elessair 0:f269e3021894 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
elessair 0:f269e3021894 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
elessair 0:f269e3021894 582 #else
elessair 0:f269e3021894 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
elessair 0:f269e3021894 584
elessair 0:f269e3021894 585 result = value; // r will be reversed bits of v; first get LSB of v
elessair 0:f269e3021894 586 for (value >>= 1; value; value >>= 1)
elessair 0:f269e3021894 587 {
elessair 0:f269e3021894 588 result <<= 1;
elessair 0:f269e3021894 589 result |= value & 1;
elessair 0:f269e3021894 590 s--;
elessair 0:f269e3021894 591 }
elessair 0:f269e3021894 592 result <<= s; // shift when v's highest bits are zero
elessair 0:f269e3021894 593 #endif
elessair 0:f269e3021894 594 return(result);
elessair 0:f269e3021894 595 }
elessair 0:f269e3021894 596
elessair 0:f269e3021894 597
elessair 0:f269e3021894 598 /** \brief Count leading zeros
elessair 0:f269e3021894 599
elessair 0:f269e3021894 600 This function counts the number of leading zeros of a data value.
elessair 0:f269e3021894 601
elessair 0:f269e3021894 602 \param [in] value Value to count the leading zeros
elessair 0:f269e3021894 603 \return number of leading zeros in value
elessair 0:f269e3021894 604 */
elessair 0:f269e3021894 605 #define __CLZ __builtin_clz
elessair 0:f269e3021894 606
elessair 0:f269e3021894 607
elessair 0:f269e3021894 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
elessair 0:f269e3021894 609
elessair 0:f269e3021894 610 /** \brief LDR Exclusive (8 bit)
elessair 0:f269e3021894 611
elessair 0:f269e3021894 612 This function executes a exclusive LDR instruction for 8 bit value.
elessair 0:f269e3021894 613
elessair 0:f269e3021894 614 \param [in] ptr Pointer to data
elessair 0:f269e3021894 615 \return value of type uint8_t at (*ptr)
elessair 0:f269e3021894 616 */
elessair 0:f269e3021894 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
elessair 0:f269e3021894 618 {
elessair 0:f269e3021894 619 uint32_t result;
elessair 0:f269e3021894 620
elessair 0:f269e3021894 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
elessair 0:f269e3021894 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 623 #else
elessair 0:f269e3021894 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
elessair 0:f269e3021894 625 accepted by assembler. So has to use following less efficient pattern.
elessair 0:f269e3021894 626 */
elessair 0:f269e3021894 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
elessair 0:f269e3021894 628 #endif
elessair 0:f269e3021894 629 return ((uint8_t) result); /* Add explicit type cast here */
elessair 0:f269e3021894 630 }
elessair 0:f269e3021894 631
elessair 0:f269e3021894 632
elessair 0:f269e3021894 633 /** \brief LDR Exclusive (16 bit)
elessair 0:f269e3021894 634
elessair 0:f269e3021894 635 This function executes a exclusive LDR instruction for 16 bit values.
elessair 0:f269e3021894 636
elessair 0:f269e3021894 637 \param [in] ptr Pointer to data
elessair 0:f269e3021894 638 \return value of type uint16_t at (*ptr)
elessair 0:f269e3021894 639 */
elessair 0:f269e3021894 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
elessair 0:f269e3021894 641 {
elessair 0:f269e3021894 642 uint32_t result;
elessair 0:f269e3021894 643
elessair 0:f269e3021894 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
elessair 0:f269e3021894 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 646 #else
elessair 0:f269e3021894 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
elessair 0:f269e3021894 648 accepted by assembler. So has to use following less efficient pattern.
elessair 0:f269e3021894 649 */
elessair 0:f269e3021894 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
elessair 0:f269e3021894 651 #endif
elessair 0:f269e3021894 652 return ((uint16_t) result); /* Add explicit type cast here */
elessair 0:f269e3021894 653 }
elessair 0:f269e3021894 654
elessair 0:f269e3021894 655
elessair 0:f269e3021894 656 /** \brief LDR Exclusive (32 bit)
elessair 0:f269e3021894 657
elessair 0:f269e3021894 658 This function executes a exclusive LDR instruction for 32 bit values.
elessair 0:f269e3021894 659
elessair 0:f269e3021894 660 \param [in] ptr Pointer to data
elessair 0:f269e3021894 661 \return value of type uint32_t at (*ptr)
elessair 0:f269e3021894 662 */
elessair 0:f269e3021894 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
elessair 0:f269e3021894 664 {
elessair 0:f269e3021894 665 uint32_t result;
elessair 0:f269e3021894 666
elessair 0:f269e3021894 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 668 return(result);
elessair 0:f269e3021894 669 }
elessair 0:f269e3021894 670
elessair 0:f269e3021894 671
elessair 0:f269e3021894 672 /** \brief STR Exclusive (8 bit)
elessair 0:f269e3021894 673
elessair 0:f269e3021894 674 This function executes a exclusive STR instruction for 8 bit values.
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676 \param [in] value Value to store
elessair 0:f269e3021894 677 \param [in] ptr Pointer to location
elessair 0:f269e3021894 678 \return 0 Function succeeded
elessair 0:f269e3021894 679 \return 1 Function failed
elessair 0:f269e3021894 680 */
elessair 0:f269e3021894 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
elessair 0:f269e3021894 682 {
elessair 0:f269e3021894 683 uint32_t result;
elessair 0:f269e3021894 684
elessair 0:f269e3021894 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
elessair 0:f269e3021894 686 return(result);
elessair 0:f269e3021894 687 }
elessair 0:f269e3021894 688
elessair 0:f269e3021894 689
elessair 0:f269e3021894 690 /** \brief STR Exclusive (16 bit)
elessair 0:f269e3021894 691
elessair 0:f269e3021894 692 This function executes a exclusive STR instruction for 16 bit values.
elessair 0:f269e3021894 693
elessair 0:f269e3021894 694 \param [in] value Value to store
elessair 0:f269e3021894 695 \param [in] ptr Pointer to location
elessair 0:f269e3021894 696 \return 0 Function succeeded
elessair 0:f269e3021894 697 \return 1 Function failed
elessair 0:f269e3021894 698 */
elessair 0:f269e3021894 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
elessair 0:f269e3021894 700 {
elessair 0:f269e3021894 701 uint32_t result;
elessair 0:f269e3021894 702
elessair 0:f269e3021894 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
elessair 0:f269e3021894 704 return(result);
elessair 0:f269e3021894 705 }
elessair 0:f269e3021894 706
elessair 0:f269e3021894 707
elessair 0:f269e3021894 708 /** \brief STR Exclusive (32 bit)
elessair 0:f269e3021894 709
elessair 0:f269e3021894 710 This function executes a exclusive STR instruction for 32 bit values.
elessair 0:f269e3021894 711
elessair 0:f269e3021894 712 \param [in] value Value to store
elessair 0:f269e3021894 713 \param [in] ptr Pointer to location
elessair 0:f269e3021894 714 \return 0 Function succeeded
elessair 0:f269e3021894 715 \return 1 Function failed
elessair 0:f269e3021894 716 */
elessair 0:f269e3021894 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
elessair 0:f269e3021894 718 {
elessair 0:f269e3021894 719 uint32_t result;
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
elessair 0:f269e3021894 722 return(result);
elessair 0:f269e3021894 723 }
elessair 0:f269e3021894 724
elessair 0:f269e3021894 725
elessair 0:f269e3021894 726 /** \brief Remove the exclusive lock
elessair 0:f269e3021894 727
elessair 0:f269e3021894 728 This function removes the exclusive lock which is created by LDREX.
elessair 0:f269e3021894 729
elessair 0:f269e3021894 730 */
elessair 0:f269e3021894 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
elessair 0:f269e3021894 732 {
elessair 0:f269e3021894 733 __ASM volatile ("clrex" ::: "memory");
elessair 0:f269e3021894 734 }
elessair 0:f269e3021894 735
elessair 0:f269e3021894 736
elessair 0:f269e3021894 737 /** \brief Signed Saturate
elessair 0:f269e3021894 738
elessair 0:f269e3021894 739 This function saturates a signed value.
elessair 0:f269e3021894 740
elessair 0:f269e3021894 741 \param [in] value Value to be saturated
elessair 0:f269e3021894 742 \param [in] sat Bit position to saturate to (1..32)
elessair 0:f269e3021894 743 \return Saturated value
elessair 0:f269e3021894 744 */
elessair 0:f269e3021894 745 #define __SSAT(ARG1,ARG2) \
elessair 0:f269e3021894 746 ({ \
elessair 0:f269e3021894 747 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 749 __RES; \
elessair 0:f269e3021894 750 })
elessair 0:f269e3021894 751
elessair 0:f269e3021894 752
elessair 0:f269e3021894 753 /** \brief Unsigned Saturate
elessair 0:f269e3021894 754
elessair 0:f269e3021894 755 This function saturates an unsigned value.
elessair 0:f269e3021894 756
elessair 0:f269e3021894 757 \param [in] value Value to be saturated
elessair 0:f269e3021894 758 \param [in] sat Bit position to saturate to (0..31)
elessair 0:f269e3021894 759 \return Saturated value
elessair 0:f269e3021894 760 */
elessair 0:f269e3021894 761 #define __USAT(ARG1,ARG2) \
elessair 0:f269e3021894 762 ({ \
elessair 0:f269e3021894 763 uint32_t __RES, __ARG1 = (ARG1); \
elessair 0:f269e3021894 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
elessair 0:f269e3021894 765 __RES; \
elessair 0:f269e3021894 766 })
elessair 0:f269e3021894 767
elessair 0:f269e3021894 768
elessair 0:f269e3021894 769 /** \brief Rotate Right with Extend (32 bit)
elessair 0:f269e3021894 770
elessair 0:f269e3021894 771 This function moves each bit of a bitstring right by one bit.
elessair 0:f269e3021894 772 The carry input is shifted in at the left end of the bitstring.
elessair 0:f269e3021894 773
elessair 0:f269e3021894 774 \param [in] value Value to rotate
elessair 0:f269e3021894 775 \return Rotated value
elessair 0:f269e3021894 776 */
elessair 0:f269e3021894 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
elessair 0:f269e3021894 778 {
elessair 0:f269e3021894 779 uint32_t result;
elessair 0:f269e3021894 780
elessair 0:f269e3021894 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
elessair 0:f269e3021894 782 return(result);
elessair 0:f269e3021894 783 }
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785
elessair 0:f269e3021894 786 /** \brief LDRT Unprivileged (8 bit)
elessair 0:f269e3021894 787
elessair 0:f269e3021894 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
elessair 0:f269e3021894 789
elessair 0:f269e3021894 790 \param [in] ptr Pointer to data
elessair 0:f269e3021894 791 \return value of type uint8_t at (*ptr)
elessair 0:f269e3021894 792 */
elessair 0:f269e3021894 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
elessair 0:f269e3021894 794 {
elessair 0:f269e3021894 795 uint32_t result;
elessair 0:f269e3021894 796
elessair 0:f269e3021894 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
elessair 0:f269e3021894 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 799 #else
elessair 0:f269e3021894 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
elessair 0:f269e3021894 801 accepted by assembler. So has to use following less efficient pattern.
elessair 0:f269e3021894 802 */
elessair 0:f269e3021894 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
elessair 0:f269e3021894 804 #endif
elessair 0:f269e3021894 805 return ((uint8_t) result); /* Add explicit type cast here */
elessair 0:f269e3021894 806 }
elessair 0:f269e3021894 807
elessair 0:f269e3021894 808
elessair 0:f269e3021894 809 /** \brief LDRT Unprivileged (16 bit)
elessair 0:f269e3021894 810
elessair 0:f269e3021894 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
elessair 0:f269e3021894 812
elessair 0:f269e3021894 813 \param [in] ptr Pointer to data
elessair 0:f269e3021894 814 \return value of type uint16_t at (*ptr)
elessair 0:f269e3021894 815 */
elessair 0:f269e3021894 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
elessair 0:f269e3021894 817 {
elessair 0:f269e3021894 818 uint32_t result;
elessair 0:f269e3021894 819
elessair 0:f269e3021894 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
elessair 0:f269e3021894 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 822 #else
elessair 0:f269e3021894 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
elessair 0:f269e3021894 824 accepted by assembler. So has to use following less efficient pattern.
elessair 0:f269e3021894 825 */
elessair 0:f269e3021894 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
elessair 0:f269e3021894 827 #endif
elessair 0:f269e3021894 828 return ((uint16_t) result); /* Add explicit type cast here */
elessair 0:f269e3021894 829 }
elessair 0:f269e3021894 830
elessair 0:f269e3021894 831
elessair 0:f269e3021894 832 /** \brief LDRT Unprivileged (32 bit)
elessair 0:f269e3021894 833
elessair 0:f269e3021894 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
elessair 0:f269e3021894 835
elessair 0:f269e3021894 836 \param [in] ptr Pointer to data
elessair 0:f269e3021894 837 \return value of type uint32_t at (*ptr)
elessair 0:f269e3021894 838 */
elessair 0:f269e3021894 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
elessair 0:f269e3021894 840 {
elessair 0:f269e3021894 841 uint32_t result;
elessair 0:f269e3021894 842
elessair 0:f269e3021894 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
elessair 0:f269e3021894 844 return(result);
elessair 0:f269e3021894 845 }
elessair 0:f269e3021894 846
elessair 0:f269e3021894 847
elessair 0:f269e3021894 848 /** \brief STRT Unprivileged (8 bit)
elessair 0:f269e3021894 849
elessair 0:f269e3021894 850 This function executes a Unprivileged STRT instruction for 8 bit values.
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 \param [in] value Value to store
elessair 0:f269e3021894 853 \param [in] ptr Pointer to location
elessair 0:f269e3021894 854 */
elessair 0:f269e3021894 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
elessair 0:f269e3021894 856 {
elessair 0:f269e3021894 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
elessair 0:f269e3021894 858 }
elessair 0:f269e3021894 859
elessair 0:f269e3021894 860
elessair 0:f269e3021894 861 /** \brief STRT Unprivileged (16 bit)
elessair 0:f269e3021894 862
elessair 0:f269e3021894 863 This function executes a Unprivileged STRT instruction for 16 bit values.
elessair 0:f269e3021894 864
elessair 0:f269e3021894 865 \param [in] value Value to store
elessair 0:f269e3021894 866 \param [in] ptr Pointer to location
elessair 0:f269e3021894 867 */
elessair 0:f269e3021894 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
elessair 0:f269e3021894 869 {
elessair 0:f269e3021894 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
elessair 0:f269e3021894 871 }
elessair 0:f269e3021894 872
elessair 0:f269e3021894 873
elessair 0:f269e3021894 874 /** \brief STRT Unprivileged (32 bit)
elessair 0:f269e3021894 875
elessair 0:f269e3021894 876 This function executes a Unprivileged STRT instruction for 32 bit values.
elessair 0:f269e3021894 877
elessair 0:f269e3021894 878 \param [in] value Value to store
elessair 0:f269e3021894 879 \param [in] ptr Pointer to location
elessair 0:f269e3021894 880 */
elessair 0:f269e3021894 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
elessair 0:f269e3021894 882 {
elessair 0:f269e3021894 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
elessair 0:f269e3021894 884 }
elessair 0:f269e3021894 885
elessair 0:f269e3021894 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
elessair 0:f269e3021894 887
elessair 0:f269e3021894 888
elessair 0:f269e3021894 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
elessair 0:f269e3021894 890 /* IAR iccarm specific functions */
elessair 0:f269e3021894 891 #include <cmsis_iar.h>
elessair 0:f269e3021894 892
elessair 0:f269e3021894 893
elessair 0:f269e3021894 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
elessair 0:f269e3021894 895 /* TI CCS specific functions */
elessair 0:f269e3021894 896 #include <cmsis_ccs.h>
elessair 0:f269e3021894 897
elessair 0:f269e3021894 898
elessair 0:f269e3021894 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
elessair 0:f269e3021894 900 /* TASKING carm specific functions */
elessair 0:f269e3021894 901 /*
elessair 0:f269e3021894 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
elessair 0:f269e3021894 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
elessair 0:f269e3021894 904 * Including the CMSIS ones.
elessair 0:f269e3021894 905 */
elessair 0:f269e3021894 906
elessair 0:f269e3021894 907
elessair 0:f269e3021894 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
elessair 0:f269e3021894 909 /* Cosmic specific functions */
elessair 0:f269e3021894 910 #include <cmsis_csm.h>
elessair 0:f269e3021894 911
elessair 0:f269e3021894 912 #endif
elessair 0:f269e3021894 913
elessair 0:f269e3021894 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
elessair 0:f269e3021894 915
elessair 0:f269e3021894 916 #endif /* __CORE_CMINSTR_H */