Lee Kai Xuan / mbed-os

mbed-os

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targets/TARGET_NXP/TARGET_LPC11U6X/device/LPC11U6x.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1
elessair 0:f269e3021894 2 /****************************************************************************************************//**
elessair 0:f269e3021894 3 * @file LPC11U6x.h
elessair 0:f269e3021894 4 *
elessair 0:f269e3021894 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
elessair 0:f269e3021894 6 * LPC11U6x from .
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * @version V0.4
elessair 0:f269e3021894 9 * @date 22. October 2013
elessair 0:f269e3021894 10 *
elessair 0:f269e3021894 11 * @note Generated with SVDConv V2.81a
elessair 0:f269e3021894 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
elessair 0:f269e3021894 13 *
elessair 0:f269e3021894 14 * modified by Keil
elessair 0:f269e3021894 15 *******************************************************************************************************/
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 /** @addtogroup (null)
elessair 0:f269e3021894 20 * @{
elessair 0:f269e3021894 21 */
elessair 0:f269e3021894 22
elessair 0:f269e3021894 23 /** @addtogroup LPC11U6x
elessair 0:f269e3021894 24 * @{
elessair 0:f269e3021894 25 */
elessair 0:f269e3021894 26
elessair 0:f269e3021894 27 #ifndef LPC11U6X_H
elessair 0:f269e3021894 28 #define LPC11U6X_H
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 #ifdef __cplusplus
elessair 0:f269e3021894 31 extern "C" {
elessair 0:f269e3021894 32 #endif
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 /* ------------------------- Interrupt Number Definition ------------------------ */
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37 typedef enum {
elessair 0:f269e3021894 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
elessair 0:f269e3021894 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
elessair 0:f269e3021894 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
elessair 0:f269e3021894 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
elessair 0:f269e3021894 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
elessair 0:f269e3021894 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
elessair 0:f269e3021894 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
elessair 0:f269e3021894 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
elessair 0:f269e3021894 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
elessair 0:f269e3021894 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
elessair 0:f269e3021894 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
elessair 0:f269e3021894 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
elessair 0:f269e3021894 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
elessair 0:f269e3021894 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
elessair 0:f269e3021894 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
elessair 0:f269e3021894 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
elessair 0:f269e3021894 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
elessair 0:f269e3021894 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
elessair 0:f269e3021894 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
elessair 0:f269e3021894 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
elessair 0:f269e3021894 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
elessair 0:f269e3021894 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
elessair 0:f269e3021894 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
elessair 0:f269e3021894 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
elessair 0:f269e3021894 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
elessair 0:f269e3021894 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
elessair 0:f269e3021894 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
elessair 0:f269e3021894 72 USART0_IRQn = 21, /*!< 21 USART0 */
elessair 0:f269e3021894 73 USB_IRQn = 22, /*!< 22 USB */
elessair 0:f269e3021894 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
elessair 0:f269e3021894 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
elessair 0:f269e3021894 76 RTC_IRQn = 25, /*!< 25 RTC */
elessair 0:f269e3021894 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
elessair 0:f269e3021894 78 FLASH_IRQn = 27, /*!< 27 FLASH */
elessair 0:f269e3021894 79 DMA_IRQn = 28, /*!< 28 DMA */
elessair 0:f269e3021894 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
elessair 0:f269e3021894 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
elessair 0:f269e3021894 82 } IRQn_Type;
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 /** @addtogroup Configuration_of_CMSIS
elessair 0:f269e3021894 86 * @{
elessair 0:f269e3021894 87 */
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 /* ================================================================================ */
elessair 0:f269e3021894 91 /* ================ Processor and Core Peripheral Section ================ */
elessair 0:f269e3021894 92 /* ================================================================================ */
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
elessair 0:f269e3021894 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
elessair 0:f269e3021894 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
elessair 0:f269e3021894 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
elessair 0:f269e3021894 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
elessair 0:f269e3021894 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
elessair 0:f269e3021894 100 /** @} */ /* End of group Configuration_of_CMSIS */
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
elessair 0:f269e3021894 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 /* ================================================================================ */
elessair 0:f269e3021894 107 /* ================ Device Specific Peripheral Section ================ */
elessair 0:f269e3021894 108 /* ================================================================================ */
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 /** @addtogroup Device_Peripheral_Registers
elessair 0:f269e3021894 112 * @{
elessair 0:f269e3021894 113 */
elessair 0:f269e3021894 114
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 /* ------------------- Start of section using anonymous unions ------------------ */
elessair 0:f269e3021894 117 #if defined(__CC_ARM)
elessair 0:f269e3021894 118 #pragma push
elessair 0:f269e3021894 119 #pragma anon_unions
elessair 0:f269e3021894 120 #elif defined(__ICCARM__)
elessair 0:f269e3021894 121 #pragma language=extended
elessair 0:f269e3021894 122 #elif defined(__GNUC__)
elessair 0:f269e3021894 123 /* anonymous unions are enabled by default */
elessair 0:f269e3021894 124 #elif defined(__TMS470__)
elessair 0:f269e3021894 125 /* anonymous unions are enabled by default */
elessair 0:f269e3021894 126 #elif defined(__TASKING__)
elessair 0:f269e3021894 127 #pragma warning 586
elessair 0:f269e3021894 128 #else
elessair 0:f269e3021894 129 #warning Not supported compiler type
elessair 0:f269e3021894 130 #endif
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 /* ================================================================================ */
elessair 0:f269e3021894 135 /* ================ I2C0 ================ */
elessair 0:f269e3021894 136 /* ================================================================================ */
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138
elessair 0:f269e3021894 139 /**
elessair 0:f269e3021894 140 * @brief I2C-bus controller (I2C0)
elessair 0:f269e3021894 141 */
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 typedef struct { /*!< I2C0 Structure */
elessair 0:f269e3021894 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
elessair 0:f269e3021894 145 this register, the corresponding bit in the I2C control register
elessair 0:f269e3021894 146 is set. Writing a zero has no effect on the corresponding bit
elessair 0:f269e3021894 147 in the I2C control register. */
elessair 0:f269e3021894 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
elessair 0:f269e3021894 149 detailed status codes that allow software to determine the next
elessair 0:f269e3021894 150 action needed. */
elessair 0:f269e3021894 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
elessair 0:f269e3021894 152 to be transmitted is written to this register. During master
elessair 0:f269e3021894 153 or slave receive mode, data that has been received may be read
elessair 0:f269e3021894 154 from this register. */
elessair 0:f269e3021894 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
elessair 0:f269e3021894 156 for operation of the I2C interface in slave mode, and is not
elessair 0:f269e3021894 157 used in master mode. The least significant bit determines whether
elessair 0:f269e3021894 158 a slave responds to the General Call address. */
elessair 0:f269e3021894 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
elessair 0:f269e3021894 160 time of the I2C clock. */
elessair 0:f269e3021894 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
elessair 0:f269e3021894 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
elessair 0:f269e3021894 163 clock frequency generated by an I2C master and certain times
elessair 0:f269e3021894 164 used in slave mode. */
elessair 0:f269e3021894 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
elessair 0:f269e3021894 166 this register, the corresponding bit in the I2C control register
elessair 0:f269e3021894 167 is cleared. Writing a zero has no effect on the corresponding
elessair 0:f269e3021894 168 bit in the I2C control register. */
elessair 0:f269e3021894 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
elessair 0:f269e3021894 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
elessair 0:f269e3021894 171 for operation of the I2C interface in slave mode, and is not
elessair 0:f269e3021894 172 used in master mode. The least significant bit determines whether
elessair 0:f269e3021894 173 a slave responds to the General Call address. */
elessair 0:f269e3021894 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
elessair 0:f269e3021894 175 for operation of the I2C interface in slave mode, and is not
elessair 0:f269e3021894 176 used in master mode. The least significant bit determines whether
elessair 0:f269e3021894 177 a slave responds to the General Call address. */
elessair 0:f269e3021894 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
elessair 0:f269e3021894 179 for operation of the I2C interface in slave mode, and is not
elessair 0:f269e3021894 180 used in master mode. The least significant bit determines whether
elessair 0:f269e3021894 181 a slave responds to the General Call address. */
elessair 0:f269e3021894 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
elessair 0:f269e3021894 183 shift register will be transferred to the DATA_BUFFER automatically
elessair 0:f269e3021894 184 after every nine bits (8 bits of data plus ACK or NACK) has
elessair 0:f269e3021894 185 been received on the bus. */
elessair 0:f269e3021894 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
elessair 0:f269e3021894 187 with I2ADR0 to determine an address match. The mask register
elessair 0:f269e3021894 188 has no effect when comparing to the General Call address (0000000). */
elessair 0:f269e3021894 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
elessair 0:f269e3021894 190 with I2ADR0 to determine an address match. The mask register
elessair 0:f269e3021894 191 has no effect when comparing to the General Call address (0000000). */
elessair 0:f269e3021894 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
elessair 0:f269e3021894 193 with I2ADR0 to determine an address match. The mask register
elessair 0:f269e3021894 194 has no effect when comparing to the General Call address (0000000). */
elessair 0:f269e3021894 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
elessair 0:f269e3021894 196 with I2ADR0 to determine an address match. The mask register
elessair 0:f269e3021894 197 has no effect when comparing to the General Call address (0000000). */
elessair 0:f269e3021894 198 } LPC_I2C0_Type;
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200
elessair 0:f269e3021894 201 /* ================================================================================ */
elessair 0:f269e3021894 202 /* ================ WWDT ================ */
elessair 0:f269e3021894 203 /* ================================================================================ */
elessair 0:f269e3021894 204
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206 /**
elessair 0:f269e3021894 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
elessair 0:f269e3021894 208 */
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 typedef struct { /*!< WWDT Structure */
elessair 0:f269e3021894 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
elessair 0:f269e3021894 212 and status of the Watchdog Timer. */
elessair 0:f269e3021894 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
elessair 0:f269e3021894 214 the time-out value. */
elessair 0:f269e3021894 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
elessair 0:f269e3021894 216 to this register reloads the Watchdog timer with the value contained
elessair 0:f269e3021894 217 in WDTC. */
elessair 0:f269e3021894 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
elessair 0:f269e3021894 219 the current value of the Watchdog timer. */
elessair 0:f269e3021894 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
elessair 0:f269e3021894 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
elessair 0:f269e3021894 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
elessair 0:f269e3021894 223 } LPC_WWDT_Type;
elessair 0:f269e3021894 224
elessair 0:f269e3021894 225
elessair 0:f269e3021894 226 /* ================================================================================ */
elessair 0:f269e3021894 227 /* ================ USART0 ================ */
elessair 0:f269e3021894 228 /* ================================================================================ */
elessair 0:f269e3021894 229
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 /**
elessair 0:f269e3021894 232 * @brief USART0 (USART0)
elessair 0:f269e3021894 233 */
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 typedef struct { /*!< USART0 Structure */
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 union {
elessair 0:f269e3021894 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
elessair 0:f269e3021894 239 value. The full divisor is used to generate a baud rate from
elessair 0:f269e3021894 240 the fractional rate divider. (DLAB=1) */
elessair 0:f269e3021894 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
elessair 0:f269e3021894 242 is written here. (DLAB=0) */
elessair 0:f269e3021894 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
elessair 0:f269e3021894 244 to be read. (DLAB=0) */
elessair 0:f269e3021894 245 };
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 union {
elessair 0:f269e3021894 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
elessair 0:f269e3021894 249 bits for the 7 potential USART interrupts. (DLAB=0) */
elessair 0:f269e3021894 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
elessair 0:f269e3021894 251 value. The full divisor is used to generate a baud rate from
elessair 0:f269e3021894 252 the fractional rate divider. (DLAB=1) */
elessair 0:f269e3021894 253 };
elessair 0:f269e3021894 254
elessair 0:f269e3021894 255 union {
elessair 0:f269e3021894 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
elessair 0:f269e3021894 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
elessair 0:f269e3021894 258 };
elessair 0:f269e3021894 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
elessair 0:f269e3021894 260 and break generation. */
elessair 0:f269e3021894 261 __IO uint32_t MCR; /*!< Modem Control Register. */
elessair 0:f269e3021894 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
elessair 0:f269e3021894 263 status, including line errors. */
elessair 0:f269e3021894 264 __I uint32_t MSR; /*!< Modem Status Register. */
elessair 0:f269e3021894 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
elessair 0:f269e3021894 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
elessair 0:f269e3021894 267 feature. */
elessair 0:f269e3021894 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
elessair 0:f269e3021894 269 control) mode. */
elessair 0:f269e3021894 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
elessair 0:f269e3021894 271 baud rate divider. */
elessair 0:f269e3021894 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
elessair 0:f269e3021894 273 each bit time. */
elessair 0:f269e3021894 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
elessair 0:f269e3021894 275 with software flow control. */
elessair 0:f269e3021894 276 __I uint32_t RESERVED0[3];
elessair 0:f269e3021894 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
elessair 0:f269e3021894 278 __I uint32_t RESERVED1;
elessair 0:f269e3021894 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
elessair 0:f269e3021894 280 the Smart Card Interface feature. */
elessair 0:f269e3021894 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
elessair 0:f269e3021894 282 aspects of RS-485/EIA-485 modes. */
elessair 0:f269e3021894 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
elessair 0:f269e3021894 284 for RS-485/EIA-485 mode. */
elessair 0:f269e3021894 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
elessair 0:f269e3021894 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
elessair 0:f269e3021894 287 } LPC_USART0_Type;
elessair 0:f269e3021894 288
elessair 0:f269e3021894 289
elessair 0:f269e3021894 290 /* ================================================================================ */
elessair 0:f269e3021894 291 /* ================ CT16B0 ================ */
elessair 0:f269e3021894 292 /* ================================================================================ */
elessair 0:f269e3021894 293
elessair 0:f269e3021894 294
elessair 0:f269e3021894 295 /**
elessair 0:f269e3021894 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
elessair 0:f269e3021894 297 */
elessair 0:f269e3021894 298
elessair 0:f269e3021894 299 typedef struct { /*!< CT16B0 Structure */
elessair 0:f269e3021894 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
elessair 0:f269e3021894 301 The IR can be read to identify which of eight possible interrupt
elessair 0:f269e3021894 302 sources are pending. */
elessair 0:f269e3021894 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
elessair 0:f269e3021894 304 Counter functions. The Timer Counter can be disabled or reset
elessair 0:f269e3021894 305 through the TCR. */
elessair 0:f269e3021894 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
elessair 0:f269e3021894 307 of PCLK. The TC is controlled through the TCR. */
elessair 0:f269e3021894 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
elessair 0:f269e3021894 309 to this value, the next clock increments the TC and clears the
elessair 0:f269e3021894 310 PC. */
elessair 0:f269e3021894 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
elessair 0:f269e3021894 312 to the value stored in PR. When the value in PR is reached,
elessair 0:f269e3021894 313 the TC is incremented and the PC is cleared. The PC is observable
elessair 0:f269e3021894 314 and controllable through the bus interface. */
elessair 0:f269e3021894 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
elessair 0:f269e3021894 316 is generated and if the TC is reset when a Match occurs. */
elessair 0:f269e3021894 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 318 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 319 time MR0 matches the TC. */
elessair 0:f269e3021894 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 321 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 322 time MR0 matches the TC. */
elessair 0:f269e3021894 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 324 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 325 time MR0 matches the TC. */
elessair 0:f269e3021894 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 327 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 328 time MR0 matches the TC. */
elessair 0:f269e3021894 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
elessair 0:f269e3021894 330 capture inputs are used to load the Capture Registers and whether
elessair 0:f269e3021894 331 or not an interrupt is generated when a capture takes place. */
elessair 0:f269e3021894 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 333 is an event on the CAP input. */
elessair 0:f269e3021894 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 335 is an event on the CAP input. */
elessair 0:f269e3021894 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 337 is an event on the CAP input. */
elessair 0:f269e3021894 338 __I uint32_t RESERVED0;
elessair 0:f269e3021894 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
elessair 0:f269e3021894 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
elessair 0:f269e3021894 341 __I uint32_t RESERVED1[12];
elessair 0:f269e3021894 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
elessair 0:f269e3021894 343 mode, and in Counter mode selects the signal and edge(s) for
elessair 0:f269e3021894 344 counting. */
elessair 0:f269e3021894 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
elessair 0:f269e3021894 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
elessair 0:f269e3021894 347 } LPC_CT16B0_Type;
elessair 0:f269e3021894 348
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 /* ================================================================================ */
elessair 0:f269e3021894 351 /* ================ CT32B0 ================ */
elessair 0:f269e3021894 352 /* ================================================================================ */
elessair 0:f269e3021894 353
elessair 0:f269e3021894 354
elessair 0:f269e3021894 355 /**
elessair 0:f269e3021894 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
elessair 0:f269e3021894 357 */
elessair 0:f269e3021894 358
elessair 0:f269e3021894 359 typedef struct { /*!< CT32B0 Structure */
elessair 0:f269e3021894 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
elessair 0:f269e3021894 361 The IR can be read to identify which of eight possible interrupt
elessair 0:f269e3021894 362 sources are pending. */
elessair 0:f269e3021894 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
elessair 0:f269e3021894 364 Counter functions. The Timer Counter can be disabled or reset
elessair 0:f269e3021894 365 through the TCR. */
elessair 0:f269e3021894 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
elessair 0:f269e3021894 367 of PCLK. The TC is controlled through the TCR. */
elessair 0:f269e3021894 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
elessair 0:f269e3021894 369 to this value, the next clock increments the TC and clears the
elessair 0:f269e3021894 370 PC. */
elessair 0:f269e3021894 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
elessair 0:f269e3021894 372 to the value stored in PR. When the value in PR is reached,
elessair 0:f269e3021894 373 the TC is incremented and the PC is cleared. The PC is observable
elessair 0:f269e3021894 374 and controllable through the bus interface. */
elessair 0:f269e3021894 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
elessair 0:f269e3021894 376 is generated and if the TC is reset when a Match occurs. */
elessair 0:f269e3021894 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 378 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 379 time MR0 matches the TC. */
elessair 0:f269e3021894 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 381 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 382 time MR0 matches the TC. */
elessair 0:f269e3021894 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 384 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 385 time MR0 matches the TC. */
elessair 0:f269e3021894 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
elessair 0:f269e3021894 387 TC, stop both the TC and PC, and/or generate an interrupt every
elessair 0:f269e3021894 388 time MR0 matches the TC. */
elessair 0:f269e3021894 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
elessair 0:f269e3021894 390 capture inputs are used to load the Capture Registers and whether
elessair 0:f269e3021894 391 or not an interrupt is generated when a capture takes place. */
elessair 0:f269e3021894 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 393 is an event on the CAP input. */
elessair 0:f269e3021894 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 395 is an event on the CAP input. */
elessair 0:f269e3021894 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
elessair 0:f269e3021894 397 is an event on the CAP input. */
elessair 0:f269e3021894 398 __I uint32_t RESERVED0;
elessair 0:f269e3021894 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
elessair 0:f269e3021894 400 and the external match pins CT32Bn_MAT[3:0]. */
elessair 0:f269e3021894 401 __I uint32_t RESERVED1[12];
elessair 0:f269e3021894 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
elessair 0:f269e3021894 403 mode, and in Counter mode selects the signal and edge(s) for
elessair 0:f269e3021894 404 counting. */
elessair 0:f269e3021894 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
elessair 0:f269e3021894 406 match pins CT32Bn_MAT[3:0]. */
elessair 0:f269e3021894 407 } LPC_CT32B0_Type;
elessair 0:f269e3021894 408
elessair 0:f269e3021894 409
elessair 0:f269e3021894 410 /* ================================================================================ */
elessair 0:f269e3021894 411 /* ================ ADC ================ */
elessair 0:f269e3021894 412 /* ================================================================================ */
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414
elessair 0:f269e3021894 415 /**
elessair 0:f269e3021894 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
elessair 0:f269e3021894 417 */
elessair 0:f269e3021894 418
elessair 0:f269e3021894 419 typedef struct { /*!< ADC Structure */
elessair 0:f269e3021894 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
elessair 0:f269e3021894 421 bits for each sequence and the A/D power-down bit. */
elessair 0:f269e3021894 422 __I uint32_t RESERVED0;
elessair 0:f269e3021894 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
elessair 0:f269e3021894 424 and channel selection for conversion sequence-A. Also specifies
elessair 0:f269e3021894 425 interrupt mode for sequence-A. */
elessair 0:f269e3021894 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
elessair 0:f269e3021894 427 and channel selection for conversion sequence-B. Also specifies
elessair 0:f269e3021894 428 interrupt mode for sequence-B. */
elessair 0:f269e3021894 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
elessair 0:f269e3021894 430 the result of the most recent A/D conversion performed under
elessair 0:f269e3021894 431 sequence-A */
elessair 0:f269e3021894 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
elessair 0:f269e3021894 433 the result of the most recent A/D conversion performed under
elessair 0:f269e3021894 434 sequence-B */
elessair 0:f269e3021894 435 __I uint32_t RESERVED1[2];
elessair 0:f269e3021894 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
elessair 0:f269e3021894 437 of the most recent conversion completed on channel 0. */
elessair 0:f269e3021894 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
elessair 0:f269e3021894 439 level for automatic threshold comparison for any channels linked
elessair 0:f269e3021894 440 to threshold pair 0. */
elessair 0:f269e3021894 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
elessair 0:f269e3021894 442 level for automatic threshold comparison for any channels linked
elessair 0:f269e3021894 443 to threshold pair 1. */
elessair 0:f269e3021894 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
elessair 0:f269e3021894 445 level for automatic threshold comparison for any channels linked
elessair 0:f269e3021894 446 to threshold pair 0. */
elessair 0:f269e3021894 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
elessair 0:f269e3021894 448 level for automatic threshold comparison for any channels linked
elessair 0:f269e3021894 449 to threshold pair 1. */
elessair 0:f269e3021894 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
elessair 0:f269e3021894 451 threshold compare registers are to be used for each channel */
elessair 0:f269e3021894 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
elessair 0:f269e3021894 453 bits that enable the sequence-A, sequence-B, threshold compare
elessair 0:f269e3021894 454 and data overrun interrupts to be generated. */
elessair 0:f269e3021894 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
elessair 0:f269e3021894 456 and the individual component overrun and threshold-compare flags.
elessair 0:f269e3021894 457 (The overrun bits replicate information stored in the result
elessair 0:f269e3021894 458 registers). */
elessair 0:f269e3021894 459 __IO uint32_t TRM; /*!< ADC trim register. */
elessair 0:f269e3021894 460 } LPC_ADC_Type;
elessair 0:f269e3021894 461
elessair 0:f269e3021894 462
elessair 0:f269e3021894 463 /* ================================================================================ */
elessair 0:f269e3021894 464 /* ================ RTC ================ */
elessair 0:f269e3021894 465 /* ================================================================================ */
elessair 0:f269e3021894 466
elessair 0:f269e3021894 467
elessair 0:f269e3021894 468 /**
elessair 0:f269e3021894 469 * @brief Real-Time Clock (RTC) (RTC)
elessair 0:f269e3021894 470 */
elessair 0:f269e3021894 471
elessair 0:f269e3021894 472 typedef struct { /*!< RTC Structure */
elessair 0:f269e3021894 473 __IO uint32_t CTRL; /*!< RTC control register */
elessair 0:f269e3021894 474 __IO uint32_t MATCH; /*!< RTC match register */
elessair 0:f269e3021894 475 __IO uint32_t COUNT; /*!< RTC counter register */
elessair 0:f269e3021894 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
elessair 0:f269e3021894 477 } LPC_RTC_Type;
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479
elessair 0:f269e3021894 480 /* ================================================================================ */
elessair 0:f269e3021894 481 /* ================ DMATRIGMUX ================ */
elessair 0:f269e3021894 482 /* ================================================================================ */
elessair 0:f269e3021894 483
elessair 0:f269e3021894 484
elessair 0:f269e3021894 485 /**
elessair 0:f269e3021894 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
elessair 0:f269e3021894 487 */
elessair 0:f269e3021894 488
elessair 0:f269e3021894 489 typedef struct { /*!< DMATRIGMUX Structure */
elessair 0:f269e3021894 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
elessair 0:f269e3021894 491 } LPC_DMATRIGMUX_Type;
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493
elessair 0:f269e3021894 494 /* ================================================================================ */
elessair 0:f269e3021894 495 /* ================ PMU ================ */
elessair 0:f269e3021894 496 /* ================================================================================ */
elessair 0:f269e3021894 497
elessair 0:f269e3021894 498
elessair 0:f269e3021894 499 /**
elessair 0:f269e3021894 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
elessair 0:f269e3021894 501 */
elessair 0:f269e3021894 502
elessair 0:f269e3021894 503 typedef struct { /*!< PMU Structure */
elessair 0:f269e3021894 504 __IO uint32_t PCON; /*!< Power control register */
elessair 0:f269e3021894 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
elessair 0:f269e3021894 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
elessair 0:f269e3021894 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
elessair 0:f269e3021894 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
elessair 0:f269e3021894 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
elessair 0:f269e3021894 510 } LPC_PMU_Type;
elessair 0:f269e3021894 511
elessair 0:f269e3021894 512
elessair 0:f269e3021894 513 /* ================================================================================ */
elessair 0:f269e3021894 514 /* ================ FLASHCTRL ================ */
elessair 0:f269e3021894 515 /* ================================================================================ */
elessair 0:f269e3021894 516
elessair 0:f269e3021894 517
elessair 0:f269e3021894 518 /**
elessair 0:f269e3021894 519 * @brief Flash controller (FLASHCTRL)
elessair 0:f269e3021894 520 */
elessair 0:f269e3021894 521
elessair 0:f269e3021894 522 typedef struct { /*!< FLASHCTRL Structure */
elessair 0:f269e3021894 523 __I uint32_t RESERVED0[4];
elessair 0:f269e3021894 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
elessair 0:f269e3021894 525 __I uint32_t RESERVED1[3];
elessair 0:f269e3021894 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
elessair 0:f269e3021894 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
elessair 0:f269e3021894 528 __I uint32_t RESERVED2;
elessair 0:f269e3021894 529 __I uint32_t FMSW0; /*!< Signature Word */
elessair 0:f269e3021894 530 } LPC_FLASHCTRL_Type;
elessair 0:f269e3021894 531
elessair 0:f269e3021894 532
elessair 0:f269e3021894 533 /* ================================================================================ */
elessair 0:f269e3021894 534 /* ================ SSP0 ================ */
elessair 0:f269e3021894 535 /* ================================================================================ */
elessair 0:f269e3021894 536
elessair 0:f269e3021894 537
elessair 0:f269e3021894 538 /**
elessair 0:f269e3021894 539 * @brief SSP/SPI (SSP0)
elessair 0:f269e3021894 540 */
elessair 0:f269e3021894 541
elessair 0:f269e3021894 542 typedef struct { /*!< SSP0 Structure */
elessair 0:f269e3021894 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
elessair 0:f269e3021894 544 and data size. */
elessair 0:f269e3021894 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
elessair 0:f269e3021894 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
elessair 0:f269e3021894 547 the receive FIFO. */
elessair 0:f269e3021894 548 __I uint32_t SR; /*!< Status Register */
elessair 0:f269e3021894 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
elessair 0:f269e3021894 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
elessair 0:f269e3021894 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
elessair 0:f269e3021894 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
elessair 0:f269e3021894 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
elessair 0:f269e3021894 554 } LPC_SSP0_Type;
elessair 0:f269e3021894 555
elessair 0:f269e3021894 556
elessair 0:f269e3021894 557 /* ================================================================================ */
elessair 0:f269e3021894 558 /* ================ IOCON ================ */
elessair 0:f269e3021894 559 /* ================================================================================ */
elessair 0:f269e3021894 560
elessair 0:f269e3021894 561
elessair 0:f269e3021894 562 /**
elessair 0:f269e3021894 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
elessair 0:f269e3021894 564 */
elessair 0:f269e3021894 565
elessair 0:f269e3021894 566 typedef struct { /*!< IOCON Structure */
elessair 0:f269e3021894 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
elessair 0:f269e3021894 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
elessair 0:f269e3021894 623 __I uint32_t RESERVED0[4];
elessair 0:f269e3021894 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 626 __I uint32_t RESERVED1;
elessair 0:f269e3021894 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
elessair 0:f269e3021894 649 } LPC_IOCON_Type;
elessair 0:f269e3021894 650
elessair 0:f269e3021894 651
elessair 0:f269e3021894 652 /* ================================================================================ */
elessair 0:f269e3021894 653 /* ================ SYSCON ================ */
elessair 0:f269e3021894 654 /* ================================================================================ */
elessair 0:f269e3021894 655
elessair 0:f269e3021894 656
elessair 0:f269e3021894 657 /**
elessair 0:f269e3021894 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
elessair 0:f269e3021894 659 */
elessair 0:f269e3021894 660
elessair 0:f269e3021894 661 typedef struct { /*!< SYSCON Structure */
elessair 0:f269e3021894 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
elessair 0:f269e3021894 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
elessair 0:f269e3021894 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
elessair 0:f269e3021894 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
elessair 0:f269e3021894 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
elessair 0:f269e3021894 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
elessair 0:f269e3021894 668 __I uint32_t RESERVED0;
elessair 0:f269e3021894 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
elessair 0:f269e3021894 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
elessair 0:f269e3021894 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
elessair 0:f269e3021894 672 __I uint32_t RESERVED1[2];
elessair 0:f269e3021894 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
elessair 0:f269e3021894 674 __I uint32_t RESERVED2[3];
elessair 0:f269e3021894 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
elessair 0:f269e3021894 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
elessair 0:f269e3021894 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
elessair 0:f269e3021894 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
elessair 0:f269e3021894 679 __I uint32_t RESERVED3[8];
elessair 0:f269e3021894 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
elessair 0:f269e3021894 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
elessair 0:f269e3021894 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
elessair 0:f269e3021894 683 __I uint32_t RESERVED4;
elessair 0:f269e3021894 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
elessair 0:f269e3021894 685 __I uint32_t RESERVED5[4];
elessair 0:f269e3021894 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
elessair 0:f269e3021894 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
elessair 0:f269e3021894 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
elessair 0:f269e3021894 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
elessair 0:f269e3021894 690 of USART1 to USART4 */
elessair 0:f269e3021894 691 __I uint32_t RESERVED6[7];
elessair 0:f269e3021894 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
elessair 0:f269e3021894 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
elessair 0:f269e3021894 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
elessair 0:f269e3021894 695 __I uint32_t RESERVED7[5];
elessair 0:f269e3021894 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
elessair 0:f269e3021894 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
elessair 0:f269e3021894 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
elessair 0:f269e3021894 699 __I uint32_t RESERVED8;
elessair 0:f269e3021894 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
elessair 0:f269e3021894 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
elessair 0:f269e3021894 702 __I uint32_t RESERVED9;
elessair 0:f269e3021894 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
elessair 0:f269e3021894 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
elessair 0:f269e3021894 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
elessair 0:f269e3021894 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
elessair 0:f269e3021894 707 __I uint32_t RESERVED10[10];
elessair 0:f269e3021894 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
elessair 0:f269e3021894 709 filter */
elessair 0:f269e3021894 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
elessair 0:f269e3021894 711 filter */
elessair 0:f269e3021894 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
elessair 0:f269e3021894 713 filter */
elessair 0:f269e3021894 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
elessair 0:f269e3021894 715 filter */
elessair 0:f269e3021894 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
elessair 0:f269e3021894 717 filter */
elessair 0:f269e3021894 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
elessair 0:f269e3021894 719 filter */
elessair 0:f269e3021894 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
elessair 0:f269e3021894 721 filter */
elessair 0:f269e3021894 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
elessair 0:f269e3021894 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
elessair 0:f269e3021894 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
elessair 0:f269e3021894 725 __I uint32_t RESERVED11[5];
elessair 0:f269e3021894 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
elessair 0:f269e3021894 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
elessair 0:f269e3021894 728 union {
elessair 0:f269e3021894 729 __IO uint32_t PINTSEL[8];
elessair 0:f269e3021894 730 struct {
elessair 0:f269e3021894 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
elessair 0:f269e3021894 739 };
elessair 0:f269e3021894 740 };
elessair 0:f269e3021894 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
elessair 0:f269e3021894 742 __I uint32_t USBCLKST; /*!< USB clock status */
elessair 0:f269e3021894 743 __I uint32_t RESERVED12[25];
elessair 0:f269e3021894 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
elessair 0:f269e3021894 745 __I uint32_t RESERVED13[3];
elessair 0:f269e3021894 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
elessair 0:f269e3021894 747 __I uint32_t RESERVED14[6];
elessair 0:f269e3021894 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
elessair 0:f269e3021894 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
elessair 0:f269e3021894 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
elessair 0:f269e3021894 751 __I uint32_t RESERVED15[110];
elessair 0:f269e3021894 752 __I uint32_t DEVICE_ID; /*!< Device ID */
elessair 0:f269e3021894 753 } LPC_SYSCON_Type;
elessair 0:f269e3021894 754
elessair 0:f269e3021894 755
elessair 0:f269e3021894 756 /* ================================================================================ */
elessair 0:f269e3021894 757 /* ================ USART4 ================ */
elessair 0:f269e3021894 758 /* ================================================================================ */
elessair 0:f269e3021894 759
elessair 0:f269e3021894 760
elessair 0:f269e3021894 761 /**
elessair 0:f269e3021894 762 * @brief USART4 (USART4)
elessair 0:f269e3021894 763 */
elessair 0:f269e3021894 764
elessair 0:f269e3021894 765 typedef struct { /*!< USART4 Structure */
elessair 0:f269e3021894 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
elessair 0:f269e3021894 767 that typically are not changed during operation. */
elessair 0:f269e3021894 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
elessair 0:f269e3021894 769 likely to change during operation. */
elessair 0:f269e3021894 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
elessair 0:f269e3021894 771 here. Writing ones clears some bits in the register. Some bits
elessair 0:f269e3021894 772 can be cleared by writing a 1 to them. */
elessair 0:f269e3021894 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
elessair 0:f269e3021894 774 interrupt enable bit for each potential USART interrupt. A complete
elessair 0:f269e3021894 775 value may be read from this register. Writing a 1 to any implemented
elessair 0:f269e3021894 776 bit position causes that bit to be set. */
elessair 0:f269e3021894 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
elessair 0:f269e3021894 778 of bits in the INTENSET register. Writing a 1 to any implemented
elessair 0:f269e3021894 779 bit position causes the corresponding bit to be cleared. */
elessair 0:f269e3021894 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
elessair 0:f269e3021894 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
elessair 0:f269e3021894 782 received with the current USART receive status. Allows DMA or
elessair 0:f269e3021894 783 software to recover incoming data and status together. */
elessair 0:f269e3021894 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
elessair 0:f269e3021894 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
elessair 0:f269e3021894 786 value. */
elessair 0:f269e3021894 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
elessair 0:f269e3021894 788 enabled. */
elessair 0:f269e3021894 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
elessair 0:f269e3021894 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
elessair 0:f269e3021894 791 } LPC_USART4_Type;
elessair 0:f269e3021894 792
elessair 0:f269e3021894 793
elessair 0:f269e3021894 794 /* ================================================================================ */
elessair 0:f269e3021894 795 /* ================ GINT0 ================ */
elessair 0:f269e3021894 796 /* ================================================================================ */
elessair 0:f269e3021894 797
elessair 0:f269e3021894 798
elessair 0:f269e3021894 799 /**
elessair 0:f269e3021894 800 * @brief GPIO group interrupt 0 (GINT0)
elessair 0:f269e3021894 801 */
elessair 0:f269e3021894 802
elessair 0:f269e3021894 803 typedef struct { /*!< GINT0 Structure */
elessair 0:f269e3021894 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
elessair 0:f269e3021894 805 __I uint32_t RESERVED0[7];
elessair 0:f269e3021894 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
elessair 0:f269e3021894 807 __I uint32_t RESERVED1[5];
elessair 0:f269e3021894 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
elessair 0:f269e3021894 809 } LPC_GINT0_Type;
elessair 0:f269e3021894 810
elessair 0:f269e3021894 811
elessair 0:f269e3021894 812 /* ================================================================================ */
elessair 0:f269e3021894 813 /* ================ USB ================ */
elessair 0:f269e3021894 814 /* ================================================================================ */
elessair 0:f269e3021894 815
elessair 0:f269e3021894 816
elessair 0:f269e3021894 817 /**
elessair 0:f269e3021894 818 * @brief USB device controller (USB)
elessair 0:f269e3021894 819 */
elessair 0:f269e3021894 820
elessair 0:f269e3021894 821 typedef struct { /*!< USB Structure */
elessair 0:f269e3021894 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
elessair 0:f269e3021894 823 __IO uint32_t INFO; /*!< USB Info register */
elessair 0:f269e3021894 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
elessair 0:f269e3021894 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
elessair 0:f269e3021894 826 __IO uint32_t LPM; /*!< Link Power Management register */
elessair 0:f269e3021894 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
elessair 0:f269e3021894 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
elessair 0:f269e3021894 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
elessair 0:f269e3021894 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
elessair 0:f269e3021894 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
elessair 0:f269e3021894 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
elessair 0:f269e3021894 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
elessair 0:f269e3021894 834 __I uint32_t RESERVED0;
elessair 0:f269e3021894 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
elessair 0:f269e3021894 836 } LPC_USB_Type;
elessair 0:f269e3021894 837
elessair 0:f269e3021894 838
elessair 0:f269e3021894 839 /* ================================================================================ */
elessair 0:f269e3021894 840 /* ================ CRC ================ */
elessair 0:f269e3021894 841 /* ================================================================================ */
elessair 0:f269e3021894 842
elessair 0:f269e3021894 843
elessair 0:f269e3021894 844 /**
elessair 0:f269e3021894 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
elessair 0:f269e3021894 846 */
elessair 0:f269e3021894 847
elessair 0:f269e3021894 848 typedef struct { /*!< CRC Structure */
elessair 0:f269e3021894 849 __IO uint32_t MODE; /*!< CRC mode register */
elessair 0:f269e3021894 850 __IO uint32_t SEED; /*!< CRC seed register */
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 union {
elessair 0:f269e3021894 853 __O uint32_t WR_DATA; /*!< CRC data register */
elessair 0:f269e3021894 854 __I uint32_t SUM; /*!< CRC checksum register */
elessair 0:f269e3021894 855 };
elessair 0:f269e3021894 856 } LPC_CRC_Type;
elessair 0:f269e3021894 857
elessair 0:f269e3021894 858
elessair 0:f269e3021894 859 /* ================================================================================ */
elessair 0:f269e3021894 860 /* ================ DMA ================ */
elessair 0:f269e3021894 861 /* ================================================================================ */
elessair 0:f269e3021894 862
elessair 0:f269e3021894 863
elessair 0:f269e3021894 864 /**
elessair 0:f269e3021894 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
elessair 0:f269e3021894 866 */
elessair 0:f269e3021894 867
elessair 0:f269e3021894 868 typedef struct { /*!< DMA Structure */
elessair 0:f269e3021894 869 __IO uint32_t CTRL; /*!< DMA control. */
elessair 0:f269e3021894 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
elessair 0:f269e3021894 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
elessair 0:f269e3021894 872 __I uint32_t RESERVED0[5];
elessair 0:f269e3021894 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
elessair 0:f269e3021894 874 __I uint32_t RESERVED1;
elessair 0:f269e3021894 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
elessair 0:f269e3021894 876 __I uint32_t RESERVED2;
elessair 0:f269e3021894 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
elessair 0:f269e3021894 878 __I uint32_t RESERVED3;
elessair 0:f269e3021894 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
elessair 0:f269e3021894 880 __I uint32_t RESERVED4;
elessair 0:f269e3021894 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
elessair 0:f269e3021894 882 __I uint32_t RESERVED5;
elessair 0:f269e3021894 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
elessair 0:f269e3021894 884 __I uint32_t RESERVED6;
elessair 0:f269e3021894 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
elessair 0:f269e3021894 886 __I uint32_t RESERVED7;
elessair 0:f269e3021894 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
elessair 0:f269e3021894 888 __I uint32_t RESERVED8;
elessair 0:f269e3021894 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
elessair 0:f269e3021894 890 __I uint32_t RESERVED9;
elessair 0:f269e3021894 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
elessair 0:f269e3021894 892 __I uint32_t RESERVED10;
elessair 0:f269e3021894 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
elessair 0:f269e3021894 894 __I uint32_t RESERVED11;
elessair 0:f269e3021894 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
elessair 0:f269e3021894 896 __I uint32_t RESERVED12[225];
elessair 0:f269e3021894 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 900 __I uint32_t RESERVED13;
elessair 0:f269e3021894 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 904 __I uint32_t RESERVED14;
elessair 0:f269e3021894 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 908 __I uint32_t RESERVED15;
elessair 0:f269e3021894 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 912 __I uint32_t RESERVED16;
elessair 0:f269e3021894 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 916 __I uint32_t RESERVED17;
elessair 0:f269e3021894 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 920 __I uint32_t RESERVED18;
elessair 0:f269e3021894 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 924 __I uint32_t RESERVED19;
elessair 0:f269e3021894 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 928 __I uint32_t RESERVED20;
elessair 0:f269e3021894 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 932 __I uint32_t RESERVED21;
elessair 0:f269e3021894 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 936 __I uint32_t RESERVED22;
elessair 0:f269e3021894 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 940 __I uint32_t RESERVED23;
elessair 0:f269e3021894 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 944 __I uint32_t RESERVED24;
elessair 0:f269e3021894 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 948 __I uint32_t RESERVED25;
elessair 0:f269e3021894 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 952 __I uint32_t RESERVED26;
elessair 0:f269e3021894 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 956 __I uint32_t RESERVED27;
elessair 0:f269e3021894 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
elessair 0:f269e3021894 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
elessair 0:f269e3021894 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
elessair 0:f269e3021894 960 } LPC_DMA_Type;
elessair 0:f269e3021894 961
elessair 0:f269e3021894 962
elessair 0:f269e3021894 963 /* ================================================================================ */
elessair 0:f269e3021894 964 /* ================ SCT0 ================ */
elessair 0:f269e3021894 965 /* ================================================================================ */
elessair 0:f269e3021894 966
elessair 0:f269e3021894 967
elessair 0:f269e3021894 968 /**
elessair 0:f269e3021894 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
elessair 0:f269e3021894 970 */
elessair 0:f269e3021894 971
elessair 0:f269e3021894 972 typedef struct { /*!< SCT0 Structure */
elessair 0:f269e3021894 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
elessair 0:f269e3021894 974 __IO uint32_t CTRL; /*!< SCT control register */
elessair 0:f269e3021894 975 __IO uint32_t LIMIT; /*!< SCT limit register */
elessair 0:f269e3021894 976 __IO uint32_t HALT; /*!< SCT halt condition register */
elessair 0:f269e3021894 977 __IO uint32_t STOP; /*!< SCT stop condition register */
elessair 0:f269e3021894 978 __IO uint32_t START; /*!< SCT start condition register */
elessair 0:f269e3021894 979 __I uint32_t RESERVED0[10];
elessair 0:f269e3021894 980 __IO uint32_t COUNT; /*!< SCT counter register */
elessair 0:f269e3021894 981 __IO uint32_t STATE; /*!< SCT state register */
elessair 0:f269e3021894 982 __I uint32_t INPUT; /*!< SCT input register */
elessair 0:f269e3021894 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
elessair 0:f269e3021894 984 __IO uint32_t OUTPUT; /*!< SCT output register */
elessair 0:f269e3021894 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
elessair 0:f269e3021894 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
elessair 0:f269e3021894 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
elessair 0:f269e3021894 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
elessair 0:f269e3021894 989 __I uint32_t RESERVED1[35];
elessair 0:f269e3021894 990 __IO uint32_t EVEN; /*!< SCT event enable register */
elessair 0:f269e3021894 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
elessair 0:f269e3021894 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
elessair 0:f269e3021894 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
elessair 0:f269e3021894 994
elessair 0:f269e3021894 995 union {
elessair 0:f269e3021894 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
elessair 0:f269e3021894 997 = 1 */
elessair 0:f269e3021894 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
elessair 0:f269e3021894 999 REGMODE4 = 0 */
elessair 0:f269e3021894 1000 };
elessair 0:f269e3021894 1001
elessair 0:f269e3021894 1002 union {
elessair 0:f269e3021894 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
elessair 0:f269e3021894 1004 = 1 */
elessair 0:f269e3021894 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
elessair 0:f269e3021894 1006 REGMODE4 = 0 */
elessair 0:f269e3021894 1007 };
elessair 0:f269e3021894 1008
elessair 0:f269e3021894 1009 union {
elessair 0:f269e3021894 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
elessair 0:f269e3021894 1011 REGMODE4 = 0 */
elessair 0:f269e3021894 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
elessair 0:f269e3021894 1013 = 1 */
elessair 0:f269e3021894 1014 };
elessair 0:f269e3021894 1015
elessair 0:f269e3021894 1016 union {
elessair 0:f269e3021894 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
elessair 0:f269e3021894 1018 = 1 */
elessair 0:f269e3021894 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
elessair 0:f269e3021894 1020 REGMODE4 = 0 */
elessair 0:f269e3021894 1021 };
elessair 0:f269e3021894 1022
elessair 0:f269e3021894 1023 union {
elessair 0:f269e3021894 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
elessair 0:f269e3021894 1025 = 1 */
elessair 0:f269e3021894 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
elessair 0:f269e3021894 1027 REGMODE4 = 0 */
elessair 0:f269e3021894 1028 };
elessair 0:f269e3021894 1029 __I uint32_t RESERVED2[59];
elessair 0:f269e3021894 1030
elessair 0:f269e3021894 1031 union {
elessair 0:f269e3021894 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
elessair 0:f269e3021894 1033 = 1 */
elessair 0:f269e3021894 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
elessair 0:f269e3021894 1035 = 0 */
elessair 0:f269e3021894 1036 };
elessair 0:f269e3021894 1037
elessair 0:f269e3021894 1038 union {
elessair 0:f269e3021894 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
elessair 0:f269e3021894 1040 = 0 */
elessair 0:f269e3021894 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
elessair 0:f269e3021894 1042 = 1 */
elessair 0:f269e3021894 1043 };
elessair 0:f269e3021894 1044
elessair 0:f269e3021894 1045 union {
elessair 0:f269e3021894 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
elessair 0:f269e3021894 1047 = 0 */
elessair 0:f269e3021894 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
elessair 0:f269e3021894 1049 = 1 */
elessair 0:f269e3021894 1050 };
elessair 0:f269e3021894 1051
elessair 0:f269e3021894 1052 union {
elessair 0:f269e3021894 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
elessair 0:f269e3021894 1054 = 1 */
elessair 0:f269e3021894 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
elessair 0:f269e3021894 1056 = 0 */
elessair 0:f269e3021894 1057 };
elessair 0:f269e3021894 1058
elessair 0:f269e3021894 1059 union {
elessair 0:f269e3021894 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
elessair 0:f269e3021894 1061 = 1 */
elessair 0:f269e3021894 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
elessair 0:f269e3021894 1063 = 0 */
elessair 0:f269e3021894 1064 };
elessair 0:f269e3021894 1065 __I uint32_t RESERVED3[59];
elessair 0:f269e3021894 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
elessair 0:f269e3021894 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
elessair 0:f269e3021894 1078 __I uint32_t RESERVED4[116];
elessair 0:f269e3021894 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
elessair 0:f269e3021894 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
elessair 0:f269e3021894 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
elessair 0:f269e3021894 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
elessair 0:f269e3021894 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
elessair 0:f269e3021894 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
elessair 0:f269e3021894 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
elessair 0:f269e3021894 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
elessair 0:f269e3021894 1087 } LPC_SCT0_Type;
elessair 0:f269e3021894 1088
elessair 0:f269e3021894 1089
elessair 0:f269e3021894 1090 /* ================================================================================ */
elessair 0:f269e3021894 1091 /* ================ GPIO_PORT ================ */
elessair 0:f269e3021894 1092 /* ================================================================================ */
elessair 0:f269e3021894 1093
elessair 0:f269e3021894 1094
elessair 0:f269e3021894 1095 /**
elessair 0:f269e3021894 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
elessair 0:f269e3021894 1097 */
elessair 0:f269e3021894 1098
elessair 0:f269e3021894 1099 typedef struct { /*!< GPIO_PORT Structure */
elessair 0:f269e3021894 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
elessair 0:f269e3021894 1101 __I uint32_t RESERVED0[42];
elessair 0:f269e3021894 1102 __IO uint32_t W[88]; /*!< Word pin registers */
elessair 0:f269e3021894 1103 __I uint32_t RESERVED1[1896];
elessair 0:f269e3021894 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
elessair 0:f269e3021894 1105 __I uint32_t RESERVED2[29];
elessair 0:f269e3021894 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
elessair 0:f269e3021894 1107 __I uint32_t RESERVED3[29];
elessair 0:f269e3021894 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
elessair 0:f269e3021894 1109 __I uint32_t RESERVED4[29];
elessair 0:f269e3021894 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
elessair 0:f269e3021894 1111 __I uint32_t RESERVED5[29];
elessair 0:f269e3021894 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
elessair 0:f269e3021894 1113 __I uint32_t RESERVED6[29];
elessair 0:f269e3021894 1114 __O uint32_t CLR[3]; /*!< Clear port */
elessair 0:f269e3021894 1115 __I uint32_t RESERVED7[29];
elessair 0:f269e3021894 1116 __O uint32_t NOT[3]; /*!< Toggle port */
elessair 0:f269e3021894 1117 } LPC_GPIO_PORT_Type;
elessair 0:f269e3021894 1118
elessair 0:f269e3021894 1119
elessair 0:f269e3021894 1120 /* ================================================================================ */
elessair 0:f269e3021894 1121 /* ================ PINT ================ */
elessair 0:f269e3021894 1122 /* ================================================================================ */
elessair 0:f269e3021894 1123
elessair 0:f269e3021894 1124
elessair 0:f269e3021894 1125 /**
elessair 0:f269e3021894 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
elessair 0:f269e3021894 1127 */
elessair 0:f269e3021894 1128
elessair 0:f269e3021894 1129 typedef struct { /*!< PINT Structure */
elessair 0:f269e3021894 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
elessair 0:f269e3021894 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
elessair 0:f269e3021894 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
elessair 0:f269e3021894 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
elessair 0:f269e3021894 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
elessair 0:f269e3021894 1135 register */
elessair 0:f269e3021894 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
elessair 0:f269e3021894 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
elessair 0:f269e3021894 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
elessair 0:f269e3021894 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
elessair 0:f269e3021894 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
elessair 0:f269e3021894 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
elessair 0:f269e3021894 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
elessair 0:f269e3021894 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
elessair 0:f269e3021894 1144 } LPC_PINT_Type;
elessair 0:f269e3021894 1145
elessair 0:f269e3021894 1146
elessair 0:f269e3021894 1147 /* -------------------- End of section using anonymous unions ------------------- */
elessair 0:f269e3021894 1148 #if defined(__CC_ARM)
elessair 0:f269e3021894 1149 #pragma pop
elessair 0:f269e3021894 1150 #elif defined(__ICCARM__)
elessair 0:f269e3021894 1151 /* leave anonymous unions enabled */
elessair 0:f269e3021894 1152 #elif defined(__GNUC__)
elessair 0:f269e3021894 1153 /* anonymous unions are enabled by default */
elessair 0:f269e3021894 1154 #elif defined(__TMS470__)
elessair 0:f269e3021894 1155 /* anonymous unions are enabled by default */
elessair 0:f269e3021894 1156 #elif defined(__TASKING__)
elessair 0:f269e3021894 1157 #pragma warning restore
elessair 0:f269e3021894 1158 #else
elessair 0:f269e3021894 1159 #warning Not supported compiler type
elessair 0:f269e3021894 1160 #endif
elessair 0:f269e3021894 1161
elessair 0:f269e3021894 1162
elessair 0:f269e3021894 1163
elessair 0:f269e3021894 1164
elessair 0:f269e3021894 1165 /* ================================================================================ */
elessair 0:f269e3021894 1166 /* ================ Peripheral memory map ================ */
elessair 0:f269e3021894 1167 /* ================================================================================ */
elessair 0:f269e3021894 1168
elessair 0:f269e3021894 1169 #define LPC_I2C0_BASE 0x40000000UL
elessair 0:f269e3021894 1170 #define LPC_WWDT_BASE 0x40004000UL
elessair 0:f269e3021894 1171 #define LPC_USART0_BASE 0x40008000UL
elessair 0:f269e3021894 1172 #define LPC_CT16B0_BASE 0x4000C000UL
elessair 0:f269e3021894 1173 #define LPC_CT16B1_BASE 0x40010000UL
elessair 0:f269e3021894 1174 #define LPC_CT32B0_BASE 0x40014000UL
elessair 0:f269e3021894 1175 #define LPC_CT32B1_BASE 0x40018000UL
elessair 0:f269e3021894 1176 #define LPC_ADC_BASE 0x4001C000UL
elessair 0:f269e3021894 1177 #define LPC_I2C1_BASE 0x40020000UL
elessair 0:f269e3021894 1178 #define LPC_RTC_BASE 0x40024000UL
elessair 0:f269e3021894 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
elessair 0:f269e3021894 1180 #define LPC_PMU_BASE 0x40038000UL
elessair 0:f269e3021894 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
elessair 0:f269e3021894 1182 #define LPC_SSP0_BASE 0x40040000UL
elessair 0:f269e3021894 1183 #define LPC_IOCON_BASE 0x40044000UL
elessair 0:f269e3021894 1184 #define LPC_SYSCON_BASE 0x40048000UL
elessair 0:f269e3021894 1185 #define LPC_USART4_BASE 0x4004C000UL
elessair 0:f269e3021894 1186 #define LPC_SSP1_BASE 0x40058000UL
elessair 0:f269e3021894 1187 #define LPC_GINT0_BASE 0x4005C000UL
elessair 0:f269e3021894 1188 #define LPC_GINT1_BASE 0x40060000UL
elessair 0:f269e3021894 1189 #define LPC_USART1_BASE 0x4006C000UL
elessair 0:f269e3021894 1190 #define LPC_USART2_BASE 0x40070000UL
elessair 0:f269e3021894 1191 #define LPC_USART3_BASE 0x40074000UL
elessair 0:f269e3021894 1192 #define LPC_USB_BASE 0x40080000UL
elessair 0:f269e3021894 1193 #define LPC_CRC_BASE 0x50000000UL
elessair 0:f269e3021894 1194 #define LPC_DMA_BASE 0x50004000UL
elessair 0:f269e3021894 1195 #define LPC_SCT0_BASE 0x5000C000UL
elessair 0:f269e3021894 1196 #define LPC_SCT1_BASE 0x5000E000UL
elessair 0:f269e3021894 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
elessair 0:f269e3021894 1198 #define LPC_PINT_BASE 0xA0004000UL
elessair 0:f269e3021894 1199
elessair 0:f269e3021894 1200
elessair 0:f269e3021894 1201 /* ================================================================================ */
elessair 0:f269e3021894 1202 /* ================ Peripheral declaration ================ */
elessair 0:f269e3021894 1203 /* ================================================================================ */
elessair 0:f269e3021894 1204
elessair 0:f269e3021894 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
elessair 0:f269e3021894 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
elessair 0:f269e3021894 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
elessair 0:f269e3021894 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
elessair 0:f269e3021894 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
elessair 0:f269e3021894 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
elessair 0:f269e3021894 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
elessair 0:f269e3021894 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
elessair 0:f269e3021894 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
elessair 0:f269e3021894 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
elessair 0:f269e3021894 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
elessair 0:f269e3021894 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
elessair 0:f269e3021894 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
elessair 0:f269e3021894 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
elessair 0:f269e3021894 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
elessair 0:f269e3021894 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
elessair 0:f269e3021894 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
elessair 0:f269e3021894 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
elessair 0:f269e3021894 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
elessair 0:f269e3021894 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
elessair 0:f269e3021894 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
elessair 0:f269e3021894 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
elessair 0:f269e3021894 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
elessair 0:f269e3021894 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
elessair 0:f269e3021894 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
elessair 0:f269e3021894 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
elessair 0:f269e3021894 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
elessair 0:f269e3021894 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
elessair 0:f269e3021894 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
elessair 0:f269e3021894 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
elessair 0:f269e3021894 1235
elessair 0:f269e3021894 1236
elessair 0:f269e3021894 1237 /** @} */ /* End of group Device_Peripheral_Registers */
elessair 0:f269e3021894 1238 /** @} */ /* End of group LPC11U6x */
elessair 0:f269e3021894 1239 /** @} */ /* End of group (null) */
elessair 0:f269e3021894 1240
elessair 0:f269e3021894 1241 #ifdef __cplusplus
elessair 0:f269e3021894 1242 }
elessair 0:f269e3021894 1243 #endif
elessair 0:f269e3021894 1244
elessair 0:f269e3021894 1245
elessair 0:f269e3021894 1246 #endif /* LPC11U6x_H */
elessair 0:f269e3021894 1247