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cmsis/core_cm0plus.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_cm0plus.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
elessair 0:f269e3021894 4 * @version V4.10
elessair 0:f269e3021894 5 * @date 18. March 2015
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #if defined ( __ICCARM__ )
elessair 0:f269e3021894 39 #pragma system_include /* treat file as system include file for MISRA check */
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #ifndef __CORE_CM0PLUS_H_GENERIC
elessair 0:f269e3021894 43 #define __CORE_CM0PLUS_H_GENERIC
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 #ifdef __cplusplus
elessair 0:f269e3021894 46 extern "C" {
elessair 0:f269e3021894 47 #endif
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
elessair 0:f269e3021894 50 CMSIS violates the following MISRA-C:2004 rules:
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 \li Required Rule 8.5, object/function definition in header file.<br>
elessair 0:f269e3021894 53 Function definitions in header files are used to allow 'inlining'.
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
elessair 0:f269e3021894 56 Unions are used for effective representation of core registers.
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
elessair 0:f269e3021894 59 Function-like macros are used to allow more efficient code.
elessair 0:f269e3021894 60 */
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 /*******************************************************************************
elessair 0:f269e3021894 64 * CMSIS definitions
elessair 0:f269e3021894 65 ******************************************************************************/
elessair 0:f269e3021894 66 /** \ingroup Cortex-M0+
elessair 0:f269e3021894 67 @{
elessair 0:f269e3021894 68 */
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 /* CMSIS CM0P definitions */
elessair 0:f269e3021894 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
elessair 0:f269e3021894 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
elessair 0:f269e3021894 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
elessair 0:f269e3021894 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 #if defined ( __CC_ARM )
elessair 0:f269e3021894 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
elessair 0:f269e3021894 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
elessair 0:f269e3021894 82 #define __STATIC_INLINE static __inline
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 #elif defined ( __GNUC__ )
elessair 0:f269e3021894 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
elessair 0:f269e3021894 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
elessair 0:f269e3021894 87 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89 #elif defined ( __ICCARM__ )
elessair 0:f269e3021894 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
elessair 0:f269e3021894 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
elessair 0:f269e3021894 92 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 #elif defined ( __TMS470__ )
elessair 0:f269e3021894 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
elessair 0:f269e3021894 96 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 #elif defined ( __TASKING__ )
elessair 0:f269e3021894 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
elessair 0:f269e3021894 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
elessair 0:f269e3021894 101 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 #elif defined ( __CSMC__ )
elessair 0:f269e3021894 104 #define __packed
elessair 0:f269e3021894 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
elessair 0:f269e3021894 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
elessair 0:f269e3021894 107 #define __STATIC_INLINE static inline
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 #endif
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 /** __FPU_USED indicates whether an FPU is used or not.
elessair 0:f269e3021894 112 This core does not support an FPU at all
elessair 0:f269e3021894 113 */
elessair 0:f269e3021894 114 #define __FPU_USED 0
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 #if defined ( __CC_ARM )
elessair 0:f269e3021894 117 #if defined __TARGET_FPU_VFP
elessair 0:f269e3021894 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 119 #endif
elessair 0:f269e3021894 120
elessair 0:f269e3021894 121 #elif defined ( __GNUC__ )
elessair 0:f269e3021894 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
elessair 0:f269e3021894 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 124 #endif
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 #elif defined ( __ICCARM__ )
elessair 0:f269e3021894 127 #if defined __ARMVFP__
elessair 0:f269e3021894 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 129 #endif
elessair 0:f269e3021894 130
elessair 0:f269e3021894 131 #elif defined ( __TMS470__ )
elessair 0:f269e3021894 132 #if defined __TI__VFP_SUPPORT____
elessair 0:f269e3021894 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 134 #endif
elessair 0:f269e3021894 135
elessair 0:f269e3021894 136 #elif defined ( __TASKING__ )
elessair 0:f269e3021894 137 #if defined __FPU_VFP__
elessair 0:f269e3021894 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 139 #endif
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 #elif defined ( __CSMC__ ) /* Cosmic */
elessair 0:f269e3021894 142 #if ( __CSMC__ & 0x400) // FPU present for parser
elessair 0:f269e3021894 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elessair 0:f269e3021894 144 #endif
elessair 0:f269e3021894 145 #endif
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 #include <stdint.h> /* standard types definitions */
elessair 0:f269e3021894 148 #include <core_cmInstr.h> /* Core Instruction Access */
elessair 0:f269e3021894 149 #include <core_cmFunc.h> /* Core Function Access */
elessair 0:f269e3021894 150
elessair 0:f269e3021894 151 #ifdef __cplusplus
elessair 0:f269e3021894 152 }
elessair 0:f269e3021894 153 #endif
elessair 0:f269e3021894 154
elessair 0:f269e3021894 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
elessair 0:f269e3021894 156
elessair 0:f269e3021894 157 #ifndef __CMSIS_GENERIC
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
elessair 0:f269e3021894 160 #define __CORE_CM0PLUS_H_DEPENDANT
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 #ifdef __cplusplus
elessair 0:f269e3021894 163 extern "C" {
elessair 0:f269e3021894 164 #endif
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 /* check device defines and use defaults */
elessair 0:f269e3021894 167 #if defined __CHECK_DEVICE_DEFINES
elessair 0:f269e3021894 168 #ifndef __CM0PLUS_REV
elessair 0:f269e3021894 169 #define __CM0PLUS_REV 0x0000
elessair 0:f269e3021894 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
elessair 0:f269e3021894 171 #endif
elessair 0:f269e3021894 172
elessair 0:f269e3021894 173 #ifndef __MPU_PRESENT
elessair 0:f269e3021894 174 #define __MPU_PRESENT 0
elessair 0:f269e3021894 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
elessair 0:f269e3021894 176 #endif
elessair 0:f269e3021894 177
elessair 0:f269e3021894 178 #ifndef __VTOR_PRESENT
elessair 0:f269e3021894 179 #define __VTOR_PRESENT 0
elessair 0:f269e3021894 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
elessair 0:f269e3021894 181 #endif
elessair 0:f269e3021894 182
elessair 0:f269e3021894 183 #ifndef __NVIC_PRIO_BITS
elessair 0:f269e3021894 184 #define __NVIC_PRIO_BITS 2
elessair 0:f269e3021894 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
elessair 0:f269e3021894 186 #endif
elessair 0:f269e3021894 187
elessair 0:f269e3021894 188 #ifndef __Vendor_SysTickConfig
elessair 0:f269e3021894 189 #define __Vendor_SysTickConfig 0
elessair 0:f269e3021894 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
elessair 0:f269e3021894 191 #endif
elessair 0:f269e3021894 192 #endif
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 /* IO definitions (access restrictions to peripheral registers) */
elessair 0:f269e3021894 195 /**
elessair 0:f269e3021894 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
elessair 0:f269e3021894 197
elessair 0:f269e3021894 198 <strong>IO Type Qualifiers</strong> are used
elessair 0:f269e3021894 199 \li to specify the access to peripheral variables.
elessair 0:f269e3021894 200 \li for automatic generation of peripheral register debug information.
elessair 0:f269e3021894 201 */
elessair 0:f269e3021894 202 #ifdef __cplusplus
elessair 0:f269e3021894 203 #define __I volatile /*!< Defines 'read only' permissions */
elessair 0:f269e3021894 204 #else
elessair 0:f269e3021894 205 #define __I volatile const /*!< Defines 'read only' permissions */
elessair 0:f269e3021894 206 #endif
elessair 0:f269e3021894 207 #define __O volatile /*!< Defines 'write only' permissions */
elessair 0:f269e3021894 208 #define __IO volatile /*!< Defines 'read / write' permissions */
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 /*@} end of group Cortex-M0+ */
elessair 0:f269e3021894 211
elessair 0:f269e3021894 212
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 /*******************************************************************************
elessair 0:f269e3021894 215 * Register Abstraction
elessair 0:f269e3021894 216 Core Register contain:
elessair 0:f269e3021894 217 - Core Register
elessair 0:f269e3021894 218 - Core NVIC Register
elessair 0:f269e3021894 219 - Core SCB Register
elessair 0:f269e3021894 220 - Core SysTick Register
elessair 0:f269e3021894 221 - Core MPU Register
elessair 0:f269e3021894 222 ******************************************************************************/
elessair 0:f269e3021894 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
elessair 0:f269e3021894 224 \brief Type definitions and defines for Cortex-M processor based devices.
elessair 0:f269e3021894 225 */
elessair 0:f269e3021894 226
elessair 0:f269e3021894 227 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 228 \defgroup CMSIS_CORE Status and Control Registers
elessair 0:f269e3021894 229 \brief Core Register type definitions.
elessair 0:f269e3021894 230 @{
elessair 0:f269e3021894 231 */
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 /** \brief Union type to access the Application Program Status Register (APSR).
elessair 0:f269e3021894 234 */
elessair 0:f269e3021894 235 typedef union
elessair 0:f269e3021894 236 {
elessair 0:f269e3021894 237 struct
elessair 0:f269e3021894 238 {
elessair 0:f269e3021894 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
elessair 0:f269e3021894 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elessair 0:f269e3021894 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elessair 0:f269e3021894 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elessair 0:f269e3021894 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elessair 0:f269e3021894 244 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 245 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 246 } APSR_Type;
elessair 0:f269e3021894 247
elessair 0:f269e3021894 248 /* APSR Register Definitions */
elessair 0:f269e3021894 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
elessair 0:f269e3021894 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
elessair 0:f269e3021894 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
elessair 0:f269e3021894 254
elessair 0:f269e3021894 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
elessair 0:f269e3021894 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
elessair 0:f269e3021894 257
elessair 0:f269e3021894 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
elessair 0:f269e3021894 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
elessair 0:f269e3021894 260
elessair 0:f269e3021894 261
elessair 0:f269e3021894 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
elessair 0:f269e3021894 263 */
elessair 0:f269e3021894 264 typedef union
elessair 0:f269e3021894 265 {
elessair 0:f269e3021894 266 struct
elessair 0:f269e3021894 267 {
elessair 0:f269e3021894 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elessair 0:f269e3021894 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
elessair 0:f269e3021894 270 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 271 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 272 } IPSR_Type;
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 /* IPSR Register Definitions */
elessair 0:f269e3021894 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
elessair 0:f269e3021894 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
elessair 0:f269e3021894 277
elessair 0:f269e3021894 278
elessair 0:f269e3021894 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
elessair 0:f269e3021894 280 */
elessair 0:f269e3021894 281 typedef union
elessair 0:f269e3021894 282 {
elessair 0:f269e3021894 283 struct
elessair 0:f269e3021894 284 {
elessair 0:f269e3021894 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elessair 0:f269e3021894 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
elessair 0:f269e3021894 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
elessair 0:f269e3021894 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
elessair 0:f269e3021894 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elessair 0:f269e3021894 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elessair 0:f269e3021894 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elessair 0:f269e3021894 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elessair 0:f269e3021894 293 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 294 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 295 } xPSR_Type;
elessair 0:f269e3021894 296
elessair 0:f269e3021894 297 /* xPSR Register Definitions */
elessair 0:f269e3021894 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
elessair 0:f269e3021894 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
elessair 0:f269e3021894 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
elessair 0:f269e3021894 303
elessair 0:f269e3021894 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
elessair 0:f269e3021894 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
elessair 0:f269e3021894 306
elessair 0:f269e3021894 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
elessair 0:f269e3021894 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
elessair 0:f269e3021894 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
elessair 0:f269e3021894 312
elessair 0:f269e3021894 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
elessair 0:f269e3021894 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
elessair 0:f269e3021894 315
elessair 0:f269e3021894 316
elessair 0:f269e3021894 317 /** \brief Union type to access the Control Registers (CONTROL).
elessair 0:f269e3021894 318 */
elessair 0:f269e3021894 319 typedef union
elessair 0:f269e3021894 320 {
elessair 0:f269e3021894 321 struct
elessair 0:f269e3021894 322 {
elessair 0:f269e3021894 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
elessair 0:f269e3021894 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
elessair 0:f269e3021894 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
elessair 0:f269e3021894 326 } b; /*!< Structure used for bit access */
elessair 0:f269e3021894 327 uint32_t w; /*!< Type used for word access */
elessair 0:f269e3021894 328 } CONTROL_Type;
elessair 0:f269e3021894 329
elessair 0:f269e3021894 330 /* CONTROL Register Definitions */
elessair 0:f269e3021894 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
elessair 0:f269e3021894 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
elessair 0:f269e3021894 333
elessair 0:f269e3021894 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
elessair 0:f269e3021894 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 /*@} end of group CMSIS_CORE */
elessair 0:f269e3021894 338
elessair 0:f269e3021894 339
elessair 0:f269e3021894 340 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
elessair 0:f269e3021894 342 \brief Type definitions for the NVIC Registers
elessair 0:f269e3021894 343 @{
elessair 0:f269e3021894 344 */
elessair 0:f269e3021894 345
elessair 0:f269e3021894 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
elessair 0:f269e3021894 347 */
elessair 0:f269e3021894 348 typedef struct
elessair 0:f269e3021894 349 {
elessair 0:f269e3021894 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
elessair 0:f269e3021894 351 uint32_t RESERVED0[31];
elessair 0:f269e3021894 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
elessair 0:f269e3021894 353 uint32_t RSERVED1[31];
elessair 0:f269e3021894 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
elessair 0:f269e3021894 355 uint32_t RESERVED2[31];
elessair 0:f269e3021894 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
elessair 0:f269e3021894 357 uint32_t RESERVED3[31];
elessair 0:f269e3021894 358 uint32_t RESERVED4[64];
elessair 0:f269e3021894 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
elessair 0:f269e3021894 360 } NVIC_Type;
elessair 0:f269e3021894 361
elessair 0:f269e3021894 362 /*@} end of group CMSIS_NVIC */
elessair 0:f269e3021894 363
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 366 \defgroup CMSIS_SCB System Control Block (SCB)
elessair 0:f269e3021894 367 \brief Type definitions for the System Control Block Registers
elessair 0:f269e3021894 368 @{
elessair 0:f269e3021894 369 */
elessair 0:f269e3021894 370
elessair 0:f269e3021894 371 /** \brief Structure type to access the System Control Block (SCB).
elessair 0:f269e3021894 372 */
elessair 0:f269e3021894 373 typedef struct
elessair 0:f269e3021894 374 {
elessair 0:f269e3021894 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
elessair 0:f269e3021894 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
elessair 0:f269e3021894 377 #if (__VTOR_PRESENT == 1)
elessair 0:f269e3021894 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
elessair 0:f269e3021894 379 #else
elessair 0:f269e3021894 380 uint32_t RESERVED0;
elessair 0:f269e3021894 381 #endif
elessair 0:f269e3021894 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
elessair 0:f269e3021894 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
elessair 0:f269e3021894 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
elessair 0:f269e3021894 385 uint32_t RESERVED1;
elessair 0:f269e3021894 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
elessair 0:f269e3021894 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
elessair 0:f269e3021894 388 } SCB_Type;
elessair 0:f269e3021894 389
elessair 0:f269e3021894 390 /* SCB CPUID Register Definitions */
elessair 0:f269e3021894 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
elessair 0:f269e3021894 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
elessair 0:f269e3021894 393
elessair 0:f269e3021894 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
elessair 0:f269e3021894 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
elessair 0:f269e3021894 396
elessair 0:f269e3021894 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
elessair 0:f269e3021894 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
elessair 0:f269e3021894 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
elessair 0:f269e3021894 402
elessair 0:f269e3021894 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
elessair 0:f269e3021894 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
elessair 0:f269e3021894 405
elessair 0:f269e3021894 406 /* SCB Interrupt Control State Register Definitions */
elessair 0:f269e3021894 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
elessair 0:f269e3021894 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
elessair 0:f269e3021894 409
elessair 0:f269e3021894 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
elessair 0:f269e3021894 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
elessair 0:f269e3021894 412
elessair 0:f269e3021894 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
elessair 0:f269e3021894 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
elessair 0:f269e3021894 415
elessair 0:f269e3021894 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
elessair 0:f269e3021894 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
elessair 0:f269e3021894 418
elessair 0:f269e3021894 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
elessair 0:f269e3021894 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
elessair 0:f269e3021894 421
elessair 0:f269e3021894 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
elessair 0:f269e3021894 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
elessair 0:f269e3021894 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
elessair 0:f269e3021894 427
elessair 0:f269e3021894 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
elessair 0:f269e3021894 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
elessair 0:f269e3021894 430
elessair 0:f269e3021894 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
elessair 0:f269e3021894 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
elessair 0:f269e3021894 433
elessair 0:f269e3021894 434 #if (__VTOR_PRESENT == 1)
elessair 0:f269e3021894 435 /* SCB Interrupt Control State Register Definitions */
elessair 0:f269e3021894 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
elessair 0:f269e3021894 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
elessair 0:f269e3021894 438 #endif
elessair 0:f269e3021894 439
elessair 0:f269e3021894 440 /* SCB Application Interrupt and Reset Control Register Definitions */
elessair 0:f269e3021894 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
elessair 0:f269e3021894 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
elessair 0:f269e3021894 443
elessair 0:f269e3021894 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
elessair 0:f269e3021894 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
elessair 0:f269e3021894 446
elessair 0:f269e3021894 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
elessair 0:f269e3021894 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
elessair 0:f269e3021894 449
elessair 0:f269e3021894 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
elessair 0:f269e3021894 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
elessair 0:f269e3021894 452
elessair 0:f269e3021894 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
elessair 0:f269e3021894 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
elessair 0:f269e3021894 455
elessair 0:f269e3021894 456 /* SCB System Control Register Definitions */
elessair 0:f269e3021894 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
elessair 0:f269e3021894 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
elessair 0:f269e3021894 459
elessair 0:f269e3021894 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
elessair 0:f269e3021894 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
elessair 0:f269e3021894 462
elessair 0:f269e3021894 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
elessair 0:f269e3021894 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
elessair 0:f269e3021894 465
elessair 0:f269e3021894 466 /* SCB Configuration Control Register Definitions */
elessair 0:f269e3021894 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
elessair 0:f269e3021894 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
elessair 0:f269e3021894 469
elessair 0:f269e3021894 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
elessair 0:f269e3021894 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
elessair 0:f269e3021894 472
elessair 0:f269e3021894 473 /* SCB System Handler Control and State Register Definitions */
elessair 0:f269e3021894 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
elessair 0:f269e3021894 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 /*@} end of group CMSIS_SCB */
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479
elessair 0:f269e3021894 480 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
elessair 0:f269e3021894 482 \brief Type definitions for the System Timer Registers.
elessair 0:f269e3021894 483 @{
elessair 0:f269e3021894 484 */
elessair 0:f269e3021894 485
elessair 0:f269e3021894 486 /** \brief Structure type to access the System Timer (SysTick).
elessair 0:f269e3021894 487 */
elessair 0:f269e3021894 488 typedef struct
elessair 0:f269e3021894 489 {
elessair 0:f269e3021894 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
elessair 0:f269e3021894 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
elessair 0:f269e3021894 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
elessair 0:f269e3021894 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
elessair 0:f269e3021894 494 } SysTick_Type;
elessair 0:f269e3021894 495
elessair 0:f269e3021894 496 /* SysTick Control / Status Register Definitions */
elessair 0:f269e3021894 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
elessair 0:f269e3021894 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
elessair 0:f269e3021894 499
elessair 0:f269e3021894 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
elessair 0:f269e3021894 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
elessair 0:f269e3021894 502
elessair 0:f269e3021894 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
elessair 0:f269e3021894 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
elessair 0:f269e3021894 505
elessair 0:f269e3021894 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
elessair 0:f269e3021894 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
elessair 0:f269e3021894 508
elessair 0:f269e3021894 509 /* SysTick Reload Register Definitions */
elessair 0:f269e3021894 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
elessair 0:f269e3021894 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
elessair 0:f269e3021894 512
elessair 0:f269e3021894 513 /* SysTick Current Register Definitions */
elessair 0:f269e3021894 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
elessair 0:f269e3021894 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
elessair 0:f269e3021894 516
elessair 0:f269e3021894 517 /* SysTick Calibration Register Definitions */
elessair 0:f269e3021894 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
elessair 0:f269e3021894 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
elessair 0:f269e3021894 520
elessair 0:f269e3021894 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
elessair 0:f269e3021894 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
elessair 0:f269e3021894 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
elessair 0:f269e3021894 526
elessair 0:f269e3021894 527 /*@} end of group CMSIS_SysTick */
elessair 0:f269e3021894 528
elessair 0:f269e3021894 529 #if (__MPU_PRESENT == 1)
elessair 0:f269e3021894 530 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
elessair 0:f269e3021894 532 \brief Type definitions for the Memory Protection Unit (MPU)
elessair 0:f269e3021894 533 @{
elessair 0:f269e3021894 534 */
elessair 0:f269e3021894 535
elessair 0:f269e3021894 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
elessair 0:f269e3021894 537 */
elessair 0:f269e3021894 538 typedef struct
elessair 0:f269e3021894 539 {
elessair 0:f269e3021894 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
elessair 0:f269e3021894 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
elessair 0:f269e3021894 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
elessair 0:f269e3021894 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
elessair 0:f269e3021894 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
elessair 0:f269e3021894 545 } MPU_Type;
elessair 0:f269e3021894 546
elessair 0:f269e3021894 547 /* MPU Type Register */
elessair 0:f269e3021894 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
elessair 0:f269e3021894 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
elessair 0:f269e3021894 550
elessair 0:f269e3021894 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
elessair 0:f269e3021894 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
elessair 0:f269e3021894 553
elessair 0:f269e3021894 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
elessair 0:f269e3021894 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
elessair 0:f269e3021894 556
elessair 0:f269e3021894 557 /* MPU Control Register */
elessair 0:f269e3021894 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
elessair 0:f269e3021894 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
elessair 0:f269e3021894 560
elessair 0:f269e3021894 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
elessair 0:f269e3021894 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
elessair 0:f269e3021894 563
elessair 0:f269e3021894 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
elessair 0:f269e3021894 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
elessair 0:f269e3021894 566
elessair 0:f269e3021894 567 /* MPU Region Number Register */
elessair 0:f269e3021894 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
elessair 0:f269e3021894 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
elessair 0:f269e3021894 570
elessair 0:f269e3021894 571 /* MPU Region Base Address Register */
elessair 0:f269e3021894 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
elessair 0:f269e3021894 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
elessair 0:f269e3021894 574
elessair 0:f269e3021894 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
elessair 0:f269e3021894 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
elessair 0:f269e3021894 577
elessair 0:f269e3021894 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
elessair 0:f269e3021894 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 /* MPU Region Attribute and Size Register */
elessair 0:f269e3021894 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
elessair 0:f269e3021894 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
elessair 0:f269e3021894 584
elessair 0:f269e3021894 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
elessair 0:f269e3021894 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
elessair 0:f269e3021894 587
elessair 0:f269e3021894 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
elessair 0:f269e3021894 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
elessair 0:f269e3021894 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
elessair 0:f269e3021894 593
elessair 0:f269e3021894 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
elessair 0:f269e3021894 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
elessair 0:f269e3021894 596
elessair 0:f269e3021894 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
elessair 0:f269e3021894 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
elessair 0:f269e3021894 599
elessair 0:f269e3021894 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
elessair 0:f269e3021894 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
elessair 0:f269e3021894 602
elessair 0:f269e3021894 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
elessair 0:f269e3021894 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
elessair 0:f269e3021894 605
elessair 0:f269e3021894 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
elessair 0:f269e3021894 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
elessair 0:f269e3021894 608
elessair 0:f269e3021894 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
elessair 0:f269e3021894 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
elessair 0:f269e3021894 611
elessair 0:f269e3021894 612 /*@} end of group CMSIS_MPU */
elessair 0:f269e3021894 613 #endif
elessair 0:f269e3021894 614
elessair 0:f269e3021894 615
elessair 0:f269e3021894 616 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
elessair 0:f269e3021894 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
elessair 0:f269e3021894 619 are only accessible over DAP and not via processor. Therefore
elessair 0:f269e3021894 620 they are not covered by the Cortex-M0 header file.
elessair 0:f269e3021894 621 @{
elessair 0:f269e3021894 622 */
elessair 0:f269e3021894 623 /*@} end of group CMSIS_CoreDebug */
elessair 0:f269e3021894 624
elessair 0:f269e3021894 625
elessair 0:f269e3021894 626 /** \ingroup CMSIS_core_register
elessair 0:f269e3021894 627 \defgroup CMSIS_core_base Core Definitions
elessair 0:f269e3021894 628 \brief Definitions for base addresses, unions, and structures.
elessair 0:f269e3021894 629 @{
elessair 0:f269e3021894 630 */
elessair 0:f269e3021894 631
elessair 0:f269e3021894 632 /* Memory mapping of Cortex-M0+ Hardware */
elessair 0:f269e3021894 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
elessair 0:f269e3021894 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
elessair 0:f269e3021894 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
elessair 0:f269e3021894 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
elessair 0:f269e3021894 637
elessair 0:f269e3021894 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
elessair 0:f269e3021894 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
elessair 0:f269e3021894 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
elessair 0:f269e3021894 641
elessair 0:f269e3021894 642 #if (__MPU_PRESENT == 1)
elessair 0:f269e3021894 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
elessair 0:f269e3021894 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
elessair 0:f269e3021894 645 #endif
elessair 0:f269e3021894 646
elessair 0:f269e3021894 647 /*@} */
elessair 0:f269e3021894 648
elessair 0:f269e3021894 649
elessair 0:f269e3021894 650
elessair 0:f269e3021894 651 /*******************************************************************************
elessair 0:f269e3021894 652 * Hardware Abstraction Layer
elessair 0:f269e3021894 653 Core Function Interface contains:
elessair 0:f269e3021894 654 - Core NVIC Functions
elessair 0:f269e3021894 655 - Core SysTick Functions
elessair 0:f269e3021894 656 - Core Register Access Functions
elessair 0:f269e3021894 657 ******************************************************************************/
elessair 0:f269e3021894 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
elessair 0:f269e3021894 659 */
elessair 0:f269e3021894 660
elessair 0:f269e3021894 661
elessair 0:f269e3021894 662
elessair 0:f269e3021894 663 /* ########################## NVIC functions #################################### */
elessair 0:f269e3021894 664 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
elessair 0:f269e3021894 666 \brief Functions that manage interrupts and exceptions via the NVIC.
elessair 0:f269e3021894 667 @{
elessair 0:f269e3021894 668 */
elessair 0:f269e3021894 669
elessair 0:f269e3021894 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
elessair 0:f269e3021894 671 /* The following MACROS handle generation of the register offset and byte masks */
elessair 0:f269e3021894 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
elessair 0:f269e3021894 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
elessair 0:f269e3021894 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676
elessair 0:f269e3021894 677 /** \brief Enable External Interrupt
elessair 0:f269e3021894 678
elessair 0:f269e3021894 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
elessair 0:f269e3021894 680
elessair 0:f269e3021894 681 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 682 */
elessair 0:f269e3021894 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 684 {
elessair 0:f269e3021894 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 686 }
elessair 0:f269e3021894 687
elessair 0:f269e3021894 688
elessair 0:f269e3021894 689 /** \brief Disable External Interrupt
elessair 0:f269e3021894 690
elessair 0:f269e3021894 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
elessair 0:f269e3021894 692
elessair 0:f269e3021894 693 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 694 */
elessair 0:f269e3021894 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 696 {
elessair 0:f269e3021894 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 698 }
elessair 0:f269e3021894 699
elessair 0:f269e3021894 700
elessair 0:f269e3021894 701 /** \brief Get Pending Interrupt
elessair 0:f269e3021894 702
elessair 0:f269e3021894 703 The function reads the pending register in the NVIC and returns the pending bit
elessair 0:f269e3021894 704 for the specified interrupt.
elessair 0:f269e3021894 705
elessair 0:f269e3021894 706 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 707
elessair 0:f269e3021894 708 \return 0 Interrupt status is not pending.
elessair 0:f269e3021894 709 \return 1 Interrupt status is pending.
elessair 0:f269e3021894 710 */
elessair 0:f269e3021894 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 712 {
elessair 0:f269e3021894 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
elessair 0:f269e3021894 714 }
elessair 0:f269e3021894 715
elessair 0:f269e3021894 716
elessair 0:f269e3021894 717 /** \brief Set Pending Interrupt
elessair 0:f269e3021894 718
elessair 0:f269e3021894 719 The function sets the pending bit of an external interrupt.
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 \param [in] IRQn Interrupt number. Value cannot be negative.
elessair 0:f269e3021894 722 */
elessair 0:f269e3021894 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 724 {
elessair 0:f269e3021894 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 726 }
elessair 0:f269e3021894 727
elessair 0:f269e3021894 728
elessair 0:f269e3021894 729 /** \brief Clear Pending Interrupt
elessair 0:f269e3021894 730
elessair 0:f269e3021894 731 The function clears the pending bit of an external interrupt.
elessair 0:f269e3021894 732
elessair 0:f269e3021894 733 \param [in] IRQn External interrupt number. Value cannot be negative.
elessair 0:f269e3021894 734 */
elessair 0:f269e3021894 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
elessair 0:f269e3021894 736 {
elessair 0:f269e3021894 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
elessair 0:f269e3021894 738 }
elessair 0:f269e3021894 739
elessair 0:f269e3021894 740
elessair 0:f269e3021894 741 /** \brief Set Interrupt Priority
elessair 0:f269e3021894 742
elessair 0:f269e3021894 743 The function sets the priority of an interrupt.
elessair 0:f269e3021894 744
elessair 0:f269e3021894 745 \note The priority cannot be set for every core interrupt.
elessair 0:f269e3021894 746
elessair 0:f269e3021894 747 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 748 \param [in] priority Priority to set.
elessair 0:f269e3021894 749 */
elessair 0:f269e3021894 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
elessair 0:f269e3021894 751 {
elessair 0:f269e3021894 752 if((int32_t)(IRQn) < 0) {
elessair 0:f269e3021894 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
elessair 0:f269e3021894 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
elessair 0:f269e3021894 755 }
elessair 0:f269e3021894 756 else {
elessair 0:f269e3021894 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
elessair 0:f269e3021894 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
elessair 0:f269e3021894 759 }
elessair 0:f269e3021894 760 }
elessair 0:f269e3021894 761
elessair 0:f269e3021894 762
elessair 0:f269e3021894 763 /** \brief Get Interrupt Priority
elessair 0:f269e3021894 764
elessair 0:f269e3021894 765 The function reads the priority of an interrupt. The interrupt
elessair 0:f269e3021894 766 number can be positive to specify an external (device specific)
elessair 0:f269e3021894 767 interrupt, or negative to specify an internal (core) interrupt.
elessair 0:f269e3021894 768
elessair 0:f269e3021894 769
elessair 0:f269e3021894 770 \param [in] IRQn Interrupt number.
elessair 0:f269e3021894 771 \return Interrupt Priority. Value is aligned automatically to the implemented
elessair 0:f269e3021894 772 priority bits of the microcontroller.
elessair 0:f269e3021894 773 */
elessair 0:f269e3021894 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
elessair 0:f269e3021894 775 {
elessair 0:f269e3021894 776
elessair 0:f269e3021894 777 if((int32_t)(IRQn) < 0) {
elessair 0:f269e3021894 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
elessair 0:f269e3021894 779 }
elessair 0:f269e3021894 780 else {
elessair 0:f269e3021894 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
elessair 0:f269e3021894 782 }
elessair 0:f269e3021894 783 }
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785
elessair 0:f269e3021894 786 /** \brief System Reset
elessair 0:f269e3021894 787
elessair 0:f269e3021894 788 The function initiates a system reset request to reset the MCU.
elessair 0:f269e3021894 789 */
elessair 0:f269e3021894 790 __STATIC_INLINE void NVIC_SystemReset(void)
elessair 0:f269e3021894 791 {
elessair 0:f269e3021894 792 __DSB(); /* Ensure all outstanding memory accesses included
elessair 0:f269e3021894 793 buffered write are completed before reset */
elessair 0:f269e3021894 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
elessair 0:f269e3021894 795 SCB_AIRCR_SYSRESETREQ_Msk);
elessair 0:f269e3021894 796 __DSB(); /* Ensure completion of memory access */
elessair 0:f269e3021894 797 while(1) { __NOP(); } /* wait until reset */
elessair 0:f269e3021894 798 }
elessair 0:f269e3021894 799
elessair 0:f269e3021894 800 /*@} end of CMSIS_Core_NVICFunctions */
elessair 0:f269e3021894 801
elessair 0:f269e3021894 802
elessair 0:f269e3021894 803
elessair 0:f269e3021894 804 /* ################################## SysTick function ############################################ */
elessair 0:f269e3021894 805 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
elessair 0:f269e3021894 807 \brief Functions that configure the System.
elessair 0:f269e3021894 808 @{
elessair 0:f269e3021894 809 */
elessair 0:f269e3021894 810
elessair 0:f269e3021894 811 #if (__Vendor_SysTickConfig == 0)
elessair 0:f269e3021894 812
elessair 0:f269e3021894 813 /** \brief System Tick Configuration
elessair 0:f269e3021894 814
elessair 0:f269e3021894 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
elessair 0:f269e3021894 816 Counter is in free running mode to generate periodic interrupts.
elessair 0:f269e3021894 817
elessair 0:f269e3021894 818 \param [in] ticks Number of ticks between two interrupts.
elessair 0:f269e3021894 819
elessair 0:f269e3021894 820 \return 0 Function succeeded.
elessair 0:f269e3021894 821 \return 1 Function failed.
elessair 0:f269e3021894 822
elessair 0:f269e3021894 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
elessair 0:f269e3021894 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
elessair 0:f269e3021894 825 must contain a vendor-specific implementation of this function.
elessair 0:f269e3021894 826
elessair 0:f269e3021894 827 */
elessair 0:f269e3021894 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
elessair 0:f269e3021894 829 {
elessair 0:f269e3021894 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
elessair 0:f269e3021894 831
elessair 0:f269e3021894 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
elessair 0:f269e3021894 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
elessair 0:f269e3021894 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
elessair 0:f269e3021894 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
elessair 0:f269e3021894 836 SysTick_CTRL_TICKINT_Msk |
elessair 0:f269e3021894 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
elessair 0:f269e3021894 838 return (0UL); /* Function successful */
elessair 0:f269e3021894 839 }
elessair 0:f269e3021894 840
elessair 0:f269e3021894 841 #endif
elessair 0:f269e3021894 842
elessair 0:f269e3021894 843 /*@} end of CMSIS_Core_SysTickFunctions */
elessair 0:f269e3021894 844
elessair 0:f269e3021894 845
elessair 0:f269e3021894 846
elessair 0:f269e3021894 847
elessair 0:f269e3021894 848 #ifdef __cplusplus
elessair 0:f269e3021894 849 }
elessair 0:f269e3021894 850 #endif
elessair 0:f269e3021894 851
elessair 0:f269e3021894 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
elessair 0:f269e3021894 853
elessair 0:f269e3021894 854 #endif /* __CMSIS_GENERIC */