Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file i2c.c
elessair 0:f269e3021894 4 * @brief I2C driver
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: $
elessair 0:f269e3021894 8 * $Date: 2016-04-12 $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup i2c
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 *
elessair 0:f269e3021894 31 * <h1> Reference document(s) </h1>
elessair 0:f269e3021894 32 * <p>
elessair 0:f269e3021894 33 * IPC7208 APB I2C Master Design Specification v1.3
elessair 0:f269e3021894 34 * </p>
elessair 0:f269e3021894 35 * The I2C bus is an industry-standard two-wire (clock and data) serial communication bus between master(initiator) and slave device.
elessair 0:f269e3021894 36 * Within the procedure of the I2C-bus, unique situations arise which are defined as START and STOP conditions .A HIGH to LOW transition on
elessair 0:f269e3021894 37 * the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.A LOW to HIGH transition on the
elessair 0:f269e3021894 38 * SDA line while SCL is HIGH defines a STOP condition.START and STOP conditions are always generated by the master. The bus is considered
elessair 0:f269e3021894 39 * to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.
elessair 0:f269e3021894 40 * A master may start a transfer only if the bus is free. Two or more masters may generate a START condition.
elessair 0:f269e3021894 41 * Every byte put on the SDA line must be 8-bits long.Each byte has to be followed by an acknowledge bit.
elessair 0:f269e3021894 42 * This APB(Advanced peripheral bus) I2C Master is an APB Slave peripheral that can also serves as an I2C bus Master. The Command register
elessair 0:f269e3021894 43 * is the programming interface to the I2C Engine. The commands arrive at the I2C Engine via the Command FIFO,so the first valid command
elessair 0:f269e3021894 44 * that is written to the Command register is the first I2C instruction implemented on the I2C bus.Because the command interface provides
elessair 0:f269e3021894 45 * the basic building blocks for any I2C transaction, access to a wide range of I2C slave devices is supported.
elessair 0:f269e3021894 46 * I2C can be enabled by setting bit 7 of the control register .
elessair 0:f269e3021894 47 * There is a generated clock (a divided version of the APB clock) in this module that may be used as the I2C System Clock.
elessair 0:f269e3021894 48 * There are two FIFO in the I2C; Command FIFO and Read data FIFO
elessair 0:f269e3021894 49 * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO.
elessair 0:f269e3021894 50 * if the command FIFO is empty , up to 32 commands can be written to the command interface , it is programmer's responsibility to keep
elessair 0:f269e3021894 51 * the track of command FIFO's status either by interrupt or by polling method by reading status register, which represents Operational
elessair 0:f269e3021894 52 * Status of the I2C Module and its sub-modules.The action from the processor may be necessary after reading the status register.Reading
elessair 0:f269e3021894 53 * the Status register clears the blkInt Interrupt signal.Read data FIFO is where data read by the processor from I2C slave is placed .
elessair 0:f269e3021894 54 *
elessair 0:f269e3021894 55 *
elessair 0:f269e3021894 56 * <h1> Functional description (internal) </h1>
elessair 0:f269e3021894 57 * <p>
elessair 0:f269e3021894 58 *
elessair 0:f269e3021894 59 * </p>
elessair 0:f269e3021894 60 */
elessair 0:f269e3021894 61 #if DEVICE_I2C
elessair 0:f269e3021894 62 #include "i2c.h"
elessair 0:f269e3021894 63
elessair 0:f269e3021894 64 /* See i2c.h for details */
elessair 0:f269e3021894 65 void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
elessair 0:f269e3021894 66 {
elessair 0:f269e3021894 67 uint32_t clockDivisor;
elessair 0:f269e3021894 68 /* determine the I2C to use */
elessair 0:f269e3021894 69 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 70 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 71 obj->membase = (I2cIpc7208Reg_pt)pinmap_merge(i2c_sda, i2c_scl);
elessair 0:f269e3021894 72 MBED_ASSERT((int)obj->membase != NC);
elessair 0:f269e3021894 73
elessair 0:f269e3021894 74 /* By default disbale interrupts */
elessair 0:f269e3021894 75 obj->membase->IER.WORD = False;
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 /* enable interrupt associated with the device */
elessair 0:f269e3021894 78 if(obj->membase == I2C1REG) {
elessair 0:f269e3021894 79 CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
elessair 0:f269e3021894 80 NVIC_ClearPendingIRQ(I2C_IRQn);
elessair 0:f269e3021894 81 NVIC_EnableIRQ(I2C_IRQn);
elessair 0:f269e3021894 82 } else {
elessair 0:f269e3021894 83 CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
elessair 0:f269e3021894 84 NVIC_ClearPendingIRQ(I2C2_IRQn);
elessair 0:f269e3021894 85 NVIC_EnableIRQ(I2C2_IRQn);
elessair 0:f269e3021894 86 }
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 /*select I2C clock source */
elessair 0:f269e3021894 89 obj->membase->CR.BITS.I2C_CLK_SRC = True;
elessair 0:f269e3021894 90
elessair 0:f269e3021894 91 /* enable I2C clock divider */
elessair 0:f269e3021894 92 obj->membase->CR.BITS.I2C_APB_CD_EN = True;
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 /* set default baud rate at 100k */
elessair 0:f269e3021894 95 clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
elessair 0:f269e3021894 96 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
elessair 0:f269e3021894 97 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 /* Cross bar setting */
elessair 0:f269e3021894 100 pinmap_pinout(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 101 pinmap_pinout(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 /*Enable open drain & pull up for sda & scl pin */
elessair 0:f269e3021894 104 pin_mode(sda, OpenDrainPullUp);
elessair 0:f269e3021894 105 pin_mode(scl, OpenDrainPullUp);
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 /* PAD drive strength */
elessair 0:f269e3021894 108 PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 109 PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 CLOCK_ENABLE(CLOCK_PAD);
elessair 0:f269e3021894 112 padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
elessair 0:f269e3021894 113 padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
elessair 0:f269e3021894 114 CLOCK_DISABLE(CLOCK_PAD);
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 CLOCK_ENABLE(CLOCK_GPIO);
elessair 0:f269e3021894 117 GPIOREG->W_OUT |= ((True << sda) | (True << scl));
elessair 0:f269e3021894 118 CLOCK_DISABLE(CLOCK_GPIO);
elessair 0:f269e3021894 119
elessair 0:f269e3021894 120 /* Enable i2c module */
elessair 0:f269e3021894 121 obj->membase->CR.BITS.I2C_MODULE_EN = True;
elessair 0:f269e3021894 122 }
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 /* See i2c.h for details */
elessair 0:f269e3021894 125 void fI2cFrequency(i2c_t *obj, uint32_t hz)
elessair 0:f269e3021894 126 {
elessair 0:f269e3021894 127 /* Set user baud rate */
elessair 0:f269e3021894 128 uint32_t clockDivisor;
elessair 0:f269e3021894 129 clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2;
elessair 0:f269e3021894 130 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
elessair 0:f269e3021894 131 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
elessair 0:f269e3021894 132 }
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 /* See i2c.h for details */
elessair 0:f269e3021894 135 int32_t fI2cStart(i2c_t *obj)
elessair 0:f269e3021894 136 {
elessair 0:f269e3021894 137 /* Send start bit */
elessair 0:f269e3021894 138 obj->membase->CMD_REG = I2C_CMD_START;
elessair 0:f269e3021894 139 return I2C_API_STATUS_SUCCESS;
elessair 0:f269e3021894 140 }
elessair 0:f269e3021894 141
elessair 0:f269e3021894 142 /* See i2c.h for details */
elessair 0:f269e3021894 143 int32_t fI2cStop(i2c_t *obj)
elessair 0:f269e3021894 144 {
elessair 0:f269e3021894 145 /* Send stop bit */
elessair 0:f269e3021894 146 obj->membase->CMD_REG = I2C_CMD_STOP;
elessair 0:f269e3021894 147 if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT |
elessair 0:f269e3021894 148 I2C_STATUS_CMD_FIFO_OFL_BIT |
elessair 0:f269e3021894 149 I2C_STATUS_BUS_ERR_BIT)) {
elessair 0:f269e3021894 150 /* I2c error occured */
elessair 0:f269e3021894 151 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 152 }
elessair 0:f269e3021894 153 return I2C_API_STATUS_SUCCESS;
elessair 0:f269e3021894 154 }
elessair 0:f269e3021894 155
elessair 0:f269e3021894 156 /* See i2c.h for details */
elessair 0:f269e3021894 157 int32_t fI2cReadB(i2c_t *d, char *buf, int len)
elessair 0:f269e3021894 158 {
elessair 0:f269e3021894 159 int32_t read = 0;
elessair 0:f269e3021894 160
elessair 0:f269e3021894 161 while (read < len) {
elessair 0:f269e3021894 162 /* Send read command */
elessair 0:f269e3021894 163 d->membase->CMD_REG = I2C_CMD_RDAT8;
elessair 0:f269e3021894 164 while(!RD_DATA_READY) {
elessair 0:f269e3021894 165 if (I2C_BUS_ERR_CHECK) {
elessair 0:f269e3021894 166 /* Bus error occured */
elessair 0:f269e3021894 167 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 168 }
elessair 0:f269e3021894 169 }
elessair 0:f269e3021894 170 buf[read++] = d->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */
elessair 0:f269e3021894 173 d->membase->CMD_REG=I2C_CMD_WDAT0; /* TODO based on requirement generate ACK or NACK Based on the requirement. */
elessair 0:f269e3021894 174 }
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 /* check for FIFO underflow */
elessair 0:f269e3021894 177 if(I2C_UFL_CHECK) {
elessair 0:f269e3021894 178 return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
elessair 0:f269e3021894 179 }
elessair 0:f269e3021894 180 if(I2C_BUS_ERR_CHECK) {
elessair 0:f269e3021894 181 /* Bus error */
elessair 0:f269e3021894 182 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 183 }
elessair 0:f269e3021894 184 }
elessair 0:f269e3021894 185
elessair 0:f269e3021894 186 return read;
elessair 0:f269e3021894 187 }
elessair 0:f269e3021894 188
elessair 0:f269e3021894 189 /* See i2c.h for details */
elessair 0:f269e3021894 190 int32_t fI2cWriteB(i2c_t *d, const char *buf, int len)
elessair 0:f269e3021894 191 {
elessair 0:f269e3021894 192 int32_t write = 0;
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 while (write < len) {
elessair 0:f269e3021894 195 /* Send write command */
elessair 0:f269e3021894 196 d->membase->CMD_REG = I2C_CMD_WDAT8;
elessair 0:f269e3021894 197 if(buf[write] == I2C_CMD_RDAT8) {
elessair 0:f269e3021894 198 /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
elessair 0:f269e3021894 199 then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a
elessair 0:f269e3021894 200 RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
elessair 0:f269e3021894 201 /* Send 0x13 bit wise */
elessair 0:f269e3021894 202 d->membase->CMD_REG = I2C_CMD_WDAT0;
elessair 0:f269e3021894 203 d->membase->CMD_REG = I2C_CMD_WDAT0;
elessair 0:f269e3021894 204 d->membase->CMD_REG = I2C_CMD_WDAT0;
elessair 0:f269e3021894 205 d->membase->CMD_REG = I2C_CMD_WDAT1;
elessair 0:f269e3021894 206
elessair 0:f269e3021894 207 d->membase->CMD_REG = I2C_CMD_WDAT0;
elessair 0:f269e3021894 208 d->membase->CMD_REG = I2C_CMD_WDAT0;
elessair 0:f269e3021894 209 d->membase->CMD_REG = I2C_CMD_WDAT1;
elessair 0:f269e3021894 210 d->membase->CMD_REG = I2C_CMD_WDAT1;
elessair 0:f269e3021894 211 } else {
elessair 0:f269e3021894 212 /* Send data */
elessair 0:f269e3021894 213 d->membase->CMD_REG = buf[write++];
elessair 0:f269e3021894 214 }
elessair 0:f269e3021894 215 d->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* TODO Verify ACK based on requirement, Do we need? */
elessair 0:f269e3021894 216
elessair 0:f269e3021894 217 while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 if (I2C_BUS_ERR_CHECK) {
elessair 0:f269e3021894 220 /* Bus error */
elessair 0:f269e3021894 221 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 222 }
elessair 0:f269e3021894 223 }
elessair 0:f269e3021894 224
elessair 0:f269e3021894 225 return write;
elessair 0:f269e3021894 226 }
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 #endif /* DEVICE_I2C */