Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_NXP/TARGET_LPC81X/spi_api.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include "mbed_assert.h"
elessair 0:f269e3021894 17 #include <math.h>
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #include "spi_api.h"
elessair 0:f269e3021894 20 #include "cmsis.h"
elessair 0:f269e3021894 21 #include "pinmap.h"
elessair 0:f269e3021894 22 #include "mbed_error.h"
elessair 0:f269e3021894 23
elessair 0:f269e3021894 24 static const SWM_Map SWM_SPI_SSEL[] = {
elessair 0:f269e3021894 25 {4, 16},
elessair 0:f269e3021894 26 {5, 16},
elessair 0:f269e3021894 27 };
elessair 0:f269e3021894 28
elessair 0:f269e3021894 29 static const SWM_Map SWM_SPI_SCLK[] = {
elessair 0:f269e3021894 30 {3, 24},
elessair 0:f269e3021894 31 {4, 24},
elessair 0:f269e3021894 32 };
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 static const SWM_Map SWM_SPI_MOSI[] = {
elessair 0:f269e3021894 35 {4, 0},
elessair 0:f269e3021894 36 {5, 0},
elessair 0:f269e3021894 37 };
elessair 0:f269e3021894 38
elessair 0:f269e3021894 39 static const SWM_Map SWM_SPI_MISO[] = {
elessair 0:f269e3021894 40 {4, 8},
elessair 0:f269e3021894 41 {5, 16},
elessair 0:f269e3021894 42 };
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 // bit flags for used SPIs
elessair 0:f269e3021894 45 static unsigned char spi_used = 0;
elessair 0:f269e3021894 46 static int get_available_spi(void) {
elessair 0:f269e3021894 47 int i;
elessair 0:f269e3021894 48 for (i=0; i<2; i++) {
elessair 0:f269e3021894 49 if ((spi_used & (1 << i)) == 0)
elessair 0:f269e3021894 50 return i;
elessair 0:f269e3021894 51 }
elessair 0:f269e3021894 52 return -1;
elessair 0:f269e3021894 53 }
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 static inline int ssp_disable(spi_t *obj);
elessair 0:f269e3021894 56 static inline int ssp_enable(spi_t *obj);
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
elessair 0:f269e3021894 59 int spi_n = get_available_spi();
elessair 0:f269e3021894 60 if (spi_n == -1) {
elessair 0:f269e3021894 61 error("No available SPI");
elessair 0:f269e3021894 62 }
elessair 0:f269e3021894 63 obj->spi_n = spi_n;
elessair 0:f269e3021894 64 spi_used |= (1 << spi_n);
elessair 0:f269e3021894 65
elessair 0:f269e3021894 66 obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 const SWM_Map *swm;
elessair 0:f269e3021894 69 uint32_t regVal;
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 swm = &SWM_SPI_SCLK[obj->spi_n];
elessair 0:f269e3021894 72 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
elessair 0:f269e3021894 73 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 swm = &SWM_SPI_MOSI[obj->spi_n];
elessair 0:f269e3021894 76 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
elessair 0:f269e3021894 77 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 swm = &SWM_SPI_MISO[obj->spi_n];
elessair 0:f269e3021894 80 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
elessair 0:f269e3021894 81 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83 swm = &SWM_SPI_SSEL[obj->spi_n];
elessair 0:f269e3021894 84 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
elessair 0:f269e3021894 85 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87 // clear interrupts
elessair 0:f269e3021894 88 obj->spi->INTENCLR = 0x3f;
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 // enable power and clocking
elessair 0:f269e3021894 91 switch (obj->spi_n) {
elessair 0:f269e3021894 92 case 0:
elessair 0:f269e3021894 93 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
elessair 0:f269e3021894 94 LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
elessair 0:f269e3021894 95 LPC_SYSCON->PRESETCTRL |= (0x1<<0);
elessair 0:f269e3021894 96 break;
elessair 0:f269e3021894 97 case 1:
elessair 0:f269e3021894 98 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
elessair 0:f269e3021894 99 LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
elessair 0:f269e3021894 100 LPC_SYSCON->PRESETCTRL |= (0x1<<1);
elessair 0:f269e3021894 101 break;
elessair 0:f269e3021894 102 }
elessair 0:f269e3021894 103 }
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105 void spi_free(spi_t *obj) {}
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 void spi_format(spi_t *obj, int bits, int mode, int slave) {
elessair 0:f269e3021894 108 MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
elessair 0:f269e3021894 109 ssp_disable(obj);
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 int polarity = (mode & 0x2) ? 1 : 0;
elessair 0:f269e3021894 112 int phase = (mode & 0x1) ? 1 : 0;
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 // set it up
elessair 0:f269e3021894 115 int DSS = bits - 1; // DSS (data select size)
elessair 0:f269e3021894 116 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
elessair 0:f269e3021894 117 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 uint32_t tmp = obj->spi->CFG;
elessair 0:f269e3021894 120 tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
elessair 0:f269e3021894 121 tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
elessair 0:f269e3021894 122 obj->spi->CFG = tmp;
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 // select frame length
elessair 0:f269e3021894 125 tmp = obj->spi->TXDATCTL;
elessair 0:f269e3021894 126 tmp &= ~(0xf << 24);
elessair 0:f269e3021894 127 tmp |= (DSS << 24);
elessair 0:f269e3021894 128 obj->spi->TXDATCTL = tmp;
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 ssp_enable(obj);
elessair 0:f269e3021894 131 }
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133 void spi_frequency(spi_t *obj, int hz) {
elessair 0:f269e3021894 134 ssp_disable(obj);
elessair 0:f269e3021894 135
elessair 0:f269e3021894 136 uint32_t PCLK = SystemCoreClock;
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 obj->spi->DIV = PCLK/hz - 1;
elessair 0:f269e3021894 139 obj->spi->DLY = 0;
elessair 0:f269e3021894 140 ssp_enable(obj);
elessair 0:f269e3021894 141 }
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 static inline int ssp_disable(spi_t *obj) {
elessair 0:f269e3021894 144 return obj->spi->CFG &= ~(1 << 0);
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 static inline int ssp_enable(spi_t *obj) {
elessair 0:f269e3021894 148 return obj->spi->CFG |= (1 << 0);
elessair 0:f269e3021894 149 }
elessair 0:f269e3021894 150
elessair 0:f269e3021894 151 static inline int ssp_readable(spi_t *obj) {
elessair 0:f269e3021894 152 return obj->spi->STAT & (1 << 0);
elessair 0:f269e3021894 153 }
elessair 0:f269e3021894 154
elessair 0:f269e3021894 155 static inline int ssp_writeable(spi_t *obj) {
elessair 0:f269e3021894 156 return obj->spi->STAT & (1 << 1);
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 static inline void ssp_write(spi_t *obj, int value) {
elessair 0:f269e3021894 160 while (!ssp_writeable(obj));
elessair 0:f269e3021894 161 // end of transfer
elessair 0:f269e3021894 162 obj->spi->TXDATCTL |= (1 << 20);
elessair 0:f269e3021894 163 obj->spi->TXDAT = value;
elessair 0:f269e3021894 164 }
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 static inline int ssp_read(spi_t *obj) {
elessair 0:f269e3021894 167 while (!ssp_readable(obj));
elessair 0:f269e3021894 168 return obj->spi->RXDAT;
elessair 0:f269e3021894 169 }
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 static inline int ssp_busy(spi_t *obj) {
elessair 0:f269e3021894 172 // checking RXOV(Receiver Overrun interrupt flag)
elessair 0:f269e3021894 173 return obj->spi->STAT & (1 << 2);
elessair 0:f269e3021894 174 }
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 int spi_master_write(spi_t *obj, int value) {
elessair 0:f269e3021894 177 ssp_write(obj, value);
elessair 0:f269e3021894 178 return ssp_read(obj);
elessair 0:f269e3021894 179 }
elessair 0:f269e3021894 180
elessair 0:f269e3021894 181 int spi_slave_receive(spi_t *obj) {
elessair 0:f269e3021894 182 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
elessair 0:f269e3021894 183 }
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 int spi_slave_read(spi_t *obj) {
elessair 0:f269e3021894 186 return obj->spi->RXDAT;
elessair 0:f269e3021894 187 }
elessair 0:f269e3021894 188
elessair 0:f269e3021894 189 void spi_slave_write(spi_t *obj, int value) {
elessair 0:f269e3021894 190 while (ssp_writeable(obj) == 0) ;
elessair 0:f269e3021894 191 obj->spi->TXDAT = value;
elessair 0:f269e3021894 192 }
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 int spi_busy(spi_t *obj) {
elessair 0:f269e3021894 195 return ssp_busy(obj);
elessair 0:f269e3021894 196 }