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targets/TARGET_NXP/TARGET_LPC15XX/device/LPC15xx.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:: xuaner
Date:: Thu Jul 20 14:26:57 2017 +0000
Revision:: 1:3deb71413561
Parent:: 0:f269e3021894

mbed_os

Who changed what in which revision?

User	Revision	Line number	New contents of line
elessair	0:f269e3021894	1
elessair	0:f269e3021894	2	/**************************************************************************************************//
elessair	0:f269e3021894	3	* @file LPC15xx.h
elessair	0:f269e3021894	4	*
elessair	0:f269e3021894	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
elessair	0:f269e3021894	6	* LPC15xx from .
elessair	0:f269e3021894	7	*
elessair	0:f269e3021894	8	* @version V0.3
elessair	0:f269e3021894	9	* @date 17. July 2013
elessair	0:f269e3021894	10	*
elessair	0:f269e3021894	11	* @note Generated with SVDConv V2.80
elessair	0:f269e3021894	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
elessair	0:f269e3021894	13	*
elessair	0:f269e3021894	14	* modified by Keil
elessair	0:f269e3021894	15	* modified by ytsuboi
elessair	0:f269e3021894	16	*******************************************************************************************************/
elessair	0:f269e3021894	17
elessair	0:f269e3021894	18
elessair	0:f269e3021894	19
elessair	0:f269e3021894	20	/** @addtogroup (null)
elessair	0:f269e3021894	21	* @{
elessair	0:f269e3021894	22	*/
elessair	0:f269e3021894	23
elessair	0:f269e3021894	24	/** @addtogroup LPC15xx
elessair	0:f269e3021894	25	* @{
elessair	0:f269e3021894	26	*/
elessair	0:f269e3021894	27
elessair	0:f269e3021894	28	#ifndef LPC15XX_H
elessair	0:f269e3021894	29	#define LPC15XX_H
elessair	0:f269e3021894	30
elessair	0:f269e3021894	31	#ifdef __cplusplus
elessair	0:f269e3021894	32	extern "C" {
elessair	0:f269e3021894	33	#endif
elessair	0:f269e3021894	34
elessair	0:f269e3021894	35
elessair	0:f269e3021894	36	/* ------------------------- Interrupt Number Definition ------------------------ */
elessair	0:f269e3021894	37
elessair	0:f269e3021894	38	typedef enum {
elessair	0:f269e3021894	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
elessair	0:f269e3021894	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
elessair	0:f269e3021894	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
elessair	0:f269e3021894	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
elessair	0:f269e3021894	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
elessair	0:f269e3021894	44	and No Match */
elessair	0:f269e3021894	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
elessair	0:f269e3021894	46	related Fault */
elessair	0:f269e3021894	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
elessair	0:f269e3021894	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
elessair	0:f269e3021894	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
elessair	0:f269e3021894	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
elessair	0:f269e3021894	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
elessair	0:f269e3021894	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
elessair	0:f269e3021894	53	WDT_IRQn = 0, /!< 0 WDT /
elessair	0:f269e3021894	54	BOD_IRQn = 1, /!< 1 BOD /
elessair	0:f269e3021894	55	FLASH_IRQn = 2, /!< 2 FLASH /
elessair	0:f269e3021894	56	EE_IRQn = 3, /!< 3 EE /
elessair	0:f269e3021894	57	DMA_IRQn = 4, /!< 4 DMA /
elessair	0:f269e3021894	58	GINT0_IRQn = 5, /!< 5 GINT0 /
elessair	0:f269e3021894	59	GINT1_IRQn = 6, /!< 6 GINT1 /
elessair	0:f269e3021894	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
elessair	0:f269e3021894	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
elessair	0:f269e3021894	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
elessair	0:f269e3021894	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
elessair	0:f269e3021894	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
elessair	0:f269e3021894	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
elessair	0:f269e3021894	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
elessair	0:f269e3021894	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
elessair	0:f269e3021894	68	RIT_IRQn = 15, /!< 15 RIT /
elessair	0:f269e3021894	69	SCT0_IRQn = 16, /!< 16 SCT0 /
elessair	0:f269e3021894	70	SCT1_IRQn = 17, /!< 17 SCT1 /
elessair	0:f269e3021894	71	SCT2_IRQn = 18, /!< 18 SCT2 /
elessair	0:f269e3021894	72	SCT3_IRQn = 19, /!< 19 SCT3 /
elessair	0:f269e3021894	73	MRT_IRQn = 20, /!< 20 MRT /
elessair	0:f269e3021894	74	UART0_IRQn = 21, /!< 21 UART0 /
elessair	0:f269e3021894	75	UART1_IRQn = 22, /!< 22 UART1 /
elessair	0:f269e3021894	76	UART2_IRQn = 23, /!< 23 UART2 /
elessair	0:f269e3021894	77	I2C0_IRQn = 24, /!< 24 I2C0 /
elessair	0:f269e3021894	78	SPI0_IRQn = 25, /!< 25 SPI0 /
elessair	0:f269e3021894	79	SPI1_IRQn = 26, /!< 26 SPI1 /
elessair	0:f269e3021894	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
elessair	0:f269e3021894	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
elessair	0:f269e3021894	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
elessair	0:f269e3021894	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
elessair	0:f269e3021894	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
elessair	0:f269e3021894	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
elessair	0:f269e3021894	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
elessair	0:f269e3021894	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
elessair	0:f269e3021894	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
elessair	0:f269e3021894	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
elessair	0:f269e3021894	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
elessair	0:f269e3021894	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
elessair	0:f269e3021894	92	DAC_IRQn = 39, /!< 39 DAC /
elessair	0:f269e3021894	93	CMP0_IRQn = 40, /!< 40 CMP0 /
elessair	0:f269e3021894	94	CMP1_IRQn = 41, /!< 41 CMP1 /
elessair	0:f269e3021894	95	CMP2_IRQn = 42, /!< 42 CMP2 /
elessair	0:f269e3021894	96	CMP3_IRQn = 43, /!< 43 CMP3 /
elessair	0:f269e3021894	97	QEI_IRQn = 44, /!< 44 QEI /
elessair	0:f269e3021894	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
elessair	0:f269e3021894	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
elessair	0:f269e3021894	100	} IRQn_Type;
elessair	0:f269e3021894	101
elessair	0:f269e3021894	102
elessair	0:f269e3021894	103	/** @addtogroup Configuration_of_CMSIS
elessair	0:f269e3021894	104	* @{
elessair	0:f269e3021894	105	*/
elessair	0:f269e3021894	106
elessair	0:f269e3021894	107
elessair	0:f269e3021894	108	/* ================================================================================ */
elessair	0:f269e3021894	109	/* ================ Processor and Core Peripheral Section ================ */
elessair	0:f269e3021894	110	/* ================================================================================ */
elessair	0:f269e3021894	111
elessair	0:f269e3021894	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
elessair	0:f269e3021894	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
elessair	0:f269e3021894	114	#define __MPU_PRESENT 0 /!< MPU present or not /
elessair	0:f269e3021894	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
elessair	0:f269e3021894	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
elessair	0:f269e3021894	117	/** @} / / End of group Configuration_of_CMSIS */
elessair	0:f269e3021894	118
elessair	0:f269e3021894	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
elessair	0:f269e3021894	120	#include "system_LPC15xx.h" /!< LPC15xx System /
elessair	0:f269e3021894	121
elessair	0:f269e3021894	122
elessair	0:f269e3021894	123	/* ================================================================================ */
elessair	0:f269e3021894	124	/* ================ Device Specific Peripheral Section ================ */
elessair	0:f269e3021894	125	/* ================================================================================ */
elessair	0:f269e3021894	126
elessair	0:f269e3021894	127
elessair	0:f269e3021894	128	/** @addtogroup Device_Peripheral_Registers
elessair	0:f269e3021894	129	* @{
elessair	0:f269e3021894	130	*/
elessair	0:f269e3021894	131
elessair	0:f269e3021894	132
elessair	0:f269e3021894	133	/* ------------------- Start of section using anonymous unions ------------------ */
elessair	0:f269e3021894	134	#if defined(__CC_ARM)
elessair	0:f269e3021894	135	#pragma push
elessair	0:f269e3021894	136	#pragma anon_unions
elessair	0:f269e3021894	137	#elif defined(__ICCARM__)
elessair	0:f269e3021894	138	#pragma language=extended
elessair	0:f269e3021894	139	#elif defined(__GNUC__)
elessair	0:f269e3021894	140	/* anonymous unions are enabled by default */
elessair	0:f269e3021894	141	#elif defined(__TMS470__)
elessair	0:f269e3021894	142	/* anonymous unions are enabled by default */
elessair	0:f269e3021894	143	#elif defined(__TASKING__)
elessair	0:f269e3021894	144	#pragma warning 586
elessair	0:f269e3021894	145	#else
elessair	0:f269e3021894	146	#warning Not supported compiler type
elessair	0:f269e3021894	147	#endif
elessair	0:f269e3021894	148
elessair	0:f269e3021894	149
elessair	0:f269e3021894	150
elessair	0:f269e3021894	151	/* ================================================================================ */
elessair	0:f269e3021894	152	/* ================ GPIO_PORT ================ */
elessair	0:f269e3021894	153	/* ================================================================================ */
elessair	0:f269e3021894	154
elessair	0:f269e3021894	155
elessair	0:f269e3021894	156	/**
elessair	0:f269e3021894	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
elessair	0:f269e3021894	158	*/
elessair	0:f269e3021894	159
elessair	0:f269e3021894	160	typedef struct { /!< GPIO_PORT Structure /
elessair	0:f269e3021894	161	__IO uint8_t B[76]; /!< Byte pin registers /
elessair	0:f269e3021894	162	__I uint32_t RESERVED0[1005];
elessair	0:f269e3021894	163	__IO uint32_t W[76]; /!< Word pin registers /
elessair	0:f269e3021894	164	__I uint32_t RESERVED1[948];
elessair	0:f269e3021894	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
elessair	0:f269e3021894	166	__I uint32_t RESERVED2[29];
elessair	0:f269e3021894	167	__IO uint32_t MASK[3]; /!< Port Mask register /
elessair	0:f269e3021894	168	__I uint32_t RESERVED3[29];
elessair	0:f269e3021894	169	__IO uint32_t PIN[3]; /!< Port pin register /
elessair	0:f269e3021894	170	__I uint32_t RESERVED4[29];
elessair	0:f269e3021894	171	__IO uint32_t MPIN[3]; /!< Masked port register /
elessair	0:f269e3021894	172	__I uint32_t RESERVED5[29];
elessair	0:f269e3021894	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
elessair	0:f269e3021894	174	__I uint32_t RESERVED6[29];
elessair	0:f269e3021894	175	__O uint32_t CLR[3]; /!< Clear port /
elessair	0:f269e3021894	176	__I uint32_t RESERVED7[29];
elessair	0:f269e3021894	177	__O uint32_t NOT[3]; /!< Toggle port /
elessair	0:f269e3021894	178	} LPC_GPIO_PORT_Type;
elessair	0:f269e3021894	179
elessair	0:f269e3021894	180
elessair	0:f269e3021894	181	/* ================================================================================ */
elessair	0:f269e3021894	182	/* ================ DMA ================ */
elessair	0:f269e3021894	183	/* ================================================================================ */
elessair	0:f269e3021894	184
elessair	0:f269e3021894	185
elessair	0:f269e3021894	186	/**
elessair	0:f269e3021894	187	* @brief DMA controller (DMA)
elessair	0:f269e3021894	188	*/
elessair	0:f269e3021894	189
elessair	0:f269e3021894	190	typedef struct { /!< DMA Structure /
elessair	0:f269e3021894	191	__IO uint32_t CTRL; /!< DMA control. /
elessair	0:f269e3021894	192	__I uint32_t INTSTAT; /!< Interrupt status. /
elessair	0:f269e3021894	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
elessair	0:f269e3021894	194	__I uint32_t RESERVED0[5];
elessair	0:f269e3021894	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
elessair	0:f269e3021894	196	__I uint32_t RESERVED1;
elessair	0:f269e3021894	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
elessair	0:f269e3021894	198	__I uint32_t RESERVED2;
elessair	0:f269e3021894	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
elessair	0:f269e3021894	200	__I uint32_t RESERVED3;
elessair	0:f269e3021894	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
elessair	0:f269e3021894	202	__I uint32_t RESERVED4;
elessair	0:f269e3021894	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
elessair	0:f269e3021894	204	__I uint32_t RESERVED5;
elessair	0:f269e3021894	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
elessair	0:f269e3021894	206	__I uint32_t RESERVED6;
elessair	0:f269e3021894	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
elessair	0:f269e3021894	208	__I uint32_t RESERVED7;
elessair	0:f269e3021894	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
elessair	0:f269e3021894	210	__I uint32_t RESERVED8;
elessair	0:f269e3021894	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
elessair	0:f269e3021894	212	__I uint32_t RESERVED9;
elessair	0:f269e3021894	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
elessair	0:f269e3021894	214	__I uint32_t RESERVED10;
elessair	0:f269e3021894	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
elessair	0:f269e3021894	216	__I uint32_t RESERVED11;
elessair	0:f269e3021894	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
elessair	0:f269e3021894	218	__I uint32_t RESERVED12[225];
elessair	0:f269e3021894	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	222	__I uint32_t RESERVED13;
elessair	0:f269e3021894	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	226	__I uint32_t RESERVED14;
elessair	0:f269e3021894	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	230	__I uint32_t RESERVED15;
elessair	0:f269e3021894	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	234	__I uint32_t RESERVED16;
elessair	0:f269e3021894	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	238	__I uint32_t RESERVED17;
elessair	0:f269e3021894	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	242	__I uint32_t RESERVED18;
elessair	0:f269e3021894	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	246	__I uint32_t RESERVED19;
elessair	0:f269e3021894	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	250	__I uint32_t RESERVED20;
elessair	0:f269e3021894	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	254	__I uint32_t RESERVED21;
elessair	0:f269e3021894	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	258	__I uint32_t RESERVED22;
elessair	0:f269e3021894	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	262	__I uint32_t RESERVED23;
elessair	0:f269e3021894	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	266	__I uint32_t RESERVED24;
elessair	0:f269e3021894	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	270	__I uint32_t RESERVED25;
elessair	0:f269e3021894	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	274	__I uint32_t RESERVED26;
elessair	0:f269e3021894	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	278	__I uint32_t RESERVED27;
elessair	0:f269e3021894	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	282	__I uint32_t RESERVED28;
elessair	0:f269e3021894	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	286	__I uint32_t RESERVED29;
elessair	0:f269e3021894	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
elessair	0:f269e3021894	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
elessair	0:f269e3021894	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
elessair	0:f269e3021894	290	} LPC_DMA_Type;
elessair	0:f269e3021894	291
elessair	0:f269e3021894	292
elessair	0:f269e3021894	293	/* ================================================================================ */
elessair	0:f269e3021894	294	/* ================ USB ================ */
elessair	0:f269e3021894	295	/* ================================================================================ */
elessair	0:f269e3021894	296
elessair	0:f269e3021894	297
elessair	0:f269e3021894	298	/**
elessair	0:f269e3021894	299	* @brief USB device controller (USB)
elessair	0:f269e3021894	300	*/
elessair	0:f269e3021894	301
elessair	0:f269e3021894	302	typedef struct { /!< USB Structure /
elessair	0:f269e3021894	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
elessair	0:f269e3021894	304	__IO uint32_t INFO; /!< USB Info register /
elessair	0:f269e3021894	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
elessair	0:f269e3021894	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
elessair	0:f269e3021894	307	__IO uint32_t LPM; /!< Link Power Management register /
elessair	0:f269e3021894	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
elessair	0:f269e3021894	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
elessair	0:f269e3021894	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
elessair	0:f269e3021894	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
elessair	0:f269e3021894	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
elessair	0:f269e3021894	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
elessair	0:f269e3021894	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
elessair	0:f269e3021894	315	__I uint32_t RESERVED0;
elessair	0:f269e3021894	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
elessair	0:f269e3021894	317	} LPC_USB_Type;
elessair	0:f269e3021894	318
elessair	0:f269e3021894	319
elessair	0:f269e3021894	320	/* ================================================================================ */
elessair	0:f269e3021894	321	/* ================ CRC ================ */
elessair	0:f269e3021894	322	/* ================================================================================ */
elessair	0:f269e3021894	323
elessair	0:f269e3021894	324
elessair	0:f269e3021894	325	/**
elessair	0:f269e3021894	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
elessair	0:f269e3021894	327	*/
elessair	0:f269e3021894	328
elessair	0:f269e3021894	329	typedef struct { /!< CRC Structure /
elessair	0:f269e3021894	330	__IO uint32_t MODE; /!< CRC mode register /
elessair	0:f269e3021894	331	__IO uint32_t SEED; /!< CRC seed register /
elessair	0:f269e3021894	332
elessair	0:f269e3021894	333	union {
elessair	0:f269e3021894	334	__O uint32_t WR_DATA; /!< CRC data register /
elessair	0:f269e3021894	335	__I uint32_t SUM; /!< CRC checksum register /
elessair	0:f269e3021894	336	};
elessair	0:f269e3021894	337	} LPC_CRC_Type;
elessair	0:f269e3021894	338
elessair	0:f269e3021894	339
elessair	0:f269e3021894	340	/* ================================================================================ */
elessair	0:f269e3021894	341	/* ================ SCT0 ================ */
elessair	0:f269e3021894	342	/* ================================================================================ */
elessair	0:f269e3021894	343
elessair	0:f269e3021894	344
elessair	0:f269e3021894	345	/**
elessair	0:f269e3021894	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
elessair	0:f269e3021894	347	*/
elessair	0:f269e3021894	348
elessair	0:f269e3021894	349	typedef struct { /!< SCT0 Structure /
elessair	0:f269e3021894	350	__IO uint32_t CONFIG; /!< SCT configuration register /
elessair	0:f269e3021894	351	__IO uint32_t CTRL; /!< SCT control register /
elessair	0:f269e3021894	352	__IO uint32_t LIMIT; /!< SCT limit register /
elessair	0:f269e3021894	353	__IO uint32_t HALT; /!< SCT halt condition register /
elessair	0:f269e3021894	354	__IO uint32_t STOP; /!< SCT stop condition register /
elessair	0:f269e3021894	355	__IO uint32_t START; /!< SCT start condition register /
elessair	0:f269e3021894	356	__IO uint32_t DITHER; /!< SCT dither condition register /
elessair	0:f269e3021894	357	__I uint32_t RESERVED0[9];
elessair	0:f269e3021894	358	__IO uint32_t COUNT; /!< SCT counter register /
elessair	0:f269e3021894	359	__IO uint32_t STATE; /!< SCT state register /
elessair	0:f269e3021894	360	__I uint32_t INPUT; /!< SCT input register /
elessair	0:f269e3021894	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
elessair	0:f269e3021894	362	__IO uint32_t OUTPUT; /!< SCT output register /
elessair	0:f269e3021894	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
elessair	0:f269e3021894	364	__IO uint32_t RES; /!< SCT conflict resolution register /
elessair	0:f269e3021894	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
elessair	0:f269e3021894	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
elessair	0:f269e3021894	367	__I uint32_t RESERVED1[35];
elessair	0:f269e3021894	368	__IO uint32_t EVEN; /!< SCT event enable register /
elessair	0:f269e3021894	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
elessair	0:f269e3021894	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
elessair	0:f269e3021894	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
elessair	0:f269e3021894	372
elessair	0:f269e3021894	373	union {
elessair	0:f269e3021894	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	375	REGMODE15 = 1 */
elessair	0:f269e3021894	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	377	to REGMODE15 = 0 */
elessair	0:f269e3021894	378	};
elessair	0:f269e3021894	379
elessair	0:f269e3021894	380	union {
elessair	0:f269e3021894	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	382	REGMODE15 = 1 */
elessair	0:f269e3021894	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	384	to REGMODE15 = 0 */
elessair	0:f269e3021894	385	};
elessair	0:f269e3021894	386
elessair	0:f269e3021894	387	union {
elessair	0:f269e3021894	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	389	REGMODE15 = 1 */
elessair	0:f269e3021894	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	391	to REGMODE15 = 0 */
elessair	0:f269e3021894	392	};
elessair	0:f269e3021894	393
elessair	0:f269e3021894	394	union {
elessair	0:f269e3021894	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	396	REGMODE15 = 1 */
elessair	0:f269e3021894	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	398	to REGMODE15 = 0 */
elessair	0:f269e3021894	399	};
elessair	0:f269e3021894	400
elessair	0:f269e3021894	401	union {
elessair	0:f269e3021894	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	403	REGMODE15 = 1 */
elessair	0:f269e3021894	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	405	to REGMODE15 = 0 */
elessair	0:f269e3021894	406	};
elessair	0:f269e3021894	407
elessair	0:f269e3021894	408	union {
elessair	0:f269e3021894	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	410	REGMODE15 = 1 */
elessair	0:f269e3021894	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	412	to REGMODE15 = 0 */
elessair	0:f269e3021894	413	};
elessair	0:f269e3021894	414
elessair	0:f269e3021894	415	union {
elessair	0:f269e3021894	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	417	REGMODE15 = 1 */
elessair	0:f269e3021894	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	419	to REGMODE15 = 0 */
elessair	0:f269e3021894	420	};
elessair	0:f269e3021894	421
elessair	0:f269e3021894	422	union {
elessair	0:f269e3021894	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	424	to REGMODE15 = 0 */
elessair	0:f269e3021894	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	426	REGMODE15 = 1 */
elessair	0:f269e3021894	427	};
elessair	0:f269e3021894	428
elessair	0:f269e3021894	429	union {
elessair	0:f269e3021894	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	431	REGMODE15 = 1 */
elessair	0:f269e3021894	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	433	to REGMODE15 = 0 */
elessair	0:f269e3021894	434	};
elessair	0:f269e3021894	435
elessair	0:f269e3021894	436	union {
elessair	0:f269e3021894	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	438	to REGMODE15 = 0 */
elessair	0:f269e3021894	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	440	REGMODE15 = 1 */
elessair	0:f269e3021894	441	};
elessair	0:f269e3021894	442
elessair	0:f269e3021894	443	union {
elessair	0:f269e3021894	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	445	to REGMODE15 = 0 */
elessair	0:f269e3021894	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	447	REGMODE15 = 1 */
elessair	0:f269e3021894	448	};
elessair	0:f269e3021894	449
elessair	0:f269e3021894	450	union {
elessair	0:f269e3021894	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	452	to REGMODE15 = 0 */
elessair	0:f269e3021894	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	454	REGMODE15 = 1 */
elessair	0:f269e3021894	455	};
elessair	0:f269e3021894	456
elessair	0:f269e3021894	457	union {
elessair	0:f269e3021894	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	459	to REGMODE15 = 0 */
elessair	0:f269e3021894	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	461	REGMODE15 = 1 */
elessair	0:f269e3021894	462	};
elessair	0:f269e3021894	463
elessair	0:f269e3021894	464	union {
elessair	0:f269e3021894	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	466	to REGMODE15 = 0 */
elessair	0:f269e3021894	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	468	REGMODE15 = 1 */
elessair	0:f269e3021894	469	};
elessair	0:f269e3021894	470
elessair	0:f269e3021894	471	union {
elessair	0:f269e3021894	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	473	REGMODE15 = 1 */
elessair	0:f269e3021894	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	475	to REGMODE15 = 0 */
elessair	0:f269e3021894	476	};
elessair	0:f269e3021894	477
elessair	0:f269e3021894	478	union {
elessair	0:f269e3021894	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
elessair	0:f269e3021894	480	to REGMODE15 = 0 */
elessair	0:f269e3021894	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
elessair	0:f269e3021894	482	REGMODE15 = 1 */
elessair	0:f269e3021894	483	};
elessair	0:f269e3021894	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	485	0 to 5. */
elessair	0:f269e3021894	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	487	0 to 5. */
elessair	0:f269e3021894	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	489	0 to 5. */
elessair	0:f269e3021894	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	491	0 to 5. */
elessair	0:f269e3021894	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	493	0 to 5. */
elessair	0:f269e3021894	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
elessair	0:f269e3021894	495	0 to 5. */
elessair	0:f269e3021894	496	__I uint32_t RESERVED2[42];
elessair	0:f269e3021894	497
elessair	0:f269e3021894	498	union {
elessair	0:f269e3021894	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	500	= 1 */
elessair	0:f269e3021894	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	502	= 0 */
elessair	0:f269e3021894	503	};
elessair	0:f269e3021894	504
elessair	0:f269e3021894	505	union {
elessair	0:f269e3021894	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	507	= 0 */
elessair	0:f269e3021894	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	509	= 1 */
elessair	0:f269e3021894	510	};
elessair	0:f269e3021894	511
elessair	0:f269e3021894	512	union {
elessair	0:f269e3021894	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	514	= 0 */
elessair	0:f269e3021894	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	516	= 1 */
elessair	0:f269e3021894	517	};
elessair	0:f269e3021894	518
elessair	0:f269e3021894	519	union {
elessair	0:f269e3021894	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	521	= 1 */
elessair	0:f269e3021894	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	523	= 0 */
elessair	0:f269e3021894	524	};
elessair	0:f269e3021894	525
elessair	0:f269e3021894	526	union {
elessair	0:f269e3021894	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	528	= 1 */
elessair	0:f269e3021894	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	530	= 0 */
elessair	0:f269e3021894	531	};
elessair	0:f269e3021894	532
elessair	0:f269e3021894	533	union {
elessair	0:f269e3021894	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	535	= 1 */
elessair	0:f269e3021894	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	537	= 0 */
elessair	0:f269e3021894	538	};
elessair	0:f269e3021894	539
elessair	0:f269e3021894	540	union {
elessair	0:f269e3021894	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	542	= 0 */
elessair	0:f269e3021894	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	544	= 1 */
elessair	0:f269e3021894	545	};
elessair	0:f269e3021894	546
elessair	0:f269e3021894	547	union {
elessair	0:f269e3021894	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	549	= 0 */
elessair	0:f269e3021894	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	551	= 1 */
elessair	0:f269e3021894	552	};
elessair	0:f269e3021894	553
elessair	0:f269e3021894	554	union {
elessair	0:f269e3021894	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	556	= 1 */
elessair	0:f269e3021894	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	558	= 0 */
elessair	0:f269e3021894	559	};
elessair	0:f269e3021894	560
elessair	0:f269e3021894	561	union {
elessair	0:f269e3021894	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	563	= 1 */
elessair	0:f269e3021894	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	565	= 0 */
elessair	0:f269e3021894	566	};
elessair	0:f269e3021894	567
elessair	0:f269e3021894	568	union {
elessair	0:f269e3021894	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	570	= 1 */
elessair	0:f269e3021894	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	572	= 0 */
elessair	0:f269e3021894	573	};
elessair	0:f269e3021894	574
elessair	0:f269e3021894	575	union {
elessair	0:f269e3021894	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	577	= 1 */
elessair	0:f269e3021894	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	579	= 0 */
elessair	0:f269e3021894	580	};
elessair	0:f269e3021894	581
elessair	0:f269e3021894	582	union {
elessair	0:f269e3021894	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	584	= 0 */
elessair	0:f269e3021894	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	586	= 1 */
elessair	0:f269e3021894	587	};
elessair	0:f269e3021894	588
elessair	0:f269e3021894	589	union {
elessair	0:f269e3021894	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	591	= 0 */
elessair	0:f269e3021894	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	593	= 1 */
elessair	0:f269e3021894	594	};
elessair	0:f269e3021894	595
elessair	0:f269e3021894	596	union {
elessair	0:f269e3021894	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	598	= 1 */
elessair	0:f269e3021894	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	600	= 0 */
elessair	0:f269e3021894	601	};
elessair	0:f269e3021894	602
elessair	0:f269e3021894	603	union {
elessair	0:f269e3021894	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
elessair	0:f269e3021894	605	= 1 */
elessair	0:f269e3021894	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
elessair	0:f269e3021894	607	= 0 */
elessair	0:f269e3021894	608	};
elessair	0:f269e3021894	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	610	registers 0 to 5. */
elessair	0:f269e3021894	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	612	registers 0 to 5. */
elessair	0:f269e3021894	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	614	registers 0 to 5. */
elessair	0:f269e3021894	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	616	registers 0 to 5. */
elessair	0:f269e3021894	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	618	registers 0 to 5. */
elessair	0:f269e3021894	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
elessair	0:f269e3021894	620	registers 0 to 5. */
elessair	0:f269e3021894	621	__I uint32_t RESERVED3[42];
elessair	0:f269e3021894	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	654	__I uint32_t RESERVED4[96];
elessair	0:f269e3021894	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	675	} LPC_SCT0_Type;
elessair	0:f269e3021894	676
elessair	0:f269e3021894	677
elessair	0:f269e3021894	678	/* ================================================================================ */
elessair	0:f269e3021894	679	/* ================ SCT2 ================ */
elessair	0:f269e3021894	680	/* ================================================================================ */
elessair	0:f269e3021894	681
elessair	0:f269e3021894	682
elessair	0:f269e3021894	683	/**
elessair	0:f269e3021894	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
elessair	0:f269e3021894	685	*/
elessair	0:f269e3021894	686
elessair	0:f269e3021894	687	typedef struct { /!< SCT2 Structure /
elessair	0:f269e3021894	688	__IO uint32_t CONFIG; /!< SCT configuration register /
elessair	0:f269e3021894	689	__IO uint32_t CTRL; /!< SCT control register /
elessair	0:f269e3021894	690	__IO uint32_t LIMIT; /!< SCT limit register /
elessair	0:f269e3021894	691	__IO uint32_t HALT; /!< SCT halt condition register /
elessair	0:f269e3021894	692	__IO uint32_t STOP; /!< SCT stop condition register /
elessair	0:f269e3021894	693	__IO uint32_t START; /!< SCT start condition register /
elessair	0:f269e3021894	694	__I uint32_t RESERVED0[10];
elessair	0:f269e3021894	695	__IO uint32_t COUNT; /!< SCT counter register /
elessair	0:f269e3021894	696	__IO uint32_t STATE; /!< SCT state register /
elessair	0:f269e3021894	697	__I uint32_t INPUT; /!< SCT input register /
elessair	0:f269e3021894	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
elessair	0:f269e3021894	699	__IO uint32_t OUTPUT; /!< SCT output register /
elessair	0:f269e3021894	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
elessair	0:f269e3021894	701	__IO uint32_t RES; /!< SCT conflict resolution register /
elessair	0:f269e3021894	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
elessair	0:f269e3021894	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
elessair	0:f269e3021894	704	__I uint32_t RESERVED1[35];
elessair	0:f269e3021894	705	__IO uint32_t EVEN; /!< SCT event enable register /
elessair	0:f269e3021894	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
elessair	0:f269e3021894	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
elessair	0:f269e3021894	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
elessair	0:f269e3021894	709
elessair	0:f269e3021894	710	union {
elessair	0:f269e3021894	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	712	= 1 */
elessair	0:f269e3021894	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	714	REGMODE7 = 0 */
elessair	0:f269e3021894	715	};
elessair	0:f269e3021894	716
elessair	0:f269e3021894	717	union {
elessair	0:f269e3021894	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	719	= 1 */
elessair	0:f269e3021894	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	721	REGMODE7 = 0 */
elessair	0:f269e3021894	722	};
elessair	0:f269e3021894	723
elessair	0:f269e3021894	724	union {
elessair	0:f269e3021894	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	726	= 1 */
elessair	0:f269e3021894	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	728	REGMODE7 = 0 */
elessair	0:f269e3021894	729	};
elessair	0:f269e3021894	730
elessair	0:f269e3021894	731	union {
elessair	0:f269e3021894	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	733	REGMODE7 = 0 */
elessair	0:f269e3021894	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	735	= 1 */
elessair	0:f269e3021894	736	};
elessair	0:f269e3021894	737
elessair	0:f269e3021894	738	union {
elessair	0:f269e3021894	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	740	= 1 */
elessair	0:f269e3021894	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	742	REGMODE7 = 0 */
elessair	0:f269e3021894	743	};
elessair	0:f269e3021894	744
elessair	0:f269e3021894	745	union {
elessair	0:f269e3021894	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	747	REGMODE7 = 0 */
elessair	0:f269e3021894	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	749	= 1 */
elessair	0:f269e3021894	750	};
elessair	0:f269e3021894	751
elessair	0:f269e3021894	752	union {
elessair	0:f269e3021894	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	754	= 1 */
elessair	0:f269e3021894	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	756	REGMODE7 = 0 */
elessair	0:f269e3021894	757	};
elessair	0:f269e3021894	758
elessair	0:f269e3021894	759	union {
elessair	0:f269e3021894	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
elessair	0:f269e3021894	761	= 1 */
elessair	0:f269e3021894	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
elessair	0:f269e3021894	763	REGMODE7 = 0 */
elessair	0:f269e3021894	764	};
elessair	0:f269e3021894	765	__I uint32_t RESERVED2[56];
elessair	0:f269e3021894	766
elessair	0:f269e3021894	767	union {
elessair	0:f269e3021894	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	769	= 1 */
elessair	0:f269e3021894	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	771	= 0 */
elessair	0:f269e3021894	772	};
elessair	0:f269e3021894	773
elessair	0:f269e3021894	774	union {
elessair	0:f269e3021894	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	776	= 1 */
elessair	0:f269e3021894	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	778	= 0 */
elessair	0:f269e3021894	779	};
elessair	0:f269e3021894	780
elessair	0:f269e3021894	781	union {
elessair	0:f269e3021894	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	783	= 1 */
elessair	0:f269e3021894	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	785	= 0 */
elessair	0:f269e3021894	786	};
elessair	0:f269e3021894	787
elessair	0:f269e3021894	788	union {
elessair	0:f269e3021894	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	790	= 0 */
elessair	0:f269e3021894	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	792	= 1 */
elessair	0:f269e3021894	793	};
elessair	0:f269e3021894	794
elessair	0:f269e3021894	795	union {
elessair	0:f269e3021894	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	797	= 1 */
elessair	0:f269e3021894	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	799	= 0 */
elessair	0:f269e3021894	800	};
elessair	0:f269e3021894	801
elessair	0:f269e3021894	802	union {
elessair	0:f269e3021894	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	804	= 0 */
elessair	0:f269e3021894	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	806	= 1 */
elessair	0:f269e3021894	807	};
elessair	0:f269e3021894	808
elessair	0:f269e3021894	809	union {
elessair	0:f269e3021894	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	811	= 1 */
elessair	0:f269e3021894	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	813	= 0 */
elessair	0:f269e3021894	814	};
elessair	0:f269e3021894	815
elessair	0:f269e3021894	816	union {
elessair	0:f269e3021894	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
elessair	0:f269e3021894	818	= 1 */
elessair	0:f269e3021894	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
elessair	0:f269e3021894	820	= 0 */
elessair	0:f269e3021894	821	};
elessair	0:f269e3021894	822	__I uint32_t RESERVED3[56];
elessair	0:f269e3021894	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
elessair	0:f269e3021894	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
elessair	0:f269e3021894	843	__I uint32_t RESERVED4[108];
elessair	0:f269e3021894	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
elessair	0:f269e3021894	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
elessair	0:f269e3021894	856	} LPC_SCT2_Type;
elessair	0:f269e3021894	857
elessair	0:f269e3021894	858
elessair	0:f269e3021894	859	/* ================================================================================ */
elessair	0:f269e3021894	860	/* ================ ADC0 ================ */
elessair	0:f269e3021894	861	/* ================================================================================ */
elessair	0:f269e3021894	862
elessair	0:f269e3021894	863
elessair	0:f269e3021894	864	/**
elessair	0:f269e3021894	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
elessair	0:f269e3021894	866	*/
elessair	0:f269e3021894	867
elessair	0:f269e3021894	868	typedef struct { /!< ADC0 Structure /
elessair	0:f269e3021894	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
elessair	0:f269e3021894	870	bits for each sequence and the A/D power-down bit. */
elessair	0:f269e3021894	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
elessair	0:f269e3021894	872	internal source for various channels */
elessair	0:f269e3021894	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
elessair	0:f269e3021894	874	and channel selection for conversion sequence-A. Also specifies
elessair	0:f269e3021894	875	interrupt mode for sequence-A. */
elessair	0:f269e3021894	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
elessair	0:f269e3021894	877	and channel selection for conversion sequence-B. Also specifies
elessair	0:f269e3021894	878	interrupt mode for sequence-B. */
elessair	0:f269e3021894	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
elessair	0:f269e3021894	880	the result of the most recent A/D conversion performed under
elessair	0:f269e3021894	881	sequence-A */
elessair	0:f269e3021894	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
elessair	0:f269e3021894	883	the result of the most recent A/D conversion performed under
elessair	0:f269e3021894	884	sequence-B */
elessair	0:f269e3021894	885	__I uint32_t RESERVED0[2];
elessair	0:f269e3021894	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
elessair	0:f269e3021894	887	of the most recent conversion completed on channel 0. */
elessair	0:f269e3021894	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
elessair	0:f269e3021894	889	level for automatic threshold comparison for any channels linked
elessair	0:f269e3021894	890	to threshold pair 0. */
elessair	0:f269e3021894	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
elessair	0:f269e3021894	892	level for automatic threshold comparison for any channels linked
elessair	0:f269e3021894	893	to threshold pair 1. */
elessair	0:f269e3021894	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
elessair	0:f269e3021894	895	level for automatic threshold comparison for any channels linked
elessair	0:f269e3021894	896	to threshold pair 0. */
elessair	0:f269e3021894	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
elessair	0:f269e3021894	898	level for automatic threshold comparison for any channels linked
elessair	0:f269e3021894	899	to threshold pair 1. */
elessair	0:f269e3021894	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
elessair	0:f269e3021894	901	threshold compare registers are to be used for each channel */
elessair	0:f269e3021894	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
elessair	0:f269e3021894	903	bits that enable the sequence-A, sequence-B, threshold compare
elessair	0:f269e3021894	904	and data overrun interrupts to be generated. */
elessair	0:f269e3021894	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
elessair	0:f269e3021894	906	and the individual component overrun and threshold-compare flags.
elessair	0:f269e3021894	907	(The overrun bits replicate information stored in the result
elessair	0:f269e3021894	908	registers). */
elessair	0:f269e3021894	909	__IO uint32_t TRM; /!< ADC trim register. /
elessair	0:f269e3021894	910	} LPC_ADC0_Type;
elessair	0:f269e3021894	911
elessair	0:f269e3021894	912
elessair	0:f269e3021894	913	/* ================================================================================ */
elessair	0:f269e3021894	914	/* ================ DAC ================ */
elessair	0:f269e3021894	915	/* ================================================================================ */
elessair	0:f269e3021894	916
elessair	0:f269e3021894	917
elessair	0:f269e3021894	918	/**
elessair	0:f269e3021894	919	* @brief 12-bit DAC Modification (DAC)
elessair	0:f269e3021894	920	*/
elessair	0:f269e3021894	921
elessair	0:f269e3021894	922	typedef struct { /!< DAC Structure /
elessair	0:f269e3021894	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
elessair	0:f269e3021894	924	value to be converted to analog. */
elessair	0:f269e3021894	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
elessair	0:f269e3021894	926	DAC operation and the interrupt/dma request flag. */
elessair	0:f269e3021894	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
elessair	0:f269e3021894	928	value for the internal DAC DMA/Interrupt timer. */
elessair	0:f269e3021894	929	} LPC_DAC_Type;
elessair	0:f269e3021894	930
elessair	0:f269e3021894	931
elessair	0:f269e3021894	932	/* ================================================================================ */
elessair	0:f269e3021894	933	/* ================ ACMP ================ */
elessair	0:f269e3021894	934	/* ================================================================================ */
elessair	0:f269e3021894	935
elessair	0:f269e3021894	936
elessair	0:f269e3021894	937	/**
elessair	0:f269e3021894	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
elessair	0:f269e3021894	939	*/
elessair	0:f269e3021894	940
elessair	0:f269e3021894	941	typedef struct { /!< ACMP Structure /
elessair	0:f269e3021894	942	__IO uint32_t CTRL; /!< Comparator block control register /
elessair	0:f269e3021894	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
elessair	0:f269e3021894	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
elessair	0:f269e3021894	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
elessair	0:f269e3021894	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
elessair	0:f269e3021894	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
elessair	0:f269e3021894	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
elessair	0:f269e3021894	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
elessair	0:f269e3021894	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
elessair	0:f269e3021894	951	} LPC_ACMP_Type;
elessair	0:f269e3021894	952
elessair	0:f269e3021894	953
elessair	0:f269e3021894	954	/* ================================================================================ */
elessair	0:f269e3021894	955	/* ================ INMUX ================ */
elessair	0:f269e3021894	956	/* ================================================================================ */
elessair	0:f269e3021894	957
elessair	0:f269e3021894	958
elessair	0:f269e3021894	959	/**
elessair	0:f269e3021894	960	* @brief Input multiplexing (INMUX) (INMUX)
elessair	0:f269e3021894	961	*/
elessair	0:f269e3021894	962
elessair	0:f269e3021894	963	typedef struct { /!< INMUX Structure /
elessair	0:f269e3021894	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
elessair	0:f269e3021894	965	__I uint32_t RESERVED0;
elessair	0:f269e3021894	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
elessair	0:f269e3021894	967	__I uint32_t RESERVED1;
elessair	0:f269e3021894	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
elessair	0:f269e3021894	969	__I uint32_t RESERVED2[5];
elessair	0:f269e3021894	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
elessair	0:f269e3021894	971	__I uint32_t RESERVED3[21];
elessair	0:f269e3021894	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
elessair	0:f269e3021894	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
elessair	0:f269e3021894	974	__I uint32_t RESERVED4[14];
elessair	0:f269e3021894	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
elessair	0:f269e3021894	976	clock */
elessair	0:f269e3021894	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
elessair	0:f269e3021894	978	} LPC_INMUX_Type;
elessair	0:f269e3021894	979
elessair	0:f269e3021894	980
elessair	0:f269e3021894	981	/* ================================================================================ */
elessair	0:f269e3021894	982	/* ================ RTC ================ */
elessair	0:f269e3021894	983	/* ================================================================================ */
elessair	0:f269e3021894	984
elessair	0:f269e3021894	985
elessair	0:f269e3021894	986	/**
elessair	0:f269e3021894	987	* @brief Real-Time Clock (RTC) (RTC)
elessair	0:f269e3021894	988	*/
elessair	0:f269e3021894	989
elessair	0:f269e3021894	990	typedef struct { /!< RTC Structure /
elessair	0:f269e3021894	991	__IO uint32_t CTRL; /!< RTC control register /
elessair	0:f269e3021894	992	__IO uint32_t MATCH; /!< RTC match register /
elessair	0:f269e3021894	993	__IO uint32_t COUNT; /!< RTC counter register /
elessair	0:f269e3021894	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
elessair	0:f269e3021894	995	} LPC_RTC_Type;
elessair	0:f269e3021894	996
elessair	0:f269e3021894	997
elessair	0:f269e3021894	998	/* ================================================================================ */
elessair	0:f269e3021894	999	/* ================ WWDT ================ */
elessair	0:f269e3021894	1000	/* ================================================================================ */
elessair	0:f269e3021894	1001
elessair	0:f269e3021894	1002
elessair	0:f269e3021894	1003	/**
elessair	0:f269e3021894	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
elessair	0:f269e3021894	1005	*/
elessair	0:f269e3021894	1006
elessair	0:f269e3021894	1007	typedef struct { /!< WWDT Structure /
elessair	0:f269e3021894	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
elessair	0:f269e3021894	1009	and status of the Watchdog Timer. */
elessair	0:f269e3021894	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
elessair	0:f269e3021894	1011	the time-out value. */
elessair	0:f269e3021894	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
elessair	0:f269e3021894	1013	to this register reloads the Watchdog timer with the value contained
elessair	0:f269e3021894	1014	in WDTC. */
elessair	0:f269e3021894	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
elessair	0:f269e3021894	1016	the current value of the Watchdog timer. */
elessair	0:f269e3021894	1017	__I uint32_t RESERVED0;
elessair	0:f269e3021894	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
elessair	0:f269e3021894	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
elessair	0:f269e3021894	1020	} LPC_WWDT_Type;
elessair	0:f269e3021894	1021
elessair	0:f269e3021894	1022
elessair	0:f269e3021894	1023	/* ================================================================================ */
elessair	0:f269e3021894	1024	/* ================ SWM ================ */
elessair	0:f269e3021894	1025	/* ================================================================================ */
elessair	0:f269e3021894	1026
elessair	0:f269e3021894	1027
elessair	0:f269e3021894	1028	/**
elessair	0:f269e3021894	1029	* @brief Switch Matrix (SWM) (SWM)
elessair	0:f269e3021894	1030	*/
elessair	0:f269e3021894	1031
elessair	0:f269e3021894	1032	typedef struct { /!< SWM Structure /
elessair	0:f269e3021894	1033	union {
elessair	0:f269e3021894	1034	__IO uint32_t PINASSIGN[16];
elessair	0:f269e3021894	1035	struct {
elessair	0:f269e3021894	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
elessair	0:f269e3021894	1037	U0_RTS, U0_CTS. */
elessair	0:f269e3021894	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
elessair	0:f269e3021894	1039	U1_RXD, U1_RTS. */
elessair	0:f269e3021894	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
elessair	0:f269e3021894	1041	U2_TXD, U2_RXD. */
elessair	0:f269e3021894	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
elessair	0:f269e3021894	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
elessair	0:f269e3021894	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
elessair	0:f269e3021894	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
elessair	0:f269e3021894	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
elessair	0:f269e3021894	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
elessair	0:f269e3021894	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
elessair	0:f269e3021894	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
elessair	0:f269e3021894	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
elessair	0:f269e3021894	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
elessair	0:f269e3021894	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
elessair	0:f269e3021894	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
elessair	0:f269e3021894	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
elessair	0:f269e3021894	1055	};
elessair	0:f269e3021894	1056	};
elessair	0:f269e3021894	1057	__I uint32_t RESERVED0[96];
elessair	0:f269e3021894	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
elessair	0:f269e3021894	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
elessair	0:f269e3021894	1060	} LPC_SWM_Type;
elessair	0:f269e3021894	1061
elessair	0:f269e3021894	1062
elessair	0:f269e3021894	1063	/* ================================================================================ */
elessair	0:f269e3021894	1064	/* ================ PMU ================ */
elessair	0:f269e3021894	1065	/* ================================================================================ */
elessair	0:f269e3021894	1066
elessair	0:f269e3021894	1067
elessair	0:f269e3021894	1068	/**
elessair	0:f269e3021894	1069	* @brief Power Management Unit (PMU) (PMU)
elessair	0:f269e3021894	1070	*/
elessair	0:f269e3021894	1071
elessair	0:f269e3021894	1072	typedef struct { /!< PMU Structure /
elessair	0:f269e3021894	1073	__IO uint32_t PCON; /!< Power control register /
elessair	0:f269e3021894	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
elessair	0:f269e3021894	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
elessair	0:f269e3021894	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
elessair	0:f269e3021894	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
elessair	0:f269e3021894	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
elessair	0:f269e3021894	1079	} LPC_PMU_Type;
elessair	0:f269e3021894	1080
elessair	0:f269e3021894	1081
elessair	0:f269e3021894	1082	/* ================================================================================ */
elessair	0:f269e3021894	1083	/* ================ USART0 ================ */
elessair	0:f269e3021894	1084	/* ================================================================================ */
elessair	0:f269e3021894	1085
elessair	0:f269e3021894	1086
elessair	0:f269e3021894	1087	/**
elessair	0:f269e3021894	1088	* @brief USART0 (USART0)
elessair	0:f269e3021894	1089	*/
elessair	0:f269e3021894	1090
elessair	0:f269e3021894	1091	typedef struct { /!< USART0 Structure /
elessair	0:f269e3021894	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
elessair	0:f269e3021894	1093	that typically are not changed during operation. */
elessair	0:f269e3021894	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
elessair	0:f269e3021894	1095	likely to change during operation. */
elessair	0:f269e3021894	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
elessair	0:f269e3021894	1097	here. Writing ones clears some bits in the register. Some bits
elessair	0:f269e3021894	1098	can be cleared by writing a 1 to them. */
elessair	0:f269e3021894	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
elessair	0:f269e3021894	1100	interrupt enable bit for each potential USART interrupt. A complete
elessair	0:f269e3021894	1101	value may be read from this register. Writing a 1 to any implemented
elessair	0:f269e3021894	1102	bit position causes that bit to be set. */
elessair	0:f269e3021894	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
elessair	0:f269e3021894	1104	of bits in the INTENSET register. Writing a 1 to any implemented
elessair	0:f269e3021894	1105	bit position causes the corresponding bit to be cleared. */
elessair	0:f269e3021894	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
elessair	0:f269e3021894	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
elessair	0:f269e3021894	1108	received with the current USART receive status. Allows DMA or
elessair	0:f269e3021894	1109	software to recover incoming data and status together. */
elessair	0:f269e3021894	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
elessair	0:f269e3021894	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
elessair	0:f269e3021894	1112	value. */
elessair	0:f269e3021894	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
elessair	0:f269e3021894	1114	enabled. */
elessair	0:f269e3021894	1115	} LPC_USART0_Type;
elessair	0:f269e3021894	1116
elessair	0:f269e3021894	1117
elessair	0:f269e3021894	1118	/* ================================================================================ */
elessair	0:f269e3021894	1119	/* ================ SPI0 ================ */
elessair	0:f269e3021894	1120	/* ================================================================================ */
elessair	0:f269e3021894	1121
elessair	0:f269e3021894	1122
elessair	0:f269e3021894	1123	/**
elessair	0:f269e3021894	1124	* @brief SPI0 (SPI0)
elessair	0:f269e3021894	1125	*/
elessair	0:f269e3021894	1126
elessair	0:f269e3021894	1127	typedef struct { /!< SPI0 Structure /
elessair	0:f269e3021894	1128	__IO uint32_t CFG; /!< SPI Configuration register /
elessair	0:f269e3021894	1129	__IO uint32_t DLY; /!< SPI Delay register /
elessair	0:f269e3021894	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
elessair	0:f269e3021894	1131	to that bit position */
elessair	0:f269e3021894	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
elessair	0:f269e3021894	1133	from this register. Writing a 1 to any implemented bit position
elessair	0:f269e3021894	1134	causes that bit to be set. */
elessair	0:f269e3021894	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
elessair	0:f269e3021894	1136	position causes the corresponding bit in INTENSET to be cleared. */
elessair	0:f269e3021894	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
elessair	0:f269e3021894	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
elessair	0:f269e3021894	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
elessair	0:f269e3021894	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
elessair	0:f269e3021894	1141	__IO uint32_t DIV; /!< SPI clock Divider /
elessair	0:f269e3021894	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
elessair	0:f269e3021894	1143	} LPC_SPI0_Type;
elessair	0:f269e3021894	1144
elessair	0:f269e3021894	1145
elessair	0:f269e3021894	1146	/* ================================================================================ */
elessair	0:f269e3021894	1147	/* ================ I2C0 ================ */
elessair	0:f269e3021894	1148	/* ================================================================================ */
elessair	0:f269e3021894	1149
elessair	0:f269e3021894	1150
elessair	0:f269e3021894	1151	/**
elessair	0:f269e3021894	1152	* @brief I2C-bus interface (I2C0)
elessair	0:f269e3021894	1153	*/
elessair	0:f269e3021894	1154
elessair	0:f269e3021894	1155	typedef struct { /!< I2C0 Structure /
elessair	0:f269e3021894	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
elessair	0:f269e3021894	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
elessair	0:f269e3021894	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
elessair	0:f269e3021894	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
elessair	0:f269e3021894	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
elessair	0:f269e3021894	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
elessair	0:f269e3021894	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
elessair	0:f269e3021894	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
elessair	0:f269e3021894	1164	__I uint32_t RESERVED0;
elessair	0:f269e3021894	1165	__IO uint32_t MSTCTL; /!< Master control register. /
elessair	0:f269e3021894	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
elessair	0:f269e3021894	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
elessair	0:f269e3021894	1168	__I uint32_t RESERVED1[5];
elessair	0:f269e3021894	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
elessair	0:f269e3021894	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
elessair	0:f269e3021894	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
elessair	0:f269e3021894	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
elessair	0:f269e3021894	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
elessair	0:f269e3021894	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
elessair	0:f269e3021894	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
elessair	0:f269e3021894	1176	__I uint32_t RESERVED2[9];
elessair	0:f269e3021894	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
elessair	0:f269e3021894	1178	} LPC_I2C0_Type;
elessair	0:f269e3021894	1179
elessair	0:f269e3021894	1180
elessair	0:f269e3021894	1181	/* ================================================================================ */
elessair	0:f269e3021894	1182	/* ================ QEI ================ */
elessair	0:f269e3021894	1183	/* ================================================================================ */
elessair	0:f269e3021894	1184
elessair	0:f269e3021894	1185
elessair	0:f269e3021894	1186	/**
elessair	0:f269e3021894	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
elessair	0:f269e3021894	1188	*/
elessair	0:f269e3021894	1189
elessair	0:f269e3021894	1190	typedef struct { /!< QEI Structure /
elessair	0:f269e3021894	1191	__O uint32_t CON; /!< Control register /
elessair	0:f269e3021894	1192	__I uint32_t STAT; /!< Encoder status register /
elessair	0:f269e3021894	1193	__IO uint32_t CONF; /!< Configuration register /
elessair	0:f269e3021894	1194	__I uint32_t POS; /!< Position register /
elessair	0:f269e3021894	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
elessair	0:f269e3021894	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
elessair	0:f269e3021894	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
elessair	0:f269e3021894	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
elessair	0:f269e3021894	1199	__I uint32_t INXCNT; /!< Index count register /
elessair	0:f269e3021894	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
elessair	0:f269e3021894	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
elessair	0:f269e3021894	1202	__I uint32_t TIME; /!< Velocity timer register /
elessair	0:f269e3021894	1203	__I uint32_t VEL; /!< Velocity counter register /
elessair	0:f269e3021894	1204	__I uint32_t CAP; /!< Velocity capture register /
elessair	0:f269e3021894	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
elessair	0:f269e3021894	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
elessair	0:f269e3021894	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
elessair	0:f269e3021894	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
elessair	0:f269e3021894	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
elessair	0:f269e3021894	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
elessair	0:f269e3021894	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
elessair	0:f269e3021894	1212	__I uint32_t RESERVED0[993];
elessair	0:f269e3021894	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
elessair	0:f269e3021894	1214	__O uint32_t IES; /!< Interrupt enable set register /
elessair	0:f269e3021894	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
elessair	0:f269e3021894	1216	__O uint32_t IE; /!< Interrupt enable clear register /
elessair	0:f269e3021894	1217	__O uint32_t CLR; /!< Interrupt status clear register /
elessair	0:f269e3021894	1218	__O uint32_t SET; /!< Interrupt status set register /
elessair	0:f269e3021894	1219	} LPC_QEI_Type;
elessair	0:f269e3021894	1220
elessair	0:f269e3021894	1221
elessair	0:f269e3021894	1222	/* ================================================================================ */
elessair	0:f269e3021894	1223	/* ================ SYSCON ================ */
elessair	0:f269e3021894	1224	/* ================================================================================ */
elessair	0:f269e3021894	1225
elessair	0:f269e3021894	1226
elessair	0:f269e3021894	1227	/**
elessair	0:f269e3021894	1228	* @brief System configuration (SYSCON) (SYSCON)
elessair	0:f269e3021894	1229	*/
elessair	0:f269e3021894	1230
elessair	0:f269e3021894	1231	typedef struct { /!< SYSCON Structure /
elessair	0:f269e3021894	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
elessair	0:f269e3021894	1233	__I uint32_t RESERVED0[4];
elessair	0:f269e3021894	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
elessair	0:f269e3021894	1235	__I uint32_t RESERVED1;
elessair	0:f269e3021894	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
elessair	0:f269e3021894	1237	__I uint32_t RESERVED2[8];
elessair	0:f269e3021894	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
elessair	0:f269e3021894	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
elessair	0:f269e3021894	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
elessair	0:f269e3021894	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
elessair	0:f269e3021894	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
elessair	0:f269e3021894	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
elessair	0:f269e3021894	1244	__I uint32_t RESERVED3[10];
elessair	0:f269e3021894	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
elessair	0:f269e3021894	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
elessair	0:f269e3021894	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
elessair	0:f269e3021894	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
elessair	0:f269e3021894	1249	__I uint32_t RESERVED4;
elessair	0:f269e3021894	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
elessair	0:f269e3021894	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
elessair	0:f269e3021894	1252	__I uint32_t RESERVED5;
elessair	0:f269e3021894	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
elessair	0:f269e3021894	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
elessair	0:f269e3021894	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
elessair	0:f269e3021894	1256	__I uint32_t RESERVED6[5];
elessair	0:f269e3021894	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
elessair	0:f269e3021894	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
elessair	0:f269e3021894	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
elessair	0:f269e3021894	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
elessair	0:f269e3021894	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
elessair	0:f269e3021894	1262	baud rate generator. */
elessair	0:f269e3021894	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
elessair	0:f269e3021894	1264	filter */
elessair	0:f269e3021894	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
elessair	0:f269e3021894	1266	__I uint32_t RESERVED7[4];
elessair	0:f269e3021894	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
elessair	0:f269e3021894	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
elessair	0:f269e3021894	1269	__I uint32_t RESERVED8;
elessair	0:f269e3021894	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
elessair	0:f269e3021894	1271	__I uint32_t RESERVED9[11];
elessair	0:f269e3021894	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
elessair	0:f269e3021894	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
elessair	0:f269e3021894	1274	__IO uint32_t USBCLKST; /!< USB clock status /
elessair	0:f269e3021894	1275	__I uint32_t RESERVED10[19];
elessair	0:f269e3021894	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
elessair	0:f269e3021894	1277	__I uint32_t RESERVED11;
elessair	0:f269e3021894	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
elessair	0:f269e3021894	1279	__I uint32_t RESERVED12;
elessair	0:f269e3021894	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
elessair	0:f269e3021894	1281	__I uint32_t RESERVED13;
elessair	0:f269e3021894	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
elessair	0:f269e3021894	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
elessair	0:f269e3021894	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
elessair	0:f269e3021894	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
elessair	0:f269e3021894	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
elessair	0:f269e3021894	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
elessair	0:f269e3021894	1288	__I uint32_t RESERVED14[21];
elessair	0:f269e3021894	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
elessair	0:f269e3021894	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
elessair	0:f269e3021894	1291	__I uint32_t RESERVED15[3];
elessair	0:f269e3021894	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
elessair	0:f269e3021894	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
elessair	0:f269e3021894	1294	} LPC_SYSCON_Type;
elessair	0:f269e3021894	1295
elessair	0:f269e3021894	1296
elessair	0:f269e3021894	1297	/* ================================================================================ */
elessair	0:f269e3021894	1298	/* ================ MRT ================ */
elessair	0:f269e3021894	1299	/* ================================================================================ */
elessair	0:f269e3021894	1300
elessair	0:f269e3021894	1301
elessair	0:f269e3021894	1302	/**
elessair	0:f269e3021894	1303	* @brief Multi-Rate Timer (MRT) (MRT)
elessair	0:f269e3021894	1304	*/
elessair	0:f269e3021894	1305
elessair	0:f269e3021894	1306	typedef struct { /!< MRT Structure /
elessair	0:f269e3021894	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
elessair	0:f269e3021894	1308	the TIMER0 register. */
elessair	0:f269e3021894	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
elessair	0:f269e3021894	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
elessair	0:f269e3021894	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
elessair	0:f269e3021894	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
elessair	0:f269e3021894	1313	the TIMER0 register. */
elessair	0:f269e3021894	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
elessair	0:f269e3021894	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
elessair	0:f269e3021894	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
elessair	0:f269e3021894	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
elessair	0:f269e3021894	1318	the TIMER0 register. */
elessair	0:f269e3021894	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
elessair	0:f269e3021894	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
elessair	0:f269e3021894	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
elessair	0:f269e3021894	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
elessair	0:f269e3021894	1323	the TIMER0 register. */
elessair	0:f269e3021894	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
elessair	0:f269e3021894	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
elessair	0:f269e3021894	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
elessair	0:f269e3021894	1327	__I uint32_t RESERVED0[45];
elessair	0:f269e3021894	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
elessair	0:f269e3021894	1329	first idle channel. */
elessair	0:f269e3021894	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
elessair	0:f269e3021894	1331	} LPC_MRT_Type;
elessair	0:f269e3021894	1332
elessair	0:f269e3021894	1333
elessair	0:f269e3021894	1334	/* ================================================================================ */
elessair	0:f269e3021894	1335	/* ================ PINT ================ */
elessair	0:f269e3021894	1336	/* ================================================================================ */
elessair	0:f269e3021894	1337
elessair	0:f269e3021894	1338
elessair	0:f269e3021894	1339	/**
elessair	0:f269e3021894	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
elessair	0:f269e3021894	1341	*/
elessair	0:f269e3021894	1342
elessair	0:f269e3021894	1343	typedef struct { /!< PINT Structure /
elessair	0:f269e3021894	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
elessair	0:f269e3021894	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
elessair	0:f269e3021894	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
elessair	0:f269e3021894	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
elessair	0:f269e3021894	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
elessair	0:f269e3021894	1349	register */
elessair	0:f269e3021894	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
elessair	0:f269e3021894	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
elessair	0:f269e3021894	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
elessair	0:f269e3021894	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
elessair	0:f269e3021894	1354	__IO uint32_t IST; /!< Pin interrupt status register /
elessair	0:f269e3021894	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
elessair	0:f269e3021894	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
elessair	0:f269e3021894	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
elessair	0:f269e3021894	1358	} LPC_PINT_Type;
elessair	0:f269e3021894	1359
elessair	0:f269e3021894	1360
elessair	0:f269e3021894	1361	/* ================================================================================ */
elessair	0:f269e3021894	1362	/* ================ GINT0 ================ */
elessair	0:f269e3021894	1363	/* ================================================================================ */
elessair	0:f269e3021894	1364
elessair	0:f269e3021894	1365
elessair	0:f269e3021894	1366	/**
elessair	0:f269e3021894	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
elessair	0:f269e3021894	1368	*/
elessair	0:f269e3021894	1369
elessair	0:f269e3021894	1370	typedef struct { /!< GINT0 Structure /
elessair	0:f269e3021894	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
elessair	0:f269e3021894	1372	__I uint32_t RESERVED0[7];
elessair	0:f269e3021894	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
elessair	0:f269e3021894	1374	__I uint32_t RESERVED1[5];
elessair	0:f269e3021894	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
elessair	0:f269e3021894	1376	} LPC_GINT0_Type;
elessair	0:f269e3021894	1377
elessair	0:f269e3021894	1378
elessair	0:f269e3021894	1379	/* ================================================================================ */
elessair	0:f269e3021894	1380	/* ================ RIT ================ */
elessair	0:f269e3021894	1381	/* ================================================================================ */
elessair	0:f269e3021894	1382
elessair	0:f269e3021894	1383
elessair	0:f269e3021894	1384	/**
elessair	0:f269e3021894	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
elessair	0:f269e3021894	1386	*/
elessair	0:f269e3021894	1387
elessair	0:f269e3021894	1388	typedef struct { /!< RIT Structure /
elessair	0:f269e3021894	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
elessair	0:f269e3021894	1390	value. */
elessair	0:f269e3021894	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
elessair	0:f269e3021894	1392	value. A 1 written to any bit will force a compare on the corresponding
elessair	0:f269e3021894	1393	bit of the counter and compare register. */
elessair	0:f269e3021894	1394	__IO uint32_t CTRL; /!< Control register. /
elessair	0:f269e3021894	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
elessair	0:f269e3021894	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
elessair	0:f269e3021894	1397	value. */
elessair	0:f269e3021894	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
elessair	0:f269e3021894	1399	value. A 1 written to any bit will force a compare on the corresponding
elessair	0:f269e3021894	1400	bit of the counter and compare register. */
elessair	0:f269e3021894	1401	__I uint32_t RESERVED0;
elessair	0:f269e3021894	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
elessair	0:f269e3021894	1403	} LPC_RIT_Type;
elessair	0:f269e3021894	1404
elessair	0:f269e3021894	1405
elessair	0:f269e3021894	1406	/* ================================================================================ */
elessair	0:f269e3021894	1407	/* ================ SCTIPU ================ */
elessair	0:f269e3021894	1408	/* ================================================================================ */
elessair	0:f269e3021894	1409
elessair	0:f269e3021894	1410
elessair	0:f269e3021894	1411	/**
elessair	0:f269e3021894	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
elessair	0:f269e3021894	1413	*/
elessair	0:f269e3021894	1414
elessair	0:f269e3021894	1415	typedef struct { /!< SCTIPU Structure /
elessair	0:f269e3021894	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
elessair	0:f269e3021894	1417	latch/sample-enable mux selects, and sample overrride bits for
elessair	0:f269e3021894	1418	the SAMPLE module. */
elessair	0:f269e3021894	1419	__I uint32_t RESERVED0[7];
elessair	0:f269e3021894	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
elessair	0:f269e3021894	1421	to ORed Abort Output 0. */
elessair	0:f269e3021894	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
elessair	0:f269e3021894	1423	input source caused abort output 0. */
elessair	0:f269e3021894	1424	__I uint32_t RESERVED1[6];
elessair	0:f269e3021894	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
elessair	0:f269e3021894	1426	to ORed Abort Output 0. */
elessair	0:f269e3021894	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
elessair	0:f269e3021894	1428	input source caused abort output 0. */
elessair	0:f269e3021894	1429	__I uint32_t RESERVED2[6];
elessair	0:f269e3021894	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
elessair	0:f269e3021894	1431	to ORed Abort Output 0. */
elessair	0:f269e3021894	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
elessair	0:f269e3021894	1433	input source caused abort output 0. */
elessair	0:f269e3021894	1434	__I uint32_t RESERVED3[6];
elessair	0:f269e3021894	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
elessair	0:f269e3021894	1436	to ORed Abort Output 0. */
elessair	0:f269e3021894	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
elessair	0:f269e3021894	1438	input source caused abort output 0. */
elessair	0:f269e3021894	1439	} LPC_SCTIPU_Type;
elessair	0:f269e3021894	1440
elessair	0:f269e3021894	1441
elessair	0:f269e3021894	1442	/* ================================================================================ */
elessair	0:f269e3021894	1443	/* ================ FLASHCTRL ================ */
elessair	0:f269e3021894	1444	/* ================================================================================ */
elessair	0:f269e3021894	1445
elessair	0:f269e3021894	1446
elessair	0:f269e3021894	1447	/**
elessair	0:f269e3021894	1448	* @brief Flash controller (FLASHCTRL)
elessair	0:f269e3021894	1449	*/
elessair	0:f269e3021894	1450
elessair	0:f269e3021894	1451	typedef struct { /!< FLASHCTRL Structure /
elessair	0:f269e3021894	1452	__I uint32_t RESERVED0[8];
elessair	0:f269e3021894	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
elessair	0:f269e3021894	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
elessair	0:f269e3021894	1455	__I uint32_t RESERVED1;
elessair	0:f269e3021894	1456	__I uint32_t FMSW0; /!< Signature word /
elessair	0:f269e3021894	1457	} LPC_FLASHCTRL_Type;
elessair	0:f269e3021894	1458
elessair	0:f269e3021894	1459
elessair	0:f269e3021894	1460	/* ================================================================================ */
elessair	0:f269e3021894	1461	/* ================ C_CAN0 ================ */
elessair	0:f269e3021894	1462	/* ================================================================================ */
elessair	0:f269e3021894	1463
elessair	0:f269e3021894	1464
elessair	0:f269e3021894	1465	/**
elessair	0:f269e3021894	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
elessair	0:f269e3021894	1467	*/
elessair	0:f269e3021894	1468
elessair	0:f269e3021894	1469	typedef struct { /!< C_CAN0 Structure /
elessair	0:f269e3021894	1470	__IO uint32_t CANCNTL; /!< CAN control /
elessair	0:f269e3021894	1471	__IO uint32_t CANSTAT; /!< Status register /
elessair	0:f269e3021894	1472	__I uint32_t CANEC; /!< Error counter /
elessair	0:f269e3021894	1473	__IO uint32_t CANBT; /!< Bit timing register /
elessair	0:f269e3021894	1474	__I uint32_t CANINT; /!< Interrupt register /
elessair	0:f269e3021894	1475	__IO uint32_t CANTEST; /!< Test register /
elessair	0:f269e3021894	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
elessair	0:f269e3021894	1477	__I uint32_t RESERVED0;
elessair	0:f269e3021894	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
elessair	0:f269e3021894	1479
elessair	0:f269e3021894	1480	union {
elessair	0:f269e3021894	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
elessair	0:f269e3021894	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
elessair	0:f269e3021894	1483	};
elessair	0:f269e3021894	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
elessair	0:f269e3021894	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
elessair	0:f269e3021894	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
elessair	0:f269e3021894	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
elessair	0:f269e3021894	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
elessair	0:f269e3021894	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
elessair	0:f269e3021894	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
elessair	0:f269e3021894	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
elessair	0:f269e3021894	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
elessair	0:f269e3021894	1493	__I uint32_t RESERVED1[13];
elessair	0:f269e3021894	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
elessair	0:f269e3021894	1495
elessair	0:f269e3021894	1496	union {
elessair	0:f269e3021894	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
elessair	0:f269e3021894	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
elessair	0:f269e3021894	1499	};
elessair	0:f269e3021894	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
elessair	0:f269e3021894	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
elessair	0:f269e3021894	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
elessair	0:f269e3021894	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
elessair	0:f269e3021894	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
elessair	0:f269e3021894	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
elessair	0:f269e3021894	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
elessair	0:f269e3021894	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
elessair	0:f269e3021894	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
elessair	0:f269e3021894	1509	__I uint32_t RESERVED2[21];
elessair	0:f269e3021894	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
elessair	0:f269e3021894	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
elessair	0:f269e3021894	1512	__I uint32_t RESERVED3[6];
elessair	0:f269e3021894	1513	__I uint32_t CANND1; /!< New data 1 /
elessair	0:f269e3021894	1514	__I uint32_t CANND2; /!< New data 2 /
elessair	0:f269e3021894	1515	__I uint32_t RESERVED4[6];
elessair	0:f269e3021894	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
elessair	0:f269e3021894	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
elessair	0:f269e3021894	1518	__I uint32_t RESERVED5[6];
elessair	0:f269e3021894	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
elessair	0:f269e3021894	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
elessair	0:f269e3021894	1521	__I uint32_t RESERVED6[6];
elessair	0:f269e3021894	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
elessair	0:f269e3021894	1523	} LPC_C_CAN0_Type;
elessair	0:f269e3021894	1524
elessair	0:f269e3021894	1525
elessair	0:f269e3021894	1526	/* ================================================================================ */
elessair	0:f269e3021894	1527	/* ================ IOCON ================ */
elessair	0:f269e3021894	1528	/* ================================================================================ */
elessair	0:f269e3021894	1529
elessair	0:f269e3021894	1530
elessair	0:f269e3021894	1531	/**
elessair	0:f269e3021894	1532	* @brief I/O pin configuration (IOCON) (IOCON)
elessair	0:f269e3021894	1533	*/
elessair	0:f269e3021894	1534
elessair	0:f269e3021894	1535	typedef struct { /!< IOCON Structure /
elessair	0:f269e3021894	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
elessair	0:f269e3021894	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
elessair	0:f269e3021894	1559	the I2C-bus SCL function. */
elessair	0:f269e3021894	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
elessair	0:f269e3021894	1561	the I2C-bus SCL function. */
elessair	0:f269e3021894	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
elessair	0:f269e3021894	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
elessair	0:f269e3021894	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
elessair	0:f269e3021894	1614	} LPC_IOCON_Type;
elessair	0:f269e3021894	1615
elessair	0:f269e3021894	1616
elessair	0:f269e3021894	1617	/* -------------------- End of section using anonymous unions ------------------- */
elessair	0:f269e3021894	1618	#if defined(__CC_ARM)
elessair	0:f269e3021894	1619	#pragma pop
elessair	0:f269e3021894	1620	#elif defined(__ICCARM__)
elessair	0:f269e3021894	1621	/* leave anonymous unions enabled */
elessair	0:f269e3021894	1622	#elif defined(__GNUC__)
elessair	0:f269e3021894	1623	/* anonymous unions are enabled by default */
elessair	0:f269e3021894	1624	#elif defined(__TMS470__)
elessair	0:f269e3021894	1625	/* anonymous unions are enabled by default */
elessair	0:f269e3021894	1626	#elif defined(__TASKING__)
elessair	0:f269e3021894	1627	#pragma warning restore
elessair	0:f269e3021894	1628	#else
elessair	0:f269e3021894	1629	#warning Not supported compiler type
elessair	0:f269e3021894	1630	#endif
elessair	0:f269e3021894	1631
elessair	0:f269e3021894	1632
elessair	0:f269e3021894	1633
elessair	0:f269e3021894	1634
elessair	0:f269e3021894	1635	/* ================================================================================ */
elessair	0:f269e3021894	1636	/* ================ Peripheral memory map ================ */
elessair	0:f269e3021894	1637	/* ================================================================================ */
elessair	0:f269e3021894	1638
elessair	0:f269e3021894	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
elessair	0:f269e3021894	1640	#define LPC_DMA_BASE 0x1C004000UL
elessair	0:f269e3021894	1641	#define LPC_USB_BASE 0x1C00C000UL
elessair	0:f269e3021894	1642	#define LPC_CRC_BASE 0x1C010000UL
elessair	0:f269e3021894	1643	#define LPC_SCT0_BASE 0x1C018000UL
elessair	0:f269e3021894	1644	#define LPC_SCT1_BASE 0x1C01C000UL
elessair	0:f269e3021894	1645	#define LPC_SCT2_BASE 0x1C020000UL
elessair	0:f269e3021894	1646	#define LPC_SCT3_BASE 0x1C024000UL
elessair	0:f269e3021894	1647	#define LPC_ADC0_BASE 0x40000000UL
elessair	0:f269e3021894	1648	#define LPC_DAC_BASE 0x40004000UL
elessair	0:f269e3021894	1649	#define LPC_ACMP_BASE 0x40008000UL
elessair	0:f269e3021894	1650	#define LPC_INMUX_BASE 0x40014000UL
elessair	0:f269e3021894	1651	#define LPC_RTC_BASE 0x40028000UL
elessair	0:f269e3021894	1652	#define LPC_WWDT_BASE 0x4002C000UL
elessair	0:f269e3021894	1653	#define LPC_SWM_BASE 0x40038000UL
elessair	0:f269e3021894	1654	#define LPC_PMU_BASE 0x4003C000UL
elessair	0:f269e3021894	1655	#define LPC_USART0_BASE 0x40040000UL
elessair	0:f269e3021894	1656	#define LPC_USART1_BASE 0x40044000UL
elessair	0:f269e3021894	1657	#define LPC_SPI0_BASE 0x40048000UL
elessair	0:f269e3021894	1658	#define LPC_SPI1_BASE 0x4004C000UL
elessair	0:f269e3021894	1659	#define LPC_I2C0_BASE 0x40050000UL
elessair	0:f269e3021894	1660	#define LPC_QEI_BASE 0x40058000UL
elessair	0:f269e3021894	1661	#define LPC_SYSCON_BASE 0x40074000UL
elessair	0:f269e3021894	1662	#define LPC_ADC1_BASE 0x40080000UL
elessair	0:f269e3021894	1663	#define LPC_MRT_BASE 0x400A0000UL
elessair	0:f269e3021894	1664	#define LPC_PINT_BASE 0x400A4000UL
elessair	0:f269e3021894	1665	#define LPC_GINT0_BASE 0x400A8000UL
elessair	0:f269e3021894	1666	#define LPC_GINT1_BASE 0x400AC000UL
elessair	0:f269e3021894	1667	#define LPC_RIT_BASE 0x400B4000UL
elessair	0:f269e3021894	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
elessair	0:f269e3021894	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
elessair	0:f269e3021894	1670	#define LPC_USART2_BASE 0x400C0000UL
elessair	0:f269e3021894	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
elessair	0:f269e3021894	1672	#define LPC_IOCON_BASE 0x400F8000UL
elessair	0:f269e3021894	1673
elessair	0:f269e3021894	1674
elessair	0:f269e3021894	1675	/* ================================================================================ */
elessair	0:f269e3021894	1676	/* ================ Peripheral declaration ================ */
elessair	0:f269e3021894	1677	/* ================================================================================ */
elessair	0:f269e3021894	1678
elessair	0:f269e3021894	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
elessair	0:f269e3021894	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
elessair	0:f269e3021894	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
elessair	0:f269e3021894	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
elessair	0:f269e3021894	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
elessair	0:f269e3021894	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
elessair	0:f269e3021894	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
elessair	0:f269e3021894	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
elessair	0:f269e3021894	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
elessair	0:f269e3021894	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
elessair	0:f269e3021894	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
elessair	0:f269e3021894	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
elessair	0:f269e3021894	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
elessair	0:f269e3021894	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
elessair	0:f269e3021894	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
elessair	0:f269e3021894	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
elessair	0:f269e3021894	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
elessair	0:f269e3021894	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
elessair	0:f269e3021894	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
elessair	0:f269e3021894	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
elessair	0:f269e3021894	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
elessair	0:f269e3021894	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
elessair	0:f269e3021894	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
elessair	0:f269e3021894	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
elessair	0:f269e3021894	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
elessair	0:f269e3021894	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
elessair	0:f269e3021894	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
elessair	0:f269e3021894	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
elessair	0:f269e3021894	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
elessair	0:f269e3021894	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
elessair	0:f269e3021894	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
elessair	0:f269e3021894	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
elessair	0:f269e3021894	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
elessair	0:f269e3021894	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
elessair	0:f269e3021894	1713
elessair	0:f269e3021894	1714
elessair	0:f269e3021894	1715	/** @} / / End of group Device_Peripheral_Registers */
elessair	0:f269e3021894	1716	/** @} / / End of group LPC15xx */
elessair	0:f269e3021894	1717	/** @} / / End of group (null) */
elessair	0:f269e3021894	1718
elessair	0:f269e3021894	1719	#ifdef __cplusplus
elessair	0:f269e3021894	1720	}
elessair	0:f269e3021894	1721	#endif
elessair	0:f269e3021894	1722
elessair	0:f269e3021894	1723
elessair	0:f269e3021894	1724	#endif /* LPC15XX_H */
elessair	0:f269e3021894	1725

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Type:	Library
Created:	20 Jul 2017
Imports:	0
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

targets/TARGET_NXP/TARGET_LPC15XX/device/LPC15xx.h@1:3deb71413561, 2017-07-20 (annotated)

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