Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Freescale/TARGET_K20XX/spi_api.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2015 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include "mbed_assert.h"
elessair 0:f269e3021894 17 #include "spi_api.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #include <math.h>
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 #include "cmsis.h"
elessair 0:f269e3021894 22 #include "pinmap.h"
elessair 0:f269e3021894 23 #include "clk_freqs.h"
elessair 0:f269e3021894 24 #include "PeripheralPins.h"
elessair 0:f269e3021894 25
elessair 0:f269e3021894 26 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
elessair 0:f269e3021894 27 // determine the SPI to use
elessair 0:f269e3021894 28 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 29 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 30 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 31 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 32 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
elessair 0:f269e3021894 33 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
elessair 0:f269e3021894 36 MBED_ASSERT((int)obj->spi != NC);
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
elessair 0:f269e3021894 39 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
elessair 0:f269e3021894 42 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 // not halt in the debug mode
elessair 0:f269e3021894 45 obj->spi->SR |= SPI_SR_EOQF_MASK;
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 // pin out the spi pins
elessair 0:f269e3021894 48 pinmap_pinout(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 49 pinmap_pinout(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 50 pinmap_pinout(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 51 if (ssel != NC) {
elessair 0:f269e3021894 52 pinmap_pinout(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 53 }
elessair 0:f269e3021894 54 }
elessair 0:f269e3021894 55
elessair 0:f269e3021894 56 void spi_free(spi_t *obj) {
elessair 0:f269e3021894 57 // [TODO]
elessair 0:f269e3021894 58 }
elessair 0:f269e3021894 59 void spi_format(spi_t *obj, int bits, int mode, int slave) {
elessair 0:f269e3021894 60 MBED_ASSERT((bits > 4) || (bits < 16));
elessair 0:f269e3021894 61 MBED_ASSERT((mode >= 0) && (mode <= 3));
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 uint8_t polarity = (mode & 0x2) ? 1 : 0;
elessair 0:f269e3021894 64 uint8_t phase = (mode & 0x1) ? 1 : 0;
elessair 0:f269e3021894 65 uint8_t old_polarity = (obj->spi->CTAR[0] & SPI_CTAR_CPOL_MASK) != 0;
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 // set master/slave
elessair 0:f269e3021894 68 if (slave) {
elessair 0:f269e3021894 69 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
elessair 0:f269e3021894 70 } else {
elessair 0:f269e3021894 71 obj->spi->MCR |= (1UL << SPI_MCR_MSTR_SHIFT);
elessair 0:f269e3021894 72 }
elessair 0:f269e3021894 73
elessair 0:f269e3021894 74 // CTAR0 is used
elessair 0:f269e3021894 75 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
elessair 0:f269e3021894 76 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 //If clk idle state was changed, start a dummy transmission
elessair 0:f269e3021894 79 //This is a 'feature' in DSPI: https://community.freescale.com/thread/105526
elessair 0:f269e3021894 80 if ((old_polarity != polarity) && (slave == 0)) {
elessair 0:f269e3021894 81 //Start transfer (CS should be high, so shouldn't matter)
elessair 0:f269e3021894 82 spi_master_write(obj, 0xFFFF);
elessair 0:f269e3021894 83 }
elessair 0:f269e3021894 84 }
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
elessair 0:f269e3021894 87 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89 void spi_frequency(spi_t *obj, int hz) {
elessair 0:f269e3021894 90 uint32_t f_error = 0;
elessair 0:f269e3021894 91 uint32_t p_error = 0xffffffff;
elessair 0:f269e3021894 92 uint32_t ref = 0;
elessair 0:f269e3021894 93 uint32_t br = 0;
elessair 0:f269e3021894 94 uint32_t ref_spr = 0;
elessair 0:f269e3021894 95 uint32_t ref_prescaler = 0;
elessair 0:f269e3021894 96 uint32_t ref_dr = 0;
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 // bus clk
elessair 0:f269e3021894 99 uint32_t PCLK = bus_frequency();
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 for (uint32_t i = 0; i < 4; i++) {
elessair 0:f269e3021894 102 for (br = 0; br <= 15; br++) {
elessair 0:f269e3021894 103 for (uint32_t dr = 0; dr < 2; dr++) {
elessair 0:f269e3021894 104 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
elessair 0:f269e3021894 105 if (ref > (uint32_t)hz)
elessair 0:f269e3021894 106 continue;
elessair 0:f269e3021894 107 f_error = hz - ref;
elessair 0:f269e3021894 108 if (f_error < p_error) {
elessair 0:f269e3021894 109 ref_spr = br;
elessair 0:f269e3021894 110 ref_prescaler = i;
elessair 0:f269e3021894 111 ref_dr = dr;
elessair 0:f269e3021894 112 p_error = f_error;
elessair 0:f269e3021894 113 }
elessair 0:f269e3021894 114 }
elessair 0:f269e3021894 115 }
elessair 0:f269e3021894 116 }
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 // set PBR and BR
elessair 0:f269e3021894 119 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
elessair 0:f269e3021894 120 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
elessair 0:f269e3021894 121 }
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 static inline int spi_writeable(spi_t *obj) {
elessair 0:f269e3021894 124 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
elessair 0:f269e3021894 125 }
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 static inline int spi_readable(spi_t *obj) {
elessair 0:f269e3021894 128 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
elessair 0:f269e3021894 129 }
elessair 0:f269e3021894 130
elessair 0:f269e3021894 131 int spi_master_write(spi_t *obj, int value) {
elessair 0:f269e3021894 132 //clear RX buffer flag
elessair 0:f269e3021894 133 obj->spi->SR |= SPI_SR_RFDF_MASK;
elessair 0:f269e3021894 134 // wait tx buffer empty
elessair 0:f269e3021894 135 while(!spi_writeable(obj));
elessair 0:f269e3021894 136 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 // wait rx buffer full
elessair 0:f269e3021894 139 while (!spi_readable(obj));
elessair 0:f269e3021894 140 return obj->spi->POPR;
elessair 0:f269e3021894 141 }
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 int spi_slave_receive(spi_t *obj) {
elessair 0:f269e3021894 144 return spi_readable(obj);
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 int spi_slave_read(spi_t *obj) {
elessair 0:f269e3021894 148 obj->spi->SR |= SPI_SR_RFDF_MASK;
elessair 0:f269e3021894 149 return obj->spi->POPR;
elessair 0:f269e3021894 150 }
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 void spi_slave_write(spi_t *obj, int value) {
elessair 0:f269e3021894 153 while (!spi_writeable(obj));
elessair 0:f269e3021894 154 }