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mbed-os

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cmsis/core_ca_mmu.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 ;/**************************************************************************//**
elessair 0:f269e3021894 2 ; * @file core_ca_mmu.h
elessair 0:f269e3021894 3 ; * @brief MMU Startup File for A9_MP Device Series
elessair 0:f269e3021894 4 ; * @version V1.01
elessair 0:f269e3021894 5 ; * @date 10 Sept 2014
elessair 0:f269e3021894 6 ; *
elessair 0:f269e3021894 7 ; * @note
elessair 0:f269e3021894 8 ; *
elessair 0:f269e3021894 9 ; ******************************************************************************/
elessair 0:f269e3021894 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
elessair 0:f269e3021894 11 ;
elessair 0:f269e3021894 12 ; All rights reserved.
elessair 0:f269e3021894 13 ; Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 ; modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 ; - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 ; notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 ; - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 ; notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 ; documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 ; - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 ; to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 ; specific prior written permission.
elessair 0:f269e3021894 23 ; *
elessair 0:f269e3021894 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 ; POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ; ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37 #ifdef __cplusplus
elessair 0:f269e3021894 38 extern "C" {
elessair 0:f269e3021894 39 #endif
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #ifndef _MMU_FUNC_H
elessair 0:f269e3021894 42 #define _MMU_FUNC_H
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #define SECTION_DESCRIPTOR (0x2)
elessair 0:f269e3021894 45 #define SECTION_MASK (0xFFFFFFFC)
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
elessair 0:f269e3021894 48 #define SECTION_B_SHIFT (2)
elessair 0:f269e3021894 49 #define SECTION_C_SHIFT (3)
elessair 0:f269e3021894 50 #define SECTION_TEX0_SHIFT (12)
elessair 0:f269e3021894 51 #define SECTION_TEX1_SHIFT (13)
elessair 0:f269e3021894 52 #define SECTION_TEX2_SHIFT (14)
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 #define SECTION_XN_MASK (0xFFFFFFEF)
elessair 0:f269e3021894 55 #define SECTION_XN_SHIFT (4)
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
elessair 0:f269e3021894 58 #define SECTION_DOMAIN_SHIFT (5)
elessair 0:f269e3021894 59
elessair 0:f269e3021894 60 #define SECTION_P_MASK (0xFFFFFDFF)
elessair 0:f269e3021894 61 #define SECTION_P_SHIFT (9)
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 #define SECTION_AP_MASK (0xFFFF73FF)
elessair 0:f269e3021894 64 #define SECTION_AP_SHIFT (10)
elessair 0:f269e3021894 65 #define SECTION_AP2_SHIFT (15)
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 #define SECTION_S_MASK (0xFFFEFFFF)
elessair 0:f269e3021894 68 #define SECTION_S_SHIFT (16)
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 #define SECTION_NG_MASK (0xFFFDFFFF)
elessair 0:f269e3021894 71 #define SECTION_NG_SHIFT (17)
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 #define SECTION_NS_MASK (0xFFF7FFFF)
elessair 0:f269e3021894 74 #define SECTION_NS_SHIFT (19)
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 #define PAGE_L1_DESCRIPTOR (0x1)
elessair 0:f269e3021894 78 #define PAGE_L1_MASK (0xFFFFFFFC)
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 #define PAGE_L2_4K_DESC (0x2)
elessair 0:f269e3021894 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83 #define PAGE_L2_64K_DESC (0x1)
elessair 0:f269e3021894 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
elessair 0:f269e3021894 87 #define PAGE_4K_B_SHIFT (2)
elessair 0:f269e3021894 88 #define PAGE_4K_C_SHIFT (3)
elessair 0:f269e3021894 89 #define PAGE_4K_TEX0_SHIFT (6)
elessair 0:f269e3021894 90 #define PAGE_4K_TEX1_SHIFT (7)
elessair 0:f269e3021894 91 #define PAGE_4K_TEX2_SHIFT (8)
elessair 0:f269e3021894 92
elessair 0:f269e3021894 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
elessair 0:f269e3021894 94 #define PAGE_64K_B_SHIFT (2)
elessair 0:f269e3021894 95 #define PAGE_64K_C_SHIFT (3)
elessair 0:f269e3021894 96 #define PAGE_64K_TEX0_SHIFT (12)
elessair 0:f269e3021894 97 #define PAGE_64K_TEX1_SHIFT (13)
elessair 0:f269e3021894 98 #define PAGE_64K_TEX2_SHIFT (14)
elessair 0:f269e3021894 99
elessair 0:f269e3021894 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
elessair 0:f269e3021894 101 #define PAGE_B_SHIFT (2)
elessair 0:f269e3021894 102 #define PAGE_C_SHIFT (3)
elessair 0:f269e3021894 103 #define PAGE_TEX_SHIFT (12)
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
elessair 0:f269e3021894 106 #define PAGE_XN_4K_SHIFT (0)
elessair 0:f269e3021894 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
elessair 0:f269e3021894 108 #define PAGE_XN_64K_SHIFT (15)
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
elessair 0:f269e3021894 112 #define PAGE_DOMAIN_SHIFT (5)
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 #define PAGE_P_MASK (0xFFFFFDFF)
elessair 0:f269e3021894 115 #define PAGE_P_SHIFT (9)
elessair 0:f269e3021894 116
elessair 0:f269e3021894 117 #define PAGE_AP_MASK (0xFFFFFDCF)
elessair 0:f269e3021894 118 #define PAGE_AP_SHIFT (4)
elessair 0:f269e3021894 119 #define PAGE_AP2_SHIFT (9)
elessair 0:f269e3021894 120
elessair 0:f269e3021894 121 #define PAGE_S_MASK (0xFFFFFBFF)
elessair 0:f269e3021894 122 #define PAGE_S_SHIFT (10)
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 #define PAGE_NG_MASK (0xFFFFF7FF)
elessair 0:f269e3021894 125 #define PAGE_NG_SHIFT (11)
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 #define PAGE_NS_MASK (0xFFFFFFF7)
elessair 0:f269e3021894 128 #define PAGE_NS_SHIFT (3)
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 #define OFFSET_1M (0x00100000)
elessair 0:f269e3021894 131 #define OFFSET_64K (0x00010000)
elessair 0:f269e3021894 132 #define OFFSET_4K (0x00001000)
elessair 0:f269e3021894 133
elessair 0:f269e3021894 134 #define DESCRIPTOR_FAULT (0x00000000)
elessair 0:f269e3021894 135
elessair 0:f269e3021894 136 /* ########################### MMU Function Access ########################### */
elessair 0:f269e3021894 137 /** \ingroup MMU_FunctionInterface
elessair 0:f269e3021894 138 \defgroup MMU_Functions MMU Functions Interface
elessair 0:f269e3021894 139 @{
elessair 0:f269e3021894 140 */
elessair 0:f269e3021894 141
elessair 0:f269e3021894 142 /* Attributes enumerations */
elessair 0:f269e3021894 143
elessair 0:f269e3021894 144 /* Region size attributes */
elessair 0:f269e3021894 145 typedef enum
elessair 0:f269e3021894 146 {
elessair 0:f269e3021894 147 SECTION,
elessair 0:f269e3021894 148 PAGE_4k,
elessair 0:f269e3021894 149 PAGE_64k,
elessair 0:f269e3021894 150 } mmu_region_size_Type;
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 /* Region type attributes */
elessair 0:f269e3021894 153 typedef enum
elessair 0:f269e3021894 154 {
elessair 0:f269e3021894 155 NORMAL,
elessair 0:f269e3021894 156 DEVICE,
elessair 0:f269e3021894 157 SHARED_DEVICE,
elessair 0:f269e3021894 158 NON_SHARED_DEVICE,
elessair 0:f269e3021894 159 STRONGLY_ORDERED
elessair 0:f269e3021894 160 } mmu_memory_Type;
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 /* Region cacheability attributes */
elessair 0:f269e3021894 163 typedef enum
elessair 0:f269e3021894 164 {
elessair 0:f269e3021894 165 NON_CACHEABLE,
elessair 0:f269e3021894 166 WB_WA,
elessair 0:f269e3021894 167 WT,
elessair 0:f269e3021894 168 WB_NO_WA,
elessair 0:f269e3021894 169 } mmu_cacheability_Type;
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 /* Region parity check attributes */
elessair 0:f269e3021894 172 typedef enum
elessair 0:f269e3021894 173 {
elessair 0:f269e3021894 174 ECC_DISABLED,
elessair 0:f269e3021894 175 ECC_ENABLED,
elessair 0:f269e3021894 176 } mmu_ecc_check_Type;
elessair 0:f269e3021894 177
elessair 0:f269e3021894 178 /* Region execution attributes */
elessair 0:f269e3021894 179 typedef enum
elessair 0:f269e3021894 180 {
elessair 0:f269e3021894 181 EXECUTE,
elessair 0:f269e3021894 182 NON_EXECUTE,
elessair 0:f269e3021894 183 } mmu_execute_Type;
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 /* Region global attributes */
elessair 0:f269e3021894 186 typedef enum
elessair 0:f269e3021894 187 {
elessair 0:f269e3021894 188 GLOBAL,
elessair 0:f269e3021894 189 NON_GLOBAL,
elessair 0:f269e3021894 190 } mmu_global_Type;
elessair 0:f269e3021894 191
elessair 0:f269e3021894 192 /* Region shareability attributes */
elessair 0:f269e3021894 193 typedef enum
elessair 0:f269e3021894 194 {
elessair 0:f269e3021894 195 NON_SHARED,
elessair 0:f269e3021894 196 SHARED,
elessair 0:f269e3021894 197 } mmu_shared_Type;
elessair 0:f269e3021894 198
elessair 0:f269e3021894 199 /* Region security attributes */
elessair 0:f269e3021894 200 typedef enum
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 SECURE,
elessair 0:f269e3021894 203 NON_SECURE,
elessair 0:f269e3021894 204 } mmu_secure_Type;
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206 /* Region access attributes */
elessair 0:f269e3021894 207 typedef enum
elessair 0:f269e3021894 208 {
elessair 0:f269e3021894 209 NO_ACCESS,
elessair 0:f269e3021894 210 RW,
elessair 0:f269e3021894 211 READ,
elessair 0:f269e3021894 212 } mmu_access_Type;
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 /* Memory Region definition */
elessair 0:f269e3021894 215 typedef struct RegionStruct {
elessair 0:f269e3021894 216 mmu_region_size_Type rg_t;
elessair 0:f269e3021894 217 mmu_memory_Type mem_t;
elessair 0:f269e3021894 218 uint8_t domain;
elessair 0:f269e3021894 219 mmu_cacheability_Type inner_norm_t;
elessair 0:f269e3021894 220 mmu_cacheability_Type outer_norm_t;
elessair 0:f269e3021894 221 mmu_ecc_check_Type e_t;
elessair 0:f269e3021894 222 mmu_execute_Type xn_t;
elessair 0:f269e3021894 223 mmu_global_Type g_t;
elessair 0:f269e3021894 224 mmu_secure_Type sec_t;
elessair 0:f269e3021894 225 mmu_access_Type priv_t;
elessair 0:f269e3021894 226 mmu_access_Type user_t;
elessair 0:f269e3021894 227 mmu_shared_Type sh_t;
elessair 0:f269e3021894 228
elessair 0:f269e3021894 229 } mmu_region_attributes_Type;
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 /** \brief Set section execution-never attribute
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 The function sets section execution-never attribute
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
elessair 0:f269e3021894 237
elessair 0:f269e3021894 238 \return 0
elessair 0:f269e3021894 239 */
elessair 0:f269e3021894 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
elessair 0:f269e3021894 241 {
elessair 0:f269e3021894 242 *descriptor_l1 &= SECTION_XN_MASK;
elessair 0:f269e3021894 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
elessair 0:f269e3021894 244 return 0;
elessair 0:f269e3021894 245 }
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 /** \brief Set section domain
elessair 0:f269e3021894 248
elessair 0:f269e3021894 249 The function sets section domain
elessair 0:f269e3021894 250
elessair 0:f269e3021894 251 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 252 \param [in] domain Section domain
elessair 0:f269e3021894 253
elessair 0:f269e3021894 254 \return 0
elessair 0:f269e3021894 255 */
elessair 0:f269e3021894 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
elessair 0:f269e3021894 257 {
elessair 0:f269e3021894 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
elessair 0:f269e3021894 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
elessair 0:f269e3021894 260 return 0;
elessair 0:f269e3021894 261 }
elessair 0:f269e3021894 262
elessair 0:f269e3021894 263 /** \brief Set section parity check
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 The function sets section parity check
elessair 0:f269e3021894 266
elessair 0:f269e3021894 267 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 \return 0
elessair 0:f269e3021894 271 */
elessair 0:f269e3021894 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
elessair 0:f269e3021894 273 {
elessair 0:f269e3021894 274 *descriptor_l1 &= SECTION_P_MASK;
elessair 0:f269e3021894 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
elessair 0:f269e3021894 276 return 0;
elessair 0:f269e3021894 277 }
elessair 0:f269e3021894 278
elessair 0:f269e3021894 279 /** \brief Set section access privileges
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 The function sets section access privileges
elessair 0:f269e3021894 282
elessair 0:f269e3021894 283 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
elessair 0:f269e3021894 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
elessair 0:f269e3021894 286 \param [in] afe Access flag enable
elessair 0:f269e3021894 287
elessair 0:f269e3021894 288 \return 0
elessair 0:f269e3021894 289 */
elessair 0:f269e3021894 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
elessair 0:f269e3021894 291 {
elessair 0:f269e3021894 292 uint32_t ap = 0;
elessair 0:f269e3021894 293
elessair 0:f269e3021894 294 if (afe == 0) { //full access
elessair 0:f269e3021894 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
elessair 0:f269e3021894 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:f269e3021894 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
elessair 0:f269e3021894 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:f269e3021894 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:f269e3021894 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
elessair 0:f269e3021894 301 }
elessair 0:f269e3021894 302
elessair 0:f269e3021894 303 else { //Simplified access
elessair 0:f269e3021894 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:f269e3021894 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:f269e3021894 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:f269e3021894 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
elessair 0:f269e3021894 308 }
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 *descriptor_l1 &= SECTION_AP_MASK;
elessair 0:f269e3021894 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
elessair 0:f269e3021894 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
elessair 0:f269e3021894 313
elessair 0:f269e3021894 314 return 0;
elessair 0:f269e3021894 315 }
elessair 0:f269e3021894 316
elessair 0:f269e3021894 317 /** \brief Set section shareability
elessair 0:f269e3021894 318
elessair 0:f269e3021894 319 The function sets section shareability
elessair 0:f269e3021894 320
elessair 0:f269e3021894 321 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 \return 0
elessair 0:f269e3021894 325 */
elessair 0:f269e3021894 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
elessair 0:f269e3021894 327 {
elessair 0:f269e3021894 328 *descriptor_l1 &= SECTION_S_MASK;
elessair 0:f269e3021894 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
elessair 0:f269e3021894 330 return 0;
elessair 0:f269e3021894 331 }
elessair 0:f269e3021894 332
elessair 0:f269e3021894 333 /** \brief Set section Global attribute
elessair 0:f269e3021894 334
elessair 0:f269e3021894 335 The function sets section Global attribute
elessair 0:f269e3021894 336
elessair 0:f269e3021894 337 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
elessair 0:f269e3021894 339
elessair 0:f269e3021894 340 \return 0
elessair 0:f269e3021894 341 */
elessair 0:f269e3021894 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
elessair 0:f269e3021894 343 {
elessair 0:f269e3021894 344 *descriptor_l1 &= SECTION_NG_MASK;
elessair 0:f269e3021894 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
elessair 0:f269e3021894 346 return 0;
elessair 0:f269e3021894 347 }
elessair 0:f269e3021894 348
elessair 0:f269e3021894 349 /** \brief Set section Security attribute
elessair 0:f269e3021894 350
elessair 0:f269e3021894 351 The function sets section Global attribute
elessair 0:f269e3021894 352
elessair 0:f269e3021894 353 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 \return 0
elessair 0:f269e3021894 357 */
elessair 0:f269e3021894 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
elessair 0:f269e3021894 359 {
elessair 0:f269e3021894 360 *descriptor_l1 &= SECTION_NS_MASK;
elessair 0:f269e3021894 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
elessair 0:f269e3021894 362 return 0;
elessair 0:f269e3021894 363 }
elessair 0:f269e3021894 364
elessair 0:f269e3021894 365 /* Page 4k or 64k */
elessair 0:f269e3021894 366 /** \brief Set 4k/64k page execution-never attribute
elessair 0:f269e3021894 367
elessair 0:f269e3021894 368 The function sets 4k/64k page execution-never attribute
elessair 0:f269e3021894 369
elessair 0:f269e3021894 370 \param [out] descriptor_l2 L2 descriptor.
elessair 0:f269e3021894 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
elessair 0:f269e3021894 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
elessair 0:f269e3021894 373
elessair 0:f269e3021894 374 \return 0
elessair 0:f269e3021894 375 */
elessair 0:f269e3021894 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
elessair 0:f269e3021894 377 {
elessair 0:f269e3021894 378 if (page == PAGE_4k)
elessair 0:f269e3021894 379 {
elessair 0:f269e3021894 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
elessair 0:f269e3021894 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
elessair 0:f269e3021894 382 }
elessair 0:f269e3021894 383 else
elessair 0:f269e3021894 384 {
elessair 0:f269e3021894 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
elessair 0:f269e3021894 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
elessair 0:f269e3021894 387 }
elessair 0:f269e3021894 388 return 0;
elessair 0:f269e3021894 389 }
elessair 0:f269e3021894 390
elessair 0:f269e3021894 391 /** \brief Set 4k/64k page domain
elessair 0:f269e3021894 392
elessair 0:f269e3021894 393 The function sets 4k/64k page domain
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 396 \param [in] domain Page domain
elessair 0:f269e3021894 397
elessair 0:f269e3021894 398 \return 0
elessair 0:f269e3021894 399 */
elessair 0:f269e3021894 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
elessair 0:f269e3021894 401 {
elessair 0:f269e3021894 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
elessair 0:f269e3021894 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
elessair 0:f269e3021894 404 return 0;
elessair 0:f269e3021894 405 }
elessair 0:f269e3021894 406
elessair 0:f269e3021894 407 /** \brief Set 4k/64k page parity check
elessair 0:f269e3021894 408
elessair 0:f269e3021894 409 The function sets 4k/64k page parity check
elessair 0:f269e3021894 410
elessair 0:f269e3021894 411 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414 \return 0
elessair 0:f269e3021894 415 */
elessair 0:f269e3021894 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
elessair 0:f269e3021894 417 {
elessair 0:f269e3021894 418 *descriptor_l1 &= SECTION_P_MASK;
elessair 0:f269e3021894 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
elessair 0:f269e3021894 420 return 0;
elessair 0:f269e3021894 421 }
elessair 0:f269e3021894 422
elessair 0:f269e3021894 423 /** \brief Set 4k/64k page access privileges
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 The function sets 4k/64k page access privileges
elessair 0:f269e3021894 426
elessair 0:f269e3021894 427 \param [out] descriptor_l2 L2 descriptor.
elessair 0:f269e3021894 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
elessair 0:f269e3021894 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
elessair 0:f269e3021894 430 \param [in] afe Access flag enable
elessair 0:f269e3021894 431
elessair 0:f269e3021894 432 \return 0
elessair 0:f269e3021894 433 */
elessair 0:f269e3021894 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
elessair 0:f269e3021894 435 {
elessair 0:f269e3021894 436 uint32_t ap = 0;
elessair 0:f269e3021894 437
elessair 0:f269e3021894 438 if (afe == 0) { //full access
elessair 0:f269e3021894 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
elessair 0:f269e3021894 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:f269e3021894 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
elessair 0:f269e3021894 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:f269e3021894 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:f269e3021894 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
elessair 0:f269e3021894 445 }
elessair 0:f269e3021894 446
elessair 0:f269e3021894 447 else { //Simplified access
elessair 0:f269e3021894 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:f269e3021894 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:f269e3021894 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:f269e3021894 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
elessair 0:f269e3021894 452 }
elessair 0:f269e3021894 453
elessair 0:f269e3021894 454 *descriptor_l2 &= PAGE_AP_MASK;
elessair 0:f269e3021894 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
elessair 0:f269e3021894 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
elessair 0:f269e3021894 457
elessair 0:f269e3021894 458 return 0;
elessair 0:f269e3021894 459 }
elessair 0:f269e3021894 460
elessair 0:f269e3021894 461 /** \brief Set 4k/64k page shareability
elessair 0:f269e3021894 462
elessair 0:f269e3021894 463 The function sets 4k/64k page shareability
elessair 0:f269e3021894 464
elessair 0:f269e3021894 465 \param [out] descriptor_l2 L2 descriptor.
elessair 0:f269e3021894 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
elessair 0:f269e3021894 467
elessair 0:f269e3021894 468 \return 0
elessair 0:f269e3021894 469 */
elessair 0:f269e3021894 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
elessair 0:f269e3021894 471 {
elessair 0:f269e3021894 472 *descriptor_l2 &= PAGE_S_MASK;
elessair 0:f269e3021894 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
elessair 0:f269e3021894 474 return 0;
elessair 0:f269e3021894 475 }
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 /** \brief Set 4k/64k page Global attribute
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479 The function sets 4k/64k page Global attribute
elessair 0:f269e3021894 480
elessair 0:f269e3021894 481 \param [out] descriptor_l2 L2 descriptor.
elessair 0:f269e3021894 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
elessair 0:f269e3021894 483
elessair 0:f269e3021894 484 \return 0
elessair 0:f269e3021894 485 */
elessair 0:f269e3021894 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
elessair 0:f269e3021894 487 {
elessair 0:f269e3021894 488 *descriptor_l2 &= PAGE_NG_MASK;
elessair 0:f269e3021894 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
elessair 0:f269e3021894 490 return 0;
elessair 0:f269e3021894 491 }
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493 /** \brief Set 4k/64k page Security attribute
elessair 0:f269e3021894 494
elessair 0:f269e3021894 495 The function sets 4k/64k page Global attribute
elessair 0:f269e3021894 496
elessair 0:f269e3021894 497 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
elessair 0:f269e3021894 499
elessair 0:f269e3021894 500 \return 0
elessair 0:f269e3021894 501 */
elessair 0:f269e3021894 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
elessair 0:f269e3021894 503 {
elessair 0:f269e3021894 504 *descriptor_l1 &= PAGE_NS_MASK;
elessair 0:f269e3021894 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
elessair 0:f269e3021894 506 return 0;
elessair 0:f269e3021894 507 }
elessair 0:f269e3021894 508
elessair 0:f269e3021894 509
elessair 0:f269e3021894 510 /** \brief Set Section memory attributes
elessair 0:f269e3021894 511
elessair 0:f269e3021894 512 The function sets section memory attributes
elessair 0:f269e3021894 513
elessair 0:f269e3021894 514 \param [out] descriptor_l1 L1 descriptor.
elessair 0:f269e3021894 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
elessair 0:f269e3021894 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:f269e3021894 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:f269e3021894 518
elessair 0:f269e3021894 519 \return 0
elessair 0:f269e3021894 520 */
elessair 0:f269e3021894 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
elessair 0:f269e3021894 522 {
elessair 0:f269e3021894 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
elessair 0:f269e3021894 524
elessair 0:f269e3021894 525 if (STRONGLY_ORDERED == mem)
elessair 0:f269e3021894 526 {
elessair 0:f269e3021894 527 return 0;
elessair 0:f269e3021894 528 }
elessair 0:f269e3021894 529 else if (SHARED_DEVICE == mem)
elessair 0:f269e3021894 530 {
elessair 0:f269e3021894 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
elessair 0:f269e3021894 532 }
elessair 0:f269e3021894 533 else if (NON_SHARED_DEVICE == mem)
elessair 0:f269e3021894 534 {
elessair 0:f269e3021894 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
elessair 0:f269e3021894 536 }
elessair 0:f269e3021894 537 else if (NORMAL == mem)
elessair 0:f269e3021894 538 {
elessair 0:f269e3021894 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
elessair 0:f269e3021894 540 switch(inner)
elessair 0:f269e3021894 541 {
elessair 0:f269e3021894 542 case NON_CACHEABLE:
elessair 0:f269e3021894 543 break;
elessair 0:f269e3021894 544 case WB_WA:
elessair 0:f269e3021894 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
elessair 0:f269e3021894 546 break;
elessair 0:f269e3021894 547 case WT:
elessair 0:f269e3021894 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
elessair 0:f269e3021894 549 break;
elessair 0:f269e3021894 550 case WB_NO_WA:
elessair 0:f269e3021894 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
elessair 0:f269e3021894 552 break;
elessair 0:f269e3021894 553 }
elessair 0:f269e3021894 554 switch(outer)
elessair 0:f269e3021894 555 {
elessair 0:f269e3021894 556 case NON_CACHEABLE:
elessair 0:f269e3021894 557 break;
elessair 0:f269e3021894 558 case WB_WA:
elessair 0:f269e3021894 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
elessair 0:f269e3021894 560 break;
elessair 0:f269e3021894 561 case WT:
elessair 0:f269e3021894 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
elessair 0:f269e3021894 563 break;
elessair 0:f269e3021894 564 case WB_NO_WA:
elessair 0:f269e3021894 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
elessair 0:f269e3021894 566 break;
elessair 0:f269e3021894 567 }
elessair 0:f269e3021894 568 }
elessair 0:f269e3021894 569
elessair 0:f269e3021894 570 return 0;
elessair 0:f269e3021894 571 }
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 /** \brief Set 4k/64k page memory attributes
elessair 0:f269e3021894 574
elessair 0:f269e3021894 575 The function sets 4k/64k page memory attributes
elessair 0:f269e3021894 576
elessair 0:f269e3021894 577 \param [out] descriptor_l2 L2 descriptor.
elessair 0:f269e3021894 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
elessair 0:f269e3021894 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:f269e3021894 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:f269e3021894 581
elessair 0:f269e3021894 582 \return 0
elessair 0:f269e3021894 583 */
elessair 0:f269e3021894 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
elessair 0:f269e3021894 585 {
elessair 0:f269e3021894 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
elessair 0:f269e3021894 587
elessair 0:f269e3021894 588 if (page == PAGE_64k)
elessair 0:f269e3021894 589 {
elessair 0:f269e3021894 590 //same as section
elessair 0:f269e3021894 591 __memory_section(descriptor_l2, mem, outer, inner);
elessair 0:f269e3021894 592 }
elessair 0:f269e3021894 593 else
elessair 0:f269e3021894 594 {
elessair 0:f269e3021894 595 if (STRONGLY_ORDERED == mem)
elessair 0:f269e3021894 596 {
elessair 0:f269e3021894 597 return 0;
elessair 0:f269e3021894 598 }
elessair 0:f269e3021894 599 else if (SHARED_DEVICE == mem)
elessair 0:f269e3021894 600 {
elessair 0:f269e3021894 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
elessair 0:f269e3021894 602 }
elessair 0:f269e3021894 603 else if (NON_SHARED_DEVICE == mem)
elessair 0:f269e3021894 604 {
elessair 0:f269e3021894 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
elessair 0:f269e3021894 606 }
elessair 0:f269e3021894 607 else if (NORMAL == mem)
elessair 0:f269e3021894 608 {
elessair 0:f269e3021894 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
elessair 0:f269e3021894 610 switch(inner)
elessair 0:f269e3021894 611 {
elessair 0:f269e3021894 612 case NON_CACHEABLE:
elessair 0:f269e3021894 613 break;
elessair 0:f269e3021894 614 case WB_WA:
elessair 0:f269e3021894 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
elessair 0:f269e3021894 616 break;
elessair 0:f269e3021894 617 case WT:
elessair 0:f269e3021894 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
elessair 0:f269e3021894 619 break;
elessair 0:f269e3021894 620 case WB_NO_WA:
elessair 0:f269e3021894 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
elessair 0:f269e3021894 622 break;
elessair 0:f269e3021894 623 }
elessair 0:f269e3021894 624 switch(outer)
elessair 0:f269e3021894 625 {
elessair 0:f269e3021894 626 case NON_CACHEABLE:
elessair 0:f269e3021894 627 break;
elessair 0:f269e3021894 628 case WB_WA:
elessair 0:f269e3021894 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
elessair 0:f269e3021894 630 break;
elessair 0:f269e3021894 631 case WT:
elessair 0:f269e3021894 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
elessair 0:f269e3021894 633 break;
elessair 0:f269e3021894 634 case WB_NO_WA:
elessair 0:f269e3021894 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
elessair 0:f269e3021894 636 break;
elessair 0:f269e3021894 637 }
elessair 0:f269e3021894 638 }
elessair 0:f269e3021894 639 }
elessair 0:f269e3021894 640
elessair 0:f269e3021894 641 return 0;
elessair 0:f269e3021894 642 }
elessair 0:f269e3021894 643
elessair 0:f269e3021894 644 /** \brief Create a L1 section descriptor
elessair 0:f269e3021894 645
elessair 0:f269e3021894 646 The function creates a section descriptor.
elessair 0:f269e3021894 647
elessair 0:f269e3021894 648 Assumptions:
elessair 0:f269e3021894 649 - 16MB super sections not supported
elessair 0:f269e3021894 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
elessair 0:f269e3021894 651 - Functions always return 0
elessair 0:f269e3021894 652
elessair 0:f269e3021894 653 \param [out] descriptor L1 descriptor
elessair 0:f269e3021894 654 \param [out] descriptor2 L2 descriptor
elessair 0:f269e3021894 655 \param [in] reg Section attributes
elessair 0:f269e3021894 656
elessair 0:f269e3021894 657 \return 0
elessair 0:f269e3021894 658 */
elessair 0:f269e3021894 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
elessair 0:f269e3021894 660 {
elessair 0:f269e3021894 661 *descriptor = 0;
elessair 0:f269e3021894 662
elessair 0:f269e3021894 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
elessair 0:f269e3021894 664 __xn_section(descriptor,reg.xn_t);
elessair 0:f269e3021894 665 __domain_section(descriptor, reg.domain);
elessair 0:f269e3021894 666 __p_section(descriptor, reg.e_t);
elessair 0:f269e3021894 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
elessair 0:f269e3021894 668 __shared_section(descriptor,reg.sh_t);
elessair 0:f269e3021894 669 __global_section(descriptor,reg.g_t);
elessair 0:f269e3021894 670 __secure_section(descriptor,reg.sec_t);
elessair 0:f269e3021894 671 *descriptor &= SECTION_MASK;
elessair 0:f269e3021894 672 *descriptor |= SECTION_DESCRIPTOR;
elessair 0:f269e3021894 673
elessair 0:f269e3021894 674 return 0;
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676 }
elessair 0:f269e3021894 677
elessair 0:f269e3021894 678
elessair 0:f269e3021894 679 /** \brief Create a L1 and L2 4k/64k page descriptor
elessair 0:f269e3021894 680
elessair 0:f269e3021894 681 The function creates a 4k/64k page descriptor.
elessair 0:f269e3021894 682 Assumptions:
elessair 0:f269e3021894 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
elessair 0:f269e3021894 684 - Functions always return 0
elessair 0:f269e3021894 685
elessair 0:f269e3021894 686 \param [out] descriptor L1 descriptor
elessair 0:f269e3021894 687 \param [out] descriptor2 L2 descriptor
elessair 0:f269e3021894 688 \param [in] reg 4k/64k page attributes
elessair 0:f269e3021894 689
elessair 0:f269e3021894 690 \return 0
elessair 0:f269e3021894 691 */
elessair 0:f269e3021894 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
elessair 0:f269e3021894 693 {
elessair 0:f269e3021894 694 *descriptor = 0;
elessair 0:f269e3021894 695 *descriptor2 = 0;
elessair 0:f269e3021894 696
elessair 0:f269e3021894 697 switch (reg.rg_t)
elessair 0:f269e3021894 698 {
elessair 0:f269e3021894 699 case PAGE_4k:
elessair 0:f269e3021894 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
elessair 0:f269e3021894 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
elessair 0:f269e3021894 702 __domain_page(descriptor, reg.domain);
elessair 0:f269e3021894 703 __p_page(descriptor, reg.e_t);
elessair 0:f269e3021894 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
elessair 0:f269e3021894 705 __shared_page(descriptor2,reg.sh_t);
elessair 0:f269e3021894 706 __global_page(descriptor2,reg.g_t);
elessair 0:f269e3021894 707 __secure_page(descriptor,reg.sec_t);
elessair 0:f269e3021894 708 *descriptor &= PAGE_L1_MASK;
elessair 0:f269e3021894 709 *descriptor |= PAGE_L1_DESCRIPTOR;
elessair 0:f269e3021894 710 *descriptor2 &= PAGE_L2_4K_MASK;
elessair 0:f269e3021894 711 *descriptor2 |= PAGE_L2_4K_DESC;
elessair 0:f269e3021894 712 break;
elessair 0:f269e3021894 713
elessair 0:f269e3021894 714 case PAGE_64k:
elessair 0:f269e3021894 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
elessair 0:f269e3021894 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
elessair 0:f269e3021894 717 __domain_page(descriptor, reg.domain);
elessair 0:f269e3021894 718 __p_page(descriptor, reg.e_t);
elessair 0:f269e3021894 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
elessair 0:f269e3021894 720 __shared_page(descriptor2,reg.sh_t);
elessair 0:f269e3021894 721 __global_page(descriptor2,reg.g_t);
elessair 0:f269e3021894 722 __secure_page(descriptor,reg.sec_t);
elessair 0:f269e3021894 723 *descriptor &= PAGE_L1_MASK;
elessair 0:f269e3021894 724 *descriptor |= PAGE_L1_DESCRIPTOR;
elessair 0:f269e3021894 725 *descriptor2 &= PAGE_L2_64K_MASK;
elessair 0:f269e3021894 726 *descriptor2 |= PAGE_L2_64K_DESC;
elessair 0:f269e3021894 727 break;
elessair 0:f269e3021894 728
elessair 0:f269e3021894 729 case SECTION:
elessair 0:f269e3021894 730 //error
elessair 0:f269e3021894 731 break;
elessair 0:f269e3021894 732
elessair 0:f269e3021894 733 }
elessair 0:f269e3021894 734
elessair 0:f269e3021894 735 return 0;
elessair 0:f269e3021894 736
elessair 0:f269e3021894 737 }
elessair 0:f269e3021894 738
elessair 0:f269e3021894 739 /** \brief Create a 1MB Section
elessair 0:f269e3021894 740
elessair 0:f269e3021894 741 \param [in] ttb Translation table base address
elessair 0:f269e3021894 742 \param [in] base_address Section base address
elessair 0:f269e3021894 743 \param [in] count Number of sections to create
elessair 0:f269e3021894 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:f269e3021894 745
elessair 0:f269e3021894 746 */
elessair 0:f269e3021894 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
elessair 0:f269e3021894 748 {
elessair 0:f269e3021894 749 uint32_t offset;
elessair 0:f269e3021894 750 uint32_t entry;
elessair 0:f269e3021894 751 uint32_t i;
elessair 0:f269e3021894 752
elessair 0:f269e3021894 753 offset = base_address >> 20;
elessair 0:f269e3021894 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
elessair 0:f269e3021894 755
elessair 0:f269e3021894 756 //4 bytes aligned
elessair 0:f269e3021894 757 ttb = ttb + offset;
elessair 0:f269e3021894 758
elessair 0:f269e3021894 759 for (i = 0; i < count; i++ )
elessair 0:f269e3021894 760 {
elessair 0:f269e3021894 761 //4 bytes aligned
elessair 0:f269e3021894 762 *ttb++ = entry;
elessair 0:f269e3021894 763 entry += OFFSET_1M;
elessair 0:f269e3021894 764 }
elessair 0:f269e3021894 765 }
elessair 0:f269e3021894 766
elessair 0:f269e3021894 767 /** \brief Create a 4k page entry
elessair 0:f269e3021894 768
elessair 0:f269e3021894 769 \param [in] ttb L1 table base address
elessair 0:f269e3021894 770 \param [in] base_address 4k base address
elessair 0:f269e3021894 771 \param [in] count Number of 4k pages to create
elessair 0:f269e3021894 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:f269e3021894 773 \param [in] ttb_l2 L2 table base address
elessair 0:f269e3021894 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
elessair 0:f269e3021894 775
elessair 0:f269e3021894 776 */
elessair 0:f269e3021894 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
elessair 0:f269e3021894 778 {
elessair 0:f269e3021894 779
elessair 0:f269e3021894 780 uint32_t offset, offset2;
elessair 0:f269e3021894 781 uint32_t entry, entry2;
elessair 0:f269e3021894 782 uint32_t i;
elessair 0:f269e3021894 783
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785 offset = base_address >> 20;
elessair 0:f269e3021894 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
elessair 0:f269e3021894 787
elessair 0:f269e3021894 788 //4 bytes aligned
elessair 0:f269e3021894 789 ttb += offset;
elessair 0:f269e3021894 790 //create l1_entry
elessair 0:f269e3021894 791 *ttb = entry;
elessair 0:f269e3021894 792
elessair 0:f269e3021894 793 offset2 = (base_address & 0xff000) >> 12;
elessair 0:f269e3021894 794 ttb_l2 += offset2;
elessair 0:f269e3021894 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
elessair 0:f269e3021894 796 for (i = 0; i < count; i++ )
elessair 0:f269e3021894 797 {
elessair 0:f269e3021894 798 //4 bytes aligned
elessair 0:f269e3021894 799 *ttb_l2++ = entry2;
elessair 0:f269e3021894 800 entry2 += OFFSET_4K;
elessair 0:f269e3021894 801 }
elessair 0:f269e3021894 802 }
elessair 0:f269e3021894 803
elessair 0:f269e3021894 804 /** \brief Create a 64k page entry
elessair 0:f269e3021894 805
elessair 0:f269e3021894 806 \param [in] ttb L1 table base address
elessair 0:f269e3021894 807 \param [in] base_address 64k base address
elessair 0:f269e3021894 808 \param [in] count Number of 64k pages to create
elessair 0:f269e3021894 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:f269e3021894 810 \param [in] ttb_l2 L2 table base address
elessair 0:f269e3021894 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
elessair 0:f269e3021894 812
elessair 0:f269e3021894 813 */
elessair 0:f269e3021894 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
elessair 0:f269e3021894 815 {
elessair 0:f269e3021894 816 uint32_t offset, offset2;
elessair 0:f269e3021894 817 uint32_t entry, entry2;
elessair 0:f269e3021894 818 uint32_t i,j;
elessair 0:f269e3021894 819
elessair 0:f269e3021894 820
elessair 0:f269e3021894 821 offset = base_address >> 20;
elessair 0:f269e3021894 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
elessair 0:f269e3021894 823
elessair 0:f269e3021894 824 //4 bytes aligned
elessair 0:f269e3021894 825 ttb += offset;
elessair 0:f269e3021894 826 //create l1_entry
elessair 0:f269e3021894 827 *ttb = entry;
elessair 0:f269e3021894 828
elessair 0:f269e3021894 829 offset2 = (base_address & 0xff000) >> 12;
elessair 0:f269e3021894 830 ttb_l2 += offset2;
elessair 0:f269e3021894 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
elessair 0:f269e3021894 832 for (i = 0; i < count; i++ )
elessair 0:f269e3021894 833 {
elessair 0:f269e3021894 834 //create 16 entries
elessair 0:f269e3021894 835 for (j = 0; j < 16; j++)
elessair 0:f269e3021894 836 //4 bytes aligned
elessair 0:f269e3021894 837 *ttb_l2++ = entry2;
elessair 0:f269e3021894 838 entry2 += OFFSET_64K;
elessair 0:f269e3021894 839 }
elessair 0:f269e3021894 840 }
elessair 0:f269e3021894 841
elessair 0:f269e3021894 842 /*@} end of MMU_Functions */
elessair 0:f269e3021894 843 #endif
elessair 0:f269e3021894 844
elessair 0:f269e3021894 845 #ifdef __cplusplus
elessair 0:f269e3021894 846 }
elessair 0:f269e3021894 847 #endif