Wim van der Vegt / RIT

RIT (Repetitive Interrupt Timer) Library.

Dependents:   ORTP-L_SensorTest ORTP-L_V01 ORTP-L_V01 RIT_Demo

RIT.cpp@4:64198265f56f, 2011-03-11 (annotated)

Committer:
wvd_vegt
Date:
Fri Mar 11 11:00:13 2011 +0000
Revision:
4:64198265f56f
Parent:
0:af45bc81d34c 
Removed Breaks from Documentation.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wvd_vegt 0:af45bc81d34c 1 /* mbed Repetitive Interrupt Timer Library
wvd_vegt 0:af45bc81d34c 2 * Copyright (c) 2011 wvd_vegt
wvd_vegt 0:af45bc81d34c 3 *
wvd_vegt 0:af45bc81d34c 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
wvd_vegt 0:af45bc81d34c 5 * of this software and associated documentation files (the "Software"), to deal
wvd_vegt 0:af45bc81d34c 6 * in the Software without restriction, including without limitation the rights
wvd_vegt 0:af45bc81d34c 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
wvd_vegt 0:af45bc81d34c 8 * copies of the Software, and to permit persons to whom the Software is
wvd_vegt 0:af45bc81d34c 9 * furnished to do so, subject to the following conditions:
wvd_vegt 0:af45bc81d34c 10 *
wvd_vegt 0:af45bc81d34c 11 * The above copyright notice and this permission notice shall be included in
wvd_vegt 0:af45bc81d34c 12 * all copies or substantial portions of the Software.
wvd_vegt 0:af45bc81d34c 13 *
wvd_vegt 0:af45bc81d34c 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
wvd_vegt 0:af45bc81d34c 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
wvd_vegt 0:af45bc81d34c 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
wvd_vegt 0:af45bc81d34c 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
wvd_vegt 0:af45bc81d34c 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
wvd_vegt 0:af45bc81d34c 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
wvd_vegt 0:af45bc81d34c 20 * THE SOFTWARE.
wvd_vegt 0:af45bc81d34c 21 */
wvd_vegt 0:af45bc81d34c 22
wvd_vegt 0:af45bc81d34c 23 #include "LPC17xx.h"
wvd_vegt 0:af45bc81d34c 24 #include "RIT.h"
wvd_vegt 0:af45bc81d34c 25 #include "mbed.h"
wvd_vegt 0:af45bc81d34c 26
wvd_vegt 0:af45bc81d34c 27 //Note: Code Ideas taken from BLDC and ADC Library.
wvd_vegt 0:af45bc81d34c 28
wvd_vegt 0:af45bc81d34c 29 //TODO Document RIT.h
wvd_vegt 0:af45bc81d34c 30 //TODO Publish as Library
wvd_vegt 0:af45bc81d34c 31
wvd_vegt 0:af45bc81d34c 32 RIT *RIT::instance;
wvd_vegt 0:af45bc81d34c 33
wvd_vegt 0:af45bc81d34c 34 //------------------------------------------------------------------------------
wvd_vegt 0:af45bc81d34c 35 //Public Stuff.
wvd_vegt 0:af45bc81d34c 36 //------------------------------------------------------------------------------
wvd_vegt 0:af45bc81d34c 37
wvd_vegt 0:af45bc81d34c 38 RIT::RIT(uint32_t ms) {
wvd_vegt 0:af45bc81d34c 39 //Default NULL global custom isr
wvd_vegt 0:af45bc81d34c 40 _rit_g_isr = NULL;
wvd_vegt 0:af45bc81d34c 41
wvd_vegt 0:af45bc81d34c 42 // Set RIT interrupt priority
wvd_vegt 0:af45bc81d34c 43 NVIC_SetPriority(RIT_IRQn, 11);
wvd_vegt 0:af45bc81d34c 44
wvd_vegt 0:af45bc81d34c 45 // Power the RIT
wvd_vegt 0:af45bc81d34c 46 power_enable();
wvd_vegt 0:af45bc81d34c 47
wvd_vegt 0:af45bc81d34c 48 // Select perhiperal clk
wvd_vegt 0:af45bc81d34c 49 select_clk();
wvd_vegt 0:af45bc81d34c 50
wvd_vegt 0:af45bc81d34c 51 // Set Clock
wvd_vegt 0:af45bc81d34c 52 setup_ms(ms);
wvd_vegt 0:af45bc81d34c 53
wvd_vegt 0:af45bc81d34c 54 // Set counter clear/reset after interrupt
wvd_vegt 0:af45bc81d34c 55 LPC_RIT->RICTRL |= (2L); //RITENCLR
wvd_vegt 0:af45bc81d34c 56
wvd_vegt 0:af45bc81d34c 57 // Connect the RIT interrupt to the interrupt handler
wvd_vegt 0:af45bc81d34c 58 instance = this;
wvd_vegt 0:af45bc81d34c 59 NVIC_SetVector(RIT_IRQn, (uint32_t)&_ritisr);
wvd_vegt 0:af45bc81d34c 60
wvd_vegt 0:af45bc81d34c 61 // Disable the RIT interrupt
wvd_vegt 0:af45bc81d34c 62 disable();
wvd_vegt 0:af45bc81d34c 63 }
wvd_vegt 0:af45bc81d34c 64
wvd_vegt 0:af45bc81d34c 65 //Setup Timing in ms.
wvd_vegt 0:af45bc81d34c 66 void RIT::setup_ms(uint32_t ms) {
wvd_vegt 0:af45bc81d34c 67 LPC_RIT->RICOMPVAL = (uint32_t)(((SYSCLK / ONEMHZ) * ms * 1000)-1);
wvd_vegt 0:af45bc81d34c 68 LPC_RIT->RICOUNTER = 0;
wvd_vegt 0:af45bc81d34c 69 }
wvd_vegt 0:af45bc81d34c 70
wvd_vegt 0:af45bc81d34c 71 //Setup Timing in us.
wvd_vegt 0:af45bc81d34c 72 void RIT::setup_us(uint32_t us) {
wvd_vegt 0:af45bc81d34c 73 LPC_RIT->RICOMPVAL = (uint32_t)(((SYSCLK / ONEMHZ) * us)-1);
wvd_vegt 0:af45bc81d34c 74 LPC_RIT->RICOUNTER = 0;
wvd_vegt 0:af45bc81d34c 75 }
wvd_vegt 0:af45bc81d34c 76
wvd_vegt 0:af45bc81d34c 77 //Attach custom interrupt handler replacing default
wvd_vegt 0:af45bc81d34c 78 void RIT::attach(void(*fptr)(void)) {
wvd_vegt 0:af45bc81d34c 79 //* Attach IRQ
wvd_vegt 0:af45bc81d34c 80 NVIC_SetVector(ADC_IRQn, (uint32_t)fptr);
wvd_vegt 0:af45bc81d34c 81 }
wvd_vegt 0:af45bc81d34c 82
wvd_vegt 0:af45bc81d34c 83 //Restore default interrupt handler
wvd_vegt 0:af45bc81d34c 84 void RIT::detach(void) {
wvd_vegt 0:af45bc81d34c 85 //* Attach IRQ
wvd_vegt 0:af45bc81d34c 86 instance = this;
wvd_vegt 0:af45bc81d34c 87
wvd_vegt 0:af45bc81d34c 88 NVIC_SetVector(ADC_IRQn, (uint32_t)&_ritisr);
wvd_vegt 0:af45bc81d34c 89 }
wvd_vegt 0:af45bc81d34c 90
wvd_vegt 0:af45bc81d34c 91 //Unappend global interrupt handler to function isr
wvd_vegt 0:af45bc81d34c 92 void RIT::append(void(*fptr)()) {
wvd_vegt 0:af45bc81d34c 93 _rit_g_isr = fptr;
wvd_vegt 0:af45bc81d34c 94 }
wvd_vegt 0:af45bc81d34c 95
wvd_vegt 0:af45bc81d34c 96 //Detach global interrupt handler to function isr
wvd_vegt 0:af45bc81d34c 97 void RIT::unappend() {
wvd_vegt 0:af45bc81d34c 98 _rit_g_isr = NULL;
wvd_vegt 0:af45bc81d34c 99 }
wvd_vegt 0:af45bc81d34c 100
wvd_vegt 0:af45bc81d34c 101 void RIT::enable(void) {
wvd_vegt 0:af45bc81d34c 102 // Enable RIT interrupt
wvd_vegt 0:af45bc81d34c 103 NVIC_EnableIRQ(RIT_IRQn);
wvd_vegt 0:af45bc81d34c 104
wvd_vegt 0:af45bc81d34c 105 // Enable the RIT
wvd_vegt 0:af45bc81d34c 106 LPC_RIT->RICTRL |= (8L); //RITEN;
wvd_vegt 0:af45bc81d34c 107 }
wvd_vegt 0:af45bc81d34c 108
wvd_vegt 0:af45bc81d34c 109 void RIT::disable(void) {
wvd_vegt 0:af45bc81d34c 110 // Disable RIT interrupt
wvd_vegt 0:af45bc81d34c 111 NVIC_DisableIRQ(RIT_IRQn);
wvd_vegt 0:af45bc81d34c 112
wvd_vegt 0:af45bc81d34c 113 // Disable the RIT
wvd_vegt 0:af45bc81d34c 114 LPC_RIT->RICTRL &= ~(8L); //RITEN;
wvd_vegt 0:af45bc81d34c 115 }
wvd_vegt 0:af45bc81d34c 116
wvd_vegt 0:af45bc81d34c 117 void RIT::power_enable(void) {
wvd_vegt 0:af45bc81d34c 118 // Power the TRIT
wvd_vegt 0:af45bc81d34c 119 LPC_SC->PCONP |= (1L<<16); //PCRIT
wvd_vegt 0:af45bc81d34c 120 }
wvd_vegt 0:af45bc81d34c 121
wvd_vegt 0:af45bc81d34c 122 void RIT::power_disable(void) {
wvd_vegt 0:af45bc81d34c 123 // Powerdown the RIT
wvd_vegt 0:af45bc81d34c 124 LPC_SC->PCONP &= ~(1L<<16); //PCRIT
wvd_vegt 0:af45bc81d34c 125 }
wvd_vegt 0:af45bc81d34c 126 //------------------------------------------------------------------------------
wvd_vegt 0:af45bc81d34c 127 //Private Stuff.
wvd_vegt 0:af45bc81d34c 128 //------------------------------------------------------------------------------
wvd_vegt 0:af45bc81d34c 129
wvd_vegt 0:af45bc81d34c 130 void RIT::_ritisr(void) {
wvd_vegt 0:af45bc81d34c 131 instance->ritisr();
wvd_vegt 0:af45bc81d34c 132 }
wvd_vegt 0:af45bc81d34c 133
wvd_vegt 0:af45bc81d34c 134 void RIT::ritisr(void) {
wvd_vegt 0:af45bc81d34c 135 // RIT interrupt occured
wvd_vegt 0:af45bc81d34c 136 if ((LPC_RIT->RICTRL & 1L) == 1L) //RITINT
wvd_vegt 0:af45bc81d34c 137 // Clear the RIT interrupt
wvd_vegt 0:af45bc81d34c 138 LPC_RIT->RICTRL |= 1L;
wvd_vegt 0:af45bc81d34c 139
wvd_vegt 0:af45bc81d34c 140 //Call User defined interrupt handlers if any
wvd_vegt 0:af45bc81d34c 141 if (_rit_g_isr != NULL)
wvd_vegt 0:af45bc81d34c 142 _rit_g_isr();
wvd_vegt 0:af45bc81d34c 143 }
wvd_vegt 0:af45bc81d34c 144
wvd_vegt 0:af45bc81d34c 145 void RIT::select_clk(void) {
wvd_vegt 0:af45bc81d34c 146 // Timer0 perhiperal clock select (01: PCLK Peripheral = CCLK)
wvd_vegt 0:af45bc81d34c 147 LPC_SC->PCLKSEL1 &= ~(3L << 26); // Clear PCLK_RIT bits;
wvd_vegt 0:af45bc81d34c 148 LPC_SC->PCLKSEL1 |= (1L << 26); // Set PCLK_RIT bits to 0x01;
wvd_vegt 0:af45bc81d34c 149 }