Wilson Tang / max14724

8:4 Matrix Multiplexer

Fork of max14661 by Maxim Integrated

This is an untested driver for the MAX14724.

max14724.h@10:5a3720e6e017, 2015-04-27 (annotated)

Committer:
wt8008
Date:
Mon Apr 27 17:24:52 2015 +0000
Revision:
10:5a3720e6e017
Initial Import

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wt8008 10:5a3720e6e017 1 /******************************************************************//**
wt8008 10:5a3720e6e017 2 * @file max14724.h
wt8008 10:5a3720e6e017 3 *
wt8008 10:5a3720e6e017 4 * @author Wilson Tang
wt8008 10:5a3720e6e017 5 *
wt8008 10:5a3720e6e017 6 * @version 1.0
wt8008 10:5a3720e6e017 7 *
wt8008 10:5a3720e6e017 8 * Started: 22APR15
wt8008 10:5a3720e6e017 9 *
wt8008 10:5a3720e6e017 10 * Updated:
wt8008 10:5a3720e6e017 11 *
wt8008 10:5a3720e6e017 12 * @brief Header file for MAX14724 class
wt8008 10:5a3720e6e017 13 *
wt8008 10:5a3720e6e017 14 * http://www.maximintegrated.com/max14724
wt8008 10:5a3720e6e017 15 *
wt8008 10:5a3720e6e017 16 ***********************************************************************
wt8008 10:5a3720e6e017 17 *
wt8008 10:5a3720e6e017 18 * @copyright
wt8008 10:5a3720e6e017 19 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
wt8008 10:5a3720e6e017 20 *
wt8008 10:5a3720e6e017 21 * Permission is hereby granted, free of charge, to any person obtaining a
wt8008 10:5a3720e6e017 22 * copy of this software and associated documentation files (the "Software"),
wt8008 10:5a3720e6e017 23 * to deal in the Software without restriction, including without limitation
wt8008 10:5a3720e6e017 24 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
wt8008 10:5a3720e6e017 25 * and/or sell copies of the Software, and to permit persons to whom the
wt8008 10:5a3720e6e017 26 * Software is furnished to do so, subject to the following conditions:
wt8008 10:5a3720e6e017 27 *
wt8008 10:5a3720e6e017 28 * The above copyright notice and this permission notice shall be included
wt8008 10:5a3720e6e017 29 * in all copies or substantial portions of the Software.
wt8008 10:5a3720e6e017 30 *
wt8008 10:5a3720e6e017 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
wt8008 10:5a3720e6e017 32 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
wt8008 10:5a3720e6e017 33 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
wt8008 10:5a3720e6e017 34 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
wt8008 10:5a3720e6e017 35 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
wt8008 10:5a3720e6e017 36 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
wt8008 10:5a3720e6e017 37 * OTHER DEALINGS IN THE SOFTWARE.
wt8008 10:5a3720e6e017 38 *
wt8008 10:5a3720e6e017 39 * Except as contained in this notice, the name of Maxim Integrated
wt8008 10:5a3720e6e017 40 * Products, Inc. shall not be used except as stated in the Maxim Integrated
wt8008 10:5a3720e6e017 41 * Products, Inc. Branding Policy.
wt8008 10:5a3720e6e017 42 *
wt8008 10:5a3720e6e017 43 * The mere transfer of this software does not imply any licenses
wt8008 10:5a3720e6e017 44 * of trade secrets, proprietary technology, copyrights, patents,
wt8008 10:5a3720e6e017 45 * trademarks, maskwork rights, or any other form of intellectual
wt8008 10:5a3720e6e017 46 * property whatsoever. Maxim Integrated Products, Inc. retains all
wt8008 10:5a3720e6e017 47 * ownership rights.
wt8008 10:5a3720e6e017 48 **********************************************************************/
wt8008 10:5a3720e6e017 49
wt8008 10:5a3720e6e017 50
wt8008 10:5a3720e6e017 51 #ifndef MAX14724_H
wt8008 10:5a3720e6e017 52 #define MAX14724_H
wt8008 10:5a3720e6e017 53
wt8008 10:5a3720e6e017 54
wt8008 10:5a3720e6e017 55 #include "mbed.h"
wt8008 10:5a3720e6e017 56
wt8008 10:5a3720e6e017 57
wt8008 10:5a3720e6e017 58 /******************************************************************//**
wt8008 10:5a3720e6e017 59 * Max14724 Class
wt8008 10:5a3720e6e017 60 **********************************************************************/
wt8008 10:5a3720e6e017 61 class Max14724 : public I2C
wt8008 10:5a3720e6e017 62 {
wt8008 10:5a3720e6e017 63 uint8_t w_adrs, r_adrs;
wt8008 10:5a3720e6e017 64
wt8008 10:5a3720e6e017 65 public:
wt8008 10:5a3720e6e017 66
wt8008 10:5a3720e6e017 67 /**
wt8008 10:5a3720e6e017 68 * max14724_i2c_adrs_t - enumerated MAX14724 I2C Addresses
wt8008 10:5a3720e6e017 69 */
wt8008 10:5a3720e6e017 70 typedef enum
wt8008 10:5a3720e6e017 71 {
wt8008 10:5a3720e6e017 72 MAX14724_I2C_ADRS0 = 0x74,
wt8008 10:5a3720e6e017 73 MAX14724_I2C_ADRS1
wt8008 10:5a3720e6e017 74 }max14724_i2c_adrs_t;
wt8008 10:5a3720e6e017 75
wt8008 10:5a3720e6e017 76
wt8008 10:5a3720e6e017 77 /**
wt8008 10:5a3720e6e017 78 * max14724_regs_t - enumerated MAX14724 register addresses
wt8008 10:5a3720e6e017 79 */
wt8008 10:5a3720e6e017 80 typedef enum
wt8008 10:5a3720e6e017 81 {
wt8008 10:5a3720e6e017 82 DIR0, //Switches 8A–1A direct read/write access
wt8008 10:5a3720e6e017 83 DIR1, //Switches 8B–1B direct read/write access
wt8008 10:5a3720e6e017 84 DIR2, //Switches 8C–1C direct read/write access
wt8008 10:5a3720e6e017 85 DIR3, //Switches 8D–1D direct read/write access
wt8008 10:5a3720e6e017 86 SHDW0 = 0x10, //Switches 8A–1A shadow read/write access
wt8008 10:5a3720e6e017 87 SHDW1, //Switches 8B–1B shadow read/write access
wt8008 10:5a3720e6e017 88 SHDW2, //Switches 8C–1C shadow read/write access
wt8008 10:5a3720e6e017 89 SHDW3, //Switches 8D–1D shadow read/write access
wt8008 10:5a3720e6e017 90 CMD0, //Set mux A and B command (reads 0x00)
wt8008 10:5a3720e6e017 91 CMD1 //Set mux C and D command (reads 0x00)
wt8008 10:5a3720e6e017 92 }max14724_regs_t;
wt8008 10:5a3720e6e017 93
wt8008 10:5a3720e6e017 94
wt8008 10:5a3720e6e017 95 /**
wt8008 10:5a3720e6e017 96 * max14724_cmds_t - enumerated MAX14724 commands
wt8008 10:5a3720e6e017 97 */
wt8008 10:5a3720e6e017 98 typedef enum
wt8008 10:5a3720e6e017 99 {
wt8008 10:5a3720e6e017 100 ENABLE_SW01, //enables sw1 on bank only
wt8008 10:5a3720e6e017 101 ENABLE_SW02, //enables sw2 on bank only
wt8008 10:5a3720e6e017 102 ENABLE_SW03, //enables sw3 on bank only
wt8008 10:5a3720e6e017 103 ENABLE_SW04, //enables sw4 on bank only
wt8008 10:5a3720e6e017 104 ENABLE_SW05, //enables sw5 on bank only
wt8008 10:5a3720e6e017 105 ENABLE_SW06, //enables sw6 on bank only
wt8008 10:5a3720e6e017 106 ENABLE_SW07, //enables sw7 on bank only
wt8008 10:5a3720e6e017 107 ENABLE_SW08, //enables sw8 on bank only
wt8008 10:5a3720e6e017 108 DISABLE_BANK, //opens all switches on bank
wt8008 10:5a3720e6e017 109 COPY_SHADOW, //copies both shadow registers for bank
wt8008 10:5a3720e6e017 110 NO_CHANGE
wt8008 10:5a3720e6e017 111 }max14724_cmds_t;
wt8008 10:5a3720e6e017 112
wt8008 10:5a3720e6e017 113
wt8008 10:5a3720e6e017 114 /**
wt8008 10:5a3720e6e017 115 * max14724_sw_t - enumerated MAX14724 switch bitmasks
wt8008 10:5a3720e6e017 116 */
wt8008 10:5a3720e6e017 117 typedef enum
wt8008 10:5a3720e6e017 118 {
wt8008 10:5a3720e6e017 119 SW01 = (1 << 0),
wt8008 10:5a3720e6e017 120 SW02 = (1 << 1),
wt8008 10:5a3720e6e017 121 SW03 = (1 << 2),
wt8008 10:5a3720e6e017 122 SW04 = (1 << 3),
wt8008 10:5a3720e6e017 123 SW05 = (1 << 4),
wt8008 10:5a3720e6e017 124 SW06 = (1 << 5),
wt8008 10:5a3720e6e017 125 SW07 = (1 << 6),
wt8008 10:5a3720e6e017 126 SW08 = (1 << 7)
wt8008 10:5a3720e6e017 127 }max14724_sw_t;
wt8008 10:5a3720e6e017 128
wt8008 10:5a3720e6e017 129
wt8008 10:5a3720e6e017 130 /**********************************************************//**
wt8008 10:5a3720e6e017 131 * Constructor for Max14724 Class
wt8008 10:5a3720e6e017 132 *
wt8008 10:5a3720e6e017 133 * On Entry:
wt8008 10:5a3720e6e017 134 * @param[in] sda - sda pin of I2C bus
wt8008 10:5a3720e6e017 135 * @param[in] scl - scl pin of I2C bus
wt8008 10:5a3720e6e017 136 * @param[in] i2c_adrs - 7-bit slave address of MAX14724
wt8008 10:5a3720e6e017 137 *
wt8008 10:5a3720e6e017 138 * On Exit:
wt8008 10:5a3720e6e017 139 * @return none
wt8008 10:5a3720e6e017 140 *
wt8008 10:5a3720e6e017 141 * Example:
wt8008 10:5a3720e6e017 142 * @code
wt8008 10:5a3720e6e017 143 *
wt8008 10:5a3720e6e017 144 * //declare mux object
wt8008 10:5a3720e6e017 145 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 146 *
wt8008 10:5a3720e6e017 147 * @endcode
wt8008 10:5a3720e6e017 148 **************************************************************/
wt8008 10:5a3720e6e017 149 Max14724(PinName sda, PinName scl, max14724_i2c_adrs_t i2c_adrs);
wt8008 10:5a3720e6e017 150
wt8008 10:5a3720e6e017 151
wt8008 10:5a3720e6e017 152 /******************************************************************//**
wt8008 10:5a3720e6e017 153 * Writes given commands to CMD_A, CMD_B, CMD_C, and CMD_D
wt8008 10:5a3720e6e017 154 *
wt8008 10:5a3720e6e017 155 * On Entry:
wt8008 10:5a3720e6e017 156 * @param[in] cmdA - command for CMD_A
wt8008 10:5a3720e6e017 157 * @param[in] cmdB - command for CMD_B
wt8008 10:5a3720e6e017 158 * @param[in] cmdC - command for CMD_C
wt8008 10:5a3720e6e017 159 * @param[in] cmdD - command for CMD_D
wt8008 10:5a3720e6e017 160 *
wt8008 10:5a3720e6e017 161 * On Exit:
wt8008 10:5a3720e6e017 162 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 163 *
wt8008 10:5a3720e6e017 164 * Example:
wt8008 10:5a3720e6e017 165 * @code
wt8008 10:5a3720e6e017 166 *
wt8008 10:5a3720e6e017 167 * //declare mux object
wt8008 10:5a3720e6e017 168 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 169 *
wt8008 10:5a3720e6e017 170 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 171 *
wt8008 10:5a3720e6e017 172 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK, DISABLE_BANK, DISABLE_BANK);
wt8008 10:5a3720e6e017 173 *
wt8008 10:5a3720e6e017 174 * @endcode
wt8008 10:5a3720e6e017 175 **********************************************************************/
wt8008 10:5a3720e6e017 176 uint16_t wrt_cmd_registers(max14724_cmds_t cmdA, max14724_cmds_t cmdB, max14724_cmds_t cmdC, max14724_cmds_t cmdD);
wt8008 10:5a3720e6e017 177
wt8008 10:5a3720e6e017 178
wt8008 10:5a3720e6e017 179 /******************************************************************//**
wt8008 10:5a3720e6e017 180 * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
wt8008 10:5a3720e6e017 181 *
wt8008 10:5a3720e6e017 182 * On Entry:
wt8008 10:5a3720e6e017 183 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 184 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 185 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 186 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 187 *
wt8008 10:5a3720e6e017 188 * On Exit:
wt8008 10:5a3720e6e017 189 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 190 *
wt8008 10:5a3720e6e017 191 * Example:
wt8008 10:5a3720e6e017 192 * @code
wt8008 10:5a3720e6e017 193 *
wt8008 10:5a3720e6e017 194 * //declare mux object
wt8008 10:5a3720e6e017 195 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 196 *
wt8008 10:5a3720e6e017 197 * uint16_t bankA = (SW03 | SW02); //example only
wt8008 10:5a3720e6e017 198 * uint16_t bankB = (SW05 | SW04);
wt8008 10:5a3720e6e017 199 * uint16_t bankC = SW07;
wt8008 10:5a3720e6e017 200 * uint16_t bankD = SW08;
wt8008 10:5a3720e6e017 201 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 202 *
wt8008 10:5a3720e6e017 203 * //wite shadow registers
wt8008 10:5a3720e6e017 204 * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 205 *
wt8008 10:5a3720e6e017 206 * @endcode
wt8008 10:5a3720e6e017 207 **********************************************************************/
wt8008 10:5a3720e6e017 208 uint16_t wrt_shadow_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
wt8008 10:5a3720e6e017 209
wt8008 10:5a3720e6e017 210
wt8008 10:5a3720e6e017 211 /******************************************************************//**
wt8008 10:5a3720e6e017 212 * Writes bankA, bankB, bankC, and bankD to coresponding direct access registers
wt8008 10:5a3720e6e017 213 *
wt8008 10:5a3720e6e017 214 * On Entry:
wt8008 10:5a3720e6e017 215 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 216 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 217 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 218 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 219 *
wt8008 10:5a3720e6e017 220 * On Exit:
wt8008 10:5a3720e6e017 221 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 222 *
wt8008 10:5a3720e6e017 223 * Example:
wt8008 10:5a3720e6e017 224 * @code
wt8008 10:5a3720e6e017 225 *
wt8008 10:5a3720e6e017 226 * //declare mux object
wt8008 10:5a3720e6e017 227 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 228 *
wt8008 10:5a3720e6e017 229 * uint16_t bankA = (SW12 | SW02); //example only
wt8008 10:5a3720e6e017 230 * uint16_t bankB = (SW11 | SW01);
wt8008 10:5a3720e6e017 231 * uint16_t bankC = SW07;
wt8008 10:5a3720e6e017 232 * uint16_t bankD = SW08;
wt8008 10:5a3720e6e017 233 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 234 *
wt8008 10:5a3720e6e017 235 * //wite shadow registers
wt8008 10:5a3720e6e017 236 * rtn_val = mux.wrt_dir_registers(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 237 *
wt8008 10:5a3720e6e017 238 * @endcode
wt8008 10:5a3720e6e017 239 **********************************************************************/
wt8008 10:5a3720e6e017 240 uint16_t wrt_dir_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
wt8008 10:5a3720e6e017 241
wt8008 10:5a3720e6e017 242
wt8008 10:5a3720e6e017 243 /******************************************************************//**
wt8008 10:5a3720e6e017 244 * Writes bankA, bankB, bankC, and bankD to coresponding shadow register and then
wt8008 10:5a3720e6e017 245 * issues copy command for both banks
wt8008 10:5a3720e6e017 246 *
wt8008 10:5a3720e6e017 247 * On Entry:
wt8008 10:5a3720e6e017 248 * @param[in] bankA - binary representation of switch states
wt8008 10:5a3720e6e017 249 * @param[in] bankB - binary representation of switch states
wt8008 10:5a3720e6e017 250 * @param[in] bankC - binary representation of switch states
wt8008 10:5a3720e6e017 251 * @param[in] bankD - binary representation of switch states
wt8008 10:5a3720e6e017 252 *
wt8008 10:5a3720e6e017 253 * On Exit:
wt8008 10:5a3720e6e017 254 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 255 *
wt8008 10:5a3720e6e017 256 * Example:
wt8008 10:5a3720e6e017 257 * @code
wt8008 10:5a3720e6e017 258 *
wt8008 10:5a3720e6e017 259 * //declare mux object
wt8008 10:5a3720e6e017 260 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 261 *
wt8008 10:5a3720e6e017 262 * uint16_t bankA = (SW12 | SW02); //example only
wt8008 10:5a3720e6e017 263 * uint16_t bankB = (SW11 | SW01);
wt8008 10:5a3720e6e017 264 * uint16_t bankC = SW07;
wt8008 10:5a3720e6e017 265 * uint16_t bankD = SW08;
wt8008 10:5a3720e6e017 266 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 267 *
wt8008 10:5a3720e6e017 268 * //wite shadow registers
wt8008 10:5a3720e6e017 269 * rtn_val = mux.set_switches(bankA, bankB, bankC, bankD);
wt8008 10:5a3720e6e017 270 *
wt8008 10:5a3720e6e017 271 * @endcode
wt8008 10:5a3720e6e017 272 **********************************************************************/
wt8008 10:5a3720e6e017 273 uint16_t set_switches(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
wt8008 10:5a3720e6e017 274
wt8008 10:5a3720e6e017 275
wt8008 10:5a3720e6e017 276 /**********************************************************//**
wt8008 10:5a3720e6e017 277 * Reads data from direct access registers starting at DIR0 and
wt8008 10:5a3720e6e017 278 * stores it in byte array pointed at by 'data'
wt8008 10:5a3720e6e017 279 *
wt8008 10:5a3720e6e017 280 * On Entry:
wt8008 10:5a3720e6e017 281 * @param[in] data - pointer to byte array for storing data
wt8008 10:5a3720e6e017 282 *
wt8008 10:5a3720e6e017 283 * On Exit:
wt8008 10:5a3720e6e017 284 * @param[out] data - data buffer now contains data read
wt8008 10:5a3720e6e017 285 * from dir registers
wt8008 10:5a3720e6e017 286 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 287 *
wt8008 10:5a3720e6e017 288 * Example:
wt8008 10:5a3720e6e017 289 * @code
wt8008 10:5a3720e6e017 290 *
wt8008 10:5a3720e6e017 291 * //declare mux object
wt8008 10:5a3720e6e017 292 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 293 *
wt8008 10:5a3720e6e017 294 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 295 * uint8_t data[4];
wt8008 10:5a3720e6e017 296 *
wt8008 10:5a3720e6e017 297 * //read direct access registers
wt8008 10:5a3720e6e017 298 * rtn_val = mux.rd_dir_registers(data);
wt8008 10:5a3720e6e017 299 *
wt8008 10:5a3720e6e017 300 * @endcode
wt8008 10:5a3720e6e017 301 **********************************************************************/
wt8008 10:5a3720e6e017 302 uint16_t rd_dir_registers(uint8_t* data);
wt8008 10:5a3720e6e017 303
wt8008 10:5a3720e6e017 304
wt8008 10:5a3720e6e017 305 /**********************************************************//**
wt8008 10:5a3720e6e017 306 * Reads data from shadow registers starting at SHDW0 and stores
wt8008 10:5a3720e6e017 307 * it in byte array pointed at by 'data'
wt8008 10:5a3720e6e017 308 *
wt8008 10:5a3720e6e017 309 * On Entry:
wt8008 10:5a3720e6e017 310 * @param[in] data - pointer to byte array for storing data
wt8008 10:5a3720e6e017 311 *
wt8008 10:5a3720e6e017 312 * On Exit:
wt8008 10:5a3720e6e017 313 * @param[out] data - data buffer now contains data read
wt8008 10:5a3720e6e017 314 * from shadow registers
wt8008 10:5a3720e6e017 315 * @return return value = 0 on success, non-0 on failure
wt8008 10:5a3720e6e017 316 *
wt8008 10:5a3720e6e017 317 * Example:
wt8008 10:5a3720e6e017 318 * @code
wt8008 10:5a3720e6e017 319 *
wt8008 10:5a3720e6e017 320 * //declare mux object
wt8008 10:5a3720e6e017 321 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
wt8008 10:5a3720e6e017 322 *
wt8008 10:5a3720e6e017 323 * uint16_t rtn_val;
wt8008 10:5a3720e6e017 324 * uint8_t data[4];
wt8008 10:5a3720e6e017 325 *
wt8008 10:5a3720e6e017 326 * //read shadow registers
wt8008 10:5a3720e6e017 327 * rtn_val = mux.rd_shadow_registers(data);
wt8008 10:5a3720e6e017 328 *
wt8008 10:5a3720e6e017 329 * @endcode
wt8008 10:5a3720e6e017 330 **************************************************************/
wt8008 10:5a3720e6e017 331 uint16_t rd_shadow_registers(uint8_t* data);
wt8008 10:5a3720e6e017 332 };
wt8008 10:5a3720e6e017 333
wt8008 10:5a3720e6e017 334
wt8008 10:5a3720e6e017 335 #endif /* MAX14724_H*/