Wim Huiskamp / SC16IS750

SPI or I2C to UART Bridge

Dependents:   SC16IS750_Test mbed_SC16IS750 Xadow_SC16IS750_Test Xadow_MPU9150AHRS

SC16IS750.cpp@4:12446ee9f9c8, 2014-12-22 (annotated)

Committer:
wim
Date:
Mon Dec 22 19:04:38 2014 +0000
Revision:
4:12446ee9f9c8
Parent:
3:9783b6bde958
Child:
5:ff3e57bebb6a
Added support for SC16IS752 Dual UART device.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 3:9783b6bde958 1 /* SC16IS750 I2C or SPI to UART bridge
wim 3:9783b6bde958 2 * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods.
wim 3:9783b6bde958 3 * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846
wim 4:12446ee9f9c8 4 * v0.2 WH, Feb 2014, Added Doxygen Documentation, Added Hardware Reset pin methods.
wim 4:12446ee9f9c8 5 * v0.3 WH, Dec 2014, Added support for SC16IS752 dual UART.
wim 0:d64854a60f95 6 *
wim 0:d64854a60f95 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
wim 0:d64854a60f95 8 * and associated documentation files (the "Software"), to deal in the Software without restriction,
wim 0:d64854a60f95 9 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
wim 0:d64854a60f95 10 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
wim 0:d64854a60f95 11 * furnished to do so, subject to the following conditions:
wim 0:d64854a60f95 12 *
wim 0:d64854a60f95 13 * The above copyright notice and this permission notice shall be included in all copies or
wim 0:d64854a60f95 14 * substantial portions of the Software.
wim 0:d64854a60f95 15 *
wim 0:d64854a60f95 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
wim 0:d64854a60f95 17 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
wim 0:d64854a60f95 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
wim 0:d64854a60f95 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
wim 0:d64854a60f95 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
wim 0:d64854a60f95 21 */
wim 0:d64854a60f95 22 #include "mbed.h"
wim 0:d64854a60f95 23 #include "SC16IS750.h"
wim 0:d64854a60f95 24
wim 3:9783b6bde958 25 #define ENABLE_BULK_TRANSFERS 1
wim 3:9783b6bde958 26 #define BULK_BLOCK_LEN 16
wim 0:d64854a60f95 27
wim 0:d64854a60f95 28 /** Abstract class SC16IS750 for converter between either SPI or I2C and a Serial port
wim 1:0440152c5387 29 * Constructor for this Abstract Class is protected
wim 0:d64854a60f95 30 * Supports both SPI and I2C interfaces through derived classes
wim 0:d64854a60f95 31 *
wim 0:d64854a60f95 32 * @code
wim 0:d64854a60f95 33 *
wim 0:d64854a60f95 34 * @endcode
wim 0:d64854a60f95 35 */
wim 3:9783b6bde958 36 SC16IS750::SC16IS750() {
wim 3:9783b6bde958 37 //SC16IS750::SC16IS750() : Serial(NC, NC) { //Fout, mag geen NC zijn
wim 3:9783b6bde958 38 //SC16IS750::SC16IS750() : SerialBase(NC, NC) { //Fout, mag geen NC zijn
wim 1:0440152c5387 39 // Dont call _init() here since the SPI or I2C port have not yet been configured...
wim 1:0440152c5387 40 //_init(); // initialise UART registers
wim 0:d64854a60f95 41 }
wim 0:d64854a60f95 42
wim 0:d64854a60f95 43
wim 0:d64854a60f95 44 /** Set baudrate of the serial port.
wim 0:d64854a60f95 45 * @param baud integer baudrate (4800, 9600 etc)
wim 0:d64854a60f95 46 * @return none
wim 0:d64854a60f95 47 */
wim 0:d64854a60f95 48 void SC16IS750::baud(int baudrate) {
wim 2:76cb93b511f2 49 unsigned long divisor = SC16IS750_BAUDRATE_DIVISOR(baudrate);
wim 0:d64854a60f95 50 char lcr_tmp;
wim 0:d64854a60f95 51
wim 0:d64854a60f95 52 _config.baudrate = baudrate; // Save baudrate
wim 0:d64854a60f95 53
wim 0:d64854a60f95 54 lcr_tmp = this->readRegister(LCR); // Read current LCR register
wim 1:0440152c5387 55 this->writeRegister(LCR, lcr_tmp | LCR_ENABLE_DIV); // Enable Divisor registers
wim 0:d64854a60f95 56 this->writeRegister(DLL, ( divisor & 0xFF)); // write divisor LSB
wim 0:d64854a60f95 57 this->writeRegister(DLH, ((divisor >> 8) & 0xFF)); // write divisor MSB
wim 0:d64854a60f95 58 this->writeRegister(LCR, lcr_tmp); // Restore LCR register, activate regular RBR, THR and IER registers
wim 1:0440152c5387 59
wim 0:d64854a60f95 60 }
wim 0:d64854a60f95 61
wim 0:d64854a60f95 62
wim 0:d64854a60f95 63 /** Set the transmission format used by the serial port.
wim 0:d64854a60f95 64 * @param bits The number of bits in a word (5-8; default = 8)
wim 0:d64854a60f95 65 * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
wim 0:d64854a60f95 66 * @param stop_bits The number of stop bits (1 or 2; default = 1)
wim 2:76cb93b511f2 67 * @return none
wim 0:d64854a60f95 68 */
wim 0:d64854a60f95 69 void SC16IS750::format(int bits, Serial::Parity parity, int stop_bits) {
wim 0:d64854a60f95 70 char lcr_tmp = 0x00;
wim 0:d64854a60f95 71
wim 0:d64854a60f95 72 switch (bits) {
wim 0:d64854a60f95 73 case 5: lcr_tmp |= LCR_BITS5;
wim 0:d64854a60f95 74 break;
wim 0:d64854a60f95 75 case 6: lcr_tmp |= LCR_BITS6;
wim 0:d64854a60f95 76 break;
wim 0:d64854a60f95 77 case 7: lcr_tmp |= LCR_BITS7;
wim 0:d64854a60f95 78 break;
wim 0:d64854a60f95 79 case 8: lcr_tmp |= LCR_BITS8;
wim 0:d64854a60f95 80 break;
wim 0:d64854a60f95 81 default: lcr_tmp |= LCR_BITS8;
wim 0:d64854a60f95 82 }
wim 0:d64854a60f95 83
wim 0:d64854a60f95 84 switch (parity) {
wim 0:d64854a60f95 85 case Serial::None: lcr_tmp |= LCR_NONE;
wim 0:d64854a60f95 86 break;
wim 0:d64854a60f95 87 case Serial::Odd: lcr_tmp |= LCR_ODD;
wim 0:d64854a60f95 88 break;
wim 0:d64854a60f95 89 case Serial::Even: lcr_tmp |= LCR_EVEN;
wim 0:d64854a60f95 90 break;
wim 0:d64854a60f95 91 case Serial::Forced1: lcr_tmp |= LCR_FORCED1;
wim 0:d64854a60f95 92 break;
wim 0:d64854a60f95 93 case Serial::Forced0: lcr_tmp |= LCR_FORCED0;
wim 0:d64854a60f95 94 break;
wim 0:d64854a60f95 95 default: lcr_tmp |= LCR_NONE;
wim 0:d64854a60f95 96 }
wim 0:d64854a60f95 97
wim 0:d64854a60f95 98 switch (stop_bits) {
wim 0:d64854a60f95 99 case 1: lcr_tmp |= LCR_BITS1;
wim 0:d64854a60f95 100 break;
wim 0:d64854a60f95 101 case 2: lcr_tmp |= LCR_BITS2;
wim 0:d64854a60f95 102 break;
wim 0:d64854a60f95 103 default: lcr_tmp |= LCR_BITS1;
wim 0:d64854a60f95 104 }
wim 0:d64854a60f95 105
wim 0:d64854a60f95 106 _config.dataformat = lcr_tmp; // Save dataformat
wim 0:d64854a60f95 107
wim 0:d64854a60f95 108 this->writeRegister(LCR, lcr_tmp); // Set LCR register, activate regular RBR, THR and IER registers
wim 0:d64854a60f95 109
wim 0:d64854a60f95 110 };
wim 0:d64854a60f95 111
wim 1:0440152c5387 112 /** Generate a break condition on the serial line
wim 2:76cb93b511f2 113 * @return none
wim 1:0440152c5387 114 */
wim 1:0440152c5387 115 void SC16IS750::send_break() {
wim 1:0440152c5387 116 // Wait for 1.5 frames before clearing the break condition
wim 1:0440152c5387 117 // This will have different effects on our platforms, but should
wim 1:0440152c5387 118 // ensure that we keep the break active for at least one frame.
wim 1:0440152c5387 119 // We consider a full frame (1 start bit + 8 data bits bits +
wim 1:0440152c5387 120 // 1 parity bit + 2 stop bits = 12 bits) for computation.
wim 1:0440152c5387 121 // One bit time (in us) = 1000000/_baud
wim 1:0440152c5387 122 // Twelve bits: 12000000/baud delay
wim 1:0440152c5387 123 // 1.5 frames: 18000000/baud delay
wim 1:0440152c5387 124 set_break(true);
wim 1:0440152c5387 125 wait_us(18000000/_config.baudrate);
wim 1:0440152c5387 126 set_break(false);
wim 1:0440152c5387 127 };
wim 1:0440152c5387 128
wim 1:0440152c5387 129 /** Set a break condition on the serial line
wim 1:0440152c5387 130 * @param enable break condition
wim 2:76cb93b511f2 131 * @return none
wim 1:0440152c5387 132 */
wim 1:0440152c5387 133 void SC16IS750::set_break(bool enable) {
wim 0:d64854a60f95 134
wim 1:0440152c5387 135 if (enable) {
wim 1:0440152c5387 136 _config.dataformat |= LCR_BRK_ENA; // Save dataformat
wim 1:0440152c5387 137 }
wim 1:0440152c5387 138 else {
wim 1:0440152c5387 139 _config.dataformat &= ~LCR_BRK_ENA; // Save dataformat
wim 1:0440152c5387 140 }
wim 1:0440152c5387 141
wim 1:0440152c5387 142 this->writeRegister(LCR, _config.dataformat); // Set LCR register
wim 1:0440152c5387 143 }
wim 1:0440152c5387 144
wim 1:0440152c5387 145 /** Set the flow control type on the serial port
wim 1:0440152c5387 146 * Added for compatibility with Serial Class.
wim 1:0440152c5387 147 * SC16IS750 supports only Flow, Pins can not be selected.
wim 3:9783b6bde958 148 * This method sets hardware flow control. SC16IS750 supports XON/XOFF, but this is not implemented.
wim 0:d64854a60f95 149 *
wim 1:0440152c5387 150 * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
wim 2:76cb93b511f2 151 * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) - NOT USED
wim 2:76cb93b511f2 152 * @param flow2 the second flow control pin (CTS for RTSCTS) - NOT USED
wim 2:76cb93b511f2 153 * @return none
wim 0:d64854a60f95 154 */
wim 1:0440152c5387 155 void SC16IS750::set_flow_control(Flow type, PinName flow1, PinName flow2) {
wim 1:0440152c5387 156 char lcr_tmp;
wim 1:0440152c5387 157 char efr_tmp = 0x00;
wim 1:0440152c5387 158
wim 1:0440152c5387 159 // We need to enable flow control to prevent overflow of buffers and
wim 1:0440152c5387 160 // lose data when used with fast devices like the WiFly.
wim 1:0440152c5387 161
wim 1:0440152c5387 162 switch (type) {
wim 1:0440152c5387 163 case Disabled :
wim 1:0440152c5387 164 break;
wim 1:0440152c5387 165 case RTS: efr_tmp = EFR_ENABLE_RTS;
wim 1:0440152c5387 166 break;
wim 1:0440152c5387 167 case CTS: efr_tmp = EFR_ENABLE_CTS;
wim 1:0440152c5387 168 break;
wim 1:0440152c5387 169 case RTSCTS: efr_tmp = EFR_ENABLE_RTS | EFR_ENABLE_CTS;
wim 1:0440152c5387 170 break;
wim 1:0440152c5387 171 default: ;
wim 1:0440152c5387 172
wim 1:0440152c5387 173 }
wim 1:0440152c5387 174
wim 2:76cb93b511f2 175 //Save flowcontrol mode and enable enhanced functions
wim 2:76cb93b511f2 176 _config.flowctrl = efr_tmp | EFR_ENABLE_ENHANCED_FUNCTIONS;
wim 1:0440152c5387 177
wim 1:0440152c5387 178 lcr_tmp = this->readRegister(LCR); // save LRC register
wim 1:0440152c5387 179 this->writeRegister(LCR, LCR_ENABLE_ENHANCED_FUNCTIONS); // write magic number 0xBF to enable access to EFR register
wim 1:0440152c5387 180 this->writeRegister(EFR, _config.flowctrl); // set flow and enable enhanced functions
wim 1:0440152c5387 181 this->writeRegister(LCR, lcr_tmp); // restore LCR register
wim 1:0440152c5387 182 }
wim 2:76cb93b511f2 183
wim 2:76cb93b511f2 184 /** Set the RX FIFO flow control levels
wim 3:9783b6bde958 185 * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented.
wim 2:76cb93b511f2 186 * Should be called BEFORE Auto RTS is enabled.
wim 2:76cb93b511f2 187 *
wim 2:76cb93b511f2 188 * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 189 * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4)
wim 2:76cb93b511f2 190 * @return none
wim 2:76cb93b511f2 191 */
wim 2:76cb93b511f2 192 void SC16IS750::set_flow_triggers(int resume, int halt) {
wim 2:76cb93b511f2 193
wim 2:76cb93b511f2 194 // sanity checks
wim 2:76cb93b511f2 195 halt = halt & 0x0F;
wim 2:76cb93b511f2 196 resume = resume & 0x0F;
wim 2:76cb93b511f2 197 if (halt <= resume) {
wim 2:76cb93b511f2 198 halt = TCR_HALT_DEFAULT;
wim 2:76cb93b511f2 199 resume = TCR_RESUME_DEFAULT;
wim 2:76cb93b511f2 200 }
wim 2:76cb93b511f2 201
wim 2:76cb93b511f2 202 // Note: TCR accessible only when EFR[4]=1 and MCR[2]=1
wim 2:76cb93b511f2 203 this->writeRegister(TCR, (resume << 4) | halt); // set TCR register
wim 2:76cb93b511f2 204 }
wim 2:76cb93b511f2 205
wim 2:76cb93b511f2 206
wim 2:76cb93b511f2 207 /** Set the Modem Control register
wim 2:76cb93b511f2 208 * This method sets prescaler, enables TCR and TLR
wim 2:76cb93b511f2 209 *
wim 2:76cb93b511f2 210 * @param none
wim 2:76cb93b511f2 211 * @return none
wim 2:76cb93b511f2 212 */
wim 2:76cb93b511f2 213 void SC16IS750::set_modem_control() {
wim 2:76cb93b511f2 214
wim 2:76cb93b511f2 215 //Note MCR[7:4] and MCR[2] only accessible when EFR[4] is set
wim 2:76cb93b511f2 216 if (SC16IS750_PRESCALER == SC16IS750_PRESCALER_1) { // Default prescaler after reset
wim 2:76cb93b511f2 217 this->writeRegister(MCR, MCR_PRESCALE_1 | MCR_ENABLE_TCR_TLR);
wim 2:76cb93b511f2 218 }
wim 2:76cb93b511f2 219 else {
wim 2:76cb93b511f2 220 this->writeRegister(MCR, MCR_PRESCALE_4 | MCR_ENABLE_TCR_TLR);
wim 2:76cb93b511f2 221 }
wim 2:76cb93b511f2 222 }
wim 2:76cb93b511f2 223
wim 1:0440152c5387 224
wim 1:0440152c5387 225
wim 1:0440152c5387 226 /** Initialise internal registers
wim 1:0440152c5387 227 * Should be in protection section. Public for testing purposes
wim 1:0440152c5387 228 * If initialisation fails this method does not return.
wim 1:0440152c5387 229 * @param none
wim 1:0440152c5387 230 * @return none
wim 1:0440152c5387 231 */
wim 1:0440152c5387 232 void SC16IS750::_init() {
wim 0:d64854a60f95 233
wim 0:d64854a60f95 234 // Initialise SC16IS750
wim 0:d64854a60f95 235
wim 4:12446ee9f9c8 236 // Hardware reset, assuming there is a HW Reset pin
wim 4:12446ee9f9c8 237 // this->hwReset();
wim 4:12446ee9f9c8 238
wim 1:0440152c5387 239 // Software reset, assuming there is no access to the HW Reset pin
wim 1:0440152c5387 240 swReset();
wim 4:12446ee9f9c8 241
wim 2:76cb93b511f2 242 // Set default baudrate (depends on prescaler) and save in _config
wim 2:76cb93b511f2 243 // DLL/DLH
wim 0:d64854a60f95 244 baud();
wim 0:d64854a60f95 245
wim 0:d64854a60f95 246 // Set default dataformat and save in _config
wim 1:0440152c5387 247 // LCR
wim 0:d64854a60f95 248 format();
wim 0:d64854a60f95 249
wim 2:76cb93b511f2 250 // Set dataflow mode and Enables enhanced functions
wim 2:76cb93b511f2 251 // Save in _config
wim 2:76cb93b511f2 252 // EFR
wim 2:76cb93b511f2 253 set_flow_control();
wim 2:76cb93b511f2 254
wim 2:76cb93b511f2 255
wim 3:9783b6bde958 256 // FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config
wim 2:76cb93b511f2 257 // Note FCR[5:4] only accessible when EFR[4] is set (enhanced functions enable)
wim 2:76cb93b511f2 258 // FCR, TLR
wim 2:76cb93b511f2 259 set_fifo_control();
wim 2:76cb93b511f2 260 flush();
wim 2:76cb93b511f2 261
wim 2:76cb93b511f2 262 // Modem control, sets prescaler, enable TCR and TLR
wim 2:76cb93b511f2 263 // Note MCR[7:4] and MCR[2] only accessible when EFR[4] is set (enhanced functions enable)
wim 2:76cb93b511f2 264 set_modem_control();
wim 2:76cb93b511f2 265
wim 2:76cb93b511f2 266 // Set RTS trigger levels
wim 2:76cb93b511f2 267 // Note TCR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set
wim 2:76cb93b511f2 268 set_flow_triggers();
wim 2:76cb93b511f2 269
wim 2:76cb93b511f2 270
wim 1:0440152c5387 271 // Set default break condition and save in _config
wim 1:0440152c5387 272 // LCR
wim 1:0440152c5387 273 //set_break();
wim 2:76cb93b511f2 274
wim 0:d64854a60f95 275 // The UART bridge should now be successfully initialised.
wim 0:d64854a60f95 276
wim 0:d64854a60f95 277 // Test if UART bridge is present and initialised
wim 0:d64854a60f95 278 if(!connected()){
wim 0:d64854a60f95 279 #if(0)
wim 0:d64854a60f95 280 // Lock up if we fail to initialise UART bridge.
wim 1:0440152c5387 281 while(1) {};
wim 0:d64854a60f95 282 #else
wim 0:d64854a60f95 283 printf("Failed to initialise UART bridge\r\n");
wim 1:0440152c5387 284 #endif
wim 1:0440152c5387 285 }
wim 1:0440152c5387 286 else {
wim 1:0440152c5387 287 printf("Initialised UART bridge!\r\n");
wim 1:0440152c5387 288 }
wim 1:0440152c5387 289
wim 1:0440152c5387 290 }
wim 1:0440152c5387 291
wim 2:76cb93b511f2 292
wim 2:76cb93b511f2 293 /** FIFO control, sets TX and RX trigger levels and enables FIFO and save in _config
wim 2:76cb93b511f2 294 * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable)
wim 2:76cb93b511f2 295 * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set
wim 2:76cb93b511f2 296 * @param none
wim 2:76cb93b511f2 297 * @return none
wim 2:76cb93b511f2 298 */
wim 2:76cb93b511f2 299 void SC16IS750::set_fifo_control() {
wim 2:76cb93b511f2 300
wim 2:76cb93b511f2 301 // Set default fifoformat
wim 2:76cb93b511f2 302 // FCR
wim 2:76cb93b511f2 303 _config.fifoenable = true;
wim 2:76cb93b511f2 304
wim 2:76cb93b511f2 305 // Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable)
wim 2:76cb93b511f2 306 // _config.fifoformat = FCR_RX_IRQ_8 | FCR_TX_IRQ_56;
wim 2:76cb93b511f2 307 _config.fifoformat = FCR_RX_IRQ_8 | FCR_TX_IRQ_8; //Default
wim 2:76cb93b511f2 308
wim 2:76cb93b511f2 309 if (_config.fifoenable)
wim 2:76cb93b511f2 310 // enable FIFO mode and set FIFO control values
wim 2:76cb93b511f2 311 this->writeRegister(FCR, _config.fifoformat | FCR_ENABLE_FIFO);
wim 2:76cb93b511f2 312 else
wim 2:76cb93b511f2 313 // disable FIFO mode and set FIFO control values
wim 2:76cb93b511f2 314 this->writeRegister(FCR, _config.fifoformat);
wim 2:76cb93b511f2 315
wim 2:76cb93b511f2 316 // Set Trigger level register TLR for RX and TX interrupt generation
wim 2:76cb93b511f2 317 // Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set
wim 2:76cb93b511f2 318 // TRL Trigger levels for RX and TX are 0..15, meaning 0-60 with a granularity of 4 chars
wim 2:76cb93b511f2 319 // When TLR for RX or TX are 'Zero' the corresponding values in FCR are used. The FCR settings
wim 2:76cb93b511f2 320 // have less resolution (only 4 levels) so TLR is considered an enhanced function.
wim 2:76cb93b511f2 321 this->writeRegister(TLR, 0x00); // Use FCR Levels
wim 2:76cb93b511f2 322 // this->writeRegister(TLR, (TLR_RX_DEFAULT << 4) | TLR_TX_DEFAULT); // Use Default enhanced levels
wim 2:76cb93b511f2 323
wim 2:76cb93b511f2 324 }
wim 2:76cb93b511f2 325
wim 2:76cb93b511f2 326
wim 1:0440152c5387 327 /**
wim 1:0440152c5387 328 * Flush the UART FIFOs while maintaining current FIFO mode.
wim 1:0440152c5387 329 * @param none
wim 1:0440152c5387 330 * @return none
wim 1:0440152c5387 331 */
wim 1:0440152c5387 332 void SC16IS750::flush() {
wim 2:76cb93b511f2 333 // FCR is Write Only, use saved _config
wim 1:0440152c5387 334
wim 1:0440152c5387 335 // reset TXFIFO, reset RXFIFO, non FIFO mode
wim 3:9783b6bde958 336 this->writeRegister(FCR, FCR_TX_FIFO_RST | FCR_RX_FIFO_RST);
wim 1:0440152c5387 337
wim 1:0440152c5387 338 if (_config.fifoenable)
wim 1:0440152c5387 339 // enable FIFO mode and set FIFO control values
wim 1:0440152c5387 340 this->writeRegister(FCR, _config.fifoformat | FCR_ENABLE_FIFO);
wim 1:0440152c5387 341 else
wim 1:0440152c5387 342 // disable FIFO mode and set FIFO control values
wim 1:0440152c5387 343 this->writeRegister(FCR, _config.fifoformat);
wim 1:0440152c5387 344
wim 1:0440152c5387 345 #if(0)
wim 1:0440152c5387 346 //original
wim 1:0440152c5387 347 /*
wim 1:0440152c5387 348 * Flush characters from SC16IS750 receive buffer.
wim 1:0440152c5387 349 */
wim 1:0440152c5387 350
wim 1:0440152c5387 351 // Note: This may not be the most appropriate flush approach.
wim 1:0440152c5387 352 // It might be better to just flush the UART's buffer
wim 1:0440152c5387 353 // rather than the buffer of the connected device
wim 1:0440152c5387 354 // which is essentially what this does.
wim 1:0440152c5387 355 while(readable() > 0) {
wim 1:0440152c5387 356 getc();
wim 0:d64854a60f95 357 }
wim 0:d64854a60f95 358 #endif
wim 0:d64854a60f95 359
wim 0:d64854a60f95 360 }
wim 0:d64854a60f95 361
wim 0:d64854a60f95 362
wim 1:0440152c5387 363
wim 0:d64854a60f95 364 /**
wim 0:d64854a60f95 365 * Check that UART is connected and operational.
wim 0:d64854a60f95 366 * @param none
wim 0:d64854a60f95 367 * @return bool true when connected, false otherwise
wim 0:d64854a60f95 368 */
wim 0:d64854a60f95 369 bool SC16IS750::connected() {
wim 0:d64854a60f95 370 // Perform read/write test to check if UART is working
wim 0:d64854a60f95 371 const char TEST_CHARACTER = 'H';
wim 0:d64854a60f95 372
wim 0:d64854a60f95 373 this->writeRegister(SPR, TEST_CHARACTER);
wim 0:d64854a60f95 374
wim 0:d64854a60f95 375 return (this->readRegister(SPR) == TEST_CHARACTER);
wim 0:d64854a60f95 376 }
wim 0:d64854a60f95 377
wim 0:d64854a60f95 378
wim 0:d64854a60f95 379
wim 0:d64854a60f95 380 /** Determine if there is a character available to read.
wim 2:76cb93b511f2 381 * This is data that's already arrived and stored in the receive
wim 2:76cb93b511f2 382 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 383 *
wim 0:d64854a60f95 384 * @return 1 if there is a character available to read, 0 otherwise
wim 0:d64854a60f95 385 */
wim 0:d64854a60f95 386 int SC16IS750::readable() {
wim 2:76cb93b511f2 387
wim 2:76cb93b511f2 388 // if (this->readableCount() > 0) { // Check count
wim 2:76cb93b511f2 389 if (this->readRegister(LSR) & LSR_DR) { // Data in Receiver Bit, at least one character waiting
wim 2:76cb93b511f2 390 return 1;
wim 2:76cb93b511f2 391 }
wim 2:76cb93b511f2 392 else {
wim 2:76cb93b511f2 393 return 0;
wim 2:76cb93b511f2 394 }
wim 2:76cb93b511f2 395
wim 0:d64854a60f95 396 }
wim 0:d64854a60f95 397
wim 1:0440152c5387 398 /** Determine how many characters are available to read.
wim 2:76cb93b511f2 399 * This is data that's already arrived and stored in the receive
wim 2:76cb93b511f2 400 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 401 *
wim 0:d64854a60f95 402 * @return int Characters available to read
wim 0:d64854a60f95 403 */
wim 0:d64854a60f95 404 int SC16IS750::readableCount() {
wim 0:d64854a60f95 405
wim 0:d64854a60f95 406 return (this->readRegister(RXLVL));
wim 0:d64854a60f95 407 }
wim 0:d64854a60f95 408
wim 0:d64854a60f95 409 /** Determine if there is space available to write a character.
wim 0:d64854a60f95 410 * @return 1 if there is a space for a character to write, 0 otherwise
wim 0:d64854a60f95 411 */
wim 0:d64854a60f95 412 int SC16IS750::writable() {
wim 2:76cb93b511f2 413
wim 2:76cb93b511f2 414 // if ((this->writableCount() > 0) { // Check count
wim 2:76cb93b511f2 415 if (this->readRegister(LSR) & LSR_THRE) { // THR Empty, space for at least one character
wim 2:76cb93b511f2 416 return 1;
wim 2:76cb93b511f2 417 }
wim 2:76cb93b511f2 418 else {
wim 2:76cb93b511f2 419 return 0;
wim 2:76cb93b511f2 420 }
wim 0:d64854a60f95 421 }
wim 0:d64854a60f95 422
wim 1:0440152c5387 423 /** Determine how much space available for writing characters.
wim 2:76cb93b511f2 424 * This considers data that's already stored in the transmit
wim 2:76cb93b511f2 425 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 426 *
wim 1:0440152c5387 427 * @return int character space available to write
wim 0:d64854a60f95 428 */
wim 0:d64854a60f95 429 int SC16IS750::writableCount() {
wim 0:d64854a60f95 430
wim 2:76cb93b511f2 431 return (this->readRegister(TXLVL)); // TX Level
wim 0:d64854a60f95 432 }
wim 0:d64854a60f95 433
wim 0:d64854a60f95 434
wim 1:0440152c5387 435 /**
wim 1:0440152c5387 436 * Read char from UART Bridge.
wim 1:0440152c5387 437 * Acts in the same manner as 'Serial.read()'.
wim 1:0440152c5387 438 * @param none
wim 1:0440152c5387 439 * @return char read or -1 if no data available.
wim 1:0440152c5387 440 */
wim 1:0440152c5387 441 int SC16IS750::getc() {
wim 0:d64854a60f95 442
wim 0:d64854a60f95 443 if (!readable()) {
wim 0:d64854a60f95 444 return -1;
wim 0:d64854a60f95 445 }
wim 0:d64854a60f95 446
wim 0:d64854a60f95 447 return this->readRegister(RHR);
wim 0:d64854a60f95 448 }
wim 0:d64854a60f95 449
wim 3:9783b6bde958 450
wim 1:0440152c5387 451 /**
wim 1:0440152c5387 452 * Write char to UART Bridge. Blocking when no free space in FIFO
wim 1:0440152c5387 453 * @param value char to be written
wim 1:0440152c5387 454 * @return value written
wim 1:0440152c5387 455 */
wim 1:0440152c5387 456 int SC16IS750::putc(int value) {
wim 2:76cb93b511f2 457
wim 0:d64854a60f95 458 while (this->readRegister(TXLVL) == 0) {
wim 0:d64854a60f95 459 // Wait for space in TX buffer
wim 1:0440152c5387 460 wait_us(10);
wim 0:d64854a60f95 461 };
wim 0:d64854a60f95 462 this->writeRegister(THR, value);
wim 1:0440152c5387 463
wim 1:0440152c5387 464 return value;
wim 0:d64854a60f95 465 }
wim 0:d64854a60f95 466
wim 3:9783b6bde958 467
wim 2:76cb93b511f2 468 /**
wim 2:76cb93b511f2 469 * Write char string to UART Bridge. Blocking when no free space in FIFO
wim 2:76cb93b511f2 470 * @param *str char string to be written
wim 2:76cb93b511f2 471 * @return none
wim 2:76cb93b511f2 472 */
wim 3:9783b6bde958 473 void SC16IS750::writeString(const char *str) {
wim 0:d64854a60f95 474
wim 0:d64854a60f95 475 #if ENABLE_BULK_TRANSFERS
wim 2:76cb93b511f2 476 int len, idx;
wim 0:d64854a60f95 477
wim 2:76cb93b511f2 478 len = strlen(str);
wim 0:d64854a60f95 479
wim 2:76cb93b511f2 480 // Write blocks of BULK_BLOCK_LEN
wim 2:76cb93b511f2 481 while (len > BULK_BLOCK_LEN) {
wim 2:76cb93b511f2 482 while(this->readRegister(TXLVL) < BULK_BLOCK_LEN) {
wim 2:76cb93b511f2 483 // Wait for space in TX buffer
wim 2:76cb93b511f2 484 wait_us(10);
wim 2:76cb93b511f2 485 };
wim 2:76cb93b511f2 486
wim 2:76cb93b511f2 487 // Write a block of BULK_BLOCK_LEN bytes
wim 3:9783b6bde958 488 #if (0)
wim 3:9783b6bde958 489 // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes.
wim 2:76cb93b511f2 490 for (idx=0; idx<BULK_BLOCK_LEN; idx++) {
wim 2:76cb93b511f2 491 this->writeRegister(THR, str[idx]);
wim 2:76cb93b511f2 492 };
wim 3:9783b6bde958 493 #else
wim 3:9783b6bde958 494 // optimized
wim 3:9783b6bde958 495 this->writeDataBlock(str, BULK_BLOCK_LEN);
wim 3:9783b6bde958 496 #endif
wim 3:9783b6bde958 497
wim 2:76cb93b511f2 498 len -= BULK_BLOCK_LEN;
wim 2:76cb93b511f2 499 str += BULK_BLOCK_LEN;
wim 0:d64854a60f95 500 }
wim 2:76cb93b511f2 501
wim 2:76cb93b511f2 502 // Write remaining bytes
wim 3:9783b6bde958 503 // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes.
wim 2:76cb93b511f2 504 for (idx=0; idx<len; idx++) {
wim 2:76cb93b511f2 505 while (this->readRegister(TXLVL) == 0) {
wim 2:76cb93b511f2 506 // Wait for space in TX buffer
wim 2:76cb93b511f2 507 wait_us(10);
wim 2:76cb93b511f2 508 };
wim 2:76cb93b511f2 509 this->writeRegister(THR, str[idx]);
wim 2:76cb93b511f2 510 }
wim 2:76cb93b511f2 511
wim 0:d64854a60f95 512
wim 2:76cb93b511f2 513 #else
wim 3:9783b6bde958 514 // Single writes instead of bulktransfer
wim 2:76cb93b511f2 515 int len, idx;
wim 2:76cb93b511f2 516
wim 2:76cb93b511f2 517 len = strlen(str);
wim 2:76cb93b511f2 518 for (idx=0; idx<len; idx++) {
wim 2:76cb93b511f2 519 while (this->readRegister(TXLVL) == 0) {
wim 2:76cb93b511f2 520 // Wait for space in TX buffer
wim 2:76cb93b511f2 521 wait_us(10);
wim 2:76cb93b511f2 522 };
wim 2:76cb93b511f2 523 this->writeRegister(THR, str[idx]);
wim 2:76cb93b511f2 524 }
wim 2:76cb93b511f2 525 #endif
wim 0:d64854a60f95 526 }
wim 2:76cb93b511f2 527
wim 2:76cb93b511f2 528
wim 3:9783b6bde958 529 /**
wim 3:9783b6bde958 530 * Write byte array to UART Bridge. Blocking when no free space in FIFO
wim 3:9783b6bde958 531 * @param *data byte array to be written
wim 3:9783b6bde958 532 * @param len number of bytes to write
wim 3:9783b6bde958 533 * @return none
wim 3:9783b6bde958 534 */
wim 3:9783b6bde958 535 void SC16IS750::writeBytes(const char *data, int len) {
wim 3:9783b6bde958 536
wim 3:9783b6bde958 537 #if ENABLE_BULK_TRANSFERS
wim 3:9783b6bde958 538 int idx;
wim 3:9783b6bde958 539
wim 3:9783b6bde958 540 // Write blocks of BULK_BLOCK_LEN
wim 3:9783b6bde958 541 while (len > BULK_BLOCK_LEN) {
wim 3:9783b6bde958 542 while(this->readRegister(TXLVL) < BULK_BLOCK_LEN) {
wim 3:9783b6bde958 543 // Wait for space in TX buffer
wim 3:9783b6bde958 544 wait_us(10);
wim 3:9783b6bde958 545 };
wim 3:9783b6bde958 546
wim 3:9783b6bde958 547 // Write a block of BULK_BLOCK_LEN bytes
wim 3:9783b6bde958 548 #if (0)
wim 3:9783b6bde958 549 // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes.
wim 3:9783b6bde958 550 for (idx=0; idx<BULK_BLOCK_LEN; idx++) {
wim 3:9783b6bde958 551 this->writeRegister(THR, data[idx]);
wim 3:9783b6bde958 552 };
wim 3:9783b6bde958 553 #else
wim 3:9783b6bde958 554 // optimized
wim 3:9783b6bde958 555 this->writeDataBlock(data, BULK_BLOCK_LEN);
wim 3:9783b6bde958 556 #endif
wim 3:9783b6bde958 557
wim 3:9783b6bde958 558 len -= BULK_BLOCK_LEN;
wim 3:9783b6bde958 559 data += BULK_BLOCK_LEN;
wim 3:9783b6bde958 560 }
wim 3:9783b6bde958 561
wim 3:9783b6bde958 562 // Write remaining bytes
wim 3:9783b6bde958 563 // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes.
wim 3:9783b6bde958 564 for (idx=0; idx<len; idx++) {
wim 3:9783b6bde958 565 while (this->readRegister(TXLVL) == 0) {
wim 3:9783b6bde958 566 // Wait for space in TX buffer
wim 3:9783b6bde958 567 wait_us(10);
wim 3:9783b6bde958 568 };
wim 3:9783b6bde958 569 this->writeRegister(THR, data[idx]);
wim 3:9783b6bde958 570 }
wim 3:9783b6bde958 571
wim 3:9783b6bde958 572
wim 3:9783b6bde958 573 #else
wim 3:9783b6bde958 574 // Single writes instead of bulktransfer
wim 3:9783b6bde958 575 int idx;
wim 3:9783b6bde958 576
wim 3:9783b6bde958 577 for (idx=0; idx<len; idx++) {
wim 3:9783b6bde958 578 while (this->readRegister(TXLVL) == 0) {
wim 3:9783b6bde958 579 // Wait for space in TX buffer
wim 3:9783b6bde958 580 wait_us(10);
wim 3:9783b6bde958 581 };
wim 3:9783b6bde958 582 this->writeRegister(THR, str[idx]);
wim 3:9783b6bde958 583 }
wim 3:9783b6bde958 584 #endif
wim 3:9783b6bde958 585 }
wim 3:9783b6bde958 586
wim 3:9783b6bde958 587
wim 3:9783b6bde958 588
wim 0:d64854a60f95 589
wim 1:0440152c5387 590 /** Set direction of I/O port pins.
wim 1:0440152c5387 591 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 592 * @param bits Bitpattern for I/O (1=output, 0=input)
wim 1:0440152c5387 593 * @return none
wim 1:0440152c5387 594 */
wim 0:d64854a60f95 595 void SC16IS750::ioSetDirection(unsigned char bits) {
wim 0:d64854a60f95 596 this->writeRegister(IODIR, bits);
wim 0:d64854a60f95 597 }
wim 0:d64854a60f95 598
wim 1:0440152c5387 599 /** Set bits of I/O port pins.
wim 1:0440152c5387 600 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 601 * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit)
wim 1:0440152c5387 602 * @return none
wim 1:0440152c5387 603 */
wim 0:d64854a60f95 604 void SC16IS750::ioSetState(unsigned char bits) {
wim 0:d64854a60f95 605 this->writeRegister(IOSTATE, bits);
wim 0:d64854a60f95 606 }
wim 0:d64854a60f95 607
wim 1:0440152c5387 608 /** Get bits of I/O port pins.
wim 1:0440152c5387 609 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 610 * @param none
wim 1:0440152c5387 611 * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared)
wim 1:0440152c5387 612 */
wim 1:0440152c5387 613 unsigned char SC16IS750::ioGetState() {
wim 1:0440152c5387 614 return this->readRegister(IOSTATE) ;
wim 1:0440152c5387 615 }
wim 0:d64854a60f95 616
wim 0:d64854a60f95 617
wim 1:0440152c5387 618 /** Software Reset SC16IS750 device.
wim 1:0440152c5387 619 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 620 * @param none
wim 1:0440152c5387 621 * @return none
wim 1:0440152c5387 622 */
wim 1:0440152c5387 623 void SC16IS750::swReset() {
wim 1:0440152c5387 624 this->writeRegister(IOCTRL, IOC_SW_RST);
wim 1:0440152c5387 625 }
wim 1:0440152c5387 626
wim 1:0440152c5387 627
wim 1:0440152c5387 628 //
wim 1:0440152c5387 629 // End Abstract Class Implementation
wim 0:d64854a60f95 630 //
wim 0:d64854a60f95 631
wim 1:0440152c5387 632
wim 1:0440152c5387 633
wim 4:12446ee9f9c8 634 //
wim 4:12446ee9f9c8 635 // Begin SPI Class Implementation
wim 4:12446ee9f9c8 636 //
wim 4:12446ee9f9c8 637
wim 4:12446ee9f9c8 638
wim 4:12446ee9f9c8 639 /** Create an SC16IS750_SPI object using a specified SPI bus and CS
wim 1:0440152c5387 640 *
wim 4:12446ee9f9c8 641 * @param SPI &spi the SPI port to connect to
wim 4:12446ee9f9c8 642 * @param cs Pinname of the CS pin (active low)
wim 4:12446ee9f9c8 643 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
wim 4:12446ee9f9c8 644 */
wim 4:12446ee9f9c8 645 SC16IS750_SPI::SC16IS750_SPI (SPI *spi, PinName cs, PinName rst) : _spi(spi), _cs(cs) {
wim 0:d64854a60f95 646 _cs = 1; // deselect
wim 0:d64854a60f95 647
wim 0:d64854a60f95 648 _spi->format(8, 0);
wim 0:d64854a60f95 649 _spi->frequency(1000000);
wim 4:12446ee9f9c8 650
wim 4:12446ee9f9c8 651 // The hardware Reset pin is optional. Test and make sure whether it exists or not to prevent illegal access.
wim 4:12446ee9f9c8 652 if (rst != NC) {
wim 4:12446ee9f9c8 653 _reset = new DigitalOut(rst); //Construct new pin
wim 4:12446ee9f9c8 654 _reset->write(1); //Deactivate
wim 4:12446ee9f9c8 655 }
wim 4:12446ee9f9c8 656 else {
wim 4:12446ee9f9c8 657 // No Hardware Reset pin
wim 4:12446ee9f9c8 658 _reset = NULL; //Construct dummy pin
wim 4:12446ee9f9c8 659 }
wim 4:12446ee9f9c8 660
wim 1:0440152c5387 661
wim 1:0440152c5387 662 // Dont call _init() until SPI port has been configured.
wim 1:0440152c5387 663 // That is why _init() is not called in parent Constructor
wim 1:0440152c5387 664 _init();
wim 1:0440152c5387 665
wim 0:d64854a60f95 666 };
wim 0:d64854a60f95 667
wim 4:12446ee9f9c8 668
wim 4:12446ee9f9c8 669 /** Destruct SC16IS750_SPI bridge object
wim 4:12446ee9f9c8 670 *
wim 4:12446ee9f9c8 671 * @param none
wim 4:12446ee9f9c8 672 * @return none
wim 4:12446ee9f9c8 673 */
wim 4:12446ee9f9c8 674 SC16IS750_SPI::~SC16IS750_SPI() {
wim 4:12446ee9f9c8 675 if (_reset != NULL) {delete _reset;} // Reset pin
wim 4:12446ee9f9c8 676 }
wim 4:12446ee9f9c8 677
wim 4:12446ee9f9c8 678
wim 4:12446ee9f9c8 679
wim 4:12446ee9f9c8 680
wim 0:d64854a60f95 681 /** Write value to internal register.
wim 0:d64854a60f95 682 * Pure virtual, must be declared in derived class.
wim 1:0440152c5387 683 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 684 * @param data The 8bit value to write
wim 0:d64854a60f95 685 * @return none
wim 0:d64854a60f95 686 */
wim 0:d64854a60f95 687 void SC16IS750_SPI::writeRegister(RegisterName registerAddress, char data) {
wim 0:d64854a60f95 688
wim 0:d64854a60f95 689 _cs = 0; // select;
wim 0:d64854a60f95 690 _spi->write(registerAddress);
wim 0:d64854a60f95 691 _spi->write(data);
wim 0:d64854a60f95 692 _cs = 1; // deselect;
wim 1:0440152c5387 693
wim 0:d64854a60f95 694 }
wim 0:d64854a60f95 695
wim 0:d64854a60f95 696
wim 0:d64854a60f95 697 /** Read value from internal register.
wim 1:0440152c5387 698 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 699 * @return char The 8bit value read from the register
wim 0:d64854a60f95 700 */
wim 0:d64854a60f95 701 char SC16IS750_SPI::readRegister(RegisterName registerAddress) {
wim 0:d64854a60f95 702
wim 0:d64854a60f95 703 // Used in SPI read operations to flush slave's shift register
wim 1:0440152c5387 704 const char SPI_DUMMY_CHAR = 0xFF;
wim 0:d64854a60f95 705
wim 0:d64854a60f95 706 char result;
wim 0:d64854a60f95 707
wim 0:d64854a60f95 708 _cs = 0; // select;
wim 0:d64854a60f95 709 _spi->write(SPI_READ_MODE_FLAG | registerAddress);
wim 1:0440152c5387 710 result = _spi->write(SPI_DUMMY_CHAR);
wim 0:d64854a60f95 711 _cs = 1; // deselect;
wim 0:d64854a60f95 712
wim 0:d64854a60f95 713 return result;
wim 0:d64854a60f95 714 }
wim 0:d64854a60f95 715
wim 3:9783b6bde958 716
wim 3:9783b6bde958 717 /** Write multiple datavalues to Transmitregister.
wim 3:9783b6bde958 718 * More Efficient implementation than writing individual bytes
wim 3:9783b6bde958 719 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 3:9783b6bde958 720 * Pure virtual, must be declared in derived class.
wim 3:9783b6bde958 721 * @param char* databytes The pointer to the block of data
wim 3:9783b6bde958 722 * @param len The number of bytes to write
wim 3:9783b6bde958 723 * @return none
wim 3:9783b6bde958 724 */
wim 3:9783b6bde958 725 void SC16IS750_SPI::writeDataBlock (const char *data, int len) {
wim 3:9783b6bde958 726 int i;
wim 3:9783b6bde958 727
wim 3:9783b6bde958 728 _cs = 0; // select;
wim 3:9783b6bde958 729
wim 3:9783b6bde958 730 // Select the Transmit Holding Register
wim 3:9783b6bde958 731 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 3:9783b6bde958 732 _spi->write(THR);
wim 3:9783b6bde958 733
wim 3:9783b6bde958 734 for (i=0; i<len; i++, data++)
wim 3:9783b6bde958 735 _spi->write(*data);
wim 3:9783b6bde958 736
wim 3:9783b6bde958 737 _cs = 1; // deselect;
wim 3:9783b6bde958 738 }
wim 3:9783b6bde958 739
wim 4:12446ee9f9c8 740
wim 4:12446ee9f9c8 741 /** Hardware Reset SC16IS750 device.
wim 4:12446ee9f9c8 742 * This method is only available when the Reset pin has been declared and is also connected
wim 4:12446ee9f9c8 743 * @param none
wim 4:12446ee9f9c8 744 * @return none
wim 4:12446ee9f9c8 745 */
wim 4:12446ee9f9c8 746 void SC16IS750_SPI::hwReset() {
wim 4:12446ee9f9c8 747
wim 4:12446ee9f9c8 748 if (_reset != NULL){
wim 4:12446ee9f9c8 749 _reset->write(0); //activate
wim 4:12446ee9f9c8 750 // wait_ms(100);
wim 4:12446ee9f9c8 751 wait_ms(1000); //test only
wim 4:12446ee9f9c8 752 _reset->write(1); //deactivate
wim 4:12446ee9f9c8 753 }
wim 4:12446ee9f9c8 754 else {
wim 4:12446ee9f9c8 755 printf("Hardware Reset pin is not available...\n\r");
wim 4:12446ee9f9c8 756 }
wim 4:12446ee9f9c8 757
wim 4:12446ee9f9c8 758 }
wim 4:12446ee9f9c8 759
wim 0:d64854a60f95 760 //
wim 0:d64854a60f95 761 // End SPI Implementation
wim 1:0440152c5387 762 //
wim 0:d64854a60f95 763
wim 0:d64854a60f95 764
wim 4:12446ee9f9c8 765
wim 4:12446ee9f9c8 766 //
wim 4:12446ee9f9c8 767 // Begin I2C Implementation
wim 4:12446ee9f9c8 768 //
wim 4:12446ee9f9c8 769
wim 4:12446ee9f9c8 770 /** Create a SC16IS750_I2C object for a bridge between I2C and a Serial port
wim 1:0440152c5387 771 *
wim 4:12446ee9f9c8 772 * @param I2C &i2c the I2C port to connect to
wim 4:12446ee9f9c8 773 * @param char deviceAddress the I2C slave address of the SC16IS750
wim 4:12446ee9f9c8 774 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
wim 4:12446ee9f9c8 775 *
wim 4:12446ee9f9c8 776 */
wim 4:12446ee9f9c8 777 SC16IS750_I2C::SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress, PinName rst) : _i2c(i2c), _slaveAddress(deviceAddress & 0xFE) {
wim 0:d64854a60f95 778
wim 1:0440152c5387 779 _i2c->frequency(400000);
wim 4:12446ee9f9c8 780
wim 4:12446ee9f9c8 781 // The hardware Reset pin is optional. Test and make sure whether it exists or not to prevent illegal access.
wim 4:12446ee9f9c8 782 if (rst != NC) {
wim 4:12446ee9f9c8 783 _reset = new DigitalOut(rst); //Construct new pin
wim 4:12446ee9f9c8 784 _reset->write(1); //Deactivate
wim 4:12446ee9f9c8 785 }
wim 4:12446ee9f9c8 786 else {
wim 4:12446ee9f9c8 787 // No Hardware Reset pin
wim 4:12446ee9f9c8 788 _reset = NULL; //Construct dummy pin
wim 4:12446ee9f9c8 789 }
wim 4:12446ee9f9c8 790
wim 1:0440152c5387 791 // Dont call _init() until I2C port has been configured.
wim 1:0440152c5387 792 // That is why _init() is not called in parent Constructor
wim 1:0440152c5387 793 _init();
wim 0:d64854a60f95 794 }
wim 0:d64854a60f95 795
wim 0:d64854a60f95 796
wim 4:12446ee9f9c8 797 /** Destruct SC16IS750_I2C bridge object
wim 4:12446ee9f9c8 798 *
wim 4:12446ee9f9c8 799 * @param none
wim 4:12446ee9f9c8 800 * @return none
wim 4:12446ee9f9c8 801 */
wim 4:12446ee9f9c8 802 SC16IS750_I2C::~SC16IS750_I2C() {
wim 4:12446ee9f9c8 803 if (_reset != NULL) {delete _reset;} // Reset pin
wim 4:12446ee9f9c8 804 }
wim 4:12446ee9f9c8 805
wim 4:12446ee9f9c8 806
wim 0:d64854a60f95 807 /** Write value to internal register.
wim 1:0440152c5387 808 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 809 * @param data The 8bit value to write
wim 0:d64854a60f95 810 * @return none
wim 0:d64854a60f95 811 */
wim 0:d64854a60f95 812 void SC16IS750_I2C::writeRegister(RegisterName registerAddress, char data) {
wim 0:d64854a60f95 813 char w[2];
wim 0:d64854a60f95 814
wim 0:d64854a60f95 815 w[0] = registerAddress;
wim 0:d64854a60f95 816 w[1] = data;
wim 0:d64854a60f95 817
wim 0:d64854a60f95 818 _i2c->write( _slaveAddress, w, 2 );
wim 0:d64854a60f95 819 }
wim 0:d64854a60f95 820
wim 0:d64854a60f95 821
wim 0:d64854a60f95 822 /** Read value from internal register.
wim 1:0440152c5387 823 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 824 * @return char The 8bit value read from the register
wim 0:d64854a60f95 825 */
wim 0:d64854a60f95 826 char SC16IS750_I2C::readRegister(RegisterName registerAddress) {
wim 0:d64854a60f95 827 /*
wim 0:d64854a60f95 828 * Read char from SC16IS750 register at <registerAddress>.
wim 0:d64854a60f95 829 */
wim 0:d64854a60f95 830 char w[1];
wim 0:d64854a60f95 831 char r[1];
wim 0:d64854a60f95 832
wim 0:d64854a60f95 833 w[0] = registerAddress;
wim 0:d64854a60f95 834
wim 0:d64854a60f95 835 _i2c->write( _slaveAddress, w, 1 );
wim 0:d64854a60f95 836 _i2c->read( _slaveAddress, r, 1 );
wim 0:d64854a60f95 837
wim 0:d64854a60f95 838 return ( r[0] );
wim 0:d64854a60f95 839 }
wim 0:d64854a60f95 840
wim 0:d64854a60f95 841
wim 3:9783b6bde958 842 /** Write multiple datavalues to Transmitregister.
wim 3:9783b6bde958 843 * More Efficient implementation than writing individual bytes
wim 3:9783b6bde958 844 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 3:9783b6bde958 845 * Pure virtual, must be declared in derived class.
wim 3:9783b6bde958 846 * @param char* databytes The pointer to the block of data
wim 3:9783b6bde958 847 * @param len The number of bytes to write
wim 3:9783b6bde958 848 * @return none
wim 3:9783b6bde958 849 */
wim 3:9783b6bde958 850 void SC16IS750_I2C::writeDataBlock (const char *data, int len) {
wim 3:9783b6bde958 851
wim 3:9783b6bde958 852 #if(0)
wim 3:9783b6bde958 853 int i;
wim 3:9783b6bde958 854 char w[BULK_BLOCK_LEN];
wim 3:9783b6bde958 855
wim 3:9783b6bde958 856 // Select the Transmit Holding Register
wim 3:9783b6bde958 857 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 3:9783b6bde958 858 w[0] = THR;
wim 3:9783b6bde958 859
wim 3:9783b6bde958 860 // copy the data..
wim 3:9783b6bde958 861 for (i=0; i<len; i++)
wim 3:9783b6bde958 862 w[i+1] = data[i];
wim 3:9783b6bde958 863
wim 3:9783b6bde958 864 _i2c->write( _slaveAddress, w, len + 1);
wim 3:9783b6bde958 865 #else
wim 3:9783b6bde958 866 int i;
wim 3:9783b6bde958 867
wim 3:9783b6bde958 868 _i2c->start();
wim 3:9783b6bde958 869 _i2c->write(_slaveAddress);
wim 3:9783b6bde958 870
wim 3:9783b6bde958 871 // Select the Transmit Holding Register
wim 3:9783b6bde958 872 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 3:9783b6bde958 873 _i2c->write(THR);
wim 3:9783b6bde958 874
wim 3:9783b6bde958 875 // send the data..
wim 3:9783b6bde958 876 for (i=0; i<len; i++)
wim 3:9783b6bde958 877 _i2c->write(data[i]);
wim 3:9783b6bde958 878
wim 3:9783b6bde958 879 _i2c->stop();
wim 3:9783b6bde958 880 #endif
wim 3:9783b6bde958 881 }
wim 3:9783b6bde958 882
wim 3:9783b6bde958 883
wim 4:12446ee9f9c8 884 /** Hardware Reset SC16IS750 device.
wim 4:12446ee9f9c8 885 * This method is only available when the Reset pin has been declared and is also connected
wim 4:12446ee9f9c8 886 * @param none
wim 4:12446ee9f9c8 887 * @return none
wim 4:12446ee9f9c8 888 */
wim 4:12446ee9f9c8 889 void SC16IS750_I2C::hwReset() {
wim 4:12446ee9f9c8 890
wim 4:12446ee9f9c8 891 if (_reset != NULL){
wim 4:12446ee9f9c8 892 _reset->write(0); //activate
wim 4:12446ee9f9c8 893 // wait_ms(100);
wim 4:12446ee9f9c8 894 wait_ms(1000); //test only
wim 4:12446ee9f9c8 895 _reset->write(1); //deactivate
wim 4:12446ee9f9c8 896 }
wim 4:12446ee9f9c8 897 else {
wim 4:12446ee9f9c8 898 printf("Hardware Reset pin is not available...\n\r");
wim 4:12446ee9f9c8 899 }
wim 4:12446ee9f9c8 900 }
wim 4:12446ee9f9c8 901
wim 4:12446ee9f9c8 902
wim 0:d64854a60f95 903 //
wim 1:0440152c5387 904 // End I2C Implementation
wim 4:12446ee9f9c8 905 //
wim 4:12446ee9f9c8 906
wim 4:12446ee9f9c8 907
wim 4:12446ee9f9c8 908
wim 4:12446ee9f9c8 909 //
wim 4:12446ee9f9c8 910 // Begin SPI Class Implementation for 16SCIS752 dual UART
wim 4:12446ee9f9c8 911 //
wim 4:12446ee9f9c8 912
wim 4:12446ee9f9c8 913
wim 4:12446ee9f9c8 914 /** Create an SC16IS752_SPI object using a specified SPI bus and CS
wim 4:12446ee9f9c8 915 *
wim 4:12446ee9f9c8 916 * @param SPI &spi the SPI port to connect to
wim 4:12446ee9f9c8 917 * @param cs Pinname of the CS pin (active low)
wim 4:12446ee9f9c8 918 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
wim 4:12446ee9f9c8 919 * @param channel UART ChannelName, Default = Channel_A
wim 4:12446ee9f9c8 920 */
wim 4:12446ee9f9c8 921 SC16IS752_SPI::SC16IS752_SPI (SPI *spi, PinName cs, PinName rst, ChannelName channel) : _spi(spi), _cs(cs), _channel(channel) {
wim 4:12446ee9f9c8 922 _cs = 1; // deselect
wim 4:12446ee9f9c8 923
wim 4:12446ee9f9c8 924 _spi->format(8, 0);
wim 4:12446ee9f9c8 925 _spi->frequency(1000000);
wim 4:12446ee9f9c8 926
wim 4:12446ee9f9c8 927 // The hardware Reset pin is optional. Test and make sure whether it exists or not to prevent illegal access.
wim 4:12446ee9f9c8 928 if (rst != NC) {
wim 4:12446ee9f9c8 929 _reset = new DigitalOut(rst); //Construct new pin
wim 4:12446ee9f9c8 930 _reset->write(1); //Deactivate
wim 4:12446ee9f9c8 931 }
wim 4:12446ee9f9c8 932 else {
wim 4:12446ee9f9c8 933 // No Hardware Reset pin
wim 4:12446ee9f9c8 934 _reset = NULL; //Construct dummy pin
wim 4:12446ee9f9c8 935 }
wim 4:12446ee9f9c8 936
wim 4:12446ee9f9c8 937
wim 4:12446ee9f9c8 938 // Dont call _init() until SPI port has been configured.
wim 4:12446ee9f9c8 939 // That is why _init() is not called in parent Constructor
wim 4:12446ee9f9c8 940 _init();
wim 4:12446ee9f9c8 941
wim 4:12446ee9f9c8 942 };
wim 4:12446ee9f9c8 943
wim 4:12446ee9f9c8 944
wim 4:12446ee9f9c8 945 /** Destruct SC16IS750_SPI bridge object
wim 4:12446ee9f9c8 946 *
wim 4:12446ee9f9c8 947 * @param none
wim 4:12446ee9f9c8 948 * @return none
wim 4:12446ee9f9c8 949 */
wim 4:12446ee9f9c8 950 SC16IS752_SPI::~SC16IS752_SPI() {
wim 4:12446ee9f9c8 951 if (_reset != NULL) {delete _reset;} // Reset pin
wim 4:12446ee9f9c8 952 }
wim 4:12446ee9f9c8 953
wim 4:12446ee9f9c8 954
wim 4:12446ee9f9c8 955
wim 4:12446ee9f9c8 956
wim 4:12446ee9f9c8 957 /** Write value to internal register.
wim 4:12446ee9f9c8 958 * Pure virtual, must be declared in derived class.
wim 4:12446ee9f9c8 959 * @param registerAddress The address of the Register (enum RegisterName)
wim 4:12446ee9f9c8 960 * @param data The 8bit value to write
wim 4:12446ee9f9c8 961 * @return none
wim 4:12446ee9f9c8 962 */
wim 4:12446ee9f9c8 963 void SC16IS752_SPI::writeRegister(RegisterName registerAddress, char data) {
wim 4:12446ee9f9c8 964
wim 4:12446ee9f9c8 965 _cs = 0; // select;
wim 4:12446ee9f9c8 966 _spi->write(registerAddress | _channel);
wim 4:12446ee9f9c8 967 _spi->write(data);
wim 4:12446ee9f9c8 968 _cs = 1; // deselect;
wim 4:12446ee9f9c8 969
wim 4:12446ee9f9c8 970 }
wim 4:12446ee9f9c8 971
wim 4:12446ee9f9c8 972
wim 4:12446ee9f9c8 973 /** Read value from internal register.
wim 4:12446ee9f9c8 974 * @param registerAddress The address of the Register (enum RegisterName)
wim 4:12446ee9f9c8 975 * @return char The 8bit value read from the register
wim 4:12446ee9f9c8 976 */
wim 4:12446ee9f9c8 977 char SC16IS752_SPI::readRegister(RegisterName registerAddress) {
wim 4:12446ee9f9c8 978
wim 4:12446ee9f9c8 979 // Used in SPI read operations to flush slave's shift register
wim 4:12446ee9f9c8 980 const char SPI_DUMMY_CHAR = 0xFF;
wim 4:12446ee9f9c8 981
wim 4:12446ee9f9c8 982 char result;
wim 4:12446ee9f9c8 983
wim 4:12446ee9f9c8 984 _cs = 0; // select;
wim 4:12446ee9f9c8 985 _spi->write(SPI_READ_MODE_FLAG | registerAddress | _channel);
wim 4:12446ee9f9c8 986 result = _spi->write(SPI_DUMMY_CHAR);
wim 4:12446ee9f9c8 987 _cs = 1; // deselect;
wim 4:12446ee9f9c8 988
wim 4:12446ee9f9c8 989 return result;
wim 4:12446ee9f9c8 990 }
wim 4:12446ee9f9c8 991
wim 4:12446ee9f9c8 992
wim 4:12446ee9f9c8 993 /** Write multiple datavalues to Transmitregister.
wim 4:12446ee9f9c8 994 * More Efficient implementation than writing individual bytes
wim 4:12446ee9f9c8 995 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 4:12446ee9f9c8 996 * Pure virtual, must be declared in derived class.
wim 4:12446ee9f9c8 997 * @param char* databytes The pointer to the block of data
wim 4:12446ee9f9c8 998 * @param len The number of bytes to write
wim 4:12446ee9f9c8 999 * @return none
wim 4:12446ee9f9c8 1000 */
wim 4:12446ee9f9c8 1001 void SC16IS752_SPI::writeDataBlock (const char *data, int len) {
wim 4:12446ee9f9c8 1002 int i;
wim 4:12446ee9f9c8 1003
wim 4:12446ee9f9c8 1004 _cs = 0; // select;
wim 4:12446ee9f9c8 1005
wim 4:12446ee9f9c8 1006 // Select the Transmit Holding Register
wim 4:12446ee9f9c8 1007 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 4:12446ee9f9c8 1008 _spi->write(THR | _channel);
wim 4:12446ee9f9c8 1009
wim 4:12446ee9f9c8 1010 for (i=0; i<len; i++, data++)
wim 4:12446ee9f9c8 1011 _spi->write(*data);
wim 4:12446ee9f9c8 1012
wim 4:12446ee9f9c8 1013 _cs = 1; // deselect;
wim 4:12446ee9f9c8 1014 }
wim 4:12446ee9f9c8 1015
wim 4:12446ee9f9c8 1016
wim 4:12446ee9f9c8 1017 /** Hardware Reset SC16IS752 device.
wim 4:12446ee9f9c8 1018 * This method is only available when the Reset pin has been declared and is also connected
wim 4:12446ee9f9c8 1019 * @param none
wim 4:12446ee9f9c8 1020 * @return none
wim 4:12446ee9f9c8 1021 */
wim 4:12446ee9f9c8 1022 void SC16IS752_SPI::hwReset() {
wim 4:12446ee9f9c8 1023
wim 4:12446ee9f9c8 1024 if (_reset != NULL){
wim 4:12446ee9f9c8 1025 _reset->write(0); //activate
wim 4:12446ee9f9c8 1026 // wait_ms(100);
wim 4:12446ee9f9c8 1027 wait_ms(1000); //test only
wim 4:12446ee9f9c8 1028 _reset->write(1); //deactivate
wim 4:12446ee9f9c8 1029 }
wim 4:12446ee9f9c8 1030 else {
wim 4:12446ee9f9c8 1031 printf("Hardware Reset pin is not available...\n\r");
wim 4:12446ee9f9c8 1032 }
wim 4:12446ee9f9c8 1033
wim 4:12446ee9f9c8 1034 }
wim 4:12446ee9f9c8 1035
wim 4:12446ee9f9c8 1036 //
wim 4:12446ee9f9c8 1037 // End SPI Implementation
wim 4:12446ee9f9c8 1038 //
wim 4:12446ee9f9c8 1039
wim 4:12446ee9f9c8 1040
wim 4:12446ee9f9c8 1041
wim 4:12446ee9f9c8 1042 //
wim 4:12446ee9f9c8 1043 // Begin I2C Implementation for 16SCIS752 dual UART
wim 4:12446ee9f9c8 1044 //
wim 4:12446ee9f9c8 1045
wim 4:12446ee9f9c8 1046 /** Create a SC16IS752_I2C object for a bridge between I2C and a Serial port
wim 4:12446ee9f9c8 1047 *
wim 4:12446ee9f9c8 1048 * @param I2C &i2c the I2C port to connect to
wim 4:12446ee9f9c8 1049 * @param char deviceAddress the I2C slave address of the SC16IS750
wim 4:12446ee9f9c8 1050 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
wim 4:12446ee9f9c8 1051 * @param channel UART Channel, Default = Channel_A
wim 4:12446ee9f9c8 1052 */
wim 4:12446ee9f9c8 1053 SC16IS752_I2C::SC16IS752_I2C(I2C *i2c, uint8_t deviceAddress, PinName rst, ChannelName channel) : _i2c(i2c), _slaveAddress(deviceAddress & 0xFE), _channel(channel) {
wim 4:12446ee9f9c8 1054
wim 4:12446ee9f9c8 1055 _i2c->frequency(400000);
wim 4:12446ee9f9c8 1056
wim 4:12446ee9f9c8 1057 // The hardware Reset pin is optional. Test and make sure whether it exists or not to prevent illegal access.
wim 4:12446ee9f9c8 1058 if (rst != NC) {
wim 4:12446ee9f9c8 1059 _reset = new DigitalOut(rst); //Construct new pin
wim 4:12446ee9f9c8 1060 _reset->write(1); //Deactivate
wim 4:12446ee9f9c8 1061 }
wim 4:12446ee9f9c8 1062 else {
wim 4:12446ee9f9c8 1063 // No Hardware Reset pin
wim 4:12446ee9f9c8 1064 _reset = NULL; //Construct dummy pin
wim 4:12446ee9f9c8 1065 }
wim 4:12446ee9f9c8 1066
wim 4:12446ee9f9c8 1067 // Dont call _init() until I2C port has been configured.
wim 4:12446ee9f9c8 1068 // That is why _init() is not called in parent Constructor
wim 4:12446ee9f9c8 1069 _init();
wim 4:12446ee9f9c8 1070 }
wim 4:12446ee9f9c8 1071
wim 4:12446ee9f9c8 1072
wim 4:12446ee9f9c8 1073 /** Destruct SC16IS752_I2C bridge object
wim 4:12446ee9f9c8 1074 *
wim 4:12446ee9f9c8 1075 * @param none
wim 4:12446ee9f9c8 1076 * @return none
wim 4:12446ee9f9c8 1077 */
wim 4:12446ee9f9c8 1078 SC16IS752_I2C::~SC16IS752_I2C() {
wim 4:12446ee9f9c8 1079 if (_reset != NULL) {delete _reset;} // Reset pin
wim 4:12446ee9f9c8 1080 }
wim 4:12446ee9f9c8 1081
wim 4:12446ee9f9c8 1082
wim 4:12446ee9f9c8 1083 /** Write value to internal register.
wim 4:12446ee9f9c8 1084 * @param registerAddress The address of the Register (enum RegisterName)
wim 4:12446ee9f9c8 1085 * @param data The 8bit value to write
wim 4:12446ee9f9c8 1086 * @return none
wim 4:12446ee9f9c8 1087 */
wim 4:12446ee9f9c8 1088 void SC16IS752_I2C::writeRegister(RegisterName registerAddress, char data) {
wim 4:12446ee9f9c8 1089 char w[2];
wim 4:12446ee9f9c8 1090
wim 4:12446ee9f9c8 1091 w[0] = registerAddress | _channel;
wim 4:12446ee9f9c8 1092 w[1] = data;
wim 4:12446ee9f9c8 1093
wim 4:12446ee9f9c8 1094 _i2c->write( _slaveAddress, w, 2 );
wim 4:12446ee9f9c8 1095 }
wim 4:12446ee9f9c8 1096
wim 4:12446ee9f9c8 1097
wim 4:12446ee9f9c8 1098 /** Read value from internal register.
wim 4:12446ee9f9c8 1099 * @param registerAddress The address of the Register (enum RegisterName)
wim 4:12446ee9f9c8 1100 * @return char The 8bit value read from the register
wim 4:12446ee9f9c8 1101 */
wim 4:12446ee9f9c8 1102 char SC16IS752_I2C::readRegister(RegisterName registerAddress) {
wim 4:12446ee9f9c8 1103 /*
wim 4:12446ee9f9c8 1104 * Read char from SC16IS752 register at <registerAddress>.
wim 4:12446ee9f9c8 1105 */
wim 4:12446ee9f9c8 1106 char w[1];
wim 4:12446ee9f9c8 1107 char r[1];
wim 4:12446ee9f9c8 1108
wim 4:12446ee9f9c8 1109 w[0] = registerAddress | _channel;
wim 4:12446ee9f9c8 1110
wim 4:12446ee9f9c8 1111 _i2c->write( _slaveAddress, w, 1 );
wim 4:12446ee9f9c8 1112 _i2c->read( _slaveAddress, r, 1 );
wim 4:12446ee9f9c8 1113
wim 4:12446ee9f9c8 1114 return ( r[0] );
wim 4:12446ee9f9c8 1115 }
wim 4:12446ee9f9c8 1116
wim 4:12446ee9f9c8 1117
wim 4:12446ee9f9c8 1118 /** Write multiple datavalues to Transmitregister.
wim 4:12446ee9f9c8 1119 * More Efficient implementation than writing individual bytes
wim 4:12446ee9f9c8 1120 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 4:12446ee9f9c8 1121 * Pure virtual, must be declared in derived class.
wim 4:12446ee9f9c8 1122 * @param char* databytes The pointer to the block of data
wim 4:12446ee9f9c8 1123 * @param len The number of bytes to write
wim 4:12446ee9f9c8 1124 * @return none
wim 4:12446ee9f9c8 1125 */
wim 4:12446ee9f9c8 1126 void SC16IS752_I2C::writeDataBlock (const char *data, int len) {
wim 4:12446ee9f9c8 1127
wim 4:12446ee9f9c8 1128 #if(0)
wim 4:12446ee9f9c8 1129 int i;
wim 4:12446ee9f9c8 1130 char w[BULK_BLOCK_LEN];
wim 4:12446ee9f9c8 1131
wim 4:12446ee9f9c8 1132 // Select the Transmit Holding Register
wim 4:12446ee9f9c8 1133 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 4:12446ee9f9c8 1134 w[0] = THR | _channel;
wim 4:12446ee9f9c8 1135
wim 4:12446ee9f9c8 1136 // copy the data..
wim 4:12446ee9f9c8 1137 for (i=0; i<len; i++)
wim 4:12446ee9f9c8 1138 w[i+1] = data[i];
wim 4:12446ee9f9c8 1139
wim 4:12446ee9f9c8 1140 _i2c->write( _slaveAddress, w, len + 1);
wim 4:12446ee9f9c8 1141 #else
wim 4:12446ee9f9c8 1142 int i;
wim 4:12446ee9f9c8 1143
wim 4:12446ee9f9c8 1144 _i2c->start();
wim 4:12446ee9f9c8 1145 _i2c->write(_slaveAddress);
wim 4:12446ee9f9c8 1146
wim 4:12446ee9f9c8 1147 // Select the Transmit Holding Register
wim 4:12446ee9f9c8 1148 // Assume that previous check confirmed that the FIFO has sufficient free space to store the data
wim 4:12446ee9f9c8 1149 _i2c->write(THR | _channel);
wim 4:12446ee9f9c8 1150
wim 4:12446ee9f9c8 1151 // send the data..
wim 4:12446ee9f9c8 1152 for (i=0; i<len; i++)
wim 4:12446ee9f9c8 1153 _i2c->write(data[i]);
wim 4:12446ee9f9c8 1154
wim 4:12446ee9f9c8 1155 _i2c->stop();
wim 4:12446ee9f9c8 1156 #endif
wim 4:12446ee9f9c8 1157 }
wim 4:12446ee9f9c8 1158
wim 4:12446ee9f9c8 1159
wim 4:12446ee9f9c8 1160 /** Hardware Reset SC16IS752 device.
wim 4:12446ee9f9c8 1161 * This method is only available when the Reset pin has been declared and is also connected
wim 4:12446ee9f9c8 1162 * @param none
wim 4:12446ee9f9c8 1163 * @return none
wim 4:12446ee9f9c8 1164 */
wim 4:12446ee9f9c8 1165 void SC16IS752_I2C::hwReset() {
wim 4:12446ee9f9c8 1166
wim 4:12446ee9f9c8 1167 if (_reset != NULL){
wim 4:12446ee9f9c8 1168 _reset->write(0); //activate
wim 4:12446ee9f9c8 1169 // wait_ms(100);
wim 4:12446ee9f9c8 1170 wait_ms(1000); //test only
wim 4:12446ee9f9c8 1171 _reset->write(1); //deactivate
wim 4:12446ee9f9c8 1172 }
wim 4:12446ee9f9c8 1173 else {
wim 4:12446ee9f9c8 1174 printf("Hardware Reset pin is not available...\n\r");
wim 4:12446ee9f9c8 1175 }
wim 4:12446ee9f9c8 1176 }
wim 4:12446ee9f9c8 1177
wim 4:12446ee9f9c8 1178
wim 4:12446ee9f9c8 1179 //
wim 4:12446ee9f9c8 1180 // End I2C Implementation
wim 4:12446ee9f9c8 1181 //
wim 4:12446ee9f9c8 1182
wim 4:12446ee9f9c8 1183
wim 4:12446ee9f9c8 1184