Diff: MCP23017.h

Revision:

4:868db61f5f4e

Parent:

3:72da9cd002bd

Child:

5:5696b886a895

diff -r 72da9cd002bd -r 868db61f5f4e MCP23017.h
--- a/MCP23017.h	Sun Aug 21 13:59:48 2011 +0000
+++ b/MCP23017.h	Mon Feb 13 21:54:29 2012 +0000
@@ -6,6 +6,7 @@
 * version 0.2 Initial Release
 * version 0.3 Cleaned up
 * version 0.4 Fixed problem with _read method
+* version 0.5 Added support for 'Banked' access to registers
 */
 #include "mbed.h"
 
@@ -15,14 +16,16 @@
 // All register addresses assume IOCON.BANK = 0 (POR default)
 #define IODIRA   0x00
 #define IODIRB   0x01
+#define IPOLA    0x02
+#define IPOLB    0x03
 #define GPINTENA 0x04
 #define GPINTENB 0x05
 #define DEFVALA  0x06
 #define DEFVALB  0x07
 #define INTCONA  0x08
 #define INTCONB  0x09
-#define IOCON    0x0A
-//#define IOCON    0x0B
+#define IOCONA   0x0A
+#define IOCONB   0x0B
 #define GPPUA    0x0C
 #define GPPUB    0x0D
 #define INTFA    0x0E
@@ -34,10 +37,50 @@
 #define OLATA    0x14
 #define OLATB    0x15
 
+// The following register addresses assume IOCON.BANK = 1 
+#define IODIRA_BNK   0x00
+#define IPOLA_BNK    0x01
+#define GPINTENA_BNK 0x02
+#define DEFVALA_BNK  0x03
+#define INTCONA_BNK  0x04
+#define GPPUA_BNK    0x05
+#define INTFA_BNK    0x06
+#define IOCONA_BNK   0x07
+#define INTCAPA_BNK  0x08
+#define GPIOA_BNK    0x09
+#define OLATA_BNK    0x0A
+
+#define IODIRB_BNK   0x10
+#define IPOLB_BNK    0x11
+#define GPINTENB_BNK 0x12
+#define DEFVALB_BNK  0x13
+#define INTCONB_BNK  0x14
+#define IOCONB_BNK   0x15
+#define GPPUB_BNK    0x16
+#define INTFB_BNK    0x17
+#define INTCAPB_BNK  0x18
+#define GPIOB_BNK    0x19
+#define OLATB_BNK    0x1A
+
+// This array allows structured access to Port_A and Port_B registers for both bankModes
+const int IODIR_AB[2][2]   = {{IODIRA, IODIRB},     {IODIRA_BNK, IODIRB_BNK}};
+const int IPOL_AB[2][2]    = {{IPOLA, IPOLB},       {IPOLA_BNK, IPOLB_BNK}};
+const int GPINTEN_AB[2][2] = {{GPINTENA, GPINTENB}, {GPINTENA_BNK, GPINTENB_BNK}};
+const int DEFVAL_AB[2][2]  = {{DEFVALA, DEFVALB},   {DEFVALA_BNK, DEFVALB_BNK}};
+const int INTCON_AB[2][2]  = {{INTCONA, INTCONB},   {INTCONA_BNK, INTCONB_BNK}};
+const int IOCON_AB[2][2]   = {{IOCONA, IOCONB},     {IOCONA_BNK, IOCONB_BNK}};
+const int GPPU_AB[2][2]    = {{GPPUA, GPPUB},       {GPPUA_BNK, GPPUB_BNK}};
+const int INTF_AB[2][2]    = {{INTFA, INTFB},       {INTFA_BNK, INTFB_BNK}};
+const int INTCAP_AB[2][2]  = {{INTCAPA, INTCAPB},   {INTCAPA_BNK, INTCAPB_BNK}};
+const int GPIO_AB[2][2]    = {{GPIOA, GPIOB},       {GPIOA_BNK, GPIOB_BNK}};
+const int OLAT_AB[2][2]    = {{OLATA, OLATB},       {OLATA_BNK, OLATB_BNK}};
+
+
 // Control settings
 #define IOCON_BANK      0x80 // Banked registers for Port A and B
 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation, Address Ptr does not increment
                              //   If Disabled and Bank = 0, operations toggle between Port A and B registers
+                             //   If Disabled and Bank = 1, operations do not increment registeraddress                             
 #define IOCON_HAEN      0x08 // Hardware address enable
 
 #define INTERRUPT_POLARITY_BIT 0x02
@@ -47,7 +90,8 @@
 #define PORT_DIR_IN    0xFF
 
 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
-enum Port { PORT_A, PORT_B };
+enum Port { PORT_A=0, PORT_B=1 };
+enum Bank { NOT_BNK=0, BNK=1 };
 
 class MCP23017 {
 public:
@@ -72,6 +116,7 @@
     */    
     void configurePullUps(Port port, char offOrOn);
 
+    void configureBanked(Bank bankmode);  
     void interruptEnable(Port port, char interruptsEnabledMask);
     void interruptPolarity(Polarity polarity);
     void mirrorInterrupts(bool mirror);
@@ -96,6 +141,7 @@
     I2C &_i2c;
     char _readOpcode;
     char _writeOpcode;
+    Bank _bankMode; 
     
     /** Init MCP23017
     *