Diff: MAX11043/MAX11043.cpp

Revision:

89:20fd6ce5e4dd

Parent:

83:29bb86cc45bc

Child:

90:d6ed8a8c5f26

diff -r e4fd5033a55f -r 20fd6ce5e4dd MAX11043/MAX11043.cpp
--- a/MAX11043/MAX11043.cpp	Fri Feb 28 00:59:24 2020 +0000
+++ b/MAX11043/MAX11043.cpp	Fri Feb 28 07:59:58 2020 +0000
@@ -621,6 +621,20 @@
 //--------------------------------------------------
 }
 
+// CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputGetValue
+// Return the state being driven onto the MAX11043 CONVRUN pin.
+//
+int MAX11043::CONVRUNoutputGetValue()
+{
+    // CODE GENERATOR: extern function definition for function CONVRUNoutputGetValue
+    // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputGetValue
+    // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
+    // TODO1: CODE GENERATOR: gpio direction output
+    // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
+    // TODO1: CODE GENERATOR: gpio function GetValue
+    return m_CONVRUN_pin;
+}
+
 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
@@ -1428,6 +1442,13 @@
     
 //--------------------------------------------------
 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
+    //----------------------------------------
+    // warning -- WIP work in progress
+    #warning "need CONVRUNoutputGetValue() -- is CONVRUN being driven high?"
+    
+    //----------------------------------------
+    // Synchronize with EOC End Of Conversion
+    // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
 // EOC# asserts low when new data is available.
 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
 #if MAX11043_EOC_INTERRUPT_POLLING
@@ -1435,20 +1456,24 @@
 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
     // TODO: poll m_EOC_pin if CONVRUN is high
-    if (m_CONVRUN_pin)
+    if (CONVRUNoutputGetValue()) // is CONVRUN being driven high?
     {
+        // CONVRUN pin is being driven high, so EOC# will be changing.
+        // Try to read as close as possible to EOC# falling edge,
+        // because if EOC# falling edge happens during SPI data readout,
+        // the data will be corrupted.
         #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
         // possible infinite loop; need a timeout or futility countdown to escape
         for (int futility_countdown = 100;
             ((futility_countdown > 0) &&
-            (m_EOC_pin != 1));
+            (EOCinputValue() != 1));
             futility_countdown--)
         {
             // spinlock waiting for logic high pin state (start of new conversion)
         }
         for (int futility_countdown = 100;
             ((futility_countdown > 0) &&
-            (m_EOC_pin != 0));
+            (EOCinputValue() != 0));
             futility_countdown--)
         {
             // spinlock waiting for logic low pin state (new data is available)
@@ -1496,6 +1521,69 @@
 }
 
 //----------------------------------------
+// Menu item 'XD'
+// Example configuration.
+// Slowest conversion rate 1:6 = 9us,
+// Bypass PGA and filters, Gain=1V/V,
+// AOUT = 2.0V
+//
+void MAX11043::Configure_Demo(void)
+{
+    
+    //----------------------------------------
+    // warning -- WIP work in progress
+    #warning "Not Tested Yet: MAX11043::Configure_Demo..."
+    
+    //----------------------------------------
+    // *Config=0x6000 (POR default, slowest conversion rate 1:6 = 9us)
+    RegWrite(CMD_0010_0000_d16_Wr08_Configuration, 0x6000);
+    
+    //----------------------------------------
+    // *ConfigA=0x0018 (Bypass PGA and filters, Gain=1V/V)
+    RegWrite(CMD_0011_0000_d16_Wr0C_ConfigA, 0x0018);
+    
+    //----------------------------------------
+    // *AGain=0x1000 (0.5) (default is 0x2000=1.0)
+    RegWrite(CMD_0100_0100_d16_Wr11_AGain, 0x1000);
+    
+    //----------------------------------------
+    // *ConfigB=0x0018 (Bypass PGA and filters, Gain=1V/V)
+    RegWrite(CMD_0011_0100_d16_Wr0D_ConfigB, 0x0018);
+    
+    //----------------------------------------
+    // *BGain=0x1000 (0.5) (default is 0x2000=1.0)
+    RegWrite(CMD_0100_1000_d16_Wr12_BGain, 0x1000);
+    
+    //----------------------------------------
+    // *ConfigC=0x0018 (Bypass PGA and filters, Gain=1V/V)
+    RegWrite(CMD_0011_1000_d16_Wr0E_ConfigC, 0x0018);
+    
+    //----------------------------------------
+    // *CGain=0x1000 (0.5) (default is 0x2000=1.0)
+    RegWrite(CMD_0100_1100_d16_Wr13_CGain, 0x1000);
+    
+    //----------------------------------------
+    // *ConfigD=0x0018 (Bypass PGA and filters, Gain=1V/V)
+    RegWrite(CMD_0011_1100_d16_Wr0F_ConfigD, 0x0018);
+    
+    //----------------------------------------
+    // *DGain=0x1000 (0.5) (default is 0x2000=1.0)
+    RegWrite(CMD_0101_0000_d16_Wr14_DGain, 0x1000);
+    
+    //----------------------------------------
+    // *DacHDacL=0xFF00 (DAC code 0xFFF fullscale 2.5V, DAC code 0x000 lowest 0V)
+    RegWrite(CMD_0010_1100_d16_Wr0B_DACHDACL, 0xFF00);
+    
+    //----------------------------------------
+    // *DacStep=0x0001 (DAC increment value triggered by DACSTEP pin)
+    RegWrite(CMD_0010_1000_d16_Wr0A_DACStep, 0x0001);
+    
+    //----------------------------------------
+    // *Dac=0x0ccc (AOUT=2V)
+    RegWrite(CMD_0010_0100_d16_Wr09_DAC, 0x0ccc);
+}
+
+//----------------------------------------
 // Menu item 'XX'
 //
 // @return 1 on success; 0 on failure