p kj / Mbed 2 deprecated LPC824-BalanceCar

Microduino

Dependencies:   mbed

Fork of BalanceCar by Li Weiyi

MPU6050.cpp@0:a4d8f5b3c546, 2016-06-04 (annotated)

Committer:
lixianyu
Date:
Sat Jun 04 03:16:52 2016 +0000
Revision:
0:a4d8f5b3c546
Child:
2:99785a1007a4
Pass compile!!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:a4d8f5b3c546 1 // I2Cdev library collection - MPU6050 I2C device class
lixianyu 0:a4d8f5b3c546 2 // Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)
lixianyu 0:a4d8f5b3c546 3 // 8/24/2011 by Jeff Rowberg <jeff@rowberg.net>
lixianyu 0:a4d8f5b3c546 4 // Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
lixianyu 0:a4d8f5b3c546 5 //
lixianyu 0:a4d8f5b3c546 6 // Changelog:
lixianyu 0:a4d8f5b3c546 7 // ... - ongoing debug release
lixianyu 0:a4d8f5b3c546 8
lixianyu 0:a4d8f5b3c546 9 // NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE
lixianyu 0:a4d8f5b3c546 10 // DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF
lixianyu 0:a4d8f5b3c546 11 // YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING.
lixianyu 0:a4d8f5b3c546 12
lixianyu 0:a4d8f5b3c546 13 /* ============================================
lixianyu 0:a4d8f5b3c546 14 I2Cdev device library code is placed under the MIT license
lixianyu 0:a4d8f5b3c546 15 Copyright (c) 2012 Jeff Rowberg
lixianyu 0:a4d8f5b3c546 16
lixianyu 0:a4d8f5b3c546 17 Permission is hereby granted, free of charge, to any person obtaining a copy
lixianyu 0:a4d8f5b3c546 18 of this software and associated documentation files (the "Software"), to deal
lixianyu 0:a4d8f5b3c546 19 in the Software without restriction, including without limitation the rights
lixianyu 0:a4d8f5b3c546 20 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
lixianyu 0:a4d8f5b3c546 21 copies of the Software, and to permit persons to whom the Software is
lixianyu 0:a4d8f5b3c546 22 furnished to do so, subject to the following conditions:
lixianyu 0:a4d8f5b3c546 23
lixianyu 0:a4d8f5b3c546 24 The above copyright notice and this permission notice shall be included in
lixianyu 0:a4d8f5b3c546 25 all copies or substantial portions of the Software.
lixianyu 0:a4d8f5b3c546 26
lixianyu 0:a4d8f5b3c546 27 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
lixianyu 0:a4d8f5b3c546 28 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
lixianyu 0:a4d8f5b3c546 29 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
lixianyu 0:a4d8f5b3c546 30 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
lixianyu 0:a4d8f5b3c546 31 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
lixianyu 0:a4d8f5b3c546 32 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
lixianyu 0:a4d8f5b3c546 33 THE SOFTWARE.
lixianyu 0:a4d8f5b3c546 34 ===============================================
lixianyu 0:a4d8f5b3c546 35 */
lixianyu 0:a4d8f5b3c546 36
lixianyu 0:a4d8f5b3c546 37 #include "MPU6050.h"
lixianyu 0:a4d8f5b3c546 38 #define pgm_read_byte(addr) (*(const unsigned char *)(addr))
lixianyu 0:a4d8f5b3c546 39 /** Default constructor, uses default I2C address.
lixianyu 0:a4d8f5b3c546 40 * @see MPU6050_DEFAULT_ADDRESS
lixianyu 0:a4d8f5b3c546 41 */
lixianyu 0:a4d8f5b3c546 42 MPU6050::MPU6050() {
lixianyu 0:a4d8f5b3c546 43 devAddr = MPU6050_DEFAULT_ADDRESS;
lixianyu 0:a4d8f5b3c546 44 }
lixianyu 0:a4d8f5b3c546 45
lixianyu 0:a4d8f5b3c546 46 /** Specific address constructor.
lixianyu 0:a4d8f5b3c546 47 * @param address I2C address
lixianyu 0:a4d8f5b3c546 48 * @see MPU6050_DEFAULT_ADDRESS
lixianyu 0:a4d8f5b3c546 49 * @see MPU6050_ADDRESS_AD0_LOW
lixianyu 0:a4d8f5b3c546 50 * @see MPU6050_ADDRESS_AD0_HIGH
lixianyu 0:a4d8f5b3c546 51 */
lixianyu 0:a4d8f5b3c546 52 MPU6050::MPU6050(uint8_t address) {
lixianyu 0:a4d8f5b3c546 53 devAddr = address;
lixianyu 0:a4d8f5b3c546 54 }
lixianyu 0:a4d8f5b3c546 55
lixianyu 0:a4d8f5b3c546 56 /** Power on and prepare for general usage.
lixianyu 0:a4d8f5b3c546 57 * This will activate the device and take it out of sleep mode (which must be done
lixianyu 0:a4d8f5b3c546 58 * after start-up). This function also sets both the accelerometer and the gyroscope
lixianyu 0:a4d8f5b3c546 59 * to their most sensitive settings, namely +/- 2g and +/- 250 degrees/sec, and sets
lixianyu 0:a4d8f5b3c546 60 * the clock source to use the X Gyro for reference, which is slightly better than
lixianyu 0:a4d8f5b3c546 61 * the default internal clock source.
lixianyu 0:a4d8f5b3c546 62 */
lixianyu 0:a4d8f5b3c546 63 void MPU6050::initialize() {
lixianyu 0:a4d8f5b3c546 64 setClockSource(MPU6050_CLOCK_PLL_XGYRO);
lixianyu 0:a4d8f5b3c546 65 setFullScaleGyroRange(MPU6050_GYRO_FS_250);
lixianyu 0:a4d8f5b3c546 66 setFullScaleAccelRange(MPU6050_ACCEL_FS_2);
lixianyu 0:a4d8f5b3c546 67 setSleepEnabled(false); // thanks to Jack Elston for pointing this one out!
lixianyu 0:a4d8f5b3c546 68 }
lixianyu 0:a4d8f5b3c546 69
lixianyu 0:a4d8f5b3c546 70 /** Verify the I2C connection.
lixianyu 0:a4d8f5b3c546 71 * Make sure the device is connected and responds as expected.
lixianyu 0:a4d8f5b3c546 72 * @return True if connection is valid, false otherwise
lixianyu 0:a4d8f5b3c546 73 */
lixianyu 0:a4d8f5b3c546 74 bool MPU6050::testConnection() {
lixianyu 0:a4d8f5b3c546 75 return getDeviceID() == 0x34;
lixianyu 0:a4d8f5b3c546 76 }
lixianyu 0:a4d8f5b3c546 77
lixianyu 0:a4d8f5b3c546 78 // AUX_VDDIO register (InvenSense demo code calls this RA_*G_OFFS_TC)
lixianyu 0:a4d8f5b3c546 79
lixianyu 0:a4d8f5b3c546 80 /** Get the auxiliary I2C supply voltage level.
lixianyu 0:a4d8f5b3c546 81 * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to
lixianyu 0:a4d8f5b3c546 82 * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to
lixianyu 0:a4d8f5b3c546 83 * the MPU-6000, which does not have a VLOGIC pin.
lixianyu 0:a4d8f5b3c546 84 * @return I2C supply voltage level (0=VLOGIC, 1=VDD)
lixianyu 0:a4d8f5b3c546 85 */
lixianyu 0:a4d8f5b3c546 86 uint8_t MPU6050::getAuxVDDIOLevel() {
lixianyu 0:a4d8f5b3c546 87 I2Cdev::readBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, buffer);
lixianyu 0:a4d8f5b3c546 88 return buffer[0];
lixianyu 0:a4d8f5b3c546 89 }
lixianyu 0:a4d8f5b3c546 90 /** Set the auxiliary I2C supply voltage level.
lixianyu 0:a4d8f5b3c546 91 * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to
lixianyu 0:a4d8f5b3c546 92 * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to
lixianyu 0:a4d8f5b3c546 93 * the MPU-6000, which does not have a VLOGIC pin.
lixianyu 0:a4d8f5b3c546 94 * @param level I2C supply voltage level (0=VLOGIC, 1=VDD)
lixianyu 0:a4d8f5b3c546 95 */
lixianyu 0:a4d8f5b3c546 96 void MPU6050::setAuxVDDIOLevel(uint8_t level) {
lixianyu 0:a4d8f5b3c546 97 I2Cdev::writeBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, level);
lixianyu 0:a4d8f5b3c546 98 }
lixianyu 0:a4d8f5b3c546 99
lixianyu 0:a4d8f5b3c546 100 // SMPLRT_DIV register
lixianyu 0:a4d8f5b3c546 101
lixianyu 0:a4d8f5b3c546 102 /** Get gyroscope output rate divider.
lixianyu 0:a4d8f5b3c546 103 * The sensor register output, FIFO output, DMP sampling, Motion detection, Zero
lixianyu 0:a4d8f5b3c546 104 * Motion detection, and Free Fall detection are all based on the Sample Rate.
lixianyu 0:a4d8f5b3c546 105 * The Sample Rate is generated by dividing the gyroscope output rate by
lixianyu 0:a4d8f5b3c546 106 * SMPLRT_DIV:
lixianyu 0:a4d8f5b3c546 107 *
lixianyu 0:a4d8f5b3c546 108 * Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV)
lixianyu 0:a4d8f5b3c546 109 *
lixianyu 0:a4d8f5b3c546 110 * where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or
lixianyu 0:a4d8f5b3c546 111 * 7), and 1kHz when the DLPF is enabled (see Register 26).
lixianyu 0:a4d8f5b3c546 112 *
lixianyu 0:a4d8f5b3c546 113 * Note: The accelerometer output rate is 1kHz. This means that for a Sample
lixianyu 0:a4d8f5b3c546 114 * Rate greater than 1kHz, the same accelerometer sample may be output to the
lixianyu 0:a4d8f5b3c546 115 * FIFO, DMP, and sensor registers more than once.
lixianyu 0:a4d8f5b3c546 116 *
lixianyu 0:a4d8f5b3c546 117 * For a diagram of the gyroscope and accelerometer signal paths, see Section 8
lixianyu 0:a4d8f5b3c546 118 * of the MPU-6000/MPU-6050 Product Specification document.
lixianyu 0:a4d8f5b3c546 119 *
lixianyu 0:a4d8f5b3c546 120 * @return Current sample rate
lixianyu 0:a4d8f5b3c546 121 * @see MPU6050_RA_SMPLRT_DIV
lixianyu 0:a4d8f5b3c546 122 */
lixianyu 0:a4d8f5b3c546 123 uint8_t MPU6050::getRate() {
lixianyu 0:a4d8f5b3c546 124 I2Cdev::readByte(devAddr, MPU6050_RA_SMPLRT_DIV, buffer);
lixianyu 0:a4d8f5b3c546 125 return buffer[0];
lixianyu 0:a4d8f5b3c546 126 }
lixianyu 0:a4d8f5b3c546 127 /** Set gyroscope sample rate divider.
lixianyu 0:a4d8f5b3c546 128 * @param rate New sample rate divider
lixianyu 0:a4d8f5b3c546 129 * @see getRate()
lixianyu 0:a4d8f5b3c546 130 * @see MPU6050_RA_SMPLRT_DIV
lixianyu 0:a4d8f5b3c546 131 */
lixianyu 0:a4d8f5b3c546 132 void MPU6050::setRate(uint8_t rate) {
lixianyu 0:a4d8f5b3c546 133 I2Cdev::writeByte(devAddr, MPU6050_RA_SMPLRT_DIV, rate);
lixianyu 0:a4d8f5b3c546 134 }
lixianyu 0:a4d8f5b3c546 135
lixianyu 0:a4d8f5b3c546 136 // CONFIG register
lixianyu 0:a4d8f5b3c546 137
lixianyu 0:a4d8f5b3c546 138 /** Get external FSYNC configuration.
lixianyu 0:a4d8f5b3c546 139 * Configures the external Frame Synchronization (FSYNC) pin sampling. An
lixianyu 0:a4d8f5b3c546 140 * external signal connected to the FSYNC pin can be sampled by configuring
lixianyu 0:a4d8f5b3c546 141 * EXT_SYNC_SET. Signal changes to the FSYNC pin are latched so that short
lixianyu 0:a4d8f5b3c546 142 * strobes may be captured. The latched FSYNC signal will be sampled at the
lixianyu 0:a4d8f5b3c546 143 * Sampling Rate, as defined in register 25. After sampling, the latch will
lixianyu 0:a4d8f5b3c546 144 * reset to the current FSYNC signal state.
lixianyu 0:a4d8f5b3c546 145 *
lixianyu 0:a4d8f5b3c546 146 * The sampled value will be reported in place of the least significant bit in
lixianyu 0:a4d8f5b3c546 147 * a sensor data register determined by the value of EXT_SYNC_SET according to
lixianyu 0:a4d8f5b3c546 148 * the following table.
lixianyu 0:a4d8f5b3c546 149 *
lixianyu 0:a4d8f5b3c546 150 * <pre>
lixianyu 0:a4d8f5b3c546 151 * EXT_SYNC_SET | FSYNC Bit Location
lixianyu 0:a4d8f5b3c546 152 * -------------+-------------------
lixianyu 0:a4d8f5b3c546 153 * 0 | Input disabled
lixianyu 0:a4d8f5b3c546 154 * 1 | TEMP_OUT_L[0]
lixianyu 0:a4d8f5b3c546 155 * 2 | GYRO_XOUT_L[0]
lixianyu 0:a4d8f5b3c546 156 * 3 | GYRO_YOUT_L[0]
lixianyu 0:a4d8f5b3c546 157 * 4 | GYRO_ZOUT_L[0]
lixianyu 0:a4d8f5b3c546 158 * 5 | ACCEL_XOUT_L[0]
lixianyu 0:a4d8f5b3c546 159 * 6 | ACCEL_YOUT_L[0]
lixianyu 0:a4d8f5b3c546 160 * 7 | ACCEL_ZOUT_L[0]
lixianyu 0:a4d8f5b3c546 161 * </pre>
lixianyu 0:a4d8f5b3c546 162 *
lixianyu 0:a4d8f5b3c546 163 * @return FSYNC configuration value
lixianyu 0:a4d8f5b3c546 164 */
lixianyu 0:a4d8f5b3c546 165 uint8_t MPU6050::getExternalFrameSync() {
lixianyu 0:a4d8f5b3c546 166 I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 167 return buffer[0];
lixianyu 0:a4d8f5b3c546 168 }
lixianyu 0:a4d8f5b3c546 169 /** Set external FSYNC configuration.
lixianyu 0:a4d8f5b3c546 170 * @see getExternalFrameSync()
lixianyu 0:a4d8f5b3c546 171 * @see MPU6050_RA_CONFIG
lixianyu 0:a4d8f5b3c546 172 * @param sync New FSYNC configuration value
lixianyu 0:a4d8f5b3c546 173 */
lixianyu 0:a4d8f5b3c546 174 void MPU6050::setExternalFrameSync(uint8_t sync) {
lixianyu 0:a4d8f5b3c546 175 I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, sync);
lixianyu 0:a4d8f5b3c546 176 }
lixianyu 0:a4d8f5b3c546 177 /** Get digital low-pass filter configuration.
lixianyu 0:a4d8f5b3c546 178 * The DLPF_CFG parameter sets the digital low pass filter configuration. It
lixianyu 0:a4d8f5b3c546 179 * also determines the internal sampling rate used by the device as shown in
lixianyu 0:a4d8f5b3c546 180 * the table below.
lixianyu 0:a4d8f5b3c546 181 *
lixianyu 0:a4d8f5b3c546 182 * Note: The accelerometer output rate is 1kHz. This means that for a Sample
lixianyu 0:a4d8f5b3c546 183 * Rate greater than 1kHz, the same accelerometer sample may be output to the
lixianyu 0:a4d8f5b3c546 184 * FIFO, DMP, and sensor registers more than once.
lixianyu 0:a4d8f5b3c546 185 *
lixianyu 0:a4d8f5b3c546 186 * <pre>
lixianyu 0:a4d8f5b3c546 187 * | ACCELEROMETER | GYROSCOPE
lixianyu 0:a4d8f5b3c546 188 * DLPF_CFG | Bandwidth | Delay | Bandwidth | Delay | Sample Rate
lixianyu 0:a4d8f5b3c546 189 * ---------+-----------+--------+-----------+--------+-------------
lixianyu 0:a4d8f5b3c546 190 * 0 | 260Hz | 0ms | 256Hz | 0.98ms | 8kHz
lixianyu 0:a4d8f5b3c546 191 * 1 | 184Hz | 2.0ms | 188Hz | 1.9ms | 1kHz
lixianyu 0:a4d8f5b3c546 192 * 2 | 94Hz | 3.0ms | 98Hz | 2.8ms | 1kHz
lixianyu 0:a4d8f5b3c546 193 * 3 | 44Hz | 4.9ms | 42Hz | 4.8ms | 1kHz
lixianyu 0:a4d8f5b3c546 194 * 4 | 21Hz | 8.5ms | 20Hz | 8.3ms | 1kHz
lixianyu 0:a4d8f5b3c546 195 * 5 | 10Hz | 13.8ms | 10Hz | 13.4ms | 1kHz
lixianyu 0:a4d8f5b3c546 196 * 6 | 5Hz | 19.0ms | 5Hz | 18.6ms | 1kHz
lixianyu 0:a4d8f5b3c546 197 * 7 | -- Reserved -- | -- Reserved -- | Reserved
lixianyu 0:a4d8f5b3c546 198 * </pre>
lixianyu 0:a4d8f5b3c546 199 *
lixianyu 0:a4d8f5b3c546 200 * @return DLFP configuration
lixianyu 0:a4d8f5b3c546 201 * @see MPU6050_RA_CONFIG
lixianyu 0:a4d8f5b3c546 202 * @see MPU6050_CFG_DLPF_CFG_BIT
lixianyu 0:a4d8f5b3c546 203 * @see MPU6050_CFG_DLPF_CFG_LENGTH
lixianyu 0:a4d8f5b3c546 204 */
lixianyu 0:a4d8f5b3c546 205 uint8_t MPU6050::getDLPFMode() {
lixianyu 0:a4d8f5b3c546 206 I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 207 return buffer[0];
lixianyu 0:a4d8f5b3c546 208 }
lixianyu 0:a4d8f5b3c546 209 /** Set digital low-pass filter configuration.
lixianyu 0:a4d8f5b3c546 210 * @param mode New DLFP configuration setting
lixianyu 0:a4d8f5b3c546 211 * @see getDLPFBandwidth()
lixianyu 0:a4d8f5b3c546 212 * @see MPU6050_DLPF_BW_256
lixianyu 0:a4d8f5b3c546 213 * @see MPU6050_RA_CONFIG
lixianyu 0:a4d8f5b3c546 214 * @see MPU6050_CFG_DLPF_CFG_BIT
lixianyu 0:a4d8f5b3c546 215 * @see MPU6050_CFG_DLPF_CFG_LENGTH
lixianyu 0:a4d8f5b3c546 216 */
lixianyu 0:a4d8f5b3c546 217 void MPU6050::setDLPFMode(uint8_t mode) {
lixianyu 0:a4d8f5b3c546 218 I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, mode);
lixianyu 0:a4d8f5b3c546 219 }
lixianyu 0:a4d8f5b3c546 220
lixianyu 0:a4d8f5b3c546 221 // GYRO_CONFIG register
lixianyu 0:a4d8f5b3c546 222
lixianyu 0:a4d8f5b3c546 223 /** Get full-scale gyroscope range.
lixianyu 0:a4d8f5b3c546 224 * The FS_SEL parameter allows setting the full-scale range of the gyro sensors,
lixianyu 0:a4d8f5b3c546 225 * as described in the table below.
lixianyu 0:a4d8f5b3c546 226 *
lixianyu 0:a4d8f5b3c546 227 * <pre>
lixianyu 0:a4d8f5b3c546 228 * 0 = +/- 250 degrees/sec
lixianyu 0:a4d8f5b3c546 229 * 1 = +/- 500 degrees/sec
lixianyu 0:a4d8f5b3c546 230 * 2 = +/- 1000 degrees/sec
lixianyu 0:a4d8f5b3c546 231 * 3 = +/- 2000 degrees/sec
lixianyu 0:a4d8f5b3c546 232 * </pre>
lixianyu 0:a4d8f5b3c546 233 *
lixianyu 0:a4d8f5b3c546 234 * @return Current full-scale gyroscope range setting
lixianyu 0:a4d8f5b3c546 235 * @see MPU6050_GYRO_FS_250
lixianyu 0:a4d8f5b3c546 236 * @see MPU6050_RA_GYRO_CONFIG
lixianyu 0:a4d8f5b3c546 237 * @see MPU6050_GCONFIG_FS_SEL_BIT
lixianyu 0:a4d8f5b3c546 238 * @see MPU6050_GCONFIG_FS_SEL_LENGTH
lixianyu 0:a4d8f5b3c546 239 */
lixianyu 0:a4d8f5b3c546 240 uint8_t MPU6050::getFullScaleGyroRange() {
lixianyu 0:a4d8f5b3c546 241 I2Cdev::readBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 242 return buffer[0];
lixianyu 0:a4d8f5b3c546 243 }
lixianyu 0:a4d8f5b3c546 244 /** Set full-scale gyroscope range.
lixianyu 0:a4d8f5b3c546 245 * @param range New full-scale gyroscope range value
lixianyu 0:a4d8f5b3c546 246 * @see getFullScaleRange()
lixianyu 0:a4d8f5b3c546 247 * @see MPU6050_GYRO_FS_250
lixianyu 0:a4d8f5b3c546 248 * @see MPU6050_RA_GYRO_CONFIG
lixianyu 0:a4d8f5b3c546 249 * @see MPU6050_GCONFIG_FS_SEL_BIT
lixianyu 0:a4d8f5b3c546 250 * @see MPU6050_GCONFIG_FS_SEL_LENGTH
lixianyu 0:a4d8f5b3c546 251 */
lixianyu 0:a4d8f5b3c546 252 void MPU6050::setFullScaleGyroRange(uint8_t range) {
lixianyu 0:a4d8f5b3c546 253 I2Cdev::writeBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range);
lixianyu 0:a4d8f5b3c546 254 }
lixianyu 0:a4d8f5b3c546 255
lixianyu 0:a4d8f5b3c546 256 // ACCEL_CONFIG register
lixianyu 0:a4d8f5b3c546 257
lixianyu 0:a4d8f5b3c546 258 /** Get self-test enabled setting for accelerometer X axis.
lixianyu 0:a4d8f5b3c546 259 * @return Self-test enabled value
lixianyu 0:a4d8f5b3c546 260 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 261 */
lixianyu 0:a4d8f5b3c546 262 bool MPU6050::getAccelXSelfTest() {
lixianyu 0:a4d8f5b3c546 263 I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, buffer);
lixianyu 0:a4d8f5b3c546 264 return buffer[0];
lixianyu 0:a4d8f5b3c546 265 }
lixianyu 0:a4d8f5b3c546 266 /** Get self-test enabled setting for accelerometer X axis.
lixianyu 0:a4d8f5b3c546 267 * @param enabled Self-test enabled value
lixianyu 0:a4d8f5b3c546 268 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 269 */
lixianyu 0:a4d8f5b3c546 270 void MPU6050::setAccelXSelfTest(bool enabled) {
lixianyu 0:a4d8f5b3c546 271 I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, enabled);
lixianyu 0:a4d8f5b3c546 272 }
lixianyu 0:a4d8f5b3c546 273 /** Get self-test enabled value for accelerometer Y axis.
lixianyu 0:a4d8f5b3c546 274 * @return Self-test enabled value
lixianyu 0:a4d8f5b3c546 275 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 276 */
lixianyu 0:a4d8f5b3c546 277 bool MPU6050::getAccelYSelfTest() {
lixianyu 0:a4d8f5b3c546 278 I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, buffer);
lixianyu 0:a4d8f5b3c546 279 return buffer[0];
lixianyu 0:a4d8f5b3c546 280 }
lixianyu 0:a4d8f5b3c546 281 /** Get self-test enabled value for accelerometer Y axis.
lixianyu 0:a4d8f5b3c546 282 * @param enabled Self-test enabled value
lixianyu 0:a4d8f5b3c546 283 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 284 */
lixianyu 0:a4d8f5b3c546 285 void MPU6050::setAccelYSelfTest(bool enabled) {
lixianyu 0:a4d8f5b3c546 286 I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, enabled);
lixianyu 0:a4d8f5b3c546 287 }
lixianyu 0:a4d8f5b3c546 288 /** Get self-test enabled value for accelerometer Z axis.
lixianyu 0:a4d8f5b3c546 289 * @return Self-test enabled value
lixianyu 0:a4d8f5b3c546 290 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 291 */
lixianyu 0:a4d8f5b3c546 292 bool MPU6050::getAccelZSelfTest() {
lixianyu 0:a4d8f5b3c546 293 I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, buffer);
lixianyu 0:a4d8f5b3c546 294 return buffer[0];
lixianyu 0:a4d8f5b3c546 295 }
lixianyu 0:a4d8f5b3c546 296 /** Set self-test enabled value for accelerometer Z axis.
lixianyu 0:a4d8f5b3c546 297 * @param enabled Self-test enabled value
lixianyu 0:a4d8f5b3c546 298 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 299 */
lixianyu 0:a4d8f5b3c546 300 void MPU6050::setAccelZSelfTest(bool enabled) {
lixianyu 0:a4d8f5b3c546 301 I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, enabled);
lixianyu 0:a4d8f5b3c546 302 }
lixianyu 0:a4d8f5b3c546 303 /** Get full-scale accelerometer range.
lixianyu 0:a4d8f5b3c546 304 * The FS_SEL parameter allows setting the full-scale range of the accelerometer
lixianyu 0:a4d8f5b3c546 305 * sensors, as described in the table below.
lixianyu 0:a4d8f5b3c546 306 *
lixianyu 0:a4d8f5b3c546 307 * <pre>
lixianyu 0:a4d8f5b3c546 308 * 0 = +/- 2g
lixianyu 0:a4d8f5b3c546 309 * 1 = +/- 4g
lixianyu 0:a4d8f5b3c546 310 * 2 = +/- 8g
lixianyu 0:a4d8f5b3c546 311 * 3 = +/- 16g
lixianyu 0:a4d8f5b3c546 312 * </pre>
lixianyu 0:a4d8f5b3c546 313 *
lixianyu 0:a4d8f5b3c546 314 * @return Current full-scale accelerometer range setting
lixianyu 0:a4d8f5b3c546 315 * @see MPU6050_ACCEL_FS_2
lixianyu 0:a4d8f5b3c546 316 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 317 * @see MPU6050_ACONFIG_AFS_SEL_BIT
lixianyu 0:a4d8f5b3c546 318 * @see MPU6050_ACONFIG_AFS_SEL_LENGTH
lixianyu 0:a4d8f5b3c546 319 */
lixianyu 0:a4d8f5b3c546 320 uint8_t MPU6050::getFullScaleAccelRange() {
lixianyu 0:a4d8f5b3c546 321 I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 322 return buffer[0];
lixianyu 0:a4d8f5b3c546 323 }
lixianyu 0:a4d8f5b3c546 324 /** Set full-scale accelerometer range.
lixianyu 0:a4d8f5b3c546 325 * @param range New full-scale accelerometer range setting
lixianyu 0:a4d8f5b3c546 326 * @see getFullScaleAccelRange()
lixianyu 0:a4d8f5b3c546 327 */
lixianyu 0:a4d8f5b3c546 328 void MPU6050::setFullScaleAccelRange(uint8_t range) {
lixianyu 0:a4d8f5b3c546 329 I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range);
lixianyu 0:a4d8f5b3c546 330 }
lixianyu 0:a4d8f5b3c546 331 /** Get the high-pass filter configuration.
lixianyu 0:a4d8f5b3c546 332 * The DHPF is a filter module in the path leading to motion detectors (Free
lixianyu 0:a4d8f5b3c546 333 * Fall, Motion threshold, and Zero Motion). The high pass filter output is not
lixianyu 0:a4d8f5b3c546 334 * available to the data registers (see Figure in Section 8 of the MPU-6000/
lixianyu 0:a4d8f5b3c546 335 * MPU-6050 Product Specification document).
lixianyu 0:a4d8f5b3c546 336 *
lixianyu 0:a4d8f5b3c546 337 * The high pass filter has three modes:
lixianyu 0:a4d8f5b3c546 338 *
lixianyu 0:a4d8f5b3c546 339 * <pre>
lixianyu 0:a4d8f5b3c546 340 * Reset: The filter output settles to zero within one sample. This
lixianyu 0:a4d8f5b3c546 341 * effectively disables the high pass filter. This mode may be toggled
lixianyu 0:a4d8f5b3c546 342 * to quickly settle the filter.
lixianyu 0:a4d8f5b3c546 343 *
lixianyu 0:a4d8f5b3c546 344 * On: The high pass filter will pass signals above the cut off frequency.
lixianyu 0:a4d8f5b3c546 345 *
lixianyu 0:a4d8f5b3c546 346 * Hold: When triggered, the filter holds the present sample. The filter
lixianyu 0:a4d8f5b3c546 347 * output will be the difference between the input sample and the held
lixianyu 0:a4d8f5b3c546 348 * sample.
lixianyu 0:a4d8f5b3c546 349 * </pre>
lixianyu 0:a4d8f5b3c546 350 *
lixianyu 0:a4d8f5b3c546 351 * <pre>
lixianyu 0:a4d8f5b3c546 352 * ACCEL_HPF | Filter Mode | Cut-off Frequency
lixianyu 0:a4d8f5b3c546 353 * ----------+-------------+------------------
lixianyu 0:a4d8f5b3c546 354 * 0 | Reset | None
lixianyu 0:a4d8f5b3c546 355 * 1 | On | 5Hz
lixianyu 0:a4d8f5b3c546 356 * 2 | On | 2.5Hz
lixianyu 0:a4d8f5b3c546 357 * 3 | On | 1.25Hz
lixianyu 0:a4d8f5b3c546 358 * 4 | On | 0.63Hz
lixianyu 0:a4d8f5b3c546 359 * 7 | Hold | None
lixianyu 0:a4d8f5b3c546 360 * </pre>
lixianyu 0:a4d8f5b3c546 361 *
lixianyu 0:a4d8f5b3c546 362 * @return Current high-pass filter configuration
lixianyu 0:a4d8f5b3c546 363 * @see MPU6050_DHPF_RESET
lixianyu 0:a4d8f5b3c546 364 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 365 */
lixianyu 0:a4d8f5b3c546 366 uint8_t MPU6050::getDHPFMode() {
lixianyu 0:a4d8f5b3c546 367 I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 368 return buffer[0];
lixianyu 0:a4d8f5b3c546 369 }
lixianyu 0:a4d8f5b3c546 370 /** Set the high-pass filter configuration.
lixianyu 0:a4d8f5b3c546 371 * @param bandwidth New high-pass filter configuration
lixianyu 0:a4d8f5b3c546 372 * @see setDHPFMode()
lixianyu 0:a4d8f5b3c546 373 * @see MPU6050_DHPF_RESET
lixianyu 0:a4d8f5b3c546 374 * @see MPU6050_RA_ACCEL_CONFIG
lixianyu 0:a4d8f5b3c546 375 */
lixianyu 0:a4d8f5b3c546 376 void MPU6050::setDHPFMode(uint8_t bandwidth) {
lixianyu 0:a4d8f5b3c546 377 I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, bandwidth);
lixianyu 0:a4d8f5b3c546 378 }
lixianyu 0:a4d8f5b3c546 379
lixianyu 0:a4d8f5b3c546 380 // FF_THR register
lixianyu 0:a4d8f5b3c546 381
lixianyu 0:a4d8f5b3c546 382 /** Get free-fall event acceleration threshold.
lixianyu 0:a4d8f5b3c546 383 * This register configures the detection threshold for Free Fall event
lixianyu 0:a4d8f5b3c546 384 * detection. The unit of FF_THR is 1LSB = 2mg. Free Fall is detected when the
lixianyu 0:a4d8f5b3c546 385 * absolute value of the accelerometer measurements for the three axes are each
lixianyu 0:a4d8f5b3c546 386 * less than the detection threshold. This condition increments the Free Fall
lixianyu 0:a4d8f5b3c546 387 * duration counter (Register 30). The Free Fall interrupt is triggered when the
lixianyu 0:a4d8f5b3c546 388 * Free Fall duration counter reaches the time specified in FF_DUR.
lixianyu 0:a4d8f5b3c546 389 *
lixianyu 0:a4d8f5b3c546 390 * For more details on the Free Fall detection interrupt, see Section 8.2 of the
lixianyu 0:a4d8f5b3c546 391 * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and
lixianyu 0:a4d8f5b3c546 392 * 58 of this document.
lixianyu 0:a4d8f5b3c546 393 *
lixianyu 0:a4d8f5b3c546 394 * @return Current free-fall acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 395 * @see MPU6050_RA_FF_THR
lixianyu 0:a4d8f5b3c546 396 */
lixianyu 0:a4d8f5b3c546 397 uint8_t MPU6050::getFreefallDetectionThreshold() {
lixianyu 0:a4d8f5b3c546 398 I2Cdev::readByte(devAddr, MPU6050_RA_FF_THR, buffer);
lixianyu 0:a4d8f5b3c546 399 return buffer[0];
lixianyu 0:a4d8f5b3c546 400 }
lixianyu 0:a4d8f5b3c546 401 /** Get free-fall event acceleration threshold.
lixianyu 0:a4d8f5b3c546 402 * @param threshold New free-fall acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 403 * @see getFreefallDetectionThreshold()
lixianyu 0:a4d8f5b3c546 404 * @see MPU6050_RA_FF_THR
lixianyu 0:a4d8f5b3c546 405 */
lixianyu 0:a4d8f5b3c546 406 void MPU6050::setFreefallDetectionThreshold(uint8_t threshold) {
lixianyu 0:a4d8f5b3c546 407 I2Cdev::writeByte(devAddr, MPU6050_RA_FF_THR, threshold);
lixianyu 0:a4d8f5b3c546 408 }
lixianyu 0:a4d8f5b3c546 409
lixianyu 0:a4d8f5b3c546 410 // FF_DUR register
lixianyu 0:a4d8f5b3c546 411
lixianyu 0:a4d8f5b3c546 412 /** Get free-fall event duration threshold.
lixianyu 0:a4d8f5b3c546 413 * This register configures the duration counter threshold for Free Fall event
lixianyu 0:a4d8f5b3c546 414 * detection. The duration counter ticks at 1kHz, therefore FF_DUR has a unit
lixianyu 0:a4d8f5b3c546 415 * of 1 LSB = 1 ms.
lixianyu 0:a4d8f5b3c546 416 *
lixianyu 0:a4d8f5b3c546 417 * The Free Fall duration counter increments while the absolute value of the
lixianyu 0:a4d8f5b3c546 418 * accelerometer measurements are each less than the detection threshold
lixianyu 0:a4d8f5b3c546 419 * (Register 29). The Free Fall interrupt is triggered when the Free Fall
lixianyu 0:a4d8f5b3c546 420 * duration counter reaches the time specified in this register.
lixianyu 0:a4d8f5b3c546 421 *
lixianyu 0:a4d8f5b3c546 422 * For more details on the Free Fall detection interrupt, see Section 8.2 of
lixianyu 0:a4d8f5b3c546 423 * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56
lixianyu 0:a4d8f5b3c546 424 * and 58 of this document.
lixianyu 0:a4d8f5b3c546 425 *
lixianyu 0:a4d8f5b3c546 426 * @return Current free-fall duration threshold value (LSB = 1ms)
lixianyu 0:a4d8f5b3c546 427 * @see MPU6050_RA_FF_DUR
lixianyu 0:a4d8f5b3c546 428 */
lixianyu 0:a4d8f5b3c546 429 uint8_t MPU6050::getFreefallDetectionDuration() {
lixianyu 0:a4d8f5b3c546 430 I2Cdev::readByte(devAddr, MPU6050_RA_FF_DUR, buffer);
lixianyu 0:a4d8f5b3c546 431 return buffer[0];
lixianyu 0:a4d8f5b3c546 432 }
lixianyu 0:a4d8f5b3c546 433 /** Get free-fall event duration threshold.
lixianyu 0:a4d8f5b3c546 434 * @param duration New free-fall duration threshold value (LSB = 1ms)
lixianyu 0:a4d8f5b3c546 435 * @see getFreefallDetectionDuration()
lixianyu 0:a4d8f5b3c546 436 * @see MPU6050_RA_FF_DUR
lixianyu 0:a4d8f5b3c546 437 */
lixianyu 0:a4d8f5b3c546 438 void MPU6050::setFreefallDetectionDuration(uint8_t duration) {
lixianyu 0:a4d8f5b3c546 439 I2Cdev::writeByte(devAddr, MPU6050_RA_FF_DUR, duration);
lixianyu 0:a4d8f5b3c546 440 }
lixianyu 0:a4d8f5b3c546 441
lixianyu 0:a4d8f5b3c546 442 // MOT_THR register
lixianyu 0:a4d8f5b3c546 443
lixianyu 0:a4d8f5b3c546 444 /** Get motion detection event acceleration threshold.
lixianyu 0:a4d8f5b3c546 445 * This register configures the detection threshold for Motion interrupt
lixianyu 0:a4d8f5b3c546 446 * generation. The unit of MOT_THR is 1LSB = 2mg. Motion is detected when the
lixianyu 0:a4d8f5b3c546 447 * absolute value of any of the accelerometer measurements exceeds this Motion
lixianyu 0:a4d8f5b3c546 448 * detection threshold. This condition increments the Motion detection duration
lixianyu 0:a4d8f5b3c546 449 * counter (Register 32). The Motion detection interrupt is triggered when the
lixianyu 0:a4d8f5b3c546 450 * Motion Detection counter reaches the time count specified in MOT_DUR
lixianyu 0:a4d8f5b3c546 451 * (Register 32).
lixianyu 0:a4d8f5b3c546 452 *
lixianyu 0:a4d8f5b3c546 453 * The Motion interrupt will indicate the axis and polarity of detected motion
lixianyu 0:a4d8f5b3c546 454 * in MOT_DETECT_STATUS (Register 97).
lixianyu 0:a4d8f5b3c546 455 *
lixianyu 0:a4d8f5b3c546 456 * For more details on the Motion detection interrupt, see Section 8.3 of the
lixianyu 0:a4d8f5b3c546 457 * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and
lixianyu 0:a4d8f5b3c546 458 * 58 of this document.
lixianyu 0:a4d8f5b3c546 459 *
lixianyu 0:a4d8f5b3c546 460 * @return Current motion detection acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 461 * @see MPU6050_RA_MOT_THR
lixianyu 0:a4d8f5b3c546 462 */
lixianyu 0:a4d8f5b3c546 463 uint8_t MPU6050::getMotionDetectionThreshold() {
lixianyu 0:a4d8f5b3c546 464 I2Cdev::readByte(devAddr, MPU6050_RA_MOT_THR, buffer);
lixianyu 0:a4d8f5b3c546 465 return buffer[0];
lixianyu 0:a4d8f5b3c546 466 }
lixianyu 0:a4d8f5b3c546 467 /** Set free-fall event acceleration threshold.
lixianyu 0:a4d8f5b3c546 468 * @param threshold New motion detection acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 469 * @see getMotionDetectionThreshold()
lixianyu 0:a4d8f5b3c546 470 * @see MPU6050_RA_MOT_THR
lixianyu 0:a4d8f5b3c546 471 */
lixianyu 0:a4d8f5b3c546 472 void MPU6050::setMotionDetectionThreshold(uint8_t threshold) {
lixianyu 0:a4d8f5b3c546 473 I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_THR, threshold);
lixianyu 0:a4d8f5b3c546 474 }
lixianyu 0:a4d8f5b3c546 475
lixianyu 0:a4d8f5b3c546 476 // MOT_DUR register
lixianyu 0:a4d8f5b3c546 477
lixianyu 0:a4d8f5b3c546 478 /** Get motion detection event duration threshold.
lixianyu 0:a4d8f5b3c546 479 * This register configures the duration counter threshold for Motion interrupt
lixianyu 0:a4d8f5b3c546 480 * generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit
lixianyu 0:a4d8f5b3c546 481 * of 1LSB = 1ms. The Motion detection duration counter increments when the
lixianyu 0:a4d8f5b3c546 482 * absolute value of any of the accelerometer measurements exceeds the Motion
lixianyu 0:a4d8f5b3c546 483 * detection threshold (Register 31). The Motion detection interrupt is
lixianyu 0:a4d8f5b3c546 484 * triggered when the Motion detection counter reaches the time count specified
lixianyu 0:a4d8f5b3c546 485 * in this register.
lixianyu 0:a4d8f5b3c546 486 *
lixianyu 0:a4d8f5b3c546 487 * For more details on the Motion detection interrupt, see Section 8.3 of the
lixianyu 0:a4d8f5b3c546 488 * MPU-6000/MPU-6050 Product Specification document.
lixianyu 0:a4d8f5b3c546 489 *
lixianyu 0:a4d8f5b3c546 490 * @return Current motion detection duration threshold value (LSB = 1ms)
lixianyu 0:a4d8f5b3c546 491 * @see MPU6050_RA_MOT_DUR
lixianyu 0:a4d8f5b3c546 492 */
lixianyu 0:a4d8f5b3c546 493 uint8_t MPU6050::getMotionDetectionDuration() {
lixianyu 0:a4d8f5b3c546 494 I2Cdev::readByte(devAddr, MPU6050_RA_MOT_DUR, buffer);
lixianyu 0:a4d8f5b3c546 495 return buffer[0];
lixianyu 0:a4d8f5b3c546 496 }
lixianyu 0:a4d8f5b3c546 497 /** Set motion detection event duration threshold.
lixianyu 0:a4d8f5b3c546 498 * @param duration New motion detection duration threshold value (LSB = 1ms)
lixianyu 0:a4d8f5b3c546 499 * @see getMotionDetectionDuration()
lixianyu 0:a4d8f5b3c546 500 * @see MPU6050_RA_MOT_DUR
lixianyu 0:a4d8f5b3c546 501 */
lixianyu 0:a4d8f5b3c546 502 void MPU6050::setMotionDetectionDuration(uint8_t duration) {
lixianyu 0:a4d8f5b3c546 503 I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_DUR, duration);
lixianyu 0:a4d8f5b3c546 504 }
lixianyu 0:a4d8f5b3c546 505
lixianyu 0:a4d8f5b3c546 506 // ZRMOT_THR register
lixianyu 0:a4d8f5b3c546 507
lixianyu 0:a4d8f5b3c546 508 /** Get zero motion detection event acceleration threshold.
lixianyu 0:a4d8f5b3c546 509 * This register configures the detection threshold for Zero Motion interrupt
lixianyu 0:a4d8f5b3c546 510 * generation. The unit of ZRMOT_THR is 1LSB = 2mg. Zero Motion is detected when
lixianyu 0:a4d8f5b3c546 511 * the absolute value of the accelerometer measurements for the 3 axes are each
lixianyu 0:a4d8f5b3c546 512 * less than the detection threshold. This condition increments the Zero Motion
lixianyu 0:a4d8f5b3c546 513 * duration counter (Register 34). The Zero Motion interrupt is triggered when
lixianyu 0:a4d8f5b3c546 514 * the Zero Motion duration counter reaches the time count specified in
lixianyu 0:a4d8f5b3c546 515 * ZRMOT_DUR (Register 34).
lixianyu 0:a4d8f5b3c546 516 *
lixianyu 0:a4d8f5b3c546 517 * Unlike Free Fall or Motion detection, Zero Motion detection triggers an
lixianyu 0:a4d8f5b3c546 518 * interrupt both when Zero Motion is first detected and when Zero Motion is no
lixianyu 0:a4d8f5b3c546 519 * longer detected.
lixianyu 0:a4d8f5b3c546 520 *
lixianyu 0:a4d8f5b3c546 521 * When a zero motion event is detected, a Zero Motion Status will be indicated
lixianyu 0:a4d8f5b3c546 522 * in the MOT_DETECT_STATUS register (Register 97). When a motion-to-zero-motion
lixianyu 0:a4d8f5b3c546 523 * condition is detected, the status bit is set to 1. When a zero-motion-to-
lixianyu 0:a4d8f5b3c546 524 * motion condition is detected, the status bit is set to 0.
lixianyu 0:a4d8f5b3c546 525 *
lixianyu 0:a4d8f5b3c546 526 * For more details on the Zero Motion detection interrupt, see Section 8.4 of
lixianyu 0:a4d8f5b3c546 527 * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56
lixianyu 0:a4d8f5b3c546 528 * and 58 of this document.
lixianyu 0:a4d8f5b3c546 529 *
lixianyu 0:a4d8f5b3c546 530 * @return Current zero motion detection acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 531 * @see MPU6050_RA_ZRMOT_THR
lixianyu 0:a4d8f5b3c546 532 */
lixianyu 0:a4d8f5b3c546 533 uint8_t MPU6050::getZeroMotionDetectionThreshold() {
lixianyu 0:a4d8f5b3c546 534 I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_THR, buffer);
lixianyu 0:a4d8f5b3c546 535 return buffer[0];
lixianyu 0:a4d8f5b3c546 536 }
lixianyu 0:a4d8f5b3c546 537 /** Set zero motion detection event acceleration threshold.
lixianyu 0:a4d8f5b3c546 538 * @param threshold New zero motion detection acceleration threshold value (LSB = 2mg)
lixianyu 0:a4d8f5b3c546 539 * @see getZeroMotionDetectionThreshold()
lixianyu 0:a4d8f5b3c546 540 * @see MPU6050_RA_ZRMOT_THR
lixianyu 0:a4d8f5b3c546 541 */
lixianyu 0:a4d8f5b3c546 542 void MPU6050::setZeroMotionDetectionThreshold(uint8_t threshold) {
lixianyu 0:a4d8f5b3c546 543 I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_THR, threshold);
lixianyu 0:a4d8f5b3c546 544 }
lixianyu 0:a4d8f5b3c546 545
lixianyu 0:a4d8f5b3c546 546 // ZRMOT_DUR register
lixianyu 0:a4d8f5b3c546 547
lixianyu 0:a4d8f5b3c546 548 /** Get zero motion detection event duration threshold.
lixianyu 0:a4d8f5b3c546 549 * This register configures the duration counter threshold for Zero Motion
lixianyu 0:a4d8f5b3c546 550 * interrupt generation. The duration counter ticks at 16 Hz, therefore
lixianyu 0:a4d8f5b3c546 551 * ZRMOT_DUR has a unit of 1 LSB = 64 ms. The Zero Motion duration counter
lixianyu 0:a4d8f5b3c546 552 * increments while the absolute value of the accelerometer measurements are
lixianyu 0:a4d8f5b3c546 553 * each less than the detection threshold (Register 33). The Zero Motion
lixianyu 0:a4d8f5b3c546 554 * interrupt is triggered when the Zero Motion duration counter reaches the time
lixianyu 0:a4d8f5b3c546 555 * count specified in this register.
lixianyu 0:a4d8f5b3c546 556 *
lixianyu 0:a4d8f5b3c546 557 * For more details on the Zero Motion detection interrupt, see Section 8.4 of
lixianyu 0:a4d8f5b3c546 558 * the MPU-6000/MPU-6050 Product Specification document, as well as Registers 56
lixianyu 0:a4d8f5b3c546 559 * and 58 of this document.
lixianyu 0:a4d8f5b3c546 560 *
lixianyu 0:a4d8f5b3c546 561 * @return Current zero motion detection duration threshold value (LSB = 64ms)
lixianyu 0:a4d8f5b3c546 562 * @see MPU6050_RA_ZRMOT_DUR
lixianyu 0:a4d8f5b3c546 563 */
lixianyu 0:a4d8f5b3c546 564 uint8_t MPU6050::getZeroMotionDetectionDuration() {
lixianyu 0:a4d8f5b3c546 565 I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_DUR, buffer);
lixianyu 0:a4d8f5b3c546 566 return buffer[0];
lixianyu 0:a4d8f5b3c546 567 }
lixianyu 0:a4d8f5b3c546 568 /** Set zero motion detection event duration threshold.
lixianyu 0:a4d8f5b3c546 569 * @param duration New zero motion detection duration threshold value (LSB = 1ms)
lixianyu 0:a4d8f5b3c546 570 * @see getZeroMotionDetectionDuration()
lixianyu 0:a4d8f5b3c546 571 * @see MPU6050_RA_ZRMOT_DUR
lixianyu 0:a4d8f5b3c546 572 */
lixianyu 0:a4d8f5b3c546 573 void MPU6050::setZeroMotionDetectionDuration(uint8_t duration) {
lixianyu 0:a4d8f5b3c546 574 I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_DUR, duration);
lixianyu 0:a4d8f5b3c546 575 }
lixianyu 0:a4d8f5b3c546 576
lixianyu 0:a4d8f5b3c546 577 // FIFO_EN register
lixianyu 0:a4d8f5b3c546 578
lixianyu 0:a4d8f5b3c546 579 /** Get temperature FIFO enabled value.
lixianyu 0:a4d8f5b3c546 580 * When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and
lixianyu 0:a4d8f5b3c546 581 * 66) to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 582 * @return Current temperature FIFO enabled value
lixianyu 0:a4d8f5b3c546 583 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 584 */
lixianyu 0:a4d8f5b3c546 585 bool MPU6050::getTempFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 586 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 587 return buffer[0];
lixianyu 0:a4d8f5b3c546 588 }
lixianyu 0:a4d8f5b3c546 589 /** Set temperature FIFO enabled value.
lixianyu 0:a4d8f5b3c546 590 * @param enabled New temperature FIFO enabled value
lixianyu 0:a4d8f5b3c546 591 * @see getTempFIFOEnabled()
lixianyu 0:a4d8f5b3c546 592 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 593 */
lixianyu 0:a4d8f5b3c546 594 void MPU6050::setTempFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 595 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 596 }
lixianyu 0:a4d8f5b3c546 597 /** Get gyroscope X-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 598 * When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L (Registers 67 and
lixianyu 0:a4d8f5b3c546 599 * 68) to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 600 * @return Current gyroscope X-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 601 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 602 */
lixianyu 0:a4d8f5b3c546 603 bool MPU6050::getXGyroFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 604 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 605 return buffer[0];
lixianyu 0:a4d8f5b3c546 606 }
lixianyu 0:a4d8f5b3c546 607 /** Set gyroscope X-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 608 * @param enabled New gyroscope X-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 609 * @see getXGyroFIFOEnabled()
lixianyu 0:a4d8f5b3c546 610 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 611 */
lixianyu 0:a4d8f5b3c546 612 void MPU6050::setXGyroFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 613 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 614 }
lixianyu 0:a4d8f5b3c546 615 /** Get gyroscope Y-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 616 * When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and
lixianyu 0:a4d8f5b3c546 617 * 70) to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 618 * @return Current gyroscope Y-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 619 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 620 */
lixianyu 0:a4d8f5b3c546 621 bool MPU6050::getYGyroFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 622 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 623 return buffer[0];
lixianyu 0:a4d8f5b3c546 624 }
lixianyu 0:a4d8f5b3c546 625 /** Set gyroscope Y-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 626 * @param enabled New gyroscope Y-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 627 * @see getYGyroFIFOEnabled()
lixianyu 0:a4d8f5b3c546 628 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 629 */
lixianyu 0:a4d8f5b3c546 630 void MPU6050::setYGyroFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 631 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 632 }
lixianyu 0:a4d8f5b3c546 633 /** Get gyroscope Z-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 634 * When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and
lixianyu 0:a4d8f5b3c546 635 * 72) to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 636 * @return Current gyroscope Z-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 637 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 638 */
lixianyu 0:a4d8f5b3c546 639 bool MPU6050::getZGyroFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 640 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 641 return buffer[0];
lixianyu 0:a4d8f5b3c546 642 }
lixianyu 0:a4d8f5b3c546 643 /** Set gyroscope Z-axis FIFO enabled value.
lixianyu 0:a4d8f5b3c546 644 * @param enabled New gyroscope Z-axis FIFO enabled value
lixianyu 0:a4d8f5b3c546 645 * @see getZGyroFIFOEnabled()
lixianyu 0:a4d8f5b3c546 646 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 647 */
lixianyu 0:a4d8f5b3c546 648 void MPU6050::setZGyroFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 649 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 650 }
lixianyu 0:a4d8f5b3c546 651 /** Get accelerometer FIFO enabled value.
lixianyu 0:a4d8f5b3c546 652 * When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H,
lixianyu 0:a4d8f5b3c546 653 * ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be
lixianyu 0:a4d8f5b3c546 654 * written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 655 * @return Current accelerometer FIFO enabled value
lixianyu 0:a4d8f5b3c546 656 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 657 */
lixianyu 0:a4d8f5b3c546 658 bool MPU6050::getAccelFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 659 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 660 return buffer[0];
lixianyu 0:a4d8f5b3c546 661 }
lixianyu 0:a4d8f5b3c546 662 /** Set accelerometer FIFO enabled value.
lixianyu 0:a4d8f5b3c546 663 * @param enabled New accelerometer FIFO enabled value
lixianyu 0:a4d8f5b3c546 664 * @see getAccelFIFOEnabled()
lixianyu 0:a4d8f5b3c546 665 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 666 */
lixianyu 0:a4d8f5b3c546 667 void MPU6050::setAccelFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 668 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 669 }
lixianyu 0:a4d8f5b3c546 670 /** Get Slave 2 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 671 * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)
lixianyu 0:a4d8f5b3c546 672 * associated with Slave 2 to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 673 * @return Current Slave 2 FIFO enabled value
lixianyu 0:a4d8f5b3c546 674 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 675 */
lixianyu 0:a4d8f5b3c546 676 bool MPU6050::getSlave2FIFOEnabled() {
lixianyu 0:a4d8f5b3c546 677 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 678 return buffer[0];
lixianyu 0:a4d8f5b3c546 679 }
lixianyu 0:a4d8f5b3c546 680 /** Set Slave 2 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 681 * @param enabled New Slave 2 FIFO enabled value
lixianyu 0:a4d8f5b3c546 682 * @see getSlave2FIFOEnabled()
lixianyu 0:a4d8f5b3c546 683 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 684 */
lixianyu 0:a4d8f5b3c546 685 void MPU6050::setSlave2FIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 686 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 687 }
lixianyu 0:a4d8f5b3c546 688 /** Get Slave 1 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 689 * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)
lixianyu 0:a4d8f5b3c546 690 * associated with Slave 1 to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 691 * @return Current Slave 1 FIFO enabled value
lixianyu 0:a4d8f5b3c546 692 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 693 */
lixianyu 0:a4d8f5b3c546 694 bool MPU6050::getSlave1FIFOEnabled() {
lixianyu 0:a4d8f5b3c546 695 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 696 return buffer[0];
lixianyu 0:a4d8f5b3c546 697 }
lixianyu 0:a4d8f5b3c546 698 /** Set Slave 1 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 699 * @param enabled New Slave 1 FIFO enabled value
lixianyu 0:a4d8f5b3c546 700 * @see getSlave1FIFOEnabled()
lixianyu 0:a4d8f5b3c546 701 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 702 */
lixianyu 0:a4d8f5b3c546 703 void MPU6050::setSlave1FIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 704 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 705 }
lixianyu 0:a4d8f5b3c546 706 /** Get Slave 0 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 707 * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)
lixianyu 0:a4d8f5b3c546 708 * associated with Slave 0 to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 709 * @return Current Slave 0 FIFO enabled value
lixianyu 0:a4d8f5b3c546 710 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 711 */
lixianyu 0:a4d8f5b3c546 712 bool MPU6050::getSlave0FIFOEnabled() {
lixianyu 0:a4d8f5b3c546 713 I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 714 return buffer[0];
lixianyu 0:a4d8f5b3c546 715 }
lixianyu 0:a4d8f5b3c546 716 /** Set Slave 0 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 717 * @param enabled New Slave 0 FIFO enabled value
lixianyu 0:a4d8f5b3c546 718 * @see getSlave0FIFOEnabled()
lixianyu 0:a4d8f5b3c546 719 * @see MPU6050_RA_FIFO_EN
lixianyu 0:a4d8f5b3c546 720 */
lixianyu 0:a4d8f5b3c546 721 void MPU6050::setSlave0FIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 722 I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 723 }
lixianyu 0:a4d8f5b3c546 724
lixianyu 0:a4d8f5b3c546 725 // I2C_MST_CTRL register
lixianyu 0:a4d8f5b3c546 726
lixianyu 0:a4d8f5b3c546 727 /** Get multi-master enabled value.
lixianyu 0:a4d8f5b3c546 728 * Multi-master capability allows multiple I2C masters to operate on the same
lixianyu 0:a4d8f5b3c546 729 * bus. In circuits where multi-master capability is required, set MULT_MST_EN
lixianyu 0:a4d8f5b3c546 730 * to 1. This will increase current drawn by approximately 30uA.
lixianyu 0:a4d8f5b3c546 731 *
lixianyu 0:a4d8f5b3c546 732 * In circuits where multi-master capability is required, the state of the I2C
lixianyu 0:a4d8f5b3c546 733 * bus must always be monitored by each separate I2C Master. Before an I2C
lixianyu 0:a4d8f5b3c546 734 * Master can assume arbitration of the bus, it must first confirm that no other
lixianyu 0:a4d8f5b3c546 735 * I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the
lixianyu 0:a4d8f5b3c546 736 * MPU-60X0's bus arbitration detection logic is turned on, enabling it to
lixianyu 0:a4d8f5b3c546 737 * detect when the bus is available.
lixianyu 0:a4d8f5b3c546 738 *
lixianyu 0:a4d8f5b3c546 739 * @return Current multi-master enabled value
lixianyu 0:a4d8f5b3c546 740 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 741 */
lixianyu 0:a4d8f5b3c546 742 bool MPU6050::getMultiMasterEnabled() {
lixianyu 0:a4d8f5b3c546 743 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 744 return buffer[0];
lixianyu 0:a4d8f5b3c546 745 }
lixianyu 0:a4d8f5b3c546 746 /** Set multi-master enabled value.
lixianyu 0:a4d8f5b3c546 747 * @param enabled New multi-master enabled value
lixianyu 0:a4d8f5b3c546 748 * @see getMultiMasterEnabled()
lixianyu 0:a4d8f5b3c546 749 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 750 */
lixianyu 0:a4d8f5b3c546 751 void MPU6050::setMultiMasterEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 752 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 753 }
lixianyu 0:a4d8f5b3c546 754 /** Get wait-for-external-sensor-data enabled value.
lixianyu 0:a4d8f5b3c546 755 * When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be
lixianyu 0:a4d8f5b3c546 756 * delayed until External Sensor data from the Slave Devices are loaded into the
lixianyu 0:a4d8f5b3c546 757 * EXT_SENS_DATA registers. This is used to ensure that both the internal sensor
lixianyu 0:a4d8f5b3c546 758 * data (i.e. from gyro and accel) and external sensor data have been loaded to
lixianyu 0:a4d8f5b3c546 759 * their respective data registers (i.e. the data is synced) when the Data Ready
lixianyu 0:a4d8f5b3c546 760 * interrupt is triggered.
lixianyu 0:a4d8f5b3c546 761 *
lixianyu 0:a4d8f5b3c546 762 * @return Current wait-for-external-sensor-data enabled value
lixianyu 0:a4d8f5b3c546 763 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 764 */
lixianyu 0:a4d8f5b3c546 765 bool MPU6050::getWaitForExternalSensorEnabled() {
lixianyu 0:a4d8f5b3c546 766 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, buffer);
lixianyu 0:a4d8f5b3c546 767 return buffer[0];
lixianyu 0:a4d8f5b3c546 768 }
lixianyu 0:a4d8f5b3c546 769 /** Set wait-for-external-sensor-data enabled value.
lixianyu 0:a4d8f5b3c546 770 * @param enabled New wait-for-external-sensor-data enabled value
lixianyu 0:a4d8f5b3c546 771 * @see getWaitForExternalSensorEnabled()
lixianyu 0:a4d8f5b3c546 772 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 773 */
lixianyu 0:a4d8f5b3c546 774 void MPU6050::setWaitForExternalSensorEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 775 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, enabled);
lixianyu 0:a4d8f5b3c546 776 }
lixianyu 0:a4d8f5b3c546 777 /** Get Slave 3 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 778 * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)
lixianyu 0:a4d8f5b3c546 779 * associated with Slave 3 to be written into the FIFO buffer.
lixianyu 0:a4d8f5b3c546 780 * @return Current Slave 3 FIFO enabled value
lixianyu 0:a4d8f5b3c546 781 * @see MPU6050_RA_MST_CTRL
lixianyu 0:a4d8f5b3c546 782 */
lixianyu 0:a4d8f5b3c546 783 bool MPU6050::getSlave3FIFOEnabled() {
lixianyu 0:a4d8f5b3c546 784 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 785 return buffer[0];
lixianyu 0:a4d8f5b3c546 786 }
lixianyu 0:a4d8f5b3c546 787 /** Set Slave 3 FIFO enabled value.
lixianyu 0:a4d8f5b3c546 788 * @param enabled New Slave 3 FIFO enabled value
lixianyu 0:a4d8f5b3c546 789 * @see getSlave3FIFOEnabled()
lixianyu 0:a4d8f5b3c546 790 * @see MPU6050_RA_MST_CTRL
lixianyu 0:a4d8f5b3c546 791 */
lixianyu 0:a4d8f5b3c546 792 void MPU6050::setSlave3FIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 793 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 794 }
lixianyu 0:a4d8f5b3c546 795 /** Get slave read/write transition enabled value.
lixianyu 0:a4d8f5b3c546 796 * The I2C_MST_P_NSR bit configures the I2C Master's transition from one slave
lixianyu 0:a4d8f5b3c546 797 * read to the next slave read. If the bit equals 0, there will be a restart
lixianyu 0:a4d8f5b3c546 798 * between reads. If the bit equals 1, there will be a stop followed by a start
lixianyu 0:a4d8f5b3c546 799 * of the following read. When a write transaction follows a read transaction,
lixianyu 0:a4d8f5b3c546 800 * the stop followed by a start of the successive write will be always used.
lixianyu 0:a4d8f5b3c546 801 *
lixianyu 0:a4d8f5b3c546 802 * @return Current slave read/write transition enabled value
lixianyu 0:a4d8f5b3c546 803 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 804 */
lixianyu 0:a4d8f5b3c546 805 bool MPU6050::getSlaveReadWriteTransitionEnabled() {
lixianyu 0:a4d8f5b3c546 806 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, buffer);
lixianyu 0:a4d8f5b3c546 807 return buffer[0];
lixianyu 0:a4d8f5b3c546 808 }
lixianyu 0:a4d8f5b3c546 809 /** Set slave read/write transition enabled value.
lixianyu 0:a4d8f5b3c546 810 * @param enabled New slave read/write transition enabled value
lixianyu 0:a4d8f5b3c546 811 * @see getSlaveReadWriteTransitionEnabled()
lixianyu 0:a4d8f5b3c546 812 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 813 */
lixianyu 0:a4d8f5b3c546 814 void MPU6050::setSlaveReadWriteTransitionEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 815 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, enabled);
lixianyu 0:a4d8f5b3c546 816 }
lixianyu 0:a4d8f5b3c546 817 /** Get I2C master clock speed.
lixianyu 0:a4d8f5b3c546 818 * I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the
lixianyu 0:a4d8f5b3c546 819 * MPU-60X0 internal 8MHz clock. It sets the I2C master clock speed according to
lixianyu 0:a4d8f5b3c546 820 * the following table:
lixianyu 0:a4d8f5b3c546 821 *
lixianyu 0:a4d8f5b3c546 822 * <pre>
lixianyu 0:a4d8f5b3c546 823 * I2C_MST_CLK | I2C Master Clock Speed | 8MHz Clock Divider
lixianyu 0:a4d8f5b3c546 824 * ------------+------------------------+-------------------
lixianyu 0:a4d8f5b3c546 825 * 0 | 348kHz | 23
lixianyu 0:a4d8f5b3c546 826 * 1 | 333kHz | 24
lixianyu 0:a4d8f5b3c546 827 * 2 | 320kHz | 25
lixianyu 0:a4d8f5b3c546 828 * 3 | 308kHz | 26
lixianyu 0:a4d8f5b3c546 829 * 4 | 296kHz | 27
lixianyu 0:a4d8f5b3c546 830 * 5 | 286kHz | 28
lixianyu 0:a4d8f5b3c546 831 * 6 | 276kHz | 29
lixianyu 0:a4d8f5b3c546 832 * 7 | 267kHz | 30
lixianyu 0:a4d8f5b3c546 833 * 8 | 258kHz | 31
lixianyu 0:a4d8f5b3c546 834 * 9 | 500kHz | 16
lixianyu 0:a4d8f5b3c546 835 * 10 | 471kHz | 17
lixianyu 0:a4d8f5b3c546 836 * 11 | 444kHz | 18
lixianyu 0:a4d8f5b3c546 837 * 12 | 421kHz | 19
lixianyu 0:a4d8f5b3c546 838 * 13 | 400kHz | 20
lixianyu 0:a4d8f5b3c546 839 * 14 | 381kHz | 21
lixianyu 0:a4d8f5b3c546 840 * 15 | 364kHz | 22
lixianyu 0:a4d8f5b3c546 841 * </pre>
lixianyu 0:a4d8f5b3c546 842 *
lixianyu 0:a4d8f5b3c546 843 * @return Current I2C master clock speed
lixianyu 0:a4d8f5b3c546 844 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 845 */
lixianyu 0:a4d8f5b3c546 846 uint8_t MPU6050::getMasterClockSpeed() {
lixianyu 0:a4d8f5b3c546 847 I2Cdev::readBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 848 return buffer[0];
lixianyu 0:a4d8f5b3c546 849 }
lixianyu 0:a4d8f5b3c546 850 /** Set I2C master clock speed.
lixianyu 0:a4d8f5b3c546 851 * @reparam speed Current I2C master clock speed
lixianyu 0:a4d8f5b3c546 852 * @see MPU6050_RA_I2C_MST_CTRL
lixianyu 0:a4d8f5b3c546 853 */
lixianyu 0:a4d8f5b3c546 854 void MPU6050::setMasterClockSpeed(uint8_t speed) {
lixianyu 0:a4d8f5b3c546 855 I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, speed);
lixianyu 0:a4d8f5b3c546 856 }
lixianyu 0:a4d8f5b3c546 857
lixianyu 0:a4d8f5b3c546 858 // I2C_SLV* registers (Slave 0-3)
lixianyu 0:a4d8f5b3c546 859
lixianyu 0:a4d8f5b3c546 860 /** Get the I2C address of the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 861 * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read
lixianyu 0:a4d8f5b3c546 862 * operation, and if it is cleared, then it's a write operation. The remaining
lixianyu 0:a4d8f5b3c546 863 * bits (6-0) are the 7-bit device address of the slave device.
lixianyu 0:a4d8f5b3c546 864 *
lixianyu 0:a4d8f5b3c546 865 * In read mode, the result of the read is placed in the lowest available
lixianyu 0:a4d8f5b3c546 866 * EXT_SENS_DATA register. For further information regarding the allocation of
lixianyu 0:a4d8f5b3c546 867 * read results, please refer to the EXT_SENS_DATA register description
lixianyu 0:a4d8f5b3c546 868 * (Registers 73 - 96).
lixianyu 0:a4d8f5b3c546 869 *
lixianyu 0:a4d8f5b3c546 870 * The MPU-6050 supports a total of five slaves, but Slave 4 has unique
lixianyu 0:a4d8f5b3c546 871 * characteristics, and so it has its own functions (getSlave4* and setSlave4*).
lixianyu 0:a4d8f5b3c546 872 *
lixianyu 0:a4d8f5b3c546 873 * I2C data transactions are performed at the Sample Rate, as defined in
lixianyu 0:a4d8f5b3c546 874 * Register 25. The user is responsible for ensuring that I2C data transactions
lixianyu 0:a4d8f5b3c546 875 * to and from each enabled Slave can be completed within a single period of the
lixianyu 0:a4d8f5b3c546 876 * Sample Rate.
lixianyu 0:a4d8f5b3c546 877 *
lixianyu 0:a4d8f5b3c546 878 * The I2C slave access rate can be reduced relative to the Sample Rate. This
lixianyu 0:a4d8f5b3c546 879 * reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a
lixianyu 0:a4d8f5b3c546 880 * slave's access rate is reduced relative to the Sample Rate is determined by
lixianyu 0:a4d8f5b3c546 881 * I2C_MST_DELAY_CTRL (Register 103).
lixianyu 0:a4d8f5b3c546 882 *
lixianyu 0:a4d8f5b3c546 883 * The processing order for the slaves is fixed. The sequence followed for
lixianyu 0:a4d8f5b3c546 884 * processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a
lixianyu 0:a4d8f5b3c546 885 * particular Slave is disabled it will be skipped.
lixianyu 0:a4d8f5b3c546 886 *
lixianyu 0:a4d8f5b3c546 887 * Each slave can either be accessed at the sample rate or at a reduced sample
lixianyu 0:a4d8f5b3c546 888 * rate. In a case where some slaves are accessed at the Sample Rate and some
lixianyu 0:a4d8f5b3c546 889 * slaves are accessed at the reduced rate, the sequence of accessing the slaves
lixianyu 0:a4d8f5b3c546 890 * (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will
lixianyu 0:a4d8f5b3c546 891 * be skipped if their access rate dictates that they should not be accessed
lixianyu 0:a4d8f5b3c546 892 * during that particular cycle. For further information regarding the reduced
lixianyu 0:a4d8f5b3c546 893 * access rate, please refer to Register 52. Whether a slave is accessed at the
lixianyu 0:a4d8f5b3c546 894 * Sample Rate or at the reduced rate is determined by the Delay Enable bits in
lixianyu 0:a4d8f5b3c546 895 * Register 103.
lixianyu 0:a4d8f5b3c546 896 *
lixianyu 0:a4d8f5b3c546 897 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 898 * @return Current address for specified slave
lixianyu 0:a4d8f5b3c546 899 * @see MPU6050_RA_I2C_SLV0_ADDR
lixianyu 0:a4d8f5b3c546 900 */
lixianyu 0:a4d8f5b3c546 901 uint8_t MPU6050::getSlaveAddress(uint8_t num) {
lixianyu 0:a4d8f5b3c546 902 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 903 I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, buffer);
lixianyu 0:a4d8f5b3c546 904 return buffer[0];
lixianyu 0:a4d8f5b3c546 905 }
lixianyu 0:a4d8f5b3c546 906 /** Set the I2C address of the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 907 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 908 * @param address New address for specified slave
lixianyu 0:a4d8f5b3c546 909 * @see getSlaveAddress()
lixianyu 0:a4d8f5b3c546 910 * @see MPU6050_RA_I2C_SLV0_ADDR
lixianyu 0:a4d8f5b3c546 911 */
lixianyu 0:a4d8f5b3c546 912 void MPU6050::setSlaveAddress(uint8_t num, uint8_t address) {
lixianyu 0:a4d8f5b3c546 913 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 914 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, address);
lixianyu 0:a4d8f5b3c546 915 }
lixianyu 0:a4d8f5b3c546 916 /** Get the active internal register for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 917 * Read/write operations for this slave will be done to whatever internal
lixianyu 0:a4d8f5b3c546 918 * register address is stored in this MPU register.
lixianyu 0:a4d8f5b3c546 919 *
lixianyu 0:a4d8f5b3c546 920 * The MPU-6050 supports a total of five slaves, but Slave 4 has unique
lixianyu 0:a4d8f5b3c546 921 * characteristics, and so it has its own functions.
lixianyu 0:a4d8f5b3c546 922 *
lixianyu 0:a4d8f5b3c546 923 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 924 * @return Current active register for specified slave
lixianyu 0:a4d8f5b3c546 925 * @see MPU6050_RA_I2C_SLV0_REG
lixianyu 0:a4d8f5b3c546 926 */
lixianyu 0:a4d8f5b3c546 927 uint8_t MPU6050::getSlaveRegister(uint8_t num) {
lixianyu 0:a4d8f5b3c546 928 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 929 I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, buffer);
lixianyu 0:a4d8f5b3c546 930 return buffer[0];
lixianyu 0:a4d8f5b3c546 931 }
lixianyu 0:a4d8f5b3c546 932 /** Set the active internal register for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 933 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 934 * @param reg New active register for specified slave
lixianyu 0:a4d8f5b3c546 935 * @see getSlaveRegister()
lixianyu 0:a4d8f5b3c546 936 * @see MPU6050_RA_I2C_SLV0_REG
lixianyu 0:a4d8f5b3c546 937 */
lixianyu 0:a4d8f5b3c546 938 void MPU6050::setSlaveRegister(uint8_t num, uint8_t reg) {
lixianyu 0:a4d8f5b3c546 939 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 940 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, reg);
lixianyu 0:a4d8f5b3c546 941 }
lixianyu 0:a4d8f5b3c546 942 /** Get the enabled value for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 943 * When set to 1, this bit enables Slave 0 for data transfer operations. When
lixianyu 0:a4d8f5b3c546 944 * cleared to 0, this bit disables Slave 0 from data transfer operations.
lixianyu 0:a4d8f5b3c546 945 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 946 * @return Current enabled value for specified slave
lixianyu 0:a4d8f5b3c546 947 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 948 */
lixianyu 0:a4d8f5b3c546 949 bool MPU6050::getSlaveEnabled(uint8_t num) {
lixianyu 0:a4d8f5b3c546 950 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 951 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 952 return buffer[0];
lixianyu 0:a4d8f5b3c546 953 }
lixianyu 0:a4d8f5b3c546 954 /** Set the enabled value for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 955 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 956 * @param enabled New enabled value for specified slave
lixianyu 0:a4d8f5b3c546 957 * @see getSlaveEnabled()
lixianyu 0:a4d8f5b3c546 958 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 959 */
lixianyu 0:a4d8f5b3c546 960 void MPU6050::setSlaveEnabled(uint8_t num, bool enabled) {
lixianyu 0:a4d8f5b3c546 961 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 962 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 963 }
lixianyu 0:a4d8f5b3c546 964 /** Get word pair byte-swapping enabled for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 965 * When set to 1, this bit enables byte swapping. When byte swapping is enabled,
lixianyu 0:a4d8f5b3c546 966 * the high and low bytes of a word pair are swapped. Please refer to
lixianyu 0:a4d8f5b3c546 967 * I2C_SLV0_GRP for the pairing convention of the word pairs. When cleared to 0,
lixianyu 0:a4d8f5b3c546 968 * bytes transferred to and from Slave 0 will be written to EXT_SENS_DATA
lixianyu 0:a4d8f5b3c546 969 * registers in the order they were transferred.
lixianyu 0:a4d8f5b3c546 970 *
lixianyu 0:a4d8f5b3c546 971 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 972 * @return Current word pair byte-swapping enabled value for specified slave
lixianyu 0:a4d8f5b3c546 973 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 974 */
lixianyu 0:a4d8f5b3c546 975 bool MPU6050::getSlaveWordByteSwap(uint8_t num) {
lixianyu 0:a4d8f5b3c546 976 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 977 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, buffer);
lixianyu 0:a4d8f5b3c546 978 return buffer[0];
lixianyu 0:a4d8f5b3c546 979 }
lixianyu 0:a4d8f5b3c546 980 /** Set word pair byte-swapping enabled for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 981 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 982 * @param enabled New word pair byte-swapping enabled value for specified slave
lixianyu 0:a4d8f5b3c546 983 * @see getSlaveWordByteSwap()
lixianyu 0:a4d8f5b3c546 984 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 985 */
lixianyu 0:a4d8f5b3c546 986 void MPU6050::setSlaveWordByteSwap(uint8_t num, bool enabled) {
lixianyu 0:a4d8f5b3c546 987 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 988 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, enabled);
lixianyu 0:a4d8f5b3c546 989 }
lixianyu 0:a4d8f5b3c546 990 /** Get write mode for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 991 * When set to 1, the transaction will read or write data only. When cleared to
lixianyu 0:a4d8f5b3c546 992 * 0, the transaction will write a register address prior to reading or writing
lixianyu 0:a4d8f5b3c546 993 * data. This should equal 0 when specifying the register address within the
lixianyu 0:a4d8f5b3c546 994 * Slave device to/from which the ensuing data transaction will take place.
lixianyu 0:a4d8f5b3c546 995 *
lixianyu 0:a4d8f5b3c546 996 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 997 * @return Current write mode for specified slave (0 = register address + data, 1 = data only)
lixianyu 0:a4d8f5b3c546 998 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 999 */
lixianyu 0:a4d8f5b3c546 1000 bool MPU6050::getSlaveWriteMode(uint8_t num) {
lixianyu 0:a4d8f5b3c546 1001 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 1002 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1003 return buffer[0];
lixianyu 0:a4d8f5b3c546 1004 }
lixianyu 0:a4d8f5b3c546 1005 /** Set write mode for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 1006 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 1007 * @param mode New write mode for specified slave (0 = register address + data, 1 = data only)
lixianyu 0:a4d8f5b3c546 1008 * @see getSlaveWriteMode()
lixianyu 0:a4d8f5b3c546 1009 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 1010 */
lixianyu 0:a4d8f5b3c546 1011 void MPU6050::setSlaveWriteMode(uint8_t num, bool mode) {
lixianyu 0:a4d8f5b3c546 1012 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 1013 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, mode);
lixianyu 0:a4d8f5b3c546 1014 }
lixianyu 0:a4d8f5b3c546 1015 /** Get word pair grouping order offset for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 1016 * This sets specifies the grouping order of word pairs received from registers.
lixianyu 0:a4d8f5b3c546 1017 * When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even,
lixianyu 0:a4d8f5b3c546 1018 * then odd register addresses) are paired to form a word. When set to 1, bytes
lixianyu 0:a4d8f5b3c546 1019 * from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even
lixianyu 0:a4d8f5b3c546 1020 * register addresses) are paired to form a word.
lixianyu 0:a4d8f5b3c546 1021 *
lixianyu 0:a4d8f5b3c546 1022 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 1023 * @return Current word pair grouping order offset for specified slave
lixianyu 0:a4d8f5b3c546 1024 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 1025 */
lixianyu 0:a4d8f5b3c546 1026 bool MPU6050::getSlaveWordGroupOffset(uint8_t num) {
lixianyu 0:a4d8f5b3c546 1027 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 1028 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1029 return buffer[0];
lixianyu 0:a4d8f5b3c546 1030 }
lixianyu 0:a4d8f5b3c546 1031 /** Set word pair grouping order offset for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 1032 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 1033 * @param enabled New word pair grouping order offset for specified slave
lixianyu 0:a4d8f5b3c546 1034 * @see getSlaveWordGroupOffset()
lixianyu 0:a4d8f5b3c546 1035 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 1036 */
lixianyu 0:a4d8f5b3c546 1037 void MPU6050::setSlaveWordGroupOffset(uint8_t num, bool enabled) {
lixianyu 0:a4d8f5b3c546 1038 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 1039 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1040 }
lixianyu 0:a4d8f5b3c546 1041 /** Get number of bytes to read for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 1042 * Specifies the number of bytes transferred to and from Slave 0. Clearing this
lixianyu 0:a4d8f5b3c546 1043 * bit to 0 is equivalent to disabling the register by writing 0 to I2C_SLV0_EN.
lixianyu 0:a4d8f5b3c546 1044 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 1045 * @return Number of bytes to read for specified slave
lixianyu 0:a4d8f5b3c546 1046 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 1047 */
lixianyu 0:a4d8f5b3c546 1048 uint8_t MPU6050::getSlaveDataLength(uint8_t num) {
lixianyu 0:a4d8f5b3c546 1049 if (num > 3) return 0;
lixianyu 0:a4d8f5b3c546 1050 I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 1051 return buffer[0];
lixianyu 0:a4d8f5b3c546 1052 }
lixianyu 0:a4d8f5b3c546 1053 /** Set number of bytes to read for the specified slave (0-3).
lixianyu 0:a4d8f5b3c546 1054 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 1055 * @param length Number of bytes to read for specified slave
lixianyu 0:a4d8f5b3c546 1056 * @see getSlaveDataLength()
lixianyu 0:a4d8f5b3c546 1057 * @see MPU6050_RA_I2C_SLV0_CTRL
lixianyu 0:a4d8f5b3c546 1058 */
lixianyu 0:a4d8f5b3c546 1059 void MPU6050::setSlaveDataLength(uint8_t num, uint8_t length) {
lixianyu 0:a4d8f5b3c546 1060 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 1061 I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, length);
lixianyu 0:a4d8f5b3c546 1062 }
lixianyu 0:a4d8f5b3c546 1063
lixianyu 0:a4d8f5b3c546 1064 // I2C_SLV* registers (Slave 4)
lixianyu 0:a4d8f5b3c546 1065
lixianyu 0:a4d8f5b3c546 1066 /** Get the I2C address of Slave 4.
lixianyu 0:a4d8f5b3c546 1067 * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read
lixianyu 0:a4d8f5b3c546 1068 * operation, and if it is cleared, then it's a write operation. The remaining
lixianyu 0:a4d8f5b3c546 1069 * bits (6-0) are the 7-bit device address of the slave device.
lixianyu 0:a4d8f5b3c546 1070 *
lixianyu 0:a4d8f5b3c546 1071 * @return Current address for Slave 4
lixianyu 0:a4d8f5b3c546 1072 * @see getSlaveAddress()
lixianyu 0:a4d8f5b3c546 1073 * @see MPU6050_RA_I2C_SLV4_ADDR
lixianyu 0:a4d8f5b3c546 1074 */
lixianyu 0:a4d8f5b3c546 1075 uint8_t MPU6050::getSlave4Address() {
lixianyu 0:a4d8f5b3c546 1076 I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, buffer);
lixianyu 0:a4d8f5b3c546 1077 return buffer[0];
lixianyu 0:a4d8f5b3c546 1078 }
lixianyu 0:a4d8f5b3c546 1079 /** Set the I2C address of Slave 4.
lixianyu 0:a4d8f5b3c546 1080 * @param address New address for Slave 4
lixianyu 0:a4d8f5b3c546 1081 * @see getSlave4Address()
lixianyu 0:a4d8f5b3c546 1082 * @see MPU6050_RA_I2C_SLV4_ADDR
lixianyu 0:a4d8f5b3c546 1083 */
lixianyu 0:a4d8f5b3c546 1084 void MPU6050::setSlave4Address(uint8_t address) {
lixianyu 0:a4d8f5b3c546 1085 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, address);
lixianyu 0:a4d8f5b3c546 1086 }
lixianyu 0:a4d8f5b3c546 1087 /** Get the active internal register for the Slave 4.
lixianyu 0:a4d8f5b3c546 1088 * Read/write operations for this slave will be done to whatever internal
lixianyu 0:a4d8f5b3c546 1089 * register address is stored in this MPU register.
lixianyu 0:a4d8f5b3c546 1090 *
lixianyu 0:a4d8f5b3c546 1091 * @return Current active register for Slave 4
lixianyu 0:a4d8f5b3c546 1092 * @see MPU6050_RA_I2C_SLV4_REG
lixianyu 0:a4d8f5b3c546 1093 */
lixianyu 0:a4d8f5b3c546 1094 uint8_t MPU6050::getSlave4Register() {
lixianyu 0:a4d8f5b3c546 1095 I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_REG, buffer);
lixianyu 0:a4d8f5b3c546 1096 return buffer[0];
lixianyu 0:a4d8f5b3c546 1097 }
lixianyu 0:a4d8f5b3c546 1098 /** Set the active internal register for Slave 4.
lixianyu 0:a4d8f5b3c546 1099 * @param reg New active register for Slave 4
lixianyu 0:a4d8f5b3c546 1100 * @see getSlave4Register()
lixianyu 0:a4d8f5b3c546 1101 * @see MPU6050_RA_I2C_SLV4_REG
lixianyu 0:a4d8f5b3c546 1102 */
lixianyu 0:a4d8f5b3c546 1103 void MPU6050::setSlave4Register(uint8_t reg) {
lixianyu 0:a4d8f5b3c546 1104 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_REG, reg);
lixianyu 0:a4d8f5b3c546 1105 }
lixianyu 0:a4d8f5b3c546 1106 /** Set new byte to write to Slave 4.
lixianyu 0:a4d8f5b3c546 1107 * This register stores the data to be written into the Slave 4. If I2C_SLV4_RW
lixianyu 0:a4d8f5b3c546 1108 * is set 1 (set to read), this register has no effect.
lixianyu 0:a4d8f5b3c546 1109 * @param data New byte to write to Slave 4
lixianyu 0:a4d8f5b3c546 1110 * @see MPU6050_RA_I2C_SLV4_DO
lixianyu 0:a4d8f5b3c546 1111 */
lixianyu 0:a4d8f5b3c546 1112 void MPU6050::setSlave4OutputByte(uint8_t data) {
lixianyu 0:a4d8f5b3c546 1113 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_DO, data);
lixianyu 0:a4d8f5b3c546 1114 }
lixianyu 0:a4d8f5b3c546 1115 /** Get the enabled value for the Slave 4.
lixianyu 0:a4d8f5b3c546 1116 * When set to 1, this bit enables Slave 4 for data transfer operations. When
lixianyu 0:a4d8f5b3c546 1117 * cleared to 0, this bit disables Slave 4 from data transfer operations.
lixianyu 0:a4d8f5b3c546 1118 * @return Current enabled value for Slave 4
lixianyu 0:a4d8f5b3c546 1119 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1120 */
lixianyu 0:a4d8f5b3c546 1121 bool MPU6050::getSlave4Enabled() {
lixianyu 0:a4d8f5b3c546 1122 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1123 return buffer[0];
lixianyu 0:a4d8f5b3c546 1124 }
lixianyu 0:a4d8f5b3c546 1125 /** Set the enabled value for Slave 4.
lixianyu 0:a4d8f5b3c546 1126 * @param enabled New enabled value for Slave 4
lixianyu 0:a4d8f5b3c546 1127 * @see getSlave4Enabled()
lixianyu 0:a4d8f5b3c546 1128 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1129 */
lixianyu 0:a4d8f5b3c546 1130 void MPU6050::setSlave4Enabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1131 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1132 }
lixianyu 0:a4d8f5b3c546 1133 /** Get the enabled value for Slave 4 transaction interrupts.
lixianyu 0:a4d8f5b3c546 1134 * When set to 1, this bit enables the generation of an interrupt signal upon
lixianyu 0:a4d8f5b3c546 1135 * completion of a Slave 4 transaction. When cleared to 0, this bit disables the
lixianyu 0:a4d8f5b3c546 1136 * generation of an interrupt signal upon completion of a Slave 4 transaction.
lixianyu 0:a4d8f5b3c546 1137 * The interrupt status can be observed in Register 54.
lixianyu 0:a4d8f5b3c546 1138 *
lixianyu 0:a4d8f5b3c546 1139 * @return Current enabled value for Slave 4 transaction interrupts.
lixianyu 0:a4d8f5b3c546 1140 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1141 */
lixianyu 0:a4d8f5b3c546 1142 bool MPU6050::getSlave4InterruptEnabled() {
lixianyu 0:a4d8f5b3c546 1143 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1144 return buffer[0];
lixianyu 0:a4d8f5b3c546 1145 }
lixianyu 0:a4d8f5b3c546 1146 /** Set the enabled value for Slave 4 transaction interrupts.
lixianyu 0:a4d8f5b3c546 1147 * @param enabled New enabled value for Slave 4 transaction interrupts.
lixianyu 0:a4d8f5b3c546 1148 * @see getSlave4InterruptEnabled()
lixianyu 0:a4d8f5b3c546 1149 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1150 */
lixianyu 0:a4d8f5b3c546 1151 void MPU6050::setSlave4InterruptEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1152 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1153 }
lixianyu 0:a4d8f5b3c546 1154 /** Get write mode for Slave 4.
lixianyu 0:a4d8f5b3c546 1155 * When set to 1, the transaction will read or write data only. When cleared to
lixianyu 0:a4d8f5b3c546 1156 * 0, the transaction will write a register address prior to reading or writing
lixianyu 0:a4d8f5b3c546 1157 * data. This should equal 0 when specifying the register address within the
lixianyu 0:a4d8f5b3c546 1158 * Slave device to/from which the ensuing data transaction will take place.
lixianyu 0:a4d8f5b3c546 1159 *
lixianyu 0:a4d8f5b3c546 1160 * @return Current write mode for Slave 4 (0 = register address + data, 1 = data only)
lixianyu 0:a4d8f5b3c546 1161 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1162 */
lixianyu 0:a4d8f5b3c546 1163 bool MPU6050::getSlave4WriteMode() {
lixianyu 0:a4d8f5b3c546 1164 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1165 return buffer[0];
lixianyu 0:a4d8f5b3c546 1166 }
lixianyu 0:a4d8f5b3c546 1167 /** Set write mode for the Slave 4.
lixianyu 0:a4d8f5b3c546 1168 * @param mode New write mode for Slave 4 (0 = register address + data, 1 = data only)
lixianyu 0:a4d8f5b3c546 1169 * @see getSlave4WriteMode()
lixianyu 0:a4d8f5b3c546 1170 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1171 */
lixianyu 0:a4d8f5b3c546 1172 void MPU6050::setSlave4WriteMode(bool mode) {
lixianyu 0:a4d8f5b3c546 1173 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, mode);
lixianyu 0:a4d8f5b3c546 1174 }
lixianyu 0:a4d8f5b3c546 1175 /** Get Slave 4 master delay value.
lixianyu 0:a4d8f5b3c546 1176 * This configures the reduced access rate of I2C slaves relative to the Sample
lixianyu 0:a4d8f5b3c546 1177 * Rate. When a slave's access rate is decreased relative to the Sample Rate,
lixianyu 0:a4d8f5b3c546 1178 * the slave is accessed every:
lixianyu 0:a4d8f5b3c546 1179 *
lixianyu 0:a4d8f5b3c546 1180 * 1 / (1 + I2C_MST_DLY) samples
lixianyu 0:a4d8f5b3c546 1181 *
lixianyu 0:a4d8f5b3c546 1182 * This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and
lixianyu 0:a4d8f5b3c546 1183 * DLPF_CFG (register 26). Whether a slave's access rate is reduced relative to
lixianyu 0:a4d8f5b3c546 1184 * the Sample Rate is determined by I2C_MST_DELAY_CTRL (register 103). For
lixianyu 0:a4d8f5b3c546 1185 * further information regarding the Sample Rate, please refer to register 25.
lixianyu 0:a4d8f5b3c546 1186 *
lixianyu 0:a4d8f5b3c546 1187 * @return Current Slave 4 master delay value
lixianyu 0:a4d8f5b3c546 1188 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1189 */
lixianyu 0:a4d8f5b3c546 1190 uint8_t MPU6050::getSlave4MasterDelay() {
lixianyu 0:a4d8f5b3c546 1191 I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 1192 return buffer[0];
lixianyu 0:a4d8f5b3c546 1193 }
lixianyu 0:a4d8f5b3c546 1194 /** Set Slave 4 master delay value.
lixianyu 0:a4d8f5b3c546 1195 * @param delay New Slave 4 master delay value
lixianyu 0:a4d8f5b3c546 1196 * @see getSlave4MasterDelay()
lixianyu 0:a4d8f5b3c546 1197 * @see MPU6050_RA_I2C_SLV4_CTRL
lixianyu 0:a4d8f5b3c546 1198 */
lixianyu 0:a4d8f5b3c546 1199 void MPU6050::setSlave4MasterDelay(uint8_t delay) {
lixianyu 0:a4d8f5b3c546 1200 I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, delay);
lixianyu 0:a4d8f5b3c546 1201 }
lixianyu 0:a4d8f5b3c546 1202 /** Get last available byte read from Slave 4.
lixianyu 0:a4d8f5b3c546 1203 * This register stores the data read from Slave 4. This field is populated
lixianyu 0:a4d8f5b3c546 1204 * after a read transaction.
lixianyu 0:a4d8f5b3c546 1205 * @return Last available byte read from to Slave 4
lixianyu 0:a4d8f5b3c546 1206 * @see MPU6050_RA_I2C_SLV4_DI
lixianyu 0:a4d8f5b3c546 1207 */
lixianyu 0:a4d8f5b3c546 1208 uint8_t MPU6050::getSlate4InputByte() {
lixianyu 0:a4d8f5b3c546 1209 I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_DI, buffer);
lixianyu 0:a4d8f5b3c546 1210 return buffer[0];
lixianyu 0:a4d8f5b3c546 1211 }
lixianyu 0:a4d8f5b3c546 1212
lixianyu 0:a4d8f5b3c546 1213 // I2C_MST_STATUS register
lixianyu 0:a4d8f5b3c546 1214
lixianyu 0:a4d8f5b3c546 1215 /** Get FSYNC interrupt status.
lixianyu 0:a4d8f5b3c546 1216 * This bit reflects the status of the FSYNC interrupt from an external device
lixianyu 0:a4d8f5b3c546 1217 * into the MPU-60X0. This is used as a way to pass an external interrupt
lixianyu 0:a4d8f5b3c546 1218 * through the MPU-60X0 to the host application processor. When set to 1, this
lixianyu 0:a4d8f5b3c546 1219 * bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1220 * (Register 55).
lixianyu 0:a4d8f5b3c546 1221 * @return FSYNC interrupt status
lixianyu 0:a4d8f5b3c546 1222 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1223 */
lixianyu 0:a4d8f5b3c546 1224 bool MPU6050::getPassthroughStatus() {
lixianyu 0:a4d8f5b3c546 1225 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_PASS_THROUGH_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1226 return buffer[0];
lixianyu 0:a4d8f5b3c546 1227 }
lixianyu 0:a4d8f5b3c546 1228 /** Get Slave 4 transaction done status.
lixianyu 0:a4d8f5b3c546 1229 * Automatically sets to 1 when a Slave 4 transaction has completed. This
lixianyu 0:a4d8f5b3c546 1230 * triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register
lixianyu 0:a4d8f5b3c546 1231 * (Register 56) is asserted and if the SLV_4_DONE_INT bit is asserted in the
lixianyu 0:a4d8f5b3c546 1232 * I2C_SLV4_CTRL register (Register 52).
lixianyu 0:a4d8f5b3c546 1233 * @return Slave 4 transaction done status
lixianyu 0:a4d8f5b3c546 1234 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1235 */
lixianyu 0:a4d8f5b3c546 1236 bool MPU6050::getSlave4IsDone() {
lixianyu 0:a4d8f5b3c546 1237 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_DONE_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1238 return buffer[0];
lixianyu 0:a4d8f5b3c546 1239 }
lixianyu 0:a4d8f5b3c546 1240 /** Get master arbitration lost status.
lixianyu 0:a4d8f5b3c546 1241 * This bit automatically sets to 1 when the I2C Master has lost arbitration of
lixianyu 0:a4d8f5b3c546 1242 * the auxiliary I2C bus (an error condition). This triggers an interrupt if the
lixianyu 0:a4d8f5b3c546 1243 * I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1244 * @return Master arbitration lost status
lixianyu 0:a4d8f5b3c546 1245 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1246 */
lixianyu 0:a4d8f5b3c546 1247 bool MPU6050::getLostArbitration() {
lixianyu 0:a4d8f5b3c546 1248 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_LOST_ARB_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1249 return buffer[0];
lixianyu 0:a4d8f5b3c546 1250 }
lixianyu 0:a4d8f5b3c546 1251 /** Get Slave 4 NACK status.
lixianyu 0:a4d8f5b3c546 1252 * This bit automatically sets to 1 when the I2C Master receives a NACK in a
lixianyu 0:a4d8f5b3c546 1253 * transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN
lixianyu 0:a4d8f5b3c546 1254 * bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1255 * @return Slave 4 NACK interrupt status
lixianyu 0:a4d8f5b3c546 1256 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1257 */
lixianyu 0:a4d8f5b3c546 1258 bool MPU6050::getSlave4Nack() {
lixianyu 0:a4d8f5b3c546 1259 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_NACK_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1260 return buffer[0];
lixianyu 0:a4d8f5b3c546 1261 }
lixianyu 0:a4d8f5b3c546 1262 /** Get Slave 3 NACK status.
lixianyu 0:a4d8f5b3c546 1263 * This bit automatically sets to 1 when the I2C Master receives a NACK in a
lixianyu 0:a4d8f5b3c546 1264 * transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN
lixianyu 0:a4d8f5b3c546 1265 * bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1266 * @return Slave 3 NACK interrupt status
lixianyu 0:a4d8f5b3c546 1267 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1268 */
lixianyu 0:a4d8f5b3c546 1269 bool MPU6050::getSlave3Nack() {
lixianyu 0:a4d8f5b3c546 1270 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV3_NACK_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1271 return buffer[0];
lixianyu 0:a4d8f5b3c546 1272 }
lixianyu 0:a4d8f5b3c546 1273 /** Get Slave 2 NACK status.
lixianyu 0:a4d8f5b3c546 1274 * This bit automatically sets to 1 when the I2C Master receives a NACK in a
lixianyu 0:a4d8f5b3c546 1275 * transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN
lixianyu 0:a4d8f5b3c546 1276 * bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1277 * @return Slave 2 NACK interrupt status
lixianyu 0:a4d8f5b3c546 1278 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1279 */
lixianyu 0:a4d8f5b3c546 1280 bool MPU6050::getSlave2Nack() {
lixianyu 0:a4d8f5b3c546 1281 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV2_NACK_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1282 return buffer[0];
lixianyu 0:a4d8f5b3c546 1283 }
lixianyu 0:a4d8f5b3c546 1284 /** Get Slave 1 NACK status.
lixianyu 0:a4d8f5b3c546 1285 * This bit automatically sets to 1 when the I2C Master receives a NACK in a
lixianyu 0:a4d8f5b3c546 1286 * transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN
lixianyu 0:a4d8f5b3c546 1287 * bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1288 * @return Slave 1 NACK interrupt status
lixianyu 0:a4d8f5b3c546 1289 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1290 */
lixianyu 0:a4d8f5b3c546 1291 bool MPU6050::getSlave1Nack() {
lixianyu 0:a4d8f5b3c546 1292 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV1_NACK_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1293 return buffer[0];
lixianyu 0:a4d8f5b3c546 1294 }
lixianyu 0:a4d8f5b3c546 1295 /** Get Slave 0 NACK status.
lixianyu 0:a4d8f5b3c546 1296 * This bit automatically sets to 1 when the I2C Master receives a NACK in a
lixianyu 0:a4d8f5b3c546 1297 * transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN
lixianyu 0:a4d8f5b3c546 1298 * bit in the INT_ENABLE register (Register 56) is asserted.
lixianyu 0:a4d8f5b3c546 1299 * @return Slave 0 NACK interrupt status
lixianyu 0:a4d8f5b3c546 1300 * @see MPU6050_RA_I2C_MST_STATUS
lixianyu 0:a4d8f5b3c546 1301 */
lixianyu 0:a4d8f5b3c546 1302 bool MPU6050::getSlave0Nack() {
lixianyu 0:a4d8f5b3c546 1303 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV0_NACK_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1304 return buffer[0];
lixianyu 0:a4d8f5b3c546 1305 }
lixianyu 0:a4d8f5b3c546 1306
lixianyu 0:a4d8f5b3c546 1307 // INT_PIN_CFG register
lixianyu 0:a4d8f5b3c546 1308
lixianyu 0:a4d8f5b3c546 1309 /** Get interrupt logic level mode.
lixianyu 0:a4d8f5b3c546 1310 * Will be set 0 for active-high, 1 for active-low.
lixianyu 0:a4d8f5b3c546 1311 * @return Current interrupt mode (0=active-high, 1=active-low)
lixianyu 0:a4d8f5b3c546 1312 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1313 * @see MPU6050_INTCFG_INT_LEVEL_BIT
lixianyu 0:a4d8f5b3c546 1314 */
lixianyu 0:a4d8f5b3c546 1315 bool MPU6050::getInterruptMode() {
lixianyu 0:a4d8f5b3c546 1316 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1317 return buffer[0];
lixianyu 0:a4d8f5b3c546 1318 }
lixianyu 0:a4d8f5b3c546 1319 /** Set interrupt logic level mode.
lixianyu 0:a4d8f5b3c546 1320 * @param mode New interrupt mode (0=active-high, 1=active-low)
lixianyu 0:a4d8f5b3c546 1321 * @see getInterruptMode()
lixianyu 0:a4d8f5b3c546 1322 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1323 * @see MPU6050_INTCFG_INT_LEVEL_BIT
lixianyu 0:a4d8f5b3c546 1324 */
lixianyu 0:a4d8f5b3c546 1325 void MPU6050::setInterruptMode(bool mode) {
lixianyu 0:a4d8f5b3c546 1326 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, mode);
lixianyu 0:a4d8f5b3c546 1327 }
lixianyu 0:a4d8f5b3c546 1328 /** Get interrupt drive mode.
lixianyu 0:a4d8f5b3c546 1329 * Will be set 0 for push-pull, 1 for open-drain.
lixianyu 0:a4d8f5b3c546 1330 * @return Current interrupt drive mode (0=push-pull, 1=open-drain)
lixianyu 0:a4d8f5b3c546 1331 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1332 * @see MPU6050_INTCFG_INT_OPEN_BIT
lixianyu 0:a4d8f5b3c546 1333 */
lixianyu 0:a4d8f5b3c546 1334 bool MPU6050::getInterruptDrive() {
lixianyu 0:a4d8f5b3c546 1335 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1336 return buffer[0];
lixianyu 0:a4d8f5b3c546 1337 }
lixianyu 0:a4d8f5b3c546 1338 /** Set interrupt drive mode.
lixianyu 0:a4d8f5b3c546 1339 * @param drive New interrupt drive mode (0=push-pull, 1=open-drain)
lixianyu 0:a4d8f5b3c546 1340 * @see getInterruptDrive()
lixianyu 0:a4d8f5b3c546 1341 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1342 * @see MPU6050_INTCFG_INT_OPEN_BIT
lixianyu 0:a4d8f5b3c546 1343 */
lixianyu 0:a4d8f5b3c546 1344 void MPU6050::setInterruptDrive(bool drive) {
lixianyu 0:a4d8f5b3c546 1345 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, drive);
lixianyu 0:a4d8f5b3c546 1346 }
lixianyu 0:a4d8f5b3c546 1347 /** Get interrupt latch mode.
lixianyu 0:a4d8f5b3c546 1348 * Will be set 0 for 50us-pulse, 1 for latch-until-int-cleared.
lixianyu 0:a4d8f5b3c546 1349 * @return Current latch mode (0=50us-pulse, 1=latch-until-int-cleared)
lixianyu 0:a4d8f5b3c546 1350 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1351 * @see MPU6050_INTCFG_LATCH_INT_EN_BIT
lixianyu 0:a4d8f5b3c546 1352 */
lixianyu 0:a4d8f5b3c546 1353 bool MPU6050::getInterruptLatch() {
lixianyu 0:a4d8f5b3c546 1354 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1355 return buffer[0];
lixianyu 0:a4d8f5b3c546 1356 }
lixianyu 0:a4d8f5b3c546 1357 /** Set interrupt latch mode.
lixianyu 0:a4d8f5b3c546 1358 * @param latch New latch mode (0=50us-pulse, 1=latch-until-int-cleared)
lixianyu 0:a4d8f5b3c546 1359 * @see getInterruptLatch()
lixianyu 0:a4d8f5b3c546 1360 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1361 * @see MPU6050_INTCFG_LATCH_INT_EN_BIT
lixianyu 0:a4d8f5b3c546 1362 */
lixianyu 0:a4d8f5b3c546 1363 void MPU6050::setInterruptLatch(bool latch) {
lixianyu 0:a4d8f5b3c546 1364 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, latch);
lixianyu 0:a4d8f5b3c546 1365 }
lixianyu 0:a4d8f5b3c546 1366 /** Get interrupt latch clear mode.
lixianyu 0:a4d8f5b3c546 1367 * Will be set 0 for status-read-only, 1 for any-register-read.
lixianyu 0:a4d8f5b3c546 1368 * @return Current latch clear mode (0=status-read-only, 1=any-register-read)
lixianyu 0:a4d8f5b3c546 1369 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1370 * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT
lixianyu 0:a4d8f5b3c546 1371 */
lixianyu 0:a4d8f5b3c546 1372 bool MPU6050::getInterruptLatchClear() {
lixianyu 0:a4d8f5b3c546 1373 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1374 return buffer[0];
lixianyu 0:a4d8f5b3c546 1375 }
lixianyu 0:a4d8f5b3c546 1376 /** Set interrupt latch clear mode.
lixianyu 0:a4d8f5b3c546 1377 * @param clear New latch clear mode (0=status-read-only, 1=any-register-read)
lixianyu 0:a4d8f5b3c546 1378 * @see getInterruptLatchClear()
lixianyu 0:a4d8f5b3c546 1379 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1380 * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT
lixianyu 0:a4d8f5b3c546 1381 */
lixianyu 0:a4d8f5b3c546 1382 void MPU6050::setInterruptLatchClear(bool clear) {
lixianyu 0:a4d8f5b3c546 1383 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, clear);
lixianyu 0:a4d8f5b3c546 1384 }
lixianyu 0:a4d8f5b3c546 1385 /** Get FSYNC interrupt logic level mode.
lixianyu 0:a4d8f5b3c546 1386 * @return Current FSYNC interrupt mode (0=active-high, 1=active-low)
lixianyu 0:a4d8f5b3c546 1387 * @see getFSyncInterruptMode()
lixianyu 0:a4d8f5b3c546 1388 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1389 * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT
lixianyu 0:a4d8f5b3c546 1390 */
lixianyu 0:a4d8f5b3c546 1391 bool MPU6050::getFSyncInterruptLevel() {
lixianyu 0:a4d8f5b3c546 1392 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1393 return buffer[0];
lixianyu 0:a4d8f5b3c546 1394 }
lixianyu 0:a4d8f5b3c546 1395 /** Set FSYNC interrupt logic level mode.
lixianyu 0:a4d8f5b3c546 1396 * @param mode New FSYNC interrupt mode (0=active-high, 1=active-low)
lixianyu 0:a4d8f5b3c546 1397 * @see getFSyncInterruptMode()
lixianyu 0:a4d8f5b3c546 1398 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1399 * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT
lixianyu 0:a4d8f5b3c546 1400 */
lixianyu 0:a4d8f5b3c546 1401 void MPU6050::setFSyncInterruptLevel(bool level) {
lixianyu 0:a4d8f5b3c546 1402 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, level);
lixianyu 0:a4d8f5b3c546 1403 }
lixianyu 0:a4d8f5b3c546 1404 /** Get FSYNC pin interrupt enabled setting.
lixianyu 0:a4d8f5b3c546 1405 * Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1406 * @return Current interrupt enabled setting
lixianyu 0:a4d8f5b3c546 1407 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1408 * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT
lixianyu 0:a4d8f5b3c546 1409 */
lixianyu 0:a4d8f5b3c546 1410 bool MPU6050::getFSyncInterruptEnabled() {
lixianyu 0:a4d8f5b3c546 1411 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1412 return buffer[0];
lixianyu 0:a4d8f5b3c546 1413 }
lixianyu 0:a4d8f5b3c546 1414 /** Set FSYNC pin interrupt enabled setting.
lixianyu 0:a4d8f5b3c546 1415 * @param enabled New FSYNC pin interrupt enabled setting
lixianyu 0:a4d8f5b3c546 1416 * @see getFSyncInterruptEnabled()
lixianyu 0:a4d8f5b3c546 1417 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1418 * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT
lixianyu 0:a4d8f5b3c546 1419 */
lixianyu 0:a4d8f5b3c546 1420 void MPU6050::setFSyncInterruptEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1421 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1422 }
lixianyu 0:a4d8f5b3c546 1423 /** Get I2C bypass enabled status.
lixianyu 0:a4d8f5b3c546 1424 * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to
lixianyu 0:a4d8f5b3c546 1425 * 0, the host application processor will be able to directly access the
lixianyu 0:a4d8f5b3c546 1426 * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host
lixianyu 0:a4d8f5b3c546 1427 * application processor will not be able to directly access the auxiliary I2C
lixianyu 0:a4d8f5b3c546 1428 * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106
lixianyu 0:a4d8f5b3c546 1429 * bit[5]).
lixianyu 0:a4d8f5b3c546 1430 * @return Current I2C bypass enabled status
lixianyu 0:a4d8f5b3c546 1431 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1432 * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT
lixianyu 0:a4d8f5b3c546 1433 */
lixianyu 0:a4d8f5b3c546 1434 bool MPU6050::getI2CBypassEnabled() {
lixianyu 0:a4d8f5b3c546 1435 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1436 return buffer[0];
lixianyu 0:a4d8f5b3c546 1437 }
lixianyu 0:a4d8f5b3c546 1438 /** Set I2C bypass enabled status.
lixianyu 0:a4d8f5b3c546 1439 * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to
lixianyu 0:a4d8f5b3c546 1440 * 0, the host application processor will be able to directly access the
lixianyu 0:a4d8f5b3c546 1441 * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host
lixianyu 0:a4d8f5b3c546 1442 * application processor will not be able to directly access the auxiliary I2C
lixianyu 0:a4d8f5b3c546 1443 * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106
lixianyu 0:a4d8f5b3c546 1444 * bit[5]).
lixianyu 0:a4d8f5b3c546 1445 * @param enabled New I2C bypass enabled status
lixianyu 0:a4d8f5b3c546 1446 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1447 * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT
lixianyu 0:a4d8f5b3c546 1448 */
lixianyu 0:a4d8f5b3c546 1449 void MPU6050::setI2CBypassEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1450 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1451 }
lixianyu 0:a4d8f5b3c546 1452 /** Get reference clock output enabled status.
lixianyu 0:a4d8f5b3c546 1453 * When this bit is equal to 1, a reference clock output is provided at the
lixianyu 0:a4d8f5b3c546 1454 * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For
lixianyu 0:a4d8f5b3c546 1455 * further information regarding CLKOUT, please refer to the MPU-60X0 Product
lixianyu 0:a4d8f5b3c546 1456 * Specification document.
lixianyu 0:a4d8f5b3c546 1457 * @return Current reference clock output enabled status
lixianyu 0:a4d8f5b3c546 1458 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1459 * @see MPU6050_INTCFG_CLKOUT_EN_BIT
lixianyu 0:a4d8f5b3c546 1460 */
lixianyu 0:a4d8f5b3c546 1461 bool MPU6050::getClockOutputEnabled() {
lixianyu 0:a4d8f5b3c546 1462 I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1463 return buffer[0];
lixianyu 0:a4d8f5b3c546 1464 }
lixianyu 0:a4d8f5b3c546 1465 /** Set reference clock output enabled status.
lixianyu 0:a4d8f5b3c546 1466 * When this bit is equal to 1, a reference clock output is provided at the
lixianyu 0:a4d8f5b3c546 1467 * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For
lixianyu 0:a4d8f5b3c546 1468 * further information regarding CLKOUT, please refer to the MPU-60X0 Product
lixianyu 0:a4d8f5b3c546 1469 * Specification document.
lixianyu 0:a4d8f5b3c546 1470 * @param enabled New reference clock output enabled status
lixianyu 0:a4d8f5b3c546 1471 * @see MPU6050_RA_INT_PIN_CFG
lixianyu 0:a4d8f5b3c546 1472 * @see MPU6050_INTCFG_CLKOUT_EN_BIT
lixianyu 0:a4d8f5b3c546 1473 */
lixianyu 0:a4d8f5b3c546 1474 void MPU6050::setClockOutputEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1475 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1476 }
lixianyu 0:a4d8f5b3c546 1477
lixianyu 0:a4d8f5b3c546 1478 // INT_ENABLE register
lixianyu 0:a4d8f5b3c546 1479
lixianyu 0:a4d8f5b3c546 1480 /** Get full interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1481 * Full register byte for all interrupts, for quick reading. Each bit will be
lixianyu 0:a4d8f5b3c546 1482 * set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1483 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1484 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1485 * @see MPU6050_INTERRUPT_FF_BIT
lixianyu 0:a4d8f5b3c546 1486 **/
lixianyu 0:a4d8f5b3c546 1487 uint8_t MPU6050::getIntEnabled() {
lixianyu 0:a4d8f5b3c546 1488 I2Cdev::readByte(devAddr, MPU6050_RA_INT_ENABLE, buffer);
lixianyu 0:a4d8f5b3c546 1489 return buffer[0];
lixianyu 0:a4d8f5b3c546 1490 }
lixianyu 0:a4d8f5b3c546 1491 /** Set full interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1492 * Full register byte for all interrupts, for quick reading. Each bit should be
lixianyu 0:a4d8f5b3c546 1493 * set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1494 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1495 * @see getIntFreefallEnabled()
lixianyu 0:a4d8f5b3c546 1496 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1497 * @see MPU6050_INTERRUPT_FF_BIT
lixianyu 0:a4d8f5b3c546 1498 **/
lixianyu 0:a4d8f5b3c546 1499 void MPU6050::setIntEnabled(uint8_t enabled) {
lixianyu 0:a4d8f5b3c546 1500 I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, enabled);
lixianyu 0:a4d8f5b3c546 1501 }
lixianyu 0:a4d8f5b3c546 1502 /** Get Free Fall interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1503 * Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1504 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1505 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1506 * @see MPU6050_INTERRUPT_FF_BIT
lixianyu 0:a4d8f5b3c546 1507 **/
lixianyu 0:a4d8f5b3c546 1508 bool MPU6050::getIntFreefallEnabled() {
lixianyu 0:a4d8f5b3c546 1509 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1510 return buffer[0];
lixianyu 0:a4d8f5b3c546 1511 }
lixianyu 0:a4d8f5b3c546 1512 /** Set Free Fall interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1513 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1514 * @see getIntFreefallEnabled()
lixianyu 0:a4d8f5b3c546 1515 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1516 * @see MPU6050_INTERRUPT_FF_BIT
lixianyu 0:a4d8f5b3c546 1517 **/
lixianyu 0:a4d8f5b3c546 1518 void MPU6050::setIntFreefallEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1519 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1520 }
lixianyu 0:a4d8f5b3c546 1521 /** Get Motion Detection interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1522 * Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1523 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1524 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1525 * @see MPU6050_INTERRUPT_MOT_BIT
lixianyu 0:a4d8f5b3c546 1526 **/
lixianyu 0:a4d8f5b3c546 1527 bool MPU6050::getIntMotionEnabled() {
lixianyu 0:a4d8f5b3c546 1528 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1529 return buffer[0];
lixianyu 0:a4d8f5b3c546 1530 }
lixianyu 0:a4d8f5b3c546 1531 /** Set Motion Detection interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1532 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1533 * @see getIntMotionEnabled()
lixianyu 0:a4d8f5b3c546 1534 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1535 * @see MPU6050_INTERRUPT_MOT_BIT
lixianyu 0:a4d8f5b3c546 1536 **/
lixianyu 0:a4d8f5b3c546 1537 void MPU6050::setIntMotionEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1538 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1539 }
lixianyu 0:a4d8f5b3c546 1540 /** Get Zero Motion Detection interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1541 * Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1542 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1543 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1544 * @see MPU6050_INTERRUPT_ZMOT_BIT
lixianyu 0:a4d8f5b3c546 1545 **/
lixianyu 0:a4d8f5b3c546 1546 bool MPU6050::getIntZeroMotionEnabled() {
lixianyu 0:a4d8f5b3c546 1547 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1548 return buffer[0];
lixianyu 0:a4d8f5b3c546 1549 }
lixianyu 0:a4d8f5b3c546 1550 /** Set Zero Motion Detection interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1551 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1552 * @see getIntZeroMotionEnabled()
lixianyu 0:a4d8f5b3c546 1553 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1554 * @see MPU6050_INTERRUPT_ZMOT_BIT
lixianyu 0:a4d8f5b3c546 1555 **/
lixianyu 0:a4d8f5b3c546 1556 void MPU6050::setIntZeroMotionEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1557 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1558 }
lixianyu 0:a4d8f5b3c546 1559 /** Get FIFO Buffer Overflow interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1560 * Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1561 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1562 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1563 * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT
lixianyu 0:a4d8f5b3c546 1564 **/
lixianyu 0:a4d8f5b3c546 1565 bool MPU6050::getIntFIFOBufferOverflowEnabled() {
lixianyu 0:a4d8f5b3c546 1566 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1567 return buffer[0];
lixianyu 0:a4d8f5b3c546 1568 }
lixianyu 0:a4d8f5b3c546 1569 /** Set FIFO Buffer Overflow interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1570 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1571 * @see getIntFIFOBufferOverflowEnabled()
lixianyu 0:a4d8f5b3c546 1572 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1573 * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT
lixianyu 0:a4d8f5b3c546 1574 **/
lixianyu 0:a4d8f5b3c546 1575 void MPU6050::setIntFIFOBufferOverflowEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1576 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1577 }
lixianyu 0:a4d8f5b3c546 1578 /** Get I2C Master interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1579 * This enables any of the I2C Master interrupt sources to generate an
lixianyu 0:a4d8f5b3c546 1580 * interrupt. Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1581 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1582 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1583 * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT
lixianyu 0:a4d8f5b3c546 1584 **/
lixianyu 0:a4d8f5b3c546 1585 bool MPU6050::getIntI2CMasterEnabled() {
lixianyu 0:a4d8f5b3c546 1586 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1587 return buffer[0];
lixianyu 0:a4d8f5b3c546 1588 }
lixianyu 0:a4d8f5b3c546 1589 /** Set I2C Master interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1590 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1591 * @see getIntI2CMasterEnabled()
lixianyu 0:a4d8f5b3c546 1592 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1593 * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT
lixianyu 0:a4d8f5b3c546 1594 **/
lixianyu 0:a4d8f5b3c546 1595 void MPU6050::setIntI2CMasterEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1596 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1597 }
lixianyu 0:a4d8f5b3c546 1598 /** Get Data Ready interrupt enabled setting.
lixianyu 0:a4d8f5b3c546 1599 * This event occurs each time a write operation to all of the sensor registers
lixianyu 0:a4d8f5b3c546 1600 * has been completed. Will be set 0 for disabled, 1 for enabled.
lixianyu 0:a4d8f5b3c546 1601 * @return Current interrupt enabled status
lixianyu 0:a4d8f5b3c546 1602 * @see MPU6050_RA_INT_ENABLE
lixianyu 0:a4d8f5b3c546 1603 * @see MPU6050_INTERRUPT_DATA_RDY_BIT
lixianyu 0:a4d8f5b3c546 1604 */
lixianyu 0:a4d8f5b3c546 1605 bool MPU6050::getIntDataReadyEnabled() {
lixianyu 0:a4d8f5b3c546 1606 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1607 return buffer[0];
lixianyu 0:a4d8f5b3c546 1608 }
lixianyu 0:a4d8f5b3c546 1609 /** Set Data Ready interrupt enabled status.
lixianyu 0:a4d8f5b3c546 1610 * @param enabled New interrupt enabled status
lixianyu 0:a4d8f5b3c546 1611 * @see getIntDataReadyEnabled()
lixianyu 0:a4d8f5b3c546 1612 * @see MPU6050_RA_INT_CFG
lixianyu 0:a4d8f5b3c546 1613 * @see MPU6050_INTERRUPT_DATA_RDY_BIT
lixianyu 0:a4d8f5b3c546 1614 */
lixianyu 0:a4d8f5b3c546 1615 void MPU6050::setIntDataReadyEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 1616 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, enabled);
lixianyu 0:a4d8f5b3c546 1617 }
lixianyu 0:a4d8f5b3c546 1618
lixianyu 0:a4d8f5b3c546 1619 // INT_STATUS register
lixianyu 0:a4d8f5b3c546 1620
lixianyu 0:a4d8f5b3c546 1621 /** Get full set of interrupt status bits.
lixianyu 0:a4d8f5b3c546 1622 * These bits clear to 0 after the register has been read. Very useful
lixianyu 0:a4d8f5b3c546 1623 * for getting multiple INT statuses, since each single bit read clears
lixianyu 0:a4d8f5b3c546 1624 * all of them because it has to read the whole byte.
lixianyu 0:a4d8f5b3c546 1625 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1626 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1627 */
lixianyu 0:a4d8f5b3c546 1628 uint8_t MPU6050::getIntStatus() {
lixianyu 0:a4d8f5b3c546 1629 I2Cdev::readByte(devAddr, MPU6050_RA_INT_STATUS, buffer);
lixianyu 0:a4d8f5b3c546 1630 return buffer[0];
lixianyu 0:a4d8f5b3c546 1631 }
lixianyu 0:a4d8f5b3c546 1632 /** Get Free Fall interrupt status.
lixianyu 0:a4d8f5b3c546 1633 * This bit automatically sets to 1 when a Free Fall interrupt has been
lixianyu 0:a4d8f5b3c546 1634 * generated. The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1635 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1636 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1637 * @see MPU6050_INTERRUPT_FF_BIT
lixianyu 0:a4d8f5b3c546 1638 */
lixianyu 0:a4d8f5b3c546 1639 bool MPU6050::getIntFreefallStatus() {
lixianyu 0:a4d8f5b3c546 1640 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FF_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1641 return buffer[0];
lixianyu 0:a4d8f5b3c546 1642 }
lixianyu 0:a4d8f5b3c546 1643 /** Get Motion Detection interrupt status.
lixianyu 0:a4d8f5b3c546 1644 * This bit automatically sets to 1 when a Motion Detection interrupt has been
lixianyu 0:a4d8f5b3c546 1645 * generated. The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1646 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1647 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1648 * @see MPU6050_INTERRUPT_MOT_BIT
lixianyu 0:a4d8f5b3c546 1649 */
lixianyu 0:a4d8f5b3c546 1650 bool MPU6050::getIntMotionStatus() {
lixianyu 0:a4d8f5b3c546 1651 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_MOT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1652 return buffer[0];
lixianyu 0:a4d8f5b3c546 1653 }
lixianyu 0:a4d8f5b3c546 1654 /** Get Zero Motion Detection interrupt status.
lixianyu 0:a4d8f5b3c546 1655 * This bit automatically sets to 1 when a Zero Motion Detection interrupt has
lixianyu 0:a4d8f5b3c546 1656 * been generated. The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1657 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1658 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1659 * @see MPU6050_INTERRUPT_ZMOT_BIT
lixianyu 0:a4d8f5b3c546 1660 */
lixianyu 0:a4d8f5b3c546 1661 bool MPU6050::getIntZeroMotionStatus() {
lixianyu 0:a4d8f5b3c546 1662 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_ZMOT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1663 return buffer[0];
lixianyu 0:a4d8f5b3c546 1664 }
lixianyu 0:a4d8f5b3c546 1665 /** Get FIFO Buffer Overflow interrupt status.
lixianyu 0:a4d8f5b3c546 1666 * This bit automatically sets to 1 when a Free Fall interrupt has been
lixianyu 0:a4d8f5b3c546 1667 * generated. The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1668 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1669 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1670 * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT
lixianyu 0:a4d8f5b3c546 1671 */
lixianyu 0:a4d8f5b3c546 1672 bool MPU6050::getIntFIFOBufferOverflowStatus() {
lixianyu 0:a4d8f5b3c546 1673 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1674 return buffer[0];
lixianyu 0:a4d8f5b3c546 1675 }
lixianyu 0:a4d8f5b3c546 1676 /** Get I2C Master interrupt status.
lixianyu 0:a4d8f5b3c546 1677 * This bit automatically sets to 1 when an I2C Master interrupt has been
lixianyu 0:a4d8f5b3c546 1678 * generated. For a list of I2C Master interrupts, please refer to Register 54.
lixianyu 0:a4d8f5b3c546 1679 * The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1680 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1681 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1682 * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT
lixianyu 0:a4d8f5b3c546 1683 */
lixianyu 0:a4d8f5b3c546 1684 bool MPU6050::getIntI2CMasterStatus() {
lixianyu 0:a4d8f5b3c546 1685 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1686 return buffer[0];
lixianyu 0:a4d8f5b3c546 1687 }
lixianyu 0:a4d8f5b3c546 1688 /** Get Data Ready interrupt status.
lixianyu 0:a4d8f5b3c546 1689 * This bit automatically sets to 1 when a Data Ready interrupt has been
lixianyu 0:a4d8f5b3c546 1690 * generated. The bit clears to 0 after the register has been read.
lixianyu 0:a4d8f5b3c546 1691 * @return Current interrupt status
lixianyu 0:a4d8f5b3c546 1692 * @see MPU6050_RA_INT_STATUS
lixianyu 0:a4d8f5b3c546 1693 * @see MPU6050_INTERRUPT_DATA_RDY_BIT
lixianyu 0:a4d8f5b3c546 1694 */
lixianyu 0:a4d8f5b3c546 1695 bool MPU6050::getIntDataReadyStatus() {
lixianyu 0:a4d8f5b3c546 1696 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer);
lixianyu 0:a4d8f5b3c546 1697 return buffer[0];
lixianyu 0:a4d8f5b3c546 1698 }
lixianyu 0:a4d8f5b3c546 1699
lixianyu 0:a4d8f5b3c546 1700 // ACCEL_*OUT_* registers
lixianyu 0:a4d8f5b3c546 1701
lixianyu 0:a4d8f5b3c546 1702 /** Get raw 9-axis motion sensor readings (accel/gyro/compass).
lixianyu 0:a4d8f5b3c546 1703 * FUNCTION NOT FULLY IMPLEMENTED YET.
lixianyu 0:a4d8f5b3c546 1704 * @param ax 16-bit signed integer container for accelerometer X-axis value
lixianyu 0:a4d8f5b3c546 1705 * @param ay 16-bit signed integer container for accelerometer Y-axis value
lixianyu 0:a4d8f5b3c546 1706 * @param az 16-bit signed integer container for accelerometer Z-axis value
lixianyu 0:a4d8f5b3c546 1707 * @param gx 16-bit signed integer container for gyroscope X-axis value
lixianyu 0:a4d8f5b3c546 1708 * @param gy 16-bit signed integer container for gyroscope Y-axis value
lixianyu 0:a4d8f5b3c546 1709 * @param gz 16-bit signed integer container for gyroscope Z-axis value
lixianyu 0:a4d8f5b3c546 1710 * @param mx 16-bit signed integer container for magnetometer X-axis value
lixianyu 0:a4d8f5b3c546 1711 * @param my 16-bit signed integer container for magnetometer Y-axis value
lixianyu 0:a4d8f5b3c546 1712 * @param mz 16-bit signed integer container for magnetometer Z-axis value
lixianyu 0:a4d8f5b3c546 1713 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1714 * @see getAcceleration()
lixianyu 0:a4d8f5b3c546 1715 * @see getRotation()
lixianyu 0:a4d8f5b3c546 1716 * @see MPU6050_RA_ACCEL_XOUT_H
lixianyu 0:a4d8f5b3c546 1717 */
lixianyu 0:a4d8f5b3c546 1718 void MPU6050::getMotion9(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* mx, int16_t* my, int16_t* mz) {
lixianyu 0:a4d8f5b3c546 1719 getMotion6(ax, ay, az, gx, gy, gz);
lixianyu 0:a4d8f5b3c546 1720 // TODO: magnetometer integration
lixianyu 0:a4d8f5b3c546 1721 }
lixianyu 0:a4d8f5b3c546 1722 /** Get raw 6-axis motion sensor readings (accel/gyro).
lixianyu 0:a4d8f5b3c546 1723 * Retrieves all currently available motion sensor values.
lixianyu 0:a4d8f5b3c546 1724 * @param ax 16-bit signed integer container for accelerometer X-axis value
lixianyu 0:a4d8f5b3c546 1725 * @param ay 16-bit signed integer container for accelerometer Y-axis value
lixianyu 0:a4d8f5b3c546 1726 * @param az 16-bit signed integer container for accelerometer Z-axis value
lixianyu 0:a4d8f5b3c546 1727 * @param gx 16-bit signed integer container for gyroscope X-axis value
lixianyu 0:a4d8f5b3c546 1728 * @param gy 16-bit signed integer container for gyroscope Y-axis value
lixianyu 0:a4d8f5b3c546 1729 * @param gz 16-bit signed integer container for gyroscope Z-axis value
lixianyu 0:a4d8f5b3c546 1730 * @see getAcceleration()
lixianyu 0:a4d8f5b3c546 1731 * @see getRotation()
lixianyu 0:a4d8f5b3c546 1732 * @see MPU6050_RA_ACCEL_XOUT_H
lixianyu 0:a4d8f5b3c546 1733 */
lixianyu 0:a4d8f5b3c546 1734 void MPU6050::getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz) {
lixianyu 0:a4d8f5b3c546 1735 I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 14, buffer);
lixianyu 0:a4d8f5b3c546 1736 *ax = (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1737 *ay = (((int16_t)buffer[2]) << 8) | buffer[3];
lixianyu 0:a4d8f5b3c546 1738 *az = (((int16_t)buffer[4]) << 8) | buffer[5];
lixianyu 0:a4d8f5b3c546 1739 *gx = (((int16_t)buffer[8]) << 8) | buffer[9];
lixianyu 0:a4d8f5b3c546 1740 *gy = (((int16_t)buffer[10]) << 8) | buffer[11];
lixianyu 0:a4d8f5b3c546 1741 *gz = (((int16_t)buffer[12]) << 8) | buffer[13];
lixianyu 0:a4d8f5b3c546 1742 }
lixianyu 0:a4d8f5b3c546 1743 /** Get 3-axis accelerometer readings.
lixianyu 0:a4d8f5b3c546 1744 * These registers store the most recent accelerometer measurements.
lixianyu 0:a4d8f5b3c546 1745 * Accelerometer measurements are written to these registers at the Sample Rate
lixianyu 0:a4d8f5b3c546 1746 * as defined in Register 25.
lixianyu 0:a4d8f5b3c546 1747 *
lixianyu 0:a4d8f5b3c546 1748 * The accelerometer measurement registers, along with the temperature
lixianyu 0:a4d8f5b3c546 1749 * measurement registers, gyroscope measurement registers, and external sensor
lixianyu 0:a4d8f5b3c546 1750 * data registers, are composed of two sets of registers: an internal register
lixianyu 0:a4d8f5b3c546 1751 * set and a user-facing read register set.
lixianyu 0:a4d8f5b3c546 1752 *
lixianyu 0:a4d8f5b3c546 1753 * The data within the accelerometer sensors' internal register set is always
lixianyu 0:a4d8f5b3c546 1754 * updated at the Sample Rate. Meanwhile, the user-facing read register set
lixianyu 0:a4d8f5b3c546 1755 * duplicates the internal register set's data values whenever the serial
lixianyu 0:a4d8f5b3c546 1756 * interface is idle. This guarantees that a burst read of sensor registers will
lixianyu 0:a4d8f5b3c546 1757 * read measurements from the same sampling instant. Note that if burst reads
lixianyu 0:a4d8f5b3c546 1758 * are not used, the user is responsible for ensuring a set of single byte reads
lixianyu 0:a4d8f5b3c546 1759 * correspond to a single sampling instant by checking the Data Ready interrupt.
lixianyu 0:a4d8f5b3c546 1760 *
lixianyu 0:a4d8f5b3c546 1761 * Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS
lixianyu 0:a4d8f5b3c546 1762 * (Register 28). For each full scale setting, the accelerometers' sensitivity
lixianyu 0:a4d8f5b3c546 1763 * per LSB in ACCEL_xOUT is shown in the table below:
lixianyu 0:a4d8f5b3c546 1764 *
lixianyu 0:a4d8f5b3c546 1765 * <pre>
lixianyu 0:a4d8f5b3c546 1766 * AFS_SEL | Full Scale Range | LSB Sensitivity
lixianyu 0:a4d8f5b3c546 1767 * --------+------------------+----------------
lixianyu 0:a4d8f5b3c546 1768 * 0 | +/- 2g | 8192 LSB/mg
lixianyu 0:a4d8f5b3c546 1769 * 1 | +/- 4g | 4096 LSB/mg
lixianyu 0:a4d8f5b3c546 1770 * 2 | +/- 8g | 2048 LSB/mg
lixianyu 0:a4d8f5b3c546 1771 * 3 | +/- 16g | 1024 LSB/mg
lixianyu 0:a4d8f5b3c546 1772 * </pre>
lixianyu 0:a4d8f5b3c546 1773 *
lixianyu 0:a4d8f5b3c546 1774 * @param x 16-bit signed integer container for X-axis acceleration
lixianyu 0:a4d8f5b3c546 1775 * @param y 16-bit signed integer container for Y-axis acceleration
lixianyu 0:a4d8f5b3c546 1776 * @param z 16-bit signed integer container for Z-axis acceleration
lixianyu 0:a4d8f5b3c546 1777 * @see MPU6050_RA_GYRO_XOUT_H
lixianyu 0:a4d8f5b3c546 1778 */
lixianyu 0:a4d8f5b3c546 1779 void MPU6050::getAcceleration(int16_t* x, int16_t* y, int16_t* z) {
lixianyu 0:a4d8f5b3c546 1780 I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 6, buffer);
lixianyu 0:a4d8f5b3c546 1781 *x = (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1782 *y = (((int16_t)buffer[2]) << 8) | buffer[3];
lixianyu 0:a4d8f5b3c546 1783 *z = (((int16_t)buffer[4]) << 8) | buffer[5];
lixianyu 0:a4d8f5b3c546 1784 }
lixianyu 0:a4d8f5b3c546 1785 /** Get X-axis accelerometer reading.
lixianyu 0:a4d8f5b3c546 1786 * @return X-axis acceleration measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1787 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1788 * @see MPU6050_RA_ACCEL_XOUT_H
lixianyu 0:a4d8f5b3c546 1789 */
lixianyu 0:a4d8f5b3c546 1790 int16_t MPU6050::getAccelerationX() {
lixianyu 0:a4d8f5b3c546 1791 I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1792 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1793 }
lixianyu 0:a4d8f5b3c546 1794 /** Get Y-axis accelerometer reading.
lixianyu 0:a4d8f5b3c546 1795 * @return Y-axis acceleration measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1796 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1797 * @see MPU6050_RA_ACCEL_YOUT_H
lixianyu 0:a4d8f5b3c546 1798 */
lixianyu 0:a4d8f5b3c546 1799 int16_t MPU6050::getAccelerationY() {
lixianyu 0:a4d8f5b3c546 1800 I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_YOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1801 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1802 }
lixianyu 0:a4d8f5b3c546 1803 /** Get Z-axis accelerometer reading.
lixianyu 0:a4d8f5b3c546 1804 * @return Z-axis acceleration measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1805 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1806 * @see MPU6050_RA_ACCEL_ZOUT_H
lixianyu 0:a4d8f5b3c546 1807 */
lixianyu 0:a4d8f5b3c546 1808 int16_t MPU6050::getAccelerationZ() {
lixianyu 0:a4d8f5b3c546 1809 I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_ZOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1810 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1811 }
lixianyu 0:a4d8f5b3c546 1812
lixianyu 0:a4d8f5b3c546 1813 // TEMP_OUT_* registers
lixianyu 0:a4d8f5b3c546 1814
lixianyu 0:a4d8f5b3c546 1815 /** Get current internal temperature.
lixianyu 0:a4d8f5b3c546 1816 * @return Temperature reading in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1817 * @see MPU6050_RA_TEMP_OUT_H
lixianyu 0:a4d8f5b3c546 1818 */
lixianyu 0:a4d8f5b3c546 1819 int16_t MPU6050::getTemperature() {
lixianyu 0:a4d8f5b3c546 1820 I2Cdev::readBytes(devAddr, MPU6050_RA_TEMP_OUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1821 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1822 }
lixianyu 0:a4d8f5b3c546 1823
lixianyu 0:a4d8f5b3c546 1824 // GYRO_*OUT_* registers
lixianyu 0:a4d8f5b3c546 1825
lixianyu 0:a4d8f5b3c546 1826 /** Get 3-axis gyroscope readings.
lixianyu 0:a4d8f5b3c546 1827 * These gyroscope measurement registers, along with the accelerometer
lixianyu 0:a4d8f5b3c546 1828 * measurement registers, temperature measurement registers, and external sensor
lixianyu 0:a4d8f5b3c546 1829 * data registers, are composed of two sets of registers: an internal register
lixianyu 0:a4d8f5b3c546 1830 * set and a user-facing read register set.
lixianyu 0:a4d8f5b3c546 1831 * The data within the gyroscope sensors' internal register set is always
lixianyu 0:a4d8f5b3c546 1832 * updated at the Sample Rate. Meanwhile, the user-facing read register set
lixianyu 0:a4d8f5b3c546 1833 * duplicates the internal register set's data values whenever the serial
lixianyu 0:a4d8f5b3c546 1834 * interface is idle. This guarantees that a burst read of sensor registers will
lixianyu 0:a4d8f5b3c546 1835 * read measurements from the same sampling instant. Note that if burst reads
lixianyu 0:a4d8f5b3c546 1836 * are not used, the user is responsible for ensuring a set of single byte reads
lixianyu 0:a4d8f5b3c546 1837 * correspond to a single sampling instant by checking the Data Ready interrupt.
lixianyu 0:a4d8f5b3c546 1838 *
lixianyu 0:a4d8f5b3c546 1839 * Each 16-bit gyroscope measurement has a full scale defined in FS_SEL
lixianyu 0:a4d8f5b3c546 1840 * (Register 27). For each full scale setting, the gyroscopes' sensitivity per
lixianyu 0:a4d8f5b3c546 1841 * LSB in GYRO_xOUT is shown in the table below:
lixianyu 0:a4d8f5b3c546 1842 *
lixianyu 0:a4d8f5b3c546 1843 * <pre>
lixianyu 0:a4d8f5b3c546 1844 * FS_SEL | Full Scale Range | LSB Sensitivity
lixianyu 0:a4d8f5b3c546 1845 * -------+--------------------+----------------
lixianyu 0:a4d8f5b3c546 1846 * 0 | +/- 250 degrees/s | 131 LSB/deg/s
lixianyu 0:a4d8f5b3c546 1847 * 1 | +/- 500 degrees/s | 65.5 LSB/deg/s
lixianyu 0:a4d8f5b3c546 1848 * 2 | +/- 1000 degrees/s | 32.8 LSB/deg/s
lixianyu 0:a4d8f5b3c546 1849 * 3 | +/- 2000 degrees/s | 16.4 LSB/deg/s
lixianyu 0:a4d8f5b3c546 1850 * </pre>
lixianyu 0:a4d8f5b3c546 1851 *
lixianyu 0:a4d8f5b3c546 1852 * @param x 16-bit signed integer container for X-axis rotation
lixianyu 0:a4d8f5b3c546 1853 * @param y 16-bit signed integer container for Y-axis rotation
lixianyu 0:a4d8f5b3c546 1854 * @param z 16-bit signed integer container for Z-axis rotation
lixianyu 0:a4d8f5b3c546 1855 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1856 * @see MPU6050_RA_GYRO_XOUT_H
lixianyu 0:a4d8f5b3c546 1857 */
lixianyu 0:a4d8f5b3c546 1858 void MPU6050::getRotation(int16_t* x, int16_t* y, int16_t* z) {
lixianyu 0:a4d8f5b3c546 1859 I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 6, buffer);
lixianyu 0:a4d8f5b3c546 1860 *x = (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1861 *y = (((int16_t)buffer[2]) << 8) | buffer[3];
lixianyu 0:a4d8f5b3c546 1862 *z = (((int16_t)buffer[4]) << 8) | buffer[5];
lixianyu 0:a4d8f5b3c546 1863 }
lixianyu 0:a4d8f5b3c546 1864 /** Get X-axis gyroscope reading.
lixianyu 0:a4d8f5b3c546 1865 * @return X-axis rotation measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1866 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1867 * @see MPU6050_RA_GYRO_XOUT_H
lixianyu 0:a4d8f5b3c546 1868 */
lixianyu 0:a4d8f5b3c546 1869 int16_t MPU6050::getRotationX() {
lixianyu 0:a4d8f5b3c546 1870 I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1871 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1872 }
lixianyu 0:a4d8f5b3c546 1873 /** Get Y-axis gyroscope reading.
lixianyu 0:a4d8f5b3c546 1874 * @return Y-axis rotation measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1875 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1876 * @see MPU6050_RA_GYRO_YOUT_H
lixianyu 0:a4d8f5b3c546 1877 */
lixianyu 0:a4d8f5b3c546 1878 int16_t MPU6050::getRotationY() {
lixianyu 0:a4d8f5b3c546 1879 I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_YOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1880 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1881 }
lixianyu 0:a4d8f5b3c546 1882 /** Get Z-axis gyroscope reading.
lixianyu 0:a4d8f5b3c546 1883 * @return Z-axis rotation measurement in 16-bit 2's complement format
lixianyu 0:a4d8f5b3c546 1884 * @see getMotion6()
lixianyu 0:a4d8f5b3c546 1885 * @see MPU6050_RA_GYRO_ZOUT_H
lixianyu 0:a4d8f5b3c546 1886 */
lixianyu 0:a4d8f5b3c546 1887 int16_t MPU6050::getRotationZ() {
lixianyu 0:a4d8f5b3c546 1888 I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_ZOUT_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 1889 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1890 }
lixianyu 0:a4d8f5b3c546 1891
lixianyu 0:a4d8f5b3c546 1892 // EXT_SENS_DATA_* registers
lixianyu 0:a4d8f5b3c546 1893
lixianyu 0:a4d8f5b3c546 1894 /** Read single byte from external sensor data register.
lixianyu 0:a4d8f5b3c546 1895 * These registers store data read from external sensors by the Slave 0, 1, 2,
lixianyu 0:a4d8f5b3c546 1896 * and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in
lixianyu 0:a4d8f5b3c546 1897 * I2C_SLV4_DI (Register 53).
lixianyu 0:a4d8f5b3c546 1898 *
lixianyu 0:a4d8f5b3c546 1899 * External sensor data is written to these registers at the Sample Rate as
lixianyu 0:a4d8f5b3c546 1900 * defined in Register 25. This access rate can be reduced by using the Slave
lixianyu 0:a4d8f5b3c546 1901 * Delay Enable registers (Register 103).
lixianyu 0:a4d8f5b3c546 1902 *
lixianyu 0:a4d8f5b3c546 1903 * External sensor data registers, along with the gyroscope measurement
lixianyu 0:a4d8f5b3c546 1904 * registers, accelerometer measurement registers, and temperature measurement
lixianyu 0:a4d8f5b3c546 1905 * registers, are composed of two sets of registers: an internal register set
lixianyu 0:a4d8f5b3c546 1906 * and a user-facing read register set.
lixianyu 0:a4d8f5b3c546 1907 *
lixianyu 0:a4d8f5b3c546 1908 * The data within the external sensors' internal register set is always updated
lixianyu 0:a4d8f5b3c546 1909 * at the Sample Rate (or the reduced access rate) whenever the serial interface
lixianyu 0:a4d8f5b3c546 1910 * is idle. This guarantees that a burst read of sensor registers will read
lixianyu 0:a4d8f5b3c546 1911 * measurements from the same sampling instant. Note that if burst reads are not
lixianyu 0:a4d8f5b3c546 1912 * used, the user is responsible for ensuring a set of single byte reads
lixianyu 0:a4d8f5b3c546 1913 * correspond to a single sampling instant by checking the Data Ready interrupt.
lixianyu 0:a4d8f5b3c546 1914 *
lixianyu 0:a4d8f5b3c546 1915 * Data is placed in these external sensor data registers according to
lixianyu 0:a4d8f5b3c546 1916 * I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39,
lixianyu 0:a4d8f5b3c546 1917 * 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from
lixianyu 0:a4d8f5b3c546 1918 * an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as
lixianyu 0:a4d8f5b3c546 1919 * defined in Register 25) or delayed rate (if specified in Register 52 and
lixianyu 0:a4d8f5b3c546 1920 * 103). During each Sample cycle, slave reads are performed in order of Slave
lixianyu 0:a4d8f5b3c546 1921 * number. If all slaves are enabled with more than zero bytes to be read, the
lixianyu 0:a4d8f5b3c546 1922 * order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3.
lixianyu 0:a4d8f5b3c546 1923 *
lixianyu 0:a4d8f5b3c546 1924 * Each enabled slave will have EXT_SENS_DATA registers associated with it by
lixianyu 0:a4d8f5b3c546 1925 * number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from
lixianyu 0:a4d8f5b3c546 1926 * EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may
lixianyu 0:a4d8f5b3c546 1927 * change the higher numbered slaves' associated registers. Furthermore, if
lixianyu 0:a4d8f5b3c546 1928 * fewer total bytes are being read from the external sensors as a result of
lixianyu 0:a4d8f5b3c546 1929 * such a change, then the data remaining in the registers which no longer have
lixianyu 0:a4d8f5b3c546 1930 * an associated slave device (i.e. high numbered registers) will remain in
lixianyu 0:a4d8f5b3c546 1931 * these previously allocated registers unless reset.
lixianyu 0:a4d8f5b3c546 1932 *
lixianyu 0:a4d8f5b3c546 1933 * If the sum of the read lengths of all SLVx transactions exceed the number of
lixianyu 0:a4d8f5b3c546 1934 * available EXT_SENS_DATA registers, the excess bytes will be dropped. There
lixianyu 0:a4d8f5b3c546 1935 * are 24 EXT_SENS_DATA registers and hence the total read lengths between all
lixianyu 0:a4d8f5b3c546 1936 * the slaves cannot be greater than 24 or some bytes will be lost.
lixianyu 0:a4d8f5b3c546 1937 *
lixianyu 0:a4d8f5b3c546 1938 * Note: Slave 4's behavior is distinct from that of Slaves 0-3. For further
lixianyu 0:a4d8f5b3c546 1939 * information regarding the characteristics of Slave 4, please refer to
lixianyu 0:a4d8f5b3c546 1940 * Registers 49 to 53.
lixianyu 0:a4d8f5b3c546 1941 *
lixianyu 0:a4d8f5b3c546 1942 * EXAMPLE:
lixianyu 0:a4d8f5b3c546 1943 * Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and
lixianyu 0:a4d8f5b3c546 1944 * I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read so that
lixianyu 0:a4d8f5b3c546 1945 * I2C_SLV1_EN = 1 and I2C_SLV1_LEN = 2. In such a situation, EXT_SENS_DATA _00
lixianyu 0:a4d8f5b3c546 1946 * through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05
lixianyu 0:a4d8f5b3c546 1947 * will be associated with Slave 1. If Slave 2 is enabled as well, registers
lixianyu 0:a4d8f5b3c546 1948 * starting from EXT_SENS_DATA_06 will be allocated to Slave 2.
lixianyu 0:a4d8f5b3c546 1949 *
lixianyu 0:a4d8f5b3c546 1950 * If Slave 2 is disabled while Slave 3 is enabled in this same situation, then
lixianyu 0:a4d8f5b3c546 1951 * registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3
lixianyu 0:a4d8f5b3c546 1952 * instead.
lixianyu 0:a4d8f5b3c546 1953 *
lixianyu 0:a4d8f5b3c546 1954 * REGISTER ALLOCATION FOR DYNAMIC DISABLE VS. NORMAL DISABLE:
lixianyu 0:a4d8f5b3c546 1955 * If a slave is disabled at any time, the space initially allocated to the
lixianyu 0:a4d8f5b3c546 1956 * slave in the EXT_SENS_DATA register, will remain associated with that slave.
lixianyu 0:a4d8f5b3c546 1957 * This is to avoid dynamic adjustment of the register allocation.
lixianyu 0:a4d8f5b3c546 1958 *
lixianyu 0:a4d8f5b3c546 1959 * The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all
lixianyu 0:a4d8f5b3c546 1960 * slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106).
lixianyu 0:a4d8f5b3c546 1961 *
lixianyu 0:a4d8f5b3c546 1962 * This above is also true if one of the slaves gets NACKed and stops
lixianyu 0:a4d8f5b3c546 1963 * functioning.
lixianyu 0:a4d8f5b3c546 1964 *
lixianyu 0:a4d8f5b3c546 1965 * @param position Starting position (0-23)
lixianyu 0:a4d8f5b3c546 1966 * @return Byte read from register
lixianyu 0:a4d8f5b3c546 1967 */
lixianyu 0:a4d8f5b3c546 1968 uint8_t MPU6050::getExternalSensorByte(int position) {
lixianyu 0:a4d8f5b3c546 1969 I2Cdev::readByte(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, buffer);
lixianyu 0:a4d8f5b3c546 1970 return buffer[0];
lixianyu 0:a4d8f5b3c546 1971 }
lixianyu 0:a4d8f5b3c546 1972 /** Read word (2 bytes) from external sensor data registers.
lixianyu 0:a4d8f5b3c546 1973 * @param position Starting position (0-21)
lixianyu 0:a4d8f5b3c546 1974 * @return Word read from register
lixianyu 0:a4d8f5b3c546 1975 * @see getExternalSensorByte()
lixianyu 0:a4d8f5b3c546 1976 */
lixianyu 0:a4d8f5b3c546 1977 uint16_t MPU6050::getExternalSensorWord(int position) {
lixianyu 0:a4d8f5b3c546 1978 I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 2, buffer);
lixianyu 0:a4d8f5b3c546 1979 return (((uint16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 1980 }
lixianyu 0:a4d8f5b3c546 1981 /** Read double word (4 bytes) from external sensor data registers.
lixianyu 0:a4d8f5b3c546 1982 * @param position Starting position (0-20)
lixianyu 0:a4d8f5b3c546 1983 * @return Double word read from registers
lixianyu 0:a4d8f5b3c546 1984 * @see getExternalSensorByte()
lixianyu 0:a4d8f5b3c546 1985 */
lixianyu 0:a4d8f5b3c546 1986 uint32_t MPU6050::getExternalSensorDWord(int position) {
lixianyu 0:a4d8f5b3c546 1987 I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 4, buffer);
lixianyu 0:a4d8f5b3c546 1988 return (((uint32_t)buffer[0]) << 24) | (((uint32_t)buffer[1]) << 16) | (((uint16_t)buffer[2]) << 8) | buffer[3];
lixianyu 0:a4d8f5b3c546 1989 }
lixianyu 0:a4d8f5b3c546 1990
lixianyu 0:a4d8f5b3c546 1991 // MOT_DETECT_STATUS register
lixianyu 0:a4d8f5b3c546 1992
lixianyu 0:a4d8f5b3c546 1993 /** Get X-axis negative motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 1994 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 1995 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 1996 * @see MPU6050_MOTION_MOT_XNEG_BIT
lixianyu 0:a4d8f5b3c546 1997 */
lixianyu 0:a4d8f5b3c546 1998 bool MPU6050::getXNegMotionDetected() {
lixianyu 0:a4d8f5b3c546 1999 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XNEG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2000 return buffer[0];
lixianyu 0:a4d8f5b3c546 2001 }
lixianyu 0:a4d8f5b3c546 2002 /** Get X-axis positive motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2003 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2004 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2005 * @see MPU6050_MOTION_MOT_XPOS_BIT
lixianyu 0:a4d8f5b3c546 2006 */
lixianyu 0:a4d8f5b3c546 2007 bool MPU6050::getXPosMotionDetected() {
lixianyu 0:a4d8f5b3c546 2008 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XPOS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2009 return buffer[0];
lixianyu 0:a4d8f5b3c546 2010 }
lixianyu 0:a4d8f5b3c546 2011 /** Get Y-axis negative motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2012 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2013 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2014 * @see MPU6050_MOTION_MOT_YNEG_BIT
lixianyu 0:a4d8f5b3c546 2015 */
lixianyu 0:a4d8f5b3c546 2016 bool MPU6050::getYNegMotionDetected() {
lixianyu 0:a4d8f5b3c546 2017 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YNEG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2018 return buffer[0];
lixianyu 0:a4d8f5b3c546 2019 }
lixianyu 0:a4d8f5b3c546 2020 /** Get Y-axis positive motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2021 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2022 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2023 * @see MPU6050_MOTION_MOT_YPOS_BIT
lixianyu 0:a4d8f5b3c546 2024 */
lixianyu 0:a4d8f5b3c546 2025 bool MPU6050::getYPosMotionDetected() {
lixianyu 0:a4d8f5b3c546 2026 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YPOS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2027 return buffer[0];
lixianyu 0:a4d8f5b3c546 2028 }
lixianyu 0:a4d8f5b3c546 2029 /** Get Z-axis negative motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2030 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2031 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2032 * @see MPU6050_MOTION_MOT_ZNEG_BIT
lixianyu 0:a4d8f5b3c546 2033 */
lixianyu 0:a4d8f5b3c546 2034 bool MPU6050::getZNegMotionDetected() {
lixianyu 0:a4d8f5b3c546 2035 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZNEG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2036 return buffer[0];
lixianyu 0:a4d8f5b3c546 2037 }
lixianyu 0:a4d8f5b3c546 2038 /** Get Z-axis positive motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2039 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2040 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2041 * @see MPU6050_MOTION_MOT_ZPOS_BIT
lixianyu 0:a4d8f5b3c546 2042 */
lixianyu 0:a4d8f5b3c546 2043 bool MPU6050::getZPosMotionDetected() {
lixianyu 0:a4d8f5b3c546 2044 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZPOS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2045 return buffer[0];
lixianyu 0:a4d8f5b3c546 2046 }
lixianyu 0:a4d8f5b3c546 2047 /** Get zero motion detection interrupt status.
lixianyu 0:a4d8f5b3c546 2048 * @return Motion detection status
lixianyu 0:a4d8f5b3c546 2049 * @see MPU6050_RA_MOT_DETECT_STATUS
lixianyu 0:a4d8f5b3c546 2050 * @see MPU6050_MOTION_MOT_ZRMOT_BIT
lixianyu 0:a4d8f5b3c546 2051 */
lixianyu 0:a4d8f5b3c546 2052 bool MPU6050::getZeroMotionDetected() {
lixianyu 0:a4d8f5b3c546 2053 I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZRMOT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2054 return buffer[0];
lixianyu 0:a4d8f5b3c546 2055 }
lixianyu 0:a4d8f5b3c546 2056
lixianyu 0:a4d8f5b3c546 2057 // I2C_SLV*_DO register
lixianyu 0:a4d8f5b3c546 2058
lixianyu 0:a4d8f5b3c546 2059 /** Write byte to Data Output container for specified slave.
lixianyu 0:a4d8f5b3c546 2060 * This register holds the output data written into Slave when Slave is set to
lixianyu 0:a4d8f5b3c546 2061 * write mode. For further information regarding Slave control, please
lixianyu 0:a4d8f5b3c546 2062 * refer to Registers 37 to 39 and immediately following.
lixianyu 0:a4d8f5b3c546 2063 * @param num Slave number (0-3)
lixianyu 0:a4d8f5b3c546 2064 * @param data Byte to write
lixianyu 0:a4d8f5b3c546 2065 * @see MPU6050_RA_I2C_SLV0_DO
lixianyu 0:a4d8f5b3c546 2066 */
lixianyu 0:a4d8f5b3c546 2067 void MPU6050::setSlaveOutputByte(uint8_t num, uint8_t data) {
lixianyu 0:a4d8f5b3c546 2068 if (num > 3) return;
lixianyu 0:a4d8f5b3c546 2069 I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_DO + num, data);
lixianyu 0:a4d8f5b3c546 2070 }
lixianyu 0:a4d8f5b3c546 2071
lixianyu 0:a4d8f5b3c546 2072 // I2C_MST_DELAY_CTRL register
lixianyu 0:a4d8f5b3c546 2073
lixianyu 0:a4d8f5b3c546 2074 /** Get external data shadow delay enabled status.
lixianyu 0:a4d8f5b3c546 2075 * This register is used to specify the timing of external sensor data
lixianyu 0:a4d8f5b3c546 2076 * shadowing. When DELAY_ES_SHADOW is set to 1, shadowing of external
lixianyu 0:a4d8f5b3c546 2077 * sensor data is delayed until all data has been received.
lixianyu 0:a4d8f5b3c546 2078 * @return Current external data shadow delay enabled status.
lixianyu 0:a4d8f5b3c546 2079 * @see MPU6050_RA_I2C_MST_DELAY_CTRL
lixianyu 0:a4d8f5b3c546 2080 * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT
lixianyu 0:a4d8f5b3c546 2081 */
lixianyu 0:a4d8f5b3c546 2082 bool MPU6050::getExternalShadowDelayEnabled() {
lixianyu 0:a4d8f5b3c546 2083 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2084 return buffer[0];
lixianyu 0:a4d8f5b3c546 2085 }
lixianyu 0:a4d8f5b3c546 2086 /** Set external data shadow delay enabled status.
lixianyu 0:a4d8f5b3c546 2087 * @param enabled New external data shadow delay enabled status.
lixianyu 0:a4d8f5b3c546 2088 * @see getExternalShadowDelayEnabled()
lixianyu 0:a4d8f5b3c546 2089 * @see MPU6050_RA_I2C_MST_DELAY_CTRL
lixianyu 0:a4d8f5b3c546 2090 * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT
lixianyu 0:a4d8f5b3c546 2091 */
lixianyu 0:a4d8f5b3c546 2092 void MPU6050::setExternalShadowDelayEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2093 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2094 }
lixianyu 0:a4d8f5b3c546 2095 /** Get slave delay enabled status.
lixianyu 0:a4d8f5b3c546 2096 * When a particular slave delay is enabled, the rate of access for the that
lixianyu 0:a4d8f5b3c546 2097 * slave device is reduced. When a slave's access rate is decreased relative to
lixianyu 0:a4d8f5b3c546 2098 * the Sample Rate, the slave is accessed every:
lixianyu 0:a4d8f5b3c546 2099 *
lixianyu 0:a4d8f5b3c546 2100 * 1 / (1 + I2C_MST_DLY) Samples
lixianyu 0:a4d8f5b3c546 2101 *
lixianyu 0:a4d8f5b3c546 2102 * This base Sample Rate in turn is determined by SMPLRT_DIV (register * 25)
lixianyu 0:a4d8f5b3c546 2103 * and DLPF_CFG (register 26).
lixianyu 0:a4d8f5b3c546 2104 *
lixianyu 0:a4d8f5b3c546 2105 * For further information regarding I2C_MST_DLY, please refer to register 52.
lixianyu 0:a4d8f5b3c546 2106 * For further information regarding the Sample Rate, please refer to register 25.
lixianyu 0:a4d8f5b3c546 2107 *
lixianyu 0:a4d8f5b3c546 2108 * @param num Slave number (0-4)
lixianyu 0:a4d8f5b3c546 2109 * @return Current slave delay enabled status.
lixianyu 0:a4d8f5b3c546 2110 * @see MPU6050_RA_I2C_MST_DELAY_CTRL
lixianyu 0:a4d8f5b3c546 2111 * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT
lixianyu 0:a4d8f5b3c546 2112 */
lixianyu 0:a4d8f5b3c546 2113 bool MPU6050::getSlaveDelayEnabled(uint8_t num) {
lixianyu 0:a4d8f5b3c546 2114 // MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT is 4, SLV3 is 3, etc.
lixianyu 0:a4d8f5b3c546 2115 if (num > 4) return 0;
lixianyu 0:a4d8f5b3c546 2116 I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, buffer);
lixianyu 0:a4d8f5b3c546 2117 return buffer[0];
lixianyu 0:a4d8f5b3c546 2118 }
lixianyu 0:a4d8f5b3c546 2119 /** Set slave delay enabled status.
lixianyu 0:a4d8f5b3c546 2120 * @param num Slave number (0-4)
lixianyu 0:a4d8f5b3c546 2121 * @param enabled New slave delay enabled status.
lixianyu 0:a4d8f5b3c546 2122 * @see MPU6050_RA_I2C_MST_DELAY_CTRL
lixianyu 0:a4d8f5b3c546 2123 * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT
lixianyu 0:a4d8f5b3c546 2124 */
lixianyu 0:a4d8f5b3c546 2125 void MPU6050::setSlaveDelayEnabled(uint8_t num, bool enabled) {
lixianyu 0:a4d8f5b3c546 2126 I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, enabled);
lixianyu 0:a4d8f5b3c546 2127 }
lixianyu 0:a4d8f5b3c546 2128
lixianyu 0:a4d8f5b3c546 2129 // SIGNAL_PATH_RESET register
lixianyu 0:a4d8f5b3c546 2130
lixianyu 0:a4d8f5b3c546 2131 /** Reset gyroscope signal path.
lixianyu 0:a4d8f5b3c546 2132 * The reset will revert the signal path analog to digital converters and
lixianyu 0:a4d8f5b3c546 2133 * filters to their power up configurations.
lixianyu 0:a4d8f5b3c546 2134 * @see MPU6050_RA_SIGNAL_PATH_RESET
lixianyu 0:a4d8f5b3c546 2135 * @see MPU6050_PATHRESET_GYRO_RESET_BIT
lixianyu 0:a4d8f5b3c546 2136 */
lixianyu 0:a4d8f5b3c546 2137 void MPU6050::resetGyroscopePath() {
lixianyu 0:a4d8f5b3c546 2138 I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_GYRO_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2139 }
lixianyu 0:a4d8f5b3c546 2140 /** Reset accelerometer signal path.
lixianyu 0:a4d8f5b3c546 2141 * The reset will revert the signal path analog to digital converters and
lixianyu 0:a4d8f5b3c546 2142 * filters to their power up configurations.
lixianyu 0:a4d8f5b3c546 2143 * @see MPU6050_RA_SIGNAL_PATH_RESET
lixianyu 0:a4d8f5b3c546 2144 * @see MPU6050_PATHRESET_ACCEL_RESET_BIT
lixianyu 0:a4d8f5b3c546 2145 */
lixianyu 0:a4d8f5b3c546 2146 void MPU6050::resetAccelerometerPath() {
lixianyu 0:a4d8f5b3c546 2147 I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_ACCEL_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2148 }
lixianyu 0:a4d8f5b3c546 2149 /** Reset temperature sensor signal path.
lixianyu 0:a4d8f5b3c546 2150 * The reset will revert the signal path analog to digital converters and
lixianyu 0:a4d8f5b3c546 2151 * filters to their power up configurations.
lixianyu 0:a4d8f5b3c546 2152 * @see MPU6050_RA_SIGNAL_PATH_RESET
lixianyu 0:a4d8f5b3c546 2153 * @see MPU6050_PATHRESET_TEMP_RESET_BIT
lixianyu 0:a4d8f5b3c546 2154 */
lixianyu 0:a4d8f5b3c546 2155 void MPU6050::resetTemperaturePath() {
lixianyu 0:a4d8f5b3c546 2156 I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_TEMP_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2157 }
lixianyu 0:a4d8f5b3c546 2158
lixianyu 0:a4d8f5b3c546 2159 // MOT_DETECT_CTRL register
lixianyu 0:a4d8f5b3c546 2160
lixianyu 0:a4d8f5b3c546 2161 /** Get accelerometer power-on delay.
lixianyu 0:a4d8f5b3c546 2162 * The accelerometer data path provides samples to the sensor registers, Motion
lixianyu 0:a4d8f5b3c546 2163 * detection, Zero Motion detection, and Free Fall detection modules. The
lixianyu 0:a4d8f5b3c546 2164 * signal path contains filters which must be flushed on wake-up with new
lixianyu 0:a4d8f5b3c546 2165 * samples before the detection modules begin operations. The default wake-up
lixianyu 0:a4d8f5b3c546 2166 * delay, of 4ms can be lengthened by up to 3ms. This additional delay is
lixianyu 0:a4d8f5b3c546 2167 * specified in ACCEL_ON_DELAY in units of 1 LSB = 1 ms. The user may select
lixianyu 0:a4d8f5b3c546 2168 * any value above zero unless instructed otherwise by InvenSense. Please refer
lixianyu 0:a4d8f5b3c546 2169 * to Section 8 of the MPU-6000/MPU-6050 Product Specification document for
lixianyu 0:a4d8f5b3c546 2170 * further information regarding the detection modules.
lixianyu 0:a4d8f5b3c546 2171 * @return Current accelerometer power-on delay
lixianyu 0:a4d8f5b3c546 2172 * @see MPU6050_RA_MOT_DETECT_CTRL
lixianyu 0:a4d8f5b3c546 2173 * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT
lixianyu 0:a4d8f5b3c546 2174 */
lixianyu 0:a4d8f5b3c546 2175 uint8_t MPU6050::getAccelerometerPowerOnDelay() {
lixianyu 0:a4d8f5b3c546 2176 I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2177 return buffer[0];
lixianyu 0:a4d8f5b3c546 2178 }
lixianyu 0:a4d8f5b3c546 2179 /** Set accelerometer power-on delay.
lixianyu 0:a4d8f5b3c546 2180 * @param delay New accelerometer power-on delay (0-3)
lixianyu 0:a4d8f5b3c546 2181 * @see getAccelerometerPowerOnDelay()
lixianyu 0:a4d8f5b3c546 2182 * @see MPU6050_RA_MOT_DETECT_CTRL
lixianyu 0:a4d8f5b3c546 2183 * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT
lixianyu 0:a4d8f5b3c546 2184 */
lixianyu 0:a4d8f5b3c546 2185 void MPU6050::setAccelerometerPowerOnDelay(uint8_t delay) {
lixianyu 0:a4d8f5b3c546 2186 I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, delay);
lixianyu 0:a4d8f5b3c546 2187 }
lixianyu 0:a4d8f5b3c546 2188 /** Get Free Fall detection counter decrement configuration.
lixianyu 0:a4d8f5b3c546 2189 * Detection is registered by the Free Fall detection module after accelerometer
lixianyu 0:a4d8f5b3c546 2190 * measurements meet their respective threshold conditions over a specified
lixianyu 0:a4d8f5b3c546 2191 * number of samples. When the threshold conditions are met, the corresponding
lixianyu 0:a4d8f5b3c546 2192 * detection counter increments by 1. The user may control the rate at which the
lixianyu 0:a4d8f5b3c546 2193 * detection counter decrements when the threshold condition is not met by
lixianyu 0:a4d8f5b3c546 2194 * configuring FF_COUNT. The decrement rate can be set according to the
lixianyu 0:a4d8f5b3c546 2195 * following table:
lixianyu 0:a4d8f5b3c546 2196 *
lixianyu 0:a4d8f5b3c546 2197 * <pre>
lixianyu 0:a4d8f5b3c546 2198 * FF_COUNT | Counter Decrement
lixianyu 0:a4d8f5b3c546 2199 * ---------+------------------
lixianyu 0:a4d8f5b3c546 2200 * 0 | Reset
lixianyu 0:a4d8f5b3c546 2201 * 1 | 1
lixianyu 0:a4d8f5b3c546 2202 * 2 | 2
lixianyu 0:a4d8f5b3c546 2203 * 3 | 4
lixianyu 0:a4d8f5b3c546 2204 * </pre>
lixianyu 0:a4d8f5b3c546 2205 *
lixianyu 0:a4d8f5b3c546 2206 * When FF_COUNT is configured to 0 (reset), any non-qualifying sample will
lixianyu 0:a4d8f5b3c546 2207 * reset the counter to 0. For further information on Free Fall detection,
lixianyu 0:a4d8f5b3c546 2208 * please refer to Registers 29 to 32.
lixianyu 0:a4d8f5b3c546 2209 *
lixianyu 0:a4d8f5b3c546 2210 * @return Current decrement configuration
lixianyu 0:a4d8f5b3c546 2211 * @see MPU6050_RA_MOT_DETECT_CTRL
lixianyu 0:a4d8f5b3c546 2212 * @see MPU6050_DETECT_FF_COUNT_BIT
lixianyu 0:a4d8f5b3c546 2213 */
lixianyu 0:a4d8f5b3c546 2214 uint8_t MPU6050::getFreefallDetectionCounterDecrement() {
lixianyu 0:a4d8f5b3c546 2215 I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2216 return buffer[0];
lixianyu 0:a4d8f5b3c546 2217 }
lixianyu 0:a4d8f5b3c546 2218 /** Set Free Fall detection counter decrement configuration.
lixianyu 0:a4d8f5b3c546 2219 * @param decrement New decrement configuration value
lixianyu 0:a4d8f5b3c546 2220 * @see getFreefallDetectionCounterDecrement()
lixianyu 0:a4d8f5b3c546 2221 * @see MPU6050_RA_MOT_DETECT_CTRL
lixianyu 0:a4d8f5b3c546 2222 * @see MPU6050_DETECT_FF_COUNT_BIT
lixianyu 0:a4d8f5b3c546 2223 */
lixianyu 0:a4d8f5b3c546 2224 void MPU6050::setFreefallDetectionCounterDecrement(uint8_t decrement) {
lixianyu 0:a4d8f5b3c546 2225 I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, decrement);
lixianyu 0:a4d8f5b3c546 2226 }
lixianyu 0:a4d8f5b3c546 2227 /** Get Motion detection counter decrement configuration.
lixianyu 0:a4d8f5b3c546 2228 * Detection is registered by the Motion detection module after accelerometer
lixianyu 0:a4d8f5b3c546 2229 * measurements meet their respective threshold conditions over a specified
lixianyu 0:a4d8f5b3c546 2230 * number of samples. When the threshold conditions are met, the corresponding
lixianyu 0:a4d8f5b3c546 2231 * detection counter increments by 1. The user may control the rate at which the
lixianyu 0:a4d8f5b3c546 2232 * detection counter decrements when the threshold condition is not met by
lixianyu 0:a4d8f5b3c546 2233 * configuring MOT_COUNT. The decrement rate can be set according to the
lixianyu 0:a4d8f5b3c546 2234 * following table:
lixianyu 0:a4d8f5b3c546 2235 *
lixianyu 0:a4d8f5b3c546 2236 * <pre>
lixianyu 0:a4d8f5b3c546 2237 * MOT_COUNT | Counter Decrement
lixianyu 0:a4d8f5b3c546 2238 * ----------+------------------
lixianyu 0:a4d8f5b3c546 2239 * 0 | Reset
lixianyu 0:a4d8f5b3c546 2240 * 1 | 1
lixianyu 0:a4d8f5b3c546 2241 * 2 | 2
lixianyu 0:a4d8f5b3c546 2242 * 3 | 4
lixianyu 0:a4d8f5b3c546 2243 * </pre>
lixianyu 0:a4d8f5b3c546 2244 *
lixianyu 0:a4d8f5b3c546 2245 * When MOT_COUNT is configured to 0 (reset), any non-qualifying sample will
lixianyu 0:a4d8f5b3c546 2246 * reset the counter to 0. For further information on Motion detection,
lixianyu 0:a4d8f5b3c546 2247 * please refer to Registers 29 to 32.
lixianyu 0:a4d8f5b3c546 2248 *
lixianyu 0:a4d8f5b3c546 2249 */
lixianyu 0:a4d8f5b3c546 2250 uint8_t MPU6050::getMotionDetectionCounterDecrement() {
lixianyu 0:a4d8f5b3c546 2251 I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2252 return buffer[0];
lixianyu 0:a4d8f5b3c546 2253 }
lixianyu 0:a4d8f5b3c546 2254 /** Set Motion detection counter decrement configuration.
lixianyu 0:a4d8f5b3c546 2255 * @param decrement New decrement configuration value
lixianyu 0:a4d8f5b3c546 2256 * @see getMotionDetectionCounterDecrement()
lixianyu 0:a4d8f5b3c546 2257 * @see MPU6050_RA_MOT_DETECT_CTRL
lixianyu 0:a4d8f5b3c546 2258 * @see MPU6050_DETECT_MOT_COUNT_BIT
lixianyu 0:a4d8f5b3c546 2259 */
lixianyu 0:a4d8f5b3c546 2260 void MPU6050::setMotionDetectionCounterDecrement(uint8_t decrement) {
lixianyu 0:a4d8f5b3c546 2261 I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, decrement);
lixianyu 0:a4d8f5b3c546 2262 }
lixianyu 0:a4d8f5b3c546 2263
lixianyu 0:a4d8f5b3c546 2264 // USER_CTRL register
lixianyu 0:a4d8f5b3c546 2265
lixianyu 0:a4d8f5b3c546 2266 /** Get FIFO enabled status.
lixianyu 0:a4d8f5b3c546 2267 * When this bit is set to 0, the FIFO buffer is disabled. The FIFO buffer
lixianyu 0:a4d8f5b3c546 2268 * cannot be written to or read from while disabled. The FIFO buffer's state
lixianyu 0:a4d8f5b3c546 2269 * does not change unless the MPU-60X0 is power cycled.
lixianyu 0:a4d8f5b3c546 2270 * @return Current FIFO enabled status
lixianyu 0:a4d8f5b3c546 2271 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2272 * @see MPU6050_USERCTRL_FIFO_EN_BIT
lixianyu 0:a4d8f5b3c546 2273 */
lixianyu 0:a4d8f5b3c546 2274 bool MPU6050::getFIFOEnabled() {
lixianyu 0:a4d8f5b3c546 2275 I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2276 return buffer[0];
lixianyu 0:a4d8f5b3c546 2277 }
lixianyu 0:a4d8f5b3c546 2278 /** Set FIFO enabled status.
lixianyu 0:a4d8f5b3c546 2279 * @param enabled New FIFO enabled status
lixianyu 0:a4d8f5b3c546 2280 * @see getFIFOEnabled()
lixianyu 0:a4d8f5b3c546 2281 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2282 * @see MPU6050_USERCTRL_FIFO_EN_BIT
lixianyu 0:a4d8f5b3c546 2283 */
lixianyu 0:a4d8f5b3c546 2284 void MPU6050::setFIFOEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2285 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2286 }
lixianyu 0:a4d8f5b3c546 2287 /** Get I2C Master Mode enabled status.
lixianyu 0:a4d8f5b3c546 2288 * When this mode is enabled, the MPU-60X0 acts as the I2C Master to the
lixianyu 0:a4d8f5b3c546 2289 * external sensor slave devices on the auxiliary I2C bus. When this bit is
lixianyu 0:a4d8f5b3c546 2290 * cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically
lixianyu 0:a4d8f5b3c546 2291 * driven by the primary I2C bus (SDA and SCL). This is a precondition to
lixianyu 0:a4d8f5b3c546 2292 * enabling Bypass Mode. For further information regarding Bypass Mode, please
lixianyu 0:a4d8f5b3c546 2293 * refer to Register 55.
lixianyu 0:a4d8f5b3c546 2294 * @return Current I2C Master Mode enabled status
lixianyu 0:a4d8f5b3c546 2295 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2296 * @see MPU6050_USERCTRL_I2C_MST_EN_BIT
lixianyu 0:a4d8f5b3c546 2297 */
lixianyu 0:a4d8f5b3c546 2298 bool MPU6050::getI2CMasterModeEnabled() {
lixianyu 0:a4d8f5b3c546 2299 I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2300 return buffer[0];
lixianyu 0:a4d8f5b3c546 2301 }
lixianyu 0:a4d8f5b3c546 2302 /** Set I2C Master Mode enabled status.
lixianyu 0:a4d8f5b3c546 2303 * @param enabled New I2C Master Mode enabled status
lixianyu 0:a4d8f5b3c546 2304 * @see getI2CMasterModeEnabled()
lixianyu 0:a4d8f5b3c546 2305 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2306 * @see MPU6050_USERCTRL_I2C_MST_EN_BIT
lixianyu 0:a4d8f5b3c546 2307 */
lixianyu 0:a4d8f5b3c546 2308 void MPU6050::setI2CMasterModeEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2309 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2310 }
lixianyu 0:a4d8f5b3c546 2311 /** Switch from I2C to SPI mode (MPU-6000 only)
lixianyu 0:a4d8f5b3c546 2312 * If this is set, the primary SPI interface will be enabled in place of the
lixianyu 0:a4d8f5b3c546 2313 * disabled primary I2C interface.
lixianyu 0:a4d8f5b3c546 2314 */
lixianyu 0:a4d8f5b3c546 2315 void MPU6050::switchSPIEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2316 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_IF_DIS_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2317 }
lixianyu 0:a4d8f5b3c546 2318 /** Reset the FIFO.
lixianyu 0:a4d8f5b3c546 2319 * This bit resets the FIFO buffer when set to 1 while FIFO_EN equals 0. This
lixianyu 0:a4d8f5b3c546 2320 * bit automatically clears to 0 after the reset has been triggered.
lixianyu 0:a4d8f5b3c546 2321 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2322 * @see MPU6050_USERCTRL_FIFO_RESET_BIT
lixianyu 0:a4d8f5b3c546 2323 */
lixianyu 0:a4d8f5b3c546 2324 void MPU6050::resetFIFO() {
lixianyu 0:a4d8f5b3c546 2325 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2326 }
lixianyu 0:a4d8f5b3c546 2327 /** Reset the I2C Master.
lixianyu 0:a4d8f5b3c546 2328 * This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0.
lixianyu 0:a4d8f5b3c546 2329 * This bit automatically clears to 0 after the reset has been triggered.
lixianyu 0:a4d8f5b3c546 2330 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2331 * @see MPU6050_USERCTRL_I2C_MST_RESET_BIT
lixianyu 0:a4d8f5b3c546 2332 */
lixianyu 0:a4d8f5b3c546 2333 void MPU6050::resetI2CMaster() {
lixianyu 0:a4d8f5b3c546 2334 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2335 }
lixianyu 0:a4d8f5b3c546 2336 /** Reset all sensor registers and signal paths.
lixianyu 0:a4d8f5b3c546 2337 * When set to 1, this bit resets the signal paths for all sensors (gyroscopes,
lixianyu 0:a4d8f5b3c546 2338 * accelerometers, and temperature sensor). This operation will also clear the
lixianyu 0:a4d8f5b3c546 2339 * sensor registers. This bit automatically clears to 0 after the reset has been
lixianyu 0:a4d8f5b3c546 2340 * triggered.
lixianyu 0:a4d8f5b3c546 2341 *
lixianyu 0:a4d8f5b3c546 2342 * When resetting only the signal path (and not the sensor registers), please
lixianyu 0:a4d8f5b3c546 2343 * use Register 104, SIGNAL_PATH_RESET.
lixianyu 0:a4d8f5b3c546 2344 *
lixianyu 0:a4d8f5b3c546 2345 * @see MPU6050_RA_USER_CTRL
lixianyu 0:a4d8f5b3c546 2346 * @see MPU6050_USERCTRL_SIG_COND_RESET_BIT
lixianyu 0:a4d8f5b3c546 2347 */
lixianyu 0:a4d8f5b3c546 2348 void MPU6050::resetSensors() {
lixianyu 0:a4d8f5b3c546 2349 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_SIG_COND_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2350 }
lixianyu 0:a4d8f5b3c546 2351
lixianyu 0:a4d8f5b3c546 2352 // PWR_MGMT_1 register
lixianyu 0:a4d8f5b3c546 2353
lixianyu 0:a4d8f5b3c546 2354 /** Trigger a full device reset.
lixianyu 0:a4d8f5b3c546 2355 * A small delay of ~50ms may be desirable after triggering a reset.
lixianyu 0:a4d8f5b3c546 2356 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2357 * @see MPU6050_PWR1_DEVICE_RESET_BIT
lixianyu 0:a4d8f5b3c546 2358 */
lixianyu 0:a4d8f5b3c546 2359 void MPU6050::reset() {
lixianyu 0:a4d8f5b3c546 2360 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_DEVICE_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2361 }
lixianyu 0:a4d8f5b3c546 2362 /** Get sleep mode status.
lixianyu 0:a4d8f5b3c546 2363 * Setting the SLEEP bit in the register puts the device into very low power
lixianyu 0:a4d8f5b3c546 2364 * sleep mode. In this mode, only the serial interface and internal registers
lixianyu 0:a4d8f5b3c546 2365 * remain active, allowing for a very low standby current. Clearing this bit
lixianyu 0:a4d8f5b3c546 2366 * puts the device back into normal mode. To save power, the individual standby
lixianyu 0:a4d8f5b3c546 2367 * selections for each of the gyros should be used if any gyro axis is not used
lixianyu 0:a4d8f5b3c546 2368 * by the application.
lixianyu 0:a4d8f5b3c546 2369 * @return Current sleep mode enabled status
lixianyu 0:a4d8f5b3c546 2370 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2371 * @see MPU6050_PWR1_SLEEP_BIT
lixianyu 0:a4d8f5b3c546 2372 */
lixianyu 0:a4d8f5b3c546 2373 bool MPU6050::getSleepEnabled() {
lixianyu 0:a4d8f5b3c546 2374 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2375 return buffer[0];
lixianyu 0:a4d8f5b3c546 2376 }
lixianyu 0:a4d8f5b3c546 2377 /** Set sleep mode status.
lixianyu 0:a4d8f5b3c546 2378 * @param enabled New sleep mode enabled status
lixianyu 0:a4d8f5b3c546 2379 * @see getSleepEnabled()
lixianyu 0:a4d8f5b3c546 2380 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2381 * @see MPU6050_PWR1_SLEEP_BIT
lixianyu 0:a4d8f5b3c546 2382 */
lixianyu 0:a4d8f5b3c546 2383 void MPU6050::setSleepEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2384 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2385 }
lixianyu 0:a4d8f5b3c546 2386 /** Get wake cycle enabled status.
lixianyu 0:a4d8f5b3c546 2387 * When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle
lixianyu 0:a4d8f5b3c546 2388 * between sleep mode and waking up to take a single sample of data from active
lixianyu 0:a4d8f5b3c546 2389 * sensors at a rate determined by LP_WAKE_CTRL (register 108).
lixianyu 0:a4d8f5b3c546 2390 * @return Current sleep mode enabled status
lixianyu 0:a4d8f5b3c546 2391 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2392 * @see MPU6050_PWR1_CYCLE_BIT
lixianyu 0:a4d8f5b3c546 2393 */
lixianyu 0:a4d8f5b3c546 2394 bool MPU6050::getWakeCycleEnabled() {
lixianyu 0:a4d8f5b3c546 2395 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2396 return buffer[0];
lixianyu 0:a4d8f5b3c546 2397 }
lixianyu 0:a4d8f5b3c546 2398 /** Set wake cycle enabled status.
lixianyu 0:a4d8f5b3c546 2399 * @param enabled New sleep mode enabled status
lixianyu 0:a4d8f5b3c546 2400 * @see getWakeCycleEnabled()
lixianyu 0:a4d8f5b3c546 2401 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2402 * @see MPU6050_PWR1_CYCLE_BIT
lixianyu 0:a4d8f5b3c546 2403 */
lixianyu 0:a4d8f5b3c546 2404 void MPU6050::setWakeCycleEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2405 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2406 }
lixianyu 0:a4d8f5b3c546 2407 /** Get temperature sensor enabled status.
lixianyu 0:a4d8f5b3c546 2408 * Control the usage of the internal temperature sensor.
lixianyu 0:a4d8f5b3c546 2409 *
lixianyu 0:a4d8f5b3c546 2410 * Note: this register stores the *disabled* value, but for consistency with the
lixianyu 0:a4d8f5b3c546 2411 * rest of the code, the function is named and used with standard true/false
lixianyu 0:a4d8f5b3c546 2412 * values to indicate whether the sensor is enabled or disabled, respectively.
lixianyu 0:a4d8f5b3c546 2413 *
lixianyu 0:a4d8f5b3c546 2414 * @return Current temperature sensor enabled status
lixianyu 0:a4d8f5b3c546 2415 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2416 * @see MPU6050_PWR1_TEMP_DIS_BIT
lixianyu 0:a4d8f5b3c546 2417 */
lixianyu 0:a4d8f5b3c546 2418 bool MPU6050::getTempSensorEnabled() {
lixianyu 0:a4d8f5b3c546 2419 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2420 return buffer[0] == 0; // 1 is actually disabled here
lixianyu 0:a4d8f5b3c546 2421 }
lixianyu 0:a4d8f5b3c546 2422 /** Set temperature sensor enabled status.
lixianyu 0:a4d8f5b3c546 2423 * Note: this register stores the *disabled* value, but for consistency with the
lixianyu 0:a4d8f5b3c546 2424 * rest of the code, the function is named and used with standard true/false
lixianyu 0:a4d8f5b3c546 2425 * values to indicate whether the sensor is enabled or disabled, respectively.
lixianyu 0:a4d8f5b3c546 2426 *
lixianyu 0:a4d8f5b3c546 2427 * @param enabled New temperature sensor enabled status
lixianyu 0:a4d8f5b3c546 2428 * @see getTempSensorEnabled()
lixianyu 0:a4d8f5b3c546 2429 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2430 * @see MPU6050_PWR1_TEMP_DIS_BIT
lixianyu 0:a4d8f5b3c546 2431 */
lixianyu 0:a4d8f5b3c546 2432 void MPU6050::setTempSensorEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2433 // 1 is actually disabled here
lixianyu 0:a4d8f5b3c546 2434 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, !enabled);
lixianyu 0:a4d8f5b3c546 2435 }
lixianyu 0:a4d8f5b3c546 2436 /** Get clock source setting.
lixianyu 0:a4d8f5b3c546 2437 * @return Current clock source setting
lixianyu 0:a4d8f5b3c546 2438 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2439 * @see MPU6050_PWR1_CLKSEL_BIT
lixianyu 0:a4d8f5b3c546 2440 * @see MPU6050_PWR1_CLKSEL_LENGTH
lixianyu 0:a4d8f5b3c546 2441 */
lixianyu 0:a4d8f5b3c546 2442 uint8_t MPU6050::getClockSource() {
lixianyu 0:a4d8f5b3c546 2443 I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2444 return buffer[0];
lixianyu 0:a4d8f5b3c546 2445 }
lixianyu 0:a4d8f5b3c546 2446 /** Set clock source setting.
lixianyu 0:a4d8f5b3c546 2447 * An internal 8MHz oscillator, gyroscope based clock, or external sources can
lixianyu 0:a4d8f5b3c546 2448 * be selected as the MPU-60X0 clock source. When the internal 8 MHz oscillator
lixianyu 0:a4d8f5b3c546 2449 * or an external source is chosen as the clock source, the MPU-60X0 can operate
lixianyu 0:a4d8f5b3c546 2450 * in low power modes with the gyroscopes disabled.
lixianyu 0:a4d8f5b3c546 2451 *
lixianyu 0:a4d8f5b3c546 2452 * Upon power up, the MPU-60X0 clock source defaults to the internal oscillator.
lixianyu 0:a4d8f5b3c546 2453 * However, it is highly recommended that the device be configured to use one of
lixianyu 0:a4d8f5b3c546 2454 * the gyroscopes (or an external clock source) as the clock reference for
lixianyu 0:a4d8f5b3c546 2455 * improved stability. The clock source can be selected according to the following table:
lixianyu 0:a4d8f5b3c546 2456 *
lixianyu 0:a4d8f5b3c546 2457 * <pre>
lixianyu 0:a4d8f5b3c546 2458 * CLK_SEL | Clock Source
lixianyu 0:a4d8f5b3c546 2459 * --------+--------------------------------------
lixianyu 0:a4d8f5b3c546 2460 * 0 | Internal oscillator
lixianyu 0:a4d8f5b3c546 2461 * 1 | PLL with X Gyro reference
lixianyu 0:a4d8f5b3c546 2462 * 2 | PLL with Y Gyro reference
lixianyu 0:a4d8f5b3c546 2463 * 3 | PLL with Z Gyro reference
lixianyu 0:a4d8f5b3c546 2464 * 4 | PLL with external 32.768kHz reference
lixianyu 0:a4d8f5b3c546 2465 * 5 | PLL with external 19.2MHz reference
lixianyu 0:a4d8f5b3c546 2466 * 6 | Reserved
lixianyu 0:a4d8f5b3c546 2467 * 7 | Stops the clock and keeps the timing generator in reset
lixianyu 0:a4d8f5b3c546 2468 * </pre>
lixianyu 0:a4d8f5b3c546 2469 *
lixianyu 0:a4d8f5b3c546 2470 * @param source New clock source setting
lixianyu 0:a4d8f5b3c546 2471 * @see getClockSource()
lixianyu 0:a4d8f5b3c546 2472 * @see MPU6050_RA_PWR_MGMT_1
lixianyu 0:a4d8f5b3c546 2473 * @see MPU6050_PWR1_CLKSEL_BIT
lixianyu 0:a4d8f5b3c546 2474 * @see MPU6050_PWR1_CLKSEL_LENGTH
lixianyu 0:a4d8f5b3c546 2475 */
lixianyu 0:a4d8f5b3c546 2476 void MPU6050::setClockSource(uint8_t source) {
lixianyu 0:a4d8f5b3c546 2477 I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source);
lixianyu 0:a4d8f5b3c546 2478 }
lixianyu 0:a4d8f5b3c546 2479
lixianyu 0:a4d8f5b3c546 2480 // PWR_MGMT_2 register
lixianyu 0:a4d8f5b3c546 2481
lixianyu 0:a4d8f5b3c546 2482 /** Get wake frequency in Accel-Only Low Power Mode.
lixianyu 0:a4d8f5b3c546 2483 * The MPU-60X0 can be put into Accerlerometer Only Low Power Mode by setting
lixianyu 0:a4d8f5b3c546 2484 * PWRSEL to 1 in the Power Management 1 register (Register 107). In this mode,
lixianyu 0:a4d8f5b3c546 2485 * the device will power off all devices except for the primary I2C interface,
lixianyu 0:a4d8f5b3c546 2486 * waking only the accelerometer at fixed intervals to take a single
lixianyu 0:a4d8f5b3c546 2487 * measurement. The frequency of wake-ups can be configured with LP_WAKE_CTRL
lixianyu 0:a4d8f5b3c546 2488 * as shown below:
lixianyu 0:a4d8f5b3c546 2489 *
lixianyu 0:a4d8f5b3c546 2490 * <pre>
lixianyu 0:a4d8f5b3c546 2491 * LP_WAKE_CTRL | Wake-up Frequency
lixianyu 0:a4d8f5b3c546 2492 * -------------+------------------
lixianyu 0:a4d8f5b3c546 2493 * 0 | 1.25 Hz
lixianyu 0:a4d8f5b3c546 2494 * 1 | 2.5 Hz
lixianyu 0:a4d8f5b3c546 2495 * 2 | 5 Hz
lixianyu 0:a4d8f5b3c546 2496 * 3 | 10 Hz
lixianyu 0:a4d8f5b3c546 2497 * <pre>
lixianyu 0:a4d8f5b3c546 2498 *
lixianyu 0:a4d8f5b3c546 2499 * For further information regarding the MPU-60X0's power modes, please refer to
lixianyu 0:a4d8f5b3c546 2500 * Register 107.
lixianyu 0:a4d8f5b3c546 2501 *
lixianyu 0:a4d8f5b3c546 2502 * @return Current wake frequency
lixianyu 0:a4d8f5b3c546 2503 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2504 */
lixianyu 0:a4d8f5b3c546 2505 uint8_t MPU6050::getWakeFrequency() {
lixianyu 0:a4d8f5b3c546 2506 I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2507 return buffer[0];
lixianyu 0:a4d8f5b3c546 2508 }
lixianyu 0:a4d8f5b3c546 2509 /** Set wake frequency in Accel-Only Low Power Mode.
lixianyu 0:a4d8f5b3c546 2510 * @param frequency New wake frequency
lixianyu 0:a4d8f5b3c546 2511 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2512 */
lixianyu 0:a4d8f5b3c546 2513 void MPU6050::setWakeFrequency(uint8_t frequency) {
lixianyu 0:a4d8f5b3c546 2514 I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, frequency);
lixianyu 0:a4d8f5b3c546 2515 }
lixianyu 0:a4d8f5b3c546 2516
lixianyu 0:a4d8f5b3c546 2517 /** Get X-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2518 * If enabled, the X-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2519 * @return Current X-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2520 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2521 * @see MPU6050_PWR2_STBY_XA_BIT
lixianyu 0:a4d8f5b3c546 2522 */
lixianyu 0:a4d8f5b3c546 2523 bool MPU6050::getStandbyXAccelEnabled() {
lixianyu 0:a4d8f5b3c546 2524 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2525 return buffer[0];
lixianyu 0:a4d8f5b3c546 2526 }
lixianyu 0:a4d8f5b3c546 2527 /** Set X-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2528 * @param New X-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2529 * @see getStandbyXAccelEnabled()
lixianyu 0:a4d8f5b3c546 2530 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2531 * @see MPU6050_PWR2_STBY_XA_BIT
lixianyu 0:a4d8f5b3c546 2532 */
lixianyu 0:a4d8f5b3c546 2533 void MPU6050::setStandbyXAccelEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2534 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2535 }
lixianyu 0:a4d8f5b3c546 2536 /** Get Y-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2537 * If enabled, the Y-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2538 * @return Current Y-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2539 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2540 * @see MPU6050_PWR2_STBY_YA_BIT
lixianyu 0:a4d8f5b3c546 2541 */
lixianyu 0:a4d8f5b3c546 2542 bool MPU6050::getStandbyYAccelEnabled() {
lixianyu 0:a4d8f5b3c546 2543 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2544 return buffer[0];
lixianyu 0:a4d8f5b3c546 2545 }
lixianyu 0:a4d8f5b3c546 2546 /** Set Y-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2547 * @param New Y-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2548 * @see getStandbyYAccelEnabled()
lixianyu 0:a4d8f5b3c546 2549 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2550 * @see MPU6050_PWR2_STBY_YA_BIT
lixianyu 0:a4d8f5b3c546 2551 */
lixianyu 0:a4d8f5b3c546 2552 void MPU6050::setStandbyYAccelEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2553 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2554 }
lixianyu 0:a4d8f5b3c546 2555 /** Get Z-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2556 * If enabled, the Z-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2557 * @return Current Z-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2558 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2559 * @see MPU6050_PWR2_STBY_ZA_BIT
lixianyu 0:a4d8f5b3c546 2560 */
lixianyu 0:a4d8f5b3c546 2561 bool MPU6050::getStandbyZAccelEnabled() {
lixianyu 0:a4d8f5b3c546 2562 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2563 return buffer[0];
lixianyu 0:a4d8f5b3c546 2564 }
lixianyu 0:a4d8f5b3c546 2565 /** Set Z-axis accelerometer standby enabled status.
lixianyu 0:a4d8f5b3c546 2566 * @param New Z-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2567 * @see getStandbyZAccelEnabled()
lixianyu 0:a4d8f5b3c546 2568 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2569 * @see MPU6050_PWR2_STBY_ZA_BIT
lixianyu 0:a4d8f5b3c546 2570 */
lixianyu 0:a4d8f5b3c546 2571 void MPU6050::setStandbyZAccelEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2572 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2573 }
lixianyu 0:a4d8f5b3c546 2574 /** Get X-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2575 * If enabled, the X-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2576 * @return Current X-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2577 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2578 * @see MPU6050_PWR2_STBY_XG_BIT
lixianyu 0:a4d8f5b3c546 2579 */
lixianyu 0:a4d8f5b3c546 2580 bool MPU6050::getStandbyXGyroEnabled() {
lixianyu 0:a4d8f5b3c546 2581 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2582 return buffer[0];
lixianyu 0:a4d8f5b3c546 2583 }
lixianyu 0:a4d8f5b3c546 2584 /** Set X-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2585 * @param New X-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2586 * @see getStandbyXGyroEnabled()
lixianyu 0:a4d8f5b3c546 2587 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2588 * @see MPU6050_PWR2_STBY_XG_BIT
lixianyu 0:a4d8f5b3c546 2589 */
lixianyu 0:a4d8f5b3c546 2590 void MPU6050::setStandbyXGyroEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2591 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2592 }
lixianyu 0:a4d8f5b3c546 2593 /** Get Y-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2594 * If enabled, the Y-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2595 * @return Current Y-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2596 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2597 * @see MPU6050_PWR2_STBY_YG_BIT
lixianyu 0:a4d8f5b3c546 2598 */
lixianyu 0:a4d8f5b3c546 2599 bool MPU6050::getStandbyYGyroEnabled() {
lixianyu 0:a4d8f5b3c546 2600 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2601 return buffer[0];
lixianyu 0:a4d8f5b3c546 2602 }
lixianyu 0:a4d8f5b3c546 2603 /** Set Y-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2604 * @param New Y-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2605 * @see getStandbyYGyroEnabled()
lixianyu 0:a4d8f5b3c546 2606 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2607 * @see MPU6050_PWR2_STBY_YG_BIT
lixianyu 0:a4d8f5b3c546 2608 */
lixianyu 0:a4d8f5b3c546 2609 void MPU6050::setStandbyYGyroEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2610 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2611 }
lixianyu 0:a4d8f5b3c546 2612 /** Get Z-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2613 * If enabled, the Z-axis will not gather or report data (or use power).
lixianyu 0:a4d8f5b3c546 2614 * @return Current Z-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2615 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2616 * @see MPU6050_PWR2_STBY_ZG_BIT
lixianyu 0:a4d8f5b3c546 2617 */
lixianyu 0:a4d8f5b3c546 2618 bool MPU6050::getStandbyZGyroEnabled() {
lixianyu 0:a4d8f5b3c546 2619 I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2620 return buffer[0];
lixianyu 0:a4d8f5b3c546 2621 }
lixianyu 0:a4d8f5b3c546 2622 /** Set Z-axis gyroscope standby enabled status.
lixianyu 0:a4d8f5b3c546 2623 * @param New Z-axis standby enabled status
lixianyu 0:a4d8f5b3c546 2624 * @see getStandbyZGyroEnabled()
lixianyu 0:a4d8f5b3c546 2625 * @see MPU6050_RA_PWR_MGMT_2
lixianyu 0:a4d8f5b3c546 2626 * @see MPU6050_PWR2_STBY_ZG_BIT
lixianyu 0:a4d8f5b3c546 2627 */
lixianyu 0:a4d8f5b3c546 2628 void MPU6050::setStandbyZGyroEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2629 I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2630 }
lixianyu 0:a4d8f5b3c546 2631
lixianyu 0:a4d8f5b3c546 2632 // FIFO_COUNT* registers
lixianyu 0:a4d8f5b3c546 2633
lixianyu 0:a4d8f5b3c546 2634 /** Get current FIFO buffer size.
lixianyu 0:a4d8f5b3c546 2635 * This value indicates the number of bytes stored in the FIFO buffer. This
lixianyu 0:a4d8f5b3c546 2636 * number is in turn the number of bytes that can be read from the FIFO buffer
lixianyu 0:a4d8f5b3c546 2637 * and it is directly proportional to the number of samples available given the
lixianyu 0:a4d8f5b3c546 2638 * set of sensor data bound to be stored in the FIFO (register 35 and 36).
lixianyu 0:a4d8f5b3c546 2639 * @return Current FIFO buffer size
lixianyu 0:a4d8f5b3c546 2640 */
lixianyu 0:a4d8f5b3c546 2641 uint16_t MPU6050::getFIFOCount() {
lixianyu 0:a4d8f5b3c546 2642 I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_COUNTH, 2, buffer);
lixianyu 0:a4d8f5b3c546 2643 return (((uint16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2644 }
lixianyu 0:a4d8f5b3c546 2645
lixianyu 0:a4d8f5b3c546 2646 // FIFO_R_W register
lixianyu 0:a4d8f5b3c546 2647
lixianyu 0:a4d8f5b3c546 2648 /** Get byte from FIFO buffer.
lixianyu 0:a4d8f5b3c546 2649 * This register is used to read and write data from the FIFO buffer. Data is
lixianyu 0:a4d8f5b3c546 2650 * written to the FIFO in order of register number (from lowest to highest). If
lixianyu 0:a4d8f5b3c546 2651 * all the FIFO enable flags (see below) are enabled and all External Sensor
lixianyu 0:a4d8f5b3c546 2652 * Data registers (Registers 73 to 96) are associated with a Slave device, the
lixianyu 0:a4d8f5b3c546 2653 * contents of registers 59 through 96 will be written in order at the Sample
lixianyu 0:a4d8f5b3c546 2654 * Rate.
lixianyu 0:a4d8f5b3c546 2655 *
lixianyu 0:a4d8f5b3c546 2656 * The contents of the sensor data registers (Registers 59 to 96) are written
lixianyu 0:a4d8f5b3c546 2657 * into the FIFO buffer when their corresponding FIFO enable flags are set to 1
lixianyu 0:a4d8f5b3c546 2658 * in FIFO_EN (Register 35). An additional flag for the sensor data registers
lixianyu 0:a4d8f5b3c546 2659 * associated with I2C Slave 3 can be found in I2C_MST_CTRL (Register 36).
lixianyu 0:a4d8f5b3c546 2660 *
lixianyu 0:a4d8f5b3c546 2661 * If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is
lixianyu 0:a4d8f5b3c546 2662 * automatically set to 1. This bit is located in INT_STATUS (Register 58).
lixianyu 0:a4d8f5b3c546 2663 * When the FIFO buffer has overflowed, the oldest data will be lost and new
lixianyu 0:a4d8f5b3c546 2664 * data will be written to the FIFO.
lixianyu 0:a4d8f5b3c546 2665 *
lixianyu 0:a4d8f5b3c546 2666 * If the FIFO buffer is empty, reading this register will return the last byte
lixianyu 0:a4d8f5b3c546 2667 * that was previously read from the FIFO until new data is available. The user
lixianyu 0:a4d8f5b3c546 2668 * should check FIFO_COUNT to ensure that the FIFO buffer is not read when
lixianyu 0:a4d8f5b3c546 2669 * empty.
lixianyu 0:a4d8f5b3c546 2670 *
lixianyu 0:a4d8f5b3c546 2671 * @return Byte from FIFO buffer
lixianyu 0:a4d8f5b3c546 2672 */
lixianyu 0:a4d8f5b3c546 2673 uint8_t MPU6050::getFIFOByte() {
lixianyu 0:a4d8f5b3c546 2674 I2Cdev::readByte(devAddr, MPU6050_RA_FIFO_R_W, buffer);
lixianyu 0:a4d8f5b3c546 2675 return buffer[0];
lixianyu 0:a4d8f5b3c546 2676 }
lixianyu 0:a4d8f5b3c546 2677 void MPU6050::getFIFOBytes(uint8_t *data, uint8_t length) {
lixianyu 0:a4d8f5b3c546 2678 I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_R_W, length, data);
lixianyu 0:a4d8f5b3c546 2679 }
lixianyu 0:a4d8f5b3c546 2680 /** Write byte to FIFO buffer.
lixianyu 0:a4d8f5b3c546 2681 * @see getFIFOByte()
lixianyu 0:a4d8f5b3c546 2682 * @see MPU6050_RA_FIFO_R_W
lixianyu 0:a4d8f5b3c546 2683 */
lixianyu 0:a4d8f5b3c546 2684 void MPU6050::setFIFOByte(uint8_t data) {
lixianyu 0:a4d8f5b3c546 2685 I2Cdev::writeByte(devAddr, MPU6050_RA_FIFO_R_W, data);
lixianyu 0:a4d8f5b3c546 2686 }
lixianyu 0:a4d8f5b3c546 2687
lixianyu 0:a4d8f5b3c546 2688 // WHO_AM_I register
lixianyu 0:a4d8f5b3c546 2689
lixianyu 0:a4d8f5b3c546 2690 /** Get Device ID.
lixianyu 0:a4d8f5b3c546 2691 * This register is used to verify the identity of the device (0b110100, 0x34).
lixianyu 0:a4d8f5b3c546 2692 * @return Device ID (6 bits only! should be 0x34)
lixianyu 0:a4d8f5b3c546 2693 * @see MPU6050_RA_WHO_AM_I
lixianyu 0:a4d8f5b3c546 2694 * @see MPU6050_WHO_AM_I_BIT
lixianyu 0:a4d8f5b3c546 2695 * @see MPU6050_WHO_AM_I_LENGTH
lixianyu 0:a4d8f5b3c546 2696 */
lixianyu 0:a4d8f5b3c546 2697 uint8_t MPU6050::getDeviceID() {
lixianyu 0:a4d8f5b3c546 2698 I2Cdev::readBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2699 return buffer[0];
lixianyu 0:a4d8f5b3c546 2700 }
lixianyu 0:a4d8f5b3c546 2701 /** Set Device ID.
lixianyu 0:a4d8f5b3c546 2702 * Write a new ID into the WHO_AM_I register (no idea why this should ever be
lixianyu 0:a4d8f5b3c546 2703 * necessary though).
lixianyu 0:a4d8f5b3c546 2704 * @param id New device ID to set.
lixianyu 0:a4d8f5b3c546 2705 * @see getDeviceID()
lixianyu 0:a4d8f5b3c546 2706 * @see MPU6050_RA_WHO_AM_I
lixianyu 0:a4d8f5b3c546 2707 * @see MPU6050_WHO_AM_I_BIT
lixianyu 0:a4d8f5b3c546 2708 * @see MPU6050_WHO_AM_I_LENGTH
lixianyu 0:a4d8f5b3c546 2709 */
lixianyu 0:a4d8f5b3c546 2710 void MPU6050::setDeviceID(uint8_t id) {
lixianyu 0:a4d8f5b3c546 2711 I2Cdev::writeBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, id);
lixianyu 0:a4d8f5b3c546 2712 }
lixianyu 0:a4d8f5b3c546 2713
lixianyu 0:a4d8f5b3c546 2714 // ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========
lixianyu 0:a4d8f5b3c546 2715
lixianyu 0:a4d8f5b3c546 2716 // XG_OFFS_TC register
lixianyu 0:a4d8f5b3c546 2717
lixianyu 0:a4d8f5b3c546 2718 uint8_t MPU6050::getOTPBankValid() {
lixianyu 0:a4d8f5b3c546 2719 I2Cdev::readBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2720 return buffer[0];
lixianyu 0:a4d8f5b3c546 2721 }
lixianyu 0:a4d8f5b3c546 2722 void MPU6050::setOTPBankValid(bool enabled) {
lixianyu 0:a4d8f5b3c546 2723 I2Cdev::writeBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2724 }
lixianyu 0:a4d8f5b3c546 2725 int8_t MPU6050::getXGyroOffsetTC() {
lixianyu 0:a4d8f5b3c546 2726 I2Cdev::readBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2727 return buffer[0];
lixianyu 0:a4d8f5b3c546 2728 }
lixianyu 0:a4d8f5b3c546 2729 void MPU6050::setXGyroOffsetTC(int8_t offset) {
lixianyu 0:a4d8f5b3c546 2730 I2Cdev::writeBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
lixianyu 0:a4d8f5b3c546 2731 }
lixianyu 0:a4d8f5b3c546 2732
lixianyu 0:a4d8f5b3c546 2733 // YG_OFFS_TC register
lixianyu 0:a4d8f5b3c546 2734
lixianyu 0:a4d8f5b3c546 2735 int8_t MPU6050::getYGyroOffsetTC() {
lixianyu 0:a4d8f5b3c546 2736 I2Cdev::readBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2737 return buffer[0];
lixianyu 0:a4d8f5b3c546 2738 }
lixianyu 0:a4d8f5b3c546 2739 void MPU6050::setYGyroOffsetTC(int8_t offset) {
lixianyu 0:a4d8f5b3c546 2740 I2Cdev::writeBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
lixianyu 0:a4d8f5b3c546 2741 }
lixianyu 0:a4d8f5b3c546 2742
lixianyu 0:a4d8f5b3c546 2743 // ZG_OFFS_TC register
lixianyu 0:a4d8f5b3c546 2744
lixianyu 0:a4d8f5b3c546 2745 int8_t MPU6050::getZGyroOffsetTC() {
lixianyu 0:a4d8f5b3c546 2746 I2Cdev::readBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
lixianyu 0:a4d8f5b3c546 2747 return buffer[0];
lixianyu 0:a4d8f5b3c546 2748 }
lixianyu 0:a4d8f5b3c546 2749 void MPU6050::setZGyroOffsetTC(int8_t offset) {
lixianyu 0:a4d8f5b3c546 2750 I2Cdev::writeBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
lixianyu 0:a4d8f5b3c546 2751 }
lixianyu 0:a4d8f5b3c546 2752
lixianyu 0:a4d8f5b3c546 2753 // X_FINE_GAIN register
lixianyu 0:a4d8f5b3c546 2754
lixianyu 0:a4d8f5b3c546 2755 int8_t MPU6050::getXFineGain() {
lixianyu 0:a4d8f5b3c546 2756 I2Cdev::readByte(devAddr, MPU6050_RA_X_FINE_GAIN, buffer);
lixianyu 0:a4d8f5b3c546 2757 return buffer[0];
lixianyu 0:a4d8f5b3c546 2758 }
lixianyu 0:a4d8f5b3c546 2759 void MPU6050::setXFineGain(int8_t gain) {
lixianyu 0:a4d8f5b3c546 2760 I2Cdev::writeByte(devAddr, MPU6050_RA_X_FINE_GAIN, gain);
lixianyu 0:a4d8f5b3c546 2761 }
lixianyu 0:a4d8f5b3c546 2762
lixianyu 0:a4d8f5b3c546 2763 // Y_FINE_GAIN register
lixianyu 0:a4d8f5b3c546 2764
lixianyu 0:a4d8f5b3c546 2765 int8_t MPU6050::getYFineGain() {
lixianyu 0:a4d8f5b3c546 2766 I2Cdev::readByte(devAddr, MPU6050_RA_Y_FINE_GAIN, buffer);
lixianyu 0:a4d8f5b3c546 2767 return buffer[0];
lixianyu 0:a4d8f5b3c546 2768 }
lixianyu 0:a4d8f5b3c546 2769 void MPU6050::setYFineGain(int8_t gain) {
lixianyu 0:a4d8f5b3c546 2770 I2Cdev::writeByte(devAddr, MPU6050_RA_Y_FINE_GAIN, gain);
lixianyu 0:a4d8f5b3c546 2771 }
lixianyu 0:a4d8f5b3c546 2772
lixianyu 0:a4d8f5b3c546 2773 // Z_FINE_GAIN register
lixianyu 0:a4d8f5b3c546 2774
lixianyu 0:a4d8f5b3c546 2775 int8_t MPU6050::getZFineGain() {
lixianyu 0:a4d8f5b3c546 2776 I2Cdev::readByte(devAddr, MPU6050_RA_Z_FINE_GAIN, buffer);
lixianyu 0:a4d8f5b3c546 2777 return buffer[0];
lixianyu 0:a4d8f5b3c546 2778 }
lixianyu 0:a4d8f5b3c546 2779 void MPU6050::setZFineGain(int8_t gain) {
lixianyu 0:a4d8f5b3c546 2780 I2Cdev::writeByte(devAddr, MPU6050_RA_Z_FINE_GAIN, gain);
lixianyu 0:a4d8f5b3c546 2781 }
lixianyu 0:a4d8f5b3c546 2782
lixianyu 0:a4d8f5b3c546 2783 // XA_OFFS_* registers
lixianyu 0:a4d8f5b3c546 2784
lixianyu 0:a4d8f5b3c546 2785 int16_t MPU6050::getXAccelOffset() {
lixianyu 0:a4d8f5b3c546 2786 I2Cdev::readBytes(devAddr, MPU6050_RA_XA_OFFS_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 2787 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2788 }
lixianyu 0:a4d8f5b3c546 2789 void MPU6050::setXAccelOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2790 I2Cdev::writeWord(devAddr, MPU6050_RA_XA_OFFS_H, offset);
lixianyu 0:a4d8f5b3c546 2791 }
lixianyu 0:a4d8f5b3c546 2792
lixianyu 0:a4d8f5b3c546 2793 // YA_OFFS_* register
lixianyu 0:a4d8f5b3c546 2794
lixianyu 0:a4d8f5b3c546 2795 int16_t MPU6050::getYAccelOffset() {
lixianyu 0:a4d8f5b3c546 2796 I2Cdev::readBytes(devAddr, MPU6050_RA_YA_OFFS_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 2797 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2798 }
lixianyu 0:a4d8f5b3c546 2799 void MPU6050::setYAccelOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2800 I2Cdev::writeWord(devAddr, MPU6050_RA_YA_OFFS_H, offset);
lixianyu 0:a4d8f5b3c546 2801 }
lixianyu 0:a4d8f5b3c546 2802
lixianyu 0:a4d8f5b3c546 2803 // ZA_OFFS_* register
lixianyu 0:a4d8f5b3c546 2804
lixianyu 0:a4d8f5b3c546 2805 int16_t MPU6050::getZAccelOffset() {
lixianyu 0:a4d8f5b3c546 2806 I2Cdev::readBytes(devAddr, MPU6050_RA_ZA_OFFS_H, 2, buffer);
lixianyu 0:a4d8f5b3c546 2807 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2808 }
lixianyu 0:a4d8f5b3c546 2809 void MPU6050::setZAccelOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2810 I2Cdev::writeWord(devAddr, MPU6050_RA_ZA_OFFS_H, offset);
lixianyu 0:a4d8f5b3c546 2811 }
lixianyu 0:a4d8f5b3c546 2812
lixianyu 0:a4d8f5b3c546 2813 // XG_OFFS_USR* registers
lixianyu 0:a4d8f5b3c546 2814
lixianyu 0:a4d8f5b3c546 2815 int16_t MPU6050::getXGyroOffset() {
lixianyu 0:a4d8f5b3c546 2816 I2Cdev::readBytes(devAddr, MPU6050_RA_XG_OFFS_USRH, 2, buffer);
lixianyu 0:a4d8f5b3c546 2817 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2818 }
lixianyu 0:a4d8f5b3c546 2819 void MPU6050::setXGyroOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2820 I2Cdev::writeWord(devAddr, MPU6050_RA_XG_OFFS_USRH, offset);
lixianyu 0:a4d8f5b3c546 2821 }
lixianyu 0:a4d8f5b3c546 2822
lixianyu 0:a4d8f5b3c546 2823 // YG_OFFS_USR* register
lixianyu 0:a4d8f5b3c546 2824
lixianyu 0:a4d8f5b3c546 2825 int16_t MPU6050::getYGyroOffset() {
lixianyu 0:a4d8f5b3c546 2826 I2Cdev::readBytes(devAddr, MPU6050_RA_YG_OFFS_USRH, 2, buffer);
lixianyu 0:a4d8f5b3c546 2827 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2828 }
lixianyu 0:a4d8f5b3c546 2829 void MPU6050::setYGyroOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2830 I2Cdev::writeWord(devAddr, MPU6050_RA_YG_OFFS_USRH, offset);
lixianyu 0:a4d8f5b3c546 2831 }
lixianyu 0:a4d8f5b3c546 2832
lixianyu 0:a4d8f5b3c546 2833 // ZG_OFFS_USR* register
lixianyu 0:a4d8f5b3c546 2834
lixianyu 0:a4d8f5b3c546 2835 int16_t MPU6050::getZGyroOffset() {
lixianyu 0:a4d8f5b3c546 2836 I2Cdev::readBytes(devAddr, MPU6050_RA_ZG_OFFS_USRH, 2, buffer);
lixianyu 0:a4d8f5b3c546 2837 return (((int16_t)buffer[0]) << 8) | buffer[1];
lixianyu 0:a4d8f5b3c546 2838 }
lixianyu 0:a4d8f5b3c546 2839 void MPU6050::setZGyroOffset(int16_t offset) {
lixianyu 0:a4d8f5b3c546 2840 I2Cdev::writeWord(devAddr, MPU6050_RA_ZG_OFFS_USRH, offset);
lixianyu 0:a4d8f5b3c546 2841 }
lixianyu 0:a4d8f5b3c546 2842
lixianyu 0:a4d8f5b3c546 2843 // INT_ENABLE register (DMP functions)
lixianyu 0:a4d8f5b3c546 2844
lixianyu 0:a4d8f5b3c546 2845 bool MPU6050::getIntPLLReadyEnabled() {
lixianyu 0:a4d8f5b3c546 2846 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2847 return buffer[0];
lixianyu 0:a4d8f5b3c546 2848 }
lixianyu 0:a4d8f5b3c546 2849 void MPU6050::setIntPLLReadyEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2850 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2851 }
lixianyu 0:a4d8f5b3c546 2852 bool MPU6050::getIntDMPEnabled() {
lixianyu 0:a4d8f5b3c546 2853 I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2854 return buffer[0];
lixianyu 0:a4d8f5b3c546 2855 }
lixianyu 0:a4d8f5b3c546 2856 void MPU6050::setIntDMPEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2857 I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2858 }
lixianyu 0:a4d8f5b3c546 2859
lixianyu 0:a4d8f5b3c546 2860 // DMP_INT_STATUS
lixianyu 0:a4d8f5b3c546 2861
lixianyu 0:a4d8f5b3c546 2862 bool MPU6050::getDMPInt5Status() {
lixianyu 0:a4d8f5b3c546 2863 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_5_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2864 return buffer[0];
lixianyu 0:a4d8f5b3c546 2865 }
lixianyu 0:a4d8f5b3c546 2866 bool MPU6050::getDMPInt4Status() {
lixianyu 0:a4d8f5b3c546 2867 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_4_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2868 return buffer[0];
lixianyu 0:a4d8f5b3c546 2869 }
lixianyu 0:a4d8f5b3c546 2870 bool MPU6050::getDMPInt3Status() {
lixianyu 0:a4d8f5b3c546 2871 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_3_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2872 return buffer[0];
lixianyu 0:a4d8f5b3c546 2873 }
lixianyu 0:a4d8f5b3c546 2874 bool MPU6050::getDMPInt2Status() {
lixianyu 0:a4d8f5b3c546 2875 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_2_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2876 return buffer[0];
lixianyu 0:a4d8f5b3c546 2877 }
lixianyu 0:a4d8f5b3c546 2878 bool MPU6050::getDMPInt1Status() {
lixianyu 0:a4d8f5b3c546 2879 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_1_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2880 return buffer[0];
lixianyu 0:a4d8f5b3c546 2881 }
lixianyu 0:a4d8f5b3c546 2882 bool MPU6050::getDMPInt0Status() {
lixianyu 0:a4d8f5b3c546 2883 I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_0_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2884 return buffer[0];
lixianyu 0:a4d8f5b3c546 2885 }
lixianyu 0:a4d8f5b3c546 2886
lixianyu 0:a4d8f5b3c546 2887 // INT_STATUS register (DMP functions)
lixianyu 0:a4d8f5b3c546 2888
lixianyu 0:a4d8f5b3c546 2889 bool MPU6050::getIntPLLReadyStatus() {
lixianyu 0:a4d8f5b3c546 2890 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2891 return buffer[0];
lixianyu 0:a4d8f5b3c546 2892 }
lixianyu 0:a4d8f5b3c546 2893 bool MPU6050::getIntDMPStatus() {
lixianyu 0:a4d8f5b3c546 2894 I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2895 return buffer[0];
lixianyu 0:a4d8f5b3c546 2896 }
lixianyu 0:a4d8f5b3c546 2897
lixianyu 0:a4d8f5b3c546 2898 // USER_CTRL register (DMP functions)
lixianyu 0:a4d8f5b3c546 2899
lixianyu 0:a4d8f5b3c546 2900 bool MPU6050::getDMPEnabled() {
lixianyu 0:a4d8f5b3c546 2901 I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, buffer);
lixianyu 0:a4d8f5b3c546 2902 return buffer[0];
lixianyu 0:a4d8f5b3c546 2903 }
lixianyu 0:a4d8f5b3c546 2904 void MPU6050::setDMPEnabled(bool enabled) {
lixianyu 0:a4d8f5b3c546 2905 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, enabled);
lixianyu 0:a4d8f5b3c546 2906 }
lixianyu 0:a4d8f5b3c546 2907 void MPU6050::resetDMP() {
lixianyu 0:a4d8f5b3c546 2908 I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_RESET_BIT, true);
lixianyu 0:a4d8f5b3c546 2909 }
lixianyu 0:a4d8f5b3c546 2910
lixianyu 0:a4d8f5b3c546 2911 // BANK_SEL register
lixianyu 0:a4d8f5b3c546 2912
lixianyu 0:a4d8f5b3c546 2913 void MPU6050::setMemoryBank(uint8_t bank, bool prefetchEnabled, bool userBank) {
lixianyu 0:a4d8f5b3c546 2914 bank &= 0x1F;
lixianyu 0:a4d8f5b3c546 2915 if (userBank) bank |= 0x20;
lixianyu 0:a4d8f5b3c546 2916 if (prefetchEnabled) bank |= 0x40;
lixianyu 0:a4d8f5b3c546 2917 I2Cdev::writeByte(devAddr, MPU6050_RA_BANK_SEL, bank);
lixianyu 0:a4d8f5b3c546 2918 }
lixianyu 0:a4d8f5b3c546 2919
lixianyu 0:a4d8f5b3c546 2920 // MEM_START_ADDR register
lixianyu 0:a4d8f5b3c546 2921
lixianyu 0:a4d8f5b3c546 2922 void MPU6050::setMemoryStartAddress(uint8_t address) {
lixianyu 0:a4d8f5b3c546 2923 I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_START_ADDR, address);
lixianyu 0:a4d8f5b3c546 2924 }
lixianyu 0:a4d8f5b3c546 2925
lixianyu 0:a4d8f5b3c546 2926 // MEM_R_W register
lixianyu 0:a4d8f5b3c546 2927
lixianyu 0:a4d8f5b3c546 2928 uint8_t MPU6050::readMemoryByte() {
lixianyu 0:a4d8f5b3c546 2929 I2Cdev::readByte(devAddr, MPU6050_RA_MEM_R_W, buffer);
lixianyu 0:a4d8f5b3c546 2930 return buffer[0];
lixianyu 0:a4d8f5b3c546 2931 }
lixianyu 0:a4d8f5b3c546 2932 void MPU6050::writeMemoryByte(uint8_t data) {
lixianyu 0:a4d8f5b3c546 2933 I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_R_W, data);
lixianyu 0:a4d8f5b3c546 2934 }
lixianyu 0:a4d8f5b3c546 2935 void MPU6050::readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address) {
lixianyu 0:a4d8f5b3c546 2936 setMemoryBank(bank);
lixianyu 0:a4d8f5b3c546 2937 setMemoryStartAddress(address);
lixianyu 0:a4d8f5b3c546 2938 uint8_t chunkSize;
lixianyu 0:a4d8f5b3c546 2939 for (uint16_t i = 0; i < dataSize;) {
lixianyu 0:a4d8f5b3c546 2940 // determine correct chunk size according to bank position and data size
lixianyu 0:a4d8f5b3c546 2941 chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;
lixianyu 0:a4d8f5b3c546 2942
lixianyu 0:a4d8f5b3c546 2943 // make sure we don't go past the data size
lixianyu 0:a4d8f5b3c546 2944 if (i + chunkSize > dataSize) chunkSize = dataSize - i;
lixianyu 0:a4d8f5b3c546 2945
lixianyu 0:a4d8f5b3c546 2946 // make sure this chunk doesn't go past the bank boundary (256 bytes)
lixianyu 0:a4d8f5b3c546 2947 if (chunkSize > 256 - address) chunkSize = 256 - address;
lixianyu 0:a4d8f5b3c546 2948
lixianyu 0:a4d8f5b3c546 2949 // read the chunk of data as specified
lixianyu 0:a4d8f5b3c546 2950 I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, data + i);
lixianyu 0:a4d8f5b3c546 2951
lixianyu 0:a4d8f5b3c546 2952 // increase byte index by [chunkSize]
lixianyu 0:a4d8f5b3c546 2953 i += chunkSize;
lixianyu 0:a4d8f5b3c546 2954
lixianyu 0:a4d8f5b3c546 2955 // uint8_t automatically wraps to 0 at 256
lixianyu 0:a4d8f5b3c546 2956 address += chunkSize;
lixianyu 0:a4d8f5b3c546 2957
lixianyu 0:a4d8f5b3c546 2958 // if we aren't done, update bank (if necessary) and address
lixianyu 0:a4d8f5b3c546 2959 if (i < dataSize) {
lixianyu 0:a4d8f5b3c546 2960 if (address == 0) bank++;
lixianyu 0:a4d8f5b3c546 2961 setMemoryBank(bank);
lixianyu 0:a4d8f5b3c546 2962 setMemoryStartAddress(address);
lixianyu 0:a4d8f5b3c546 2963 }
lixianyu 0:a4d8f5b3c546 2964 }
lixianyu 0:a4d8f5b3c546 2965 }
lixianyu 0:a4d8f5b3c546 2966 bool MPU6050::writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify, bool useProgMem) {
lixianyu 0:a4d8f5b3c546 2967 setMemoryBank(bank);
lixianyu 0:a4d8f5b3c546 2968 setMemoryStartAddress(address);
lixianyu 0:a4d8f5b3c546 2969 uint8_t chunkSize;
lixianyu 0:a4d8f5b3c546 2970 uint8_t *verifyBuffer;
lixianyu 0:a4d8f5b3c546 2971 uint8_t *progBuffer;
lixianyu 0:a4d8f5b3c546 2972 uint16_t i;
lixianyu 0:a4d8f5b3c546 2973 uint8_t j;
lixianyu 0:a4d8f5b3c546 2974 if (verify) verifyBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);
lixianyu 0:a4d8f5b3c546 2975 if (useProgMem) progBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);
lixianyu 0:a4d8f5b3c546 2976 for (i = 0; i < dataSize;) {
lixianyu 0:a4d8f5b3c546 2977 // determine correct chunk size according to bank position and data size
lixianyu 0:a4d8f5b3c546 2978 chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;
lixianyu 0:a4d8f5b3c546 2979
lixianyu 0:a4d8f5b3c546 2980 // make sure we don't go past the data size
lixianyu 0:a4d8f5b3c546 2981 if (i + chunkSize > dataSize) chunkSize = dataSize - i;
lixianyu 0:a4d8f5b3c546 2982
lixianyu 0:a4d8f5b3c546 2983 // make sure this chunk doesn't go past the bank boundary (256 bytes)
lixianyu 0:a4d8f5b3c546 2984 if (chunkSize > 256 - address) chunkSize = 256 - address;
lixianyu 0:a4d8f5b3c546 2985
lixianyu 0:a4d8f5b3c546 2986 if (useProgMem) {
lixianyu 0:a4d8f5b3c546 2987 // write the chunk of data as specified
lixianyu 0:a4d8f5b3c546 2988 for (j = 0; j < chunkSize; j++) progBuffer[j] = pgm_read_byte(data + i + j);
lixianyu 0:a4d8f5b3c546 2989 } else {
lixianyu 0:a4d8f5b3c546 2990 // write the chunk of data as specified
lixianyu 0:a4d8f5b3c546 2991 progBuffer = (uint8_t *)data + i;
lixianyu 0:a4d8f5b3c546 2992 }
lixianyu 0:a4d8f5b3c546 2993
lixianyu 0:a4d8f5b3c546 2994 I2Cdev::writeBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, progBuffer);
lixianyu 0:a4d8f5b3c546 2995
lixianyu 0:a4d8f5b3c546 2996 // verify data if needed
lixianyu 0:a4d8f5b3c546 2997 if (verify && verifyBuffer) {
lixianyu 0:a4d8f5b3c546 2998 setMemoryBank(bank);
lixianyu 0:a4d8f5b3c546 2999 setMemoryStartAddress(address);
lixianyu 0:a4d8f5b3c546 3000 I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, verifyBuffer);
lixianyu 0:a4d8f5b3c546 3001 if (memcmp(progBuffer, verifyBuffer, chunkSize) != 0) {
lixianyu 0:a4d8f5b3c546 3002 /*Serial.print("Block write verification error, bank ");
lixianyu 0:a4d8f5b3c546 3003 Serial.print(bank, DEC);
lixianyu 0:a4d8f5b3c546 3004 Serial.print(", address ");
lixianyu 0:a4d8f5b3c546 3005 Serial.print(address, DEC);
lixianyu 0:a4d8f5b3c546 3006 Serial.print("!\nExpected:");
lixianyu 0:a4d8f5b3c546 3007 for (j = 0; j < chunkSize; j++) {
lixianyu 0:a4d8f5b3c546 3008 Serial.print(" 0x");
lixianyu 0:a4d8f5b3c546 3009 if (progBuffer[j] < 16) Serial.print("0");
lixianyu 0:a4d8f5b3c546 3010 Serial.print(progBuffer[j], HEX);
lixianyu 0:a4d8f5b3c546 3011 }
lixianyu 0:a4d8f5b3c546 3012 Serial.print("\nReceived:");
lixianyu 0:a4d8f5b3c546 3013 for (uint8_t j = 0; j < chunkSize; j++) {
lixianyu 0:a4d8f5b3c546 3014 Serial.print(" 0x");
lixianyu 0:a4d8f5b3c546 3015 if (verifyBuffer[i + j] < 16) Serial.print("0");
lixianyu 0:a4d8f5b3c546 3016 Serial.print(verifyBuffer[i + j], HEX);
lixianyu 0:a4d8f5b3c546 3017 }
lixianyu 0:a4d8f5b3c546 3018 Serial.print("\n");*/
lixianyu 0:a4d8f5b3c546 3019 free(verifyBuffer);
lixianyu 0:a4d8f5b3c546 3020 if (useProgMem) free(progBuffer);
lixianyu 0:a4d8f5b3c546 3021 return false; // uh oh.
lixianyu 0:a4d8f5b3c546 3022 }
lixianyu 0:a4d8f5b3c546 3023 }
lixianyu 0:a4d8f5b3c546 3024
lixianyu 0:a4d8f5b3c546 3025 // increase byte index by [chunkSize]
lixianyu 0:a4d8f5b3c546 3026 i += chunkSize;
lixianyu 0:a4d8f5b3c546 3027
lixianyu 0:a4d8f5b3c546 3028 // uint8_t automatically wraps to 0 at 256
lixianyu 0:a4d8f5b3c546 3029 address += chunkSize;
lixianyu 0:a4d8f5b3c546 3030
lixianyu 0:a4d8f5b3c546 3031 // if we aren't done, update bank (if necessary) and address
lixianyu 0:a4d8f5b3c546 3032 if (i < dataSize) {
lixianyu 0:a4d8f5b3c546 3033 if (address == 0) bank++;
lixianyu 0:a4d8f5b3c546 3034 setMemoryBank(bank);
lixianyu 0:a4d8f5b3c546 3035 setMemoryStartAddress(address);
lixianyu 0:a4d8f5b3c546 3036 }
lixianyu 0:a4d8f5b3c546 3037 }
lixianyu 0:a4d8f5b3c546 3038 if (verify) free(verifyBuffer);
lixianyu 0:a4d8f5b3c546 3039 if (useProgMem) free(progBuffer);
lixianyu 0:a4d8f5b3c546 3040 return true;
lixianyu 0:a4d8f5b3c546 3041 }
lixianyu 0:a4d8f5b3c546 3042 bool MPU6050::writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify) {
lixianyu 0:a4d8f5b3c546 3043 return writeMemoryBlock(data, dataSize, bank, address, verify, true);
lixianyu 0:a4d8f5b3c546 3044 }
lixianyu 0:a4d8f5b3c546 3045 bool MPU6050::writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem) {
lixianyu 0:a4d8f5b3c546 3046 uint8_t *progBuffer, success, special;
lixianyu 0:a4d8f5b3c546 3047 uint16_t i, j;
lixianyu 0:a4d8f5b3c546 3048 if (useProgMem) {
lixianyu 0:a4d8f5b3c546 3049 progBuffer = (uint8_t *)malloc(8); // assume 8-byte blocks, realloc later if necessary
lixianyu 0:a4d8f5b3c546 3050 }
lixianyu 0:a4d8f5b3c546 3051
lixianyu 0:a4d8f5b3c546 3052 // config set data is a long string of blocks with the following structure:
lixianyu 0:a4d8f5b3c546 3053 // [bank] [offset] [length] [byte[0], byte[1], ..., byte[length]]
lixianyu 0:a4d8f5b3c546 3054 uint8_t bank, offset, length;
lixianyu 0:a4d8f5b3c546 3055 for (i = 0; i < dataSize;) {
lixianyu 0:a4d8f5b3c546 3056 if (useProgMem) {
lixianyu 0:a4d8f5b3c546 3057 bank = pgm_read_byte(data + i++);
lixianyu 0:a4d8f5b3c546 3058 offset = pgm_read_byte(data + i++);
lixianyu 0:a4d8f5b3c546 3059 length = pgm_read_byte(data + i++);
lixianyu 0:a4d8f5b3c546 3060 } else {
lixianyu 0:a4d8f5b3c546 3061 bank = data[i++];
lixianyu 0:a4d8f5b3c546 3062 offset = data[i++];
lixianyu 0:a4d8f5b3c546 3063 length = data[i++];
lixianyu 0:a4d8f5b3c546 3064 }
lixianyu 0:a4d8f5b3c546 3065
lixianyu 0:a4d8f5b3c546 3066 // write data or perform special action
lixianyu 0:a4d8f5b3c546 3067 if (length > 0) {
lixianyu 0:a4d8f5b3c546 3068 // regular block of data to write
lixianyu 0:a4d8f5b3c546 3069 /*Serial.print("Writing config block to bank ");
lixianyu 0:a4d8f5b3c546 3070 Serial.print(bank);
lixianyu 0:a4d8f5b3c546 3071 Serial.print(", offset ");
lixianyu 0:a4d8f5b3c546 3072 Serial.print(offset);
lixianyu 0:a4d8f5b3c546 3073 Serial.print(", length=");
lixianyu 0:a4d8f5b3c546 3074 Serial.println(length);*/
lixianyu 0:a4d8f5b3c546 3075 if (useProgMem) {
lixianyu 0:a4d8f5b3c546 3076 if (sizeof(progBuffer) < length) progBuffer = (uint8_t *)realloc(progBuffer, length);
lixianyu 0:a4d8f5b3c546 3077 for (j = 0; j < length; j++) progBuffer[j] = pgm_read_byte(data + i + j);
lixianyu 0:a4d8f5b3c546 3078 } else {
lixianyu 0:a4d8f5b3c546 3079 progBuffer = (uint8_t *)data + i;
lixianyu 0:a4d8f5b3c546 3080 }
lixianyu 0:a4d8f5b3c546 3081 success = writeMemoryBlock(progBuffer, length, bank, offset, true);
lixianyu 0:a4d8f5b3c546 3082 i += length;
lixianyu 0:a4d8f5b3c546 3083 } else {
lixianyu 0:a4d8f5b3c546 3084 // special instruction
lixianyu 0:a4d8f5b3c546 3085 // NOTE: this kind of behavior (what and when to do certain things)
lixianyu 0:a4d8f5b3c546 3086 // is totally undocumented. This code is in here based on observed
lixianyu 0:a4d8f5b3c546 3087 // behavior only, and exactly why (or even whether) it has to be here
lixianyu 0:a4d8f5b3c546 3088 // is anybody's guess for now.
lixianyu 0:a4d8f5b3c546 3089 if (useProgMem) {
lixianyu 0:a4d8f5b3c546 3090 special = pgm_read_byte(data + i++);
lixianyu 0:a4d8f5b3c546 3091 } else {
lixianyu 0:a4d8f5b3c546 3092 special = data[i++];
lixianyu 0:a4d8f5b3c546 3093 }
lixianyu 0:a4d8f5b3c546 3094 /*Serial.print("Special command code ");
lixianyu 0:a4d8f5b3c546 3095 Serial.print(special, HEX);
lixianyu 0:a4d8f5b3c546 3096 Serial.println(" found...");*/
lixianyu 0:a4d8f5b3c546 3097 if (special == 0x01) {
lixianyu 0:a4d8f5b3c546 3098 // enable DMP-related interrupts
lixianyu 0:a4d8f5b3c546 3099
lixianyu 0:a4d8f5b3c546 3100 //setIntZeroMotionEnabled(true);
lixianyu 0:a4d8f5b3c546 3101 //setIntFIFOBufferOverflowEnabled(true);
lixianyu 0:a4d8f5b3c546 3102 //setIntDMPEnabled(true);
lixianyu 0:a4d8f5b3c546 3103 I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, 0x32); // single operation
lixianyu 0:a4d8f5b3c546 3104
lixianyu 0:a4d8f5b3c546 3105 success = true;
lixianyu 0:a4d8f5b3c546 3106 } else {
lixianyu 0:a4d8f5b3c546 3107 // unknown special command
lixianyu 0:a4d8f5b3c546 3108 success = false;
lixianyu 0:a4d8f5b3c546 3109 }
lixianyu 0:a4d8f5b3c546 3110 }
lixianyu 0:a4d8f5b3c546 3111
lixianyu 0:a4d8f5b3c546 3112 if (!success) {
lixianyu 0:a4d8f5b3c546 3113 if (useProgMem) free(progBuffer);
lixianyu 0:a4d8f5b3c546 3114 return false; // uh oh
lixianyu 0:a4d8f5b3c546 3115 }
lixianyu 0:a4d8f5b3c546 3116 }
lixianyu 0:a4d8f5b3c546 3117 if (useProgMem) free(progBuffer);
lixianyu 0:a4d8f5b3c546 3118 return true;
lixianyu 0:a4d8f5b3c546 3119 }
lixianyu 0:a4d8f5b3c546 3120 bool MPU6050::writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize) {
lixianyu 0:a4d8f5b3c546 3121 return writeDMPConfigurationSet(data, dataSize, true);
lixianyu 0:a4d8f5b3c546 3122 }
lixianyu 0:a4d8f5b3c546 3123
lixianyu 0:a4d8f5b3c546 3124 // DMP_CFG_1 register
lixianyu 0:a4d8f5b3c546 3125
lixianyu 0:a4d8f5b3c546 3126 uint8_t MPU6050::getDMPConfig1() {
lixianyu 0:a4d8f5b3c546 3127 I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_1, buffer);
lixianyu 0:a4d8f5b3c546 3128 return buffer[0];
lixianyu 0:a4d8f5b3c546 3129 }
lixianyu 0:a4d8f5b3c546 3130 void MPU6050::setDMPConfig1(uint8_t config) {
lixianyu 0:a4d8f5b3c546 3131 I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_1, config);
lixianyu 0:a4d8f5b3c546 3132 }
lixianyu 0:a4d8f5b3c546 3133
lixianyu 0:a4d8f5b3c546 3134 // DMP_CFG_2 register
lixianyu 0:a4d8f5b3c546 3135
lixianyu 0:a4d8f5b3c546 3136 uint8_t MPU6050::getDMPConfig2() {
lixianyu 0:a4d8f5b3c546 3137 I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_2, buffer);
lixianyu 0:a4d8f5b3c546 3138 return buffer[0];
lixianyu 0:a4d8f5b3c546 3139 }
lixianyu 0:a4d8f5b3c546 3140 void MPU6050::setDMPConfig2(uint8_t config) {
lixianyu 0:a4d8f5b3c546 3141 I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_2, config);
lixianyu 0:a4d8f5b3c546 3142 }