How to measure water in a reservoir
Dependencies: Cayenne-MQTT-mbed Cayenne-LPP
mbed-lora-radio-drv/SX1272/registers/sx1272Regs-LoRa.h@0:7bfeb237e600, 2019-03-08 (annotated)
- Committer:
- wamae
- Date:
- Fri Mar 08 11:34:56 2019 +0000
- Revision:
- 0:7bfeb237e600
working code
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wamae | 0:7bfeb237e600 | 1 | /** |
wamae | 0:7bfeb237e600 | 2 | / _____) _ | | |
wamae | 0:7bfeb237e600 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
wamae | 0:7bfeb237e600 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
wamae | 0:7bfeb237e600 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
wamae | 0:7bfeb237e600 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
wamae | 0:7bfeb237e600 | 7 | (C) 2015 Semtech |
wamae | 0:7bfeb237e600 | 8 | |
wamae | 0:7bfeb237e600 | 9 | Description: SX1272 LoRa modem registers and bits definitions |
wamae | 0:7bfeb237e600 | 10 | |
wamae | 0:7bfeb237e600 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
wamae | 0:7bfeb237e600 | 12 | |
wamae | 0:7bfeb237e600 | 13 | Maintainer: Miguel Luis and Gregory Cristian |
wamae | 0:7bfeb237e600 | 14 | |
wamae | 0:7bfeb237e600 | 15 | Copyright (c) 2017, Arm Limited and affiliates. |
wamae | 0:7bfeb237e600 | 16 | |
wamae | 0:7bfeb237e600 | 17 | SPDX-License-Identifier: BSD-3-Clause |
wamae | 0:7bfeb237e600 | 18 | */ |
wamae | 0:7bfeb237e600 | 19 | #ifndef __SX1272_REGS_LORA_H__ |
wamae | 0:7bfeb237e600 | 20 | #define __SX1272_REGS_LORA_H__ |
wamae | 0:7bfeb237e600 | 21 | |
wamae | 0:7bfeb237e600 | 22 | /*! |
wamae | 0:7bfeb237e600 | 23 | * ============================================================================ |
wamae | 0:7bfeb237e600 | 24 | * SX1272 Internal registers Address |
wamae | 0:7bfeb237e600 | 25 | * ============================================================================ |
wamae | 0:7bfeb237e600 | 26 | */ |
wamae | 0:7bfeb237e600 | 27 | #define REG_LR_FIFO 0x00 |
wamae | 0:7bfeb237e600 | 28 | // Common settings |
wamae | 0:7bfeb237e600 | 29 | #define REG_LR_OPMODE 0x01 |
wamae | 0:7bfeb237e600 | 30 | #define REG_LR_FRFMSB 0x06 |
wamae | 0:7bfeb237e600 | 31 | #define REG_LR_FRFMID 0x07 |
wamae | 0:7bfeb237e600 | 32 | #define REG_LR_FRFLSB 0x08 |
wamae | 0:7bfeb237e600 | 33 | // Tx settings |
wamae | 0:7bfeb237e600 | 34 | #define REG_LR_PACONFIG 0x09 |
wamae | 0:7bfeb237e600 | 35 | #define REG_LR_PARAMP 0x0A |
wamae | 0:7bfeb237e600 | 36 | #define REG_LR_OCP 0x0B |
wamae | 0:7bfeb237e600 | 37 | // Rx settings |
wamae | 0:7bfeb237e600 | 38 | #define REG_LR_LNA 0x0C |
wamae | 0:7bfeb237e600 | 39 | // LoRa registers |
wamae | 0:7bfeb237e600 | 40 | #define REG_LR_FIFOADDRPTR 0x0D |
wamae | 0:7bfeb237e600 | 41 | #define REG_LR_FIFOTXBASEADDR 0x0E |
wamae | 0:7bfeb237e600 | 42 | #define REG_LR_FIFORXBASEADDR 0x0F |
wamae | 0:7bfeb237e600 | 43 | #define REG_LR_FIFORXCURRENTADDR 0x10 |
wamae | 0:7bfeb237e600 | 44 | #define REG_LR_IRQFLAGSMASK 0x11 |
wamae | 0:7bfeb237e600 | 45 | #define REG_LR_IRQFLAGS 0x12 |
wamae | 0:7bfeb237e600 | 46 | #define REG_LR_RXNBBYTES 0x13 |
wamae | 0:7bfeb237e600 | 47 | #define REG_LR_RXHEADERCNTVALUEMSB 0x14 |
wamae | 0:7bfeb237e600 | 48 | #define REG_LR_RXHEADERCNTVALUELSB 0x15 |
wamae | 0:7bfeb237e600 | 49 | #define REG_LR_RXPACKETCNTVALUEMSB 0x16 |
wamae | 0:7bfeb237e600 | 50 | #define REG_LR_RXPACKETCNTVALUELSB 0x17 |
wamae | 0:7bfeb237e600 | 51 | #define REG_LR_MODEMSTAT 0x18 |
wamae | 0:7bfeb237e600 | 52 | #define REG_LR_PKTSNRVALUE 0x19 |
wamae | 0:7bfeb237e600 | 53 | #define REG_LR_PKTRSSIVALUE 0x1A |
wamae | 0:7bfeb237e600 | 54 | #define REG_LR_RSSIVALUE 0x1B |
wamae | 0:7bfeb237e600 | 55 | #define REG_LR_HOPCHANNEL 0x1C |
wamae | 0:7bfeb237e600 | 56 | #define REG_LR_MODEMCONFIG1 0x1D |
wamae | 0:7bfeb237e600 | 57 | #define REG_LR_MODEMCONFIG2 0x1E |
wamae | 0:7bfeb237e600 | 58 | #define REG_LR_SYMBTIMEOUTLSB 0x1F |
wamae | 0:7bfeb237e600 | 59 | #define REG_LR_PREAMBLEMSB 0x20 |
wamae | 0:7bfeb237e600 | 60 | #define REG_LR_PREAMBLELSB 0x21 |
wamae | 0:7bfeb237e600 | 61 | #define REG_LR_PAYLOADLENGTH 0x22 |
wamae | 0:7bfeb237e600 | 62 | #define REG_LR_PAYLOADMAXLENGTH 0x23 |
wamae | 0:7bfeb237e600 | 63 | #define REG_LR_HOPPERIOD 0x24 |
wamae | 0:7bfeb237e600 | 64 | #define REG_LR_FIFORXBYTEADDR 0x25 |
wamae | 0:7bfeb237e600 | 65 | #define REG_LR_FEIMSB 0x28 |
wamae | 0:7bfeb237e600 | 66 | #define REG_LR_FEIMID 0x29 |
wamae | 0:7bfeb237e600 | 67 | #define REG_LR_FEILSB 0x2A |
wamae | 0:7bfeb237e600 | 68 | #define REG_LR_RSSIWIDEBAND 0x2C |
wamae | 0:7bfeb237e600 | 69 | #define REG_LR_DETECTOPTIMIZE 0x31 |
wamae | 0:7bfeb237e600 | 70 | #define REG_LR_INVERTIQ 0x33 |
wamae | 0:7bfeb237e600 | 71 | #define REG_LR_DETECTIONTHRESHOLD 0x37 |
wamae | 0:7bfeb237e600 | 72 | #define REG_LR_SYNCWORD 0x39 |
wamae | 0:7bfeb237e600 | 73 | #define REG_LR_INVERTIQ2 0x3B |
wamae | 0:7bfeb237e600 | 74 | |
wamae | 0:7bfeb237e600 | 75 | // end of documented register in datasheet |
wamae | 0:7bfeb237e600 | 76 | // I/O settings |
wamae | 0:7bfeb237e600 | 77 | #define REG_LR_DIOMAPPING1 0x40 |
wamae | 0:7bfeb237e600 | 78 | #define REG_LR_DIOMAPPING2 0x41 |
wamae | 0:7bfeb237e600 | 79 | // Version |
wamae | 0:7bfeb237e600 | 80 | #define REG_LR_VERSION 0x42 |
wamae | 0:7bfeb237e600 | 81 | // Additional settings |
wamae | 0:7bfeb237e600 | 82 | #define REG_LR_AGCREF 0x43 |
wamae | 0:7bfeb237e600 | 83 | #define REG_LR_AGCTHRESH1 0x44 |
wamae | 0:7bfeb237e600 | 84 | #define REG_LR_AGCTHRESH2 0x45 |
wamae | 0:7bfeb237e600 | 85 | #define REG_LR_AGCTHRESH3 0x46 |
wamae | 0:7bfeb237e600 | 86 | #define REG_LR_PLLHOP 0x4B |
wamae | 0:7bfeb237e600 | 87 | #define REG_LR_TCXO 0x58 |
wamae | 0:7bfeb237e600 | 88 | #define REG_LR_PADAC 0x5A |
wamae | 0:7bfeb237e600 | 89 | #define REG_LR_PLL 0x5C |
wamae | 0:7bfeb237e600 | 90 | #define REG_LR_PLLLOWPN 0x5E |
wamae | 0:7bfeb237e600 | 91 | #define REG_LR_FORMERTEMP 0x6C |
wamae | 0:7bfeb237e600 | 92 | |
wamae | 0:7bfeb237e600 | 93 | /*! |
wamae | 0:7bfeb237e600 | 94 | * ============================================================================ |
wamae | 0:7bfeb237e600 | 95 | * SX1272 LoRa bits control definition |
wamae | 0:7bfeb237e600 | 96 | * ============================================================================ |
wamae | 0:7bfeb237e600 | 97 | */ |
wamae | 0:7bfeb237e600 | 98 | |
wamae | 0:7bfeb237e600 | 99 | /*! |
wamae | 0:7bfeb237e600 | 100 | * RegFifo |
wamae | 0:7bfeb237e600 | 101 | */ |
wamae | 0:7bfeb237e600 | 102 | |
wamae | 0:7bfeb237e600 | 103 | /*! |
wamae | 0:7bfeb237e600 | 104 | * RegOpMode |
wamae | 0:7bfeb237e600 | 105 | */ |
wamae | 0:7bfeb237e600 | 106 | #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F |
wamae | 0:7bfeb237e600 | 107 | #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 108 | #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 |
wamae | 0:7bfeb237e600 | 109 | |
wamae | 0:7bfeb237e600 | 110 | #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF |
wamae | 0:7bfeb237e600 | 111 | #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 |
wamae | 0:7bfeb237e600 | 112 | #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default |
wamae | 0:7bfeb237e600 | 113 | |
wamae | 0:7bfeb237e600 | 114 | #define RFLR_OPMODE_MASK 0xF8 |
wamae | 0:7bfeb237e600 | 115 | #define RFLR_OPMODE_SLEEP 0x00 |
wamae | 0:7bfeb237e600 | 116 | #define RFLR_OPMODE_STANDBY 0x01 // Default |
wamae | 0:7bfeb237e600 | 117 | #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 |
wamae | 0:7bfeb237e600 | 118 | #define RFLR_OPMODE_TRANSMITTER 0x03 |
wamae | 0:7bfeb237e600 | 119 | #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 |
wamae | 0:7bfeb237e600 | 120 | #define RFLR_OPMODE_RECEIVER 0x05 |
wamae | 0:7bfeb237e600 | 121 | // LoRa specific modes |
wamae | 0:7bfeb237e600 | 122 | #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 |
wamae | 0:7bfeb237e600 | 123 | #define RFLR_OPMODE_CAD 0x07 |
wamae | 0:7bfeb237e600 | 124 | |
wamae | 0:7bfeb237e600 | 125 | /*! |
wamae | 0:7bfeb237e600 | 126 | * RegFrf (MHz) |
wamae | 0:7bfeb237e600 | 127 | */ |
wamae | 0:7bfeb237e600 | 128 | #define RFLR_FRFMSB_915_MHZ 0xE4 // Default |
wamae | 0:7bfeb237e600 | 129 | #define RFLR_FRFMID_915_MHZ 0xC0 // Default |
wamae | 0:7bfeb237e600 | 130 | #define RFLR_FRFLSB_915_MHZ 0x00 // Default |
wamae | 0:7bfeb237e600 | 131 | |
wamae | 0:7bfeb237e600 | 132 | /*! |
wamae | 0:7bfeb237e600 | 133 | * RegPaConfig |
wamae | 0:7bfeb237e600 | 134 | */ |
wamae | 0:7bfeb237e600 | 135 | #define RFLR_PACONFIG_PASELECT_MASK 0x7F |
wamae | 0:7bfeb237e600 | 136 | #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 |
wamae | 0:7bfeb237e600 | 137 | #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default |
wamae | 0:7bfeb237e600 | 138 | |
wamae | 0:7bfeb237e600 | 139 | #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 |
wamae | 0:7bfeb237e600 | 140 | |
wamae | 0:7bfeb237e600 | 141 | /*! |
wamae | 0:7bfeb237e600 | 142 | * RegPaRamp |
wamae | 0:7bfeb237e600 | 143 | */ |
wamae | 0:7bfeb237e600 | 144 | #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 |
wamae | 0:7bfeb237e600 | 145 | #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default |
wamae | 0:7bfeb237e600 | 146 | #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 |
wamae | 0:7bfeb237e600 | 147 | |
wamae | 0:7bfeb237e600 | 148 | #define RFLR_PARAMP_MASK 0xF0 |
wamae | 0:7bfeb237e600 | 149 | #define RFLR_PARAMP_3400_US 0x00 |
wamae | 0:7bfeb237e600 | 150 | #define RFLR_PARAMP_2000_US 0x01 |
wamae | 0:7bfeb237e600 | 151 | #define RFLR_PARAMP_1000_US 0x02 |
wamae | 0:7bfeb237e600 | 152 | #define RFLR_PARAMP_0500_US 0x03 |
wamae | 0:7bfeb237e600 | 153 | #define RFLR_PARAMP_0250_US 0x04 |
wamae | 0:7bfeb237e600 | 154 | #define RFLR_PARAMP_0125_US 0x05 |
wamae | 0:7bfeb237e600 | 155 | #define RFLR_PARAMP_0100_US 0x06 |
wamae | 0:7bfeb237e600 | 156 | #define RFLR_PARAMP_0062_US 0x07 |
wamae | 0:7bfeb237e600 | 157 | #define RFLR_PARAMP_0050_US 0x08 |
wamae | 0:7bfeb237e600 | 158 | #define RFLR_PARAMP_0040_US 0x09 // Default |
wamae | 0:7bfeb237e600 | 159 | #define RFLR_PARAMP_0031_US 0x0A |
wamae | 0:7bfeb237e600 | 160 | #define RFLR_PARAMP_0025_US 0x0B |
wamae | 0:7bfeb237e600 | 161 | #define RFLR_PARAMP_0020_US 0x0C |
wamae | 0:7bfeb237e600 | 162 | #define RFLR_PARAMP_0015_US 0x0D |
wamae | 0:7bfeb237e600 | 163 | #define RFLR_PARAMP_0012_US 0x0E |
wamae | 0:7bfeb237e600 | 164 | #define RFLR_PARAMP_0010_US 0x0F |
wamae | 0:7bfeb237e600 | 165 | |
wamae | 0:7bfeb237e600 | 166 | /*! |
wamae | 0:7bfeb237e600 | 167 | * RegOcp |
wamae | 0:7bfeb237e600 | 168 | */ |
wamae | 0:7bfeb237e600 | 169 | #define RFLR_OCP_MASK 0xDF |
wamae | 0:7bfeb237e600 | 170 | #define RFLR_OCP_ON 0x20 // Default |
wamae | 0:7bfeb237e600 | 171 | #define RFLR_OCP_OFF 0x00 |
wamae | 0:7bfeb237e600 | 172 | |
wamae | 0:7bfeb237e600 | 173 | #define RFLR_OCP_TRIM_MASK 0xE0 |
wamae | 0:7bfeb237e600 | 174 | #define RFLR_OCP_TRIM_045_MA 0x00 |
wamae | 0:7bfeb237e600 | 175 | #define RFLR_OCP_TRIM_050_MA 0x01 |
wamae | 0:7bfeb237e600 | 176 | #define RFLR_OCP_TRIM_055_MA 0x02 |
wamae | 0:7bfeb237e600 | 177 | #define RFLR_OCP_TRIM_060_MA 0x03 |
wamae | 0:7bfeb237e600 | 178 | #define RFLR_OCP_TRIM_065_MA 0x04 |
wamae | 0:7bfeb237e600 | 179 | #define RFLR_OCP_TRIM_070_MA 0x05 |
wamae | 0:7bfeb237e600 | 180 | #define RFLR_OCP_TRIM_075_MA 0x06 |
wamae | 0:7bfeb237e600 | 181 | #define RFLR_OCP_TRIM_080_MA 0x07 |
wamae | 0:7bfeb237e600 | 182 | #define RFLR_OCP_TRIM_085_MA 0x08 |
wamae | 0:7bfeb237e600 | 183 | #define RFLR_OCP_TRIM_090_MA 0x09 |
wamae | 0:7bfeb237e600 | 184 | #define RFLR_OCP_TRIM_095_MA 0x0A |
wamae | 0:7bfeb237e600 | 185 | #define RFLR_OCP_TRIM_100_MA 0x0B // Default |
wamae | 0:7bfeb237e600 | 186 | #define RFLR_OCP_TRIM_105_MA 0x0C |
wamae | 0:7bfeb237e600 | 187 | #define RFLR_OCP_TRIM_110_MA 0x0D |
wamae | 0:7bfeb237e600 | 188 | #define RFLR_OCP_TRIM_115_MA 0x0E |
wamae | 0:7bfeb237e600 | 189 | #define RFLR_OCP_TRIM_120_MA 0x0F |
wamae | 0:7bfeb237e600 | 190 | #define RFLR_OCP_TRIM_130_MA 0x10 |
wamae | 0:7bfeb237e600 | 191 | #define RFLR_OCP_TRIM_140_MA 0x11 |
wamae | 0:7bfeb237e600 | 192 | #define RFLR_OCP_TRIM_150_MA 0x12 |
wamae | 0:7bfeb237e600 | 193 | #define RFLR_OCP_TRIM_160_MA 0x13 |
wamae | 0:7bfeb237e600 | 194 | #define RFLR_OCP_TRIM_170_MA 0x14 |
wamae | 0:7bfeb237e600 | 195 | #define RFLR_OCP_TRIM_180_MA 0x15 |
wamae | 0:7bfeb237e600 | 196 | #define RFLR_OCP_TRIM_190_MA 0x16 |
wamae | 0:7bfeb237e600 | 197 | #define RFLR_OCP_TRIM_200_MA 0x17 |
wamae | 0:7bfeb237e600 | 198 | #define RFLR_OCP_TRIM_210_MA 0x18 |
wamae | 0:7bfeb237e600 | 199 | #define RFLR_OCP_TRIM_220_MA 0x19 |
wamae | 0:7bfeb237e600 | 200 | #define RFLR_OCP_TRIM_230_MA 0x1A |
wamae | 0:7bfeb237e600 | 201 | #define RFLR_OCP_TRIM_240_MA 0x1B |
wamae | 0:7bfeb237e600 | 202 | |
wamae | 0:7bfeb237e600 | 203 | /*! |
wamae | 0:7bfeb237e600 | 204 | * RegLna |
wamae | 0:7bfeb237e600 | 205 | */ |
wamae | 0:7bfeb237e600 | 206 | #define RFLR_LNA_GAIN_MASK 0x1F |
wamae | 0:7bfeb237e600 | 207 | #define RFLR_LNA_GAIN_G1 0x20 // Default |
wamae | 0:7bfeb237e600 | 208 | #define RFLR_LNA_GAIN_G2 0x40 |
wamae | 0:7bfeb237e600 | 209 | #define RFLR_LNA_GAIN_G3 0x60 |
wamae | 0:7bfeb237e600 | 210 | #define RFLR_LNA_GAIN_G4 0x80 |
wamae | 0:7bfeb237e600 | 211 | #define RFLR_LNA_GAIN_G5 0xA0 |
wamae | 0:7bfeb237e600 | 212 | #define RFLR_LNA_GAIN_G6 0xC0 |
wamae | 0:7bfeb237e600 | 213 | |
wamae | 0:7bfeb237e600 | 214 | #define RFLR_LNA_BOOST_MASK 0xFC |
wamae | 0:7bfeb237e600 | 215 | #define RFLR_LNA_BOOST_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 216 | #define RFLR_LNA_BOOST_ON 0x03 |
wamae | 0:7bfeb237e600 | 217 | |
wamae | 0:7bfeb237e600 | 218 | /*! |
wamae | 0:7bfeb237e600 | 219 | * RegFifoAddrPtr |
wamae | 0:7bfeb237e600 | 220 | */ |
wamae | 0:7bfeb237e600 | 221 | #define RFLR_FIFOADDRPTR 0x00 // Default |
wamae | 0:7bfeb237e600 | 222 | |
wamae | 0:7bfeb237e600 | 223 | /*! |
wamae | 0:7bfeb237e600 | 224 | * RegFifoTxBaseAddr |
wamae | 0:7bfeb237e600 | 225 | */ |
wamae | 0:7bfeb237e600 | 226 | #define RFLR_FIFOTXBASEADDR 0x80 // Default |
wamae | 0:7bfeb237e600 | 227 | |
wamae | 0:7bfeb237e600 | 228 | /*! |
wamae | 0:7bfeb237e600 | 229 | * RegFifoTxBaseAddr |
wamae | 0:7bfeb237e600 | 230 | */ |
wamae | 0:7bfeb237e600 | 231 | #define RFLR_FIFORXBASEADDR 0x00 // Default |
wamae | 0:7bfeb237e600 | 232 | |
wamae | 0:7bfeb237e600 | 233 | /*! |
wamae | 0:7bfeb237e600 | 234 | * RegFifoRxCurrentAddr (Read Only) |
wamae | 0:7bfeb237e600 | 235 | */ |
wamae | 0:7bfeb237e600 | 236 | |
wamae | 0:7bfeb237e600 | 237 | /*! |
wamae | 0:7bfeb237e600 | 238 | * RegIrqFlagsMask |
wamae | 0:7bfeb237e600 | 239 | */ |
wamae | 0:7bfeb237e600 | 240 | #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 |
wamae | 0:7bfeb237e600 | 241 | #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 |
wamae | 0:7bfeb237e600 | 242 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 |
wamae | 0:7bfeb237e600 | 243 | #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 |
wamae | 0:7bfeb237e600 | 244 | #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 |
wamae | 0:7bfeb237e600 | 245 | #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 |
wamae | 0:7bfeb237e600 | 246 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 |
wamae | 0:7bfeb237e600 | 247 | #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 |
wamae | 0:7bfeb237e600 | 248 | |
wamae | 0:7bfeb237e600 | 249 | /*! |
wamae | 0:7bfeb237e600 | 250 | * RegIrqFlags |
wamae | 0:7bfeb237e600 | 251 | */ |
wamae | 0:7bfeb237e600 | 252 | #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 |
wamae | 0:7bfeb237e600 | 253 | #define RFLR_IRQFLAGS_RXDONE 0x40 |
wamae | 0:7bfeb237e600 | 254 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 |
wamae | 0:7bfeb237e600 | 255 | #define RFLR_IRQFLAGS_VALIDHEADER 0x10 |
wamae | 0:7bfeb237e600 | 256 | #define RFLR_IRQFLAGS_TXDONE 0x08 |
wamae | 0:7bfeb237e600 | 257 | #define RFLR_IRQFLAGS_CADDONE 0x04 |
wamae | 0:7bfeb237e600 | 258 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 |
wamae | 0:7bfeb237e600 | 259 | #define RFLR_IRQFLAGS_CADDETECTED 0x01 |
wamae | 0:7bfeb237e600 | 260 | |
wamae | 0:7bfeb237e600 | 261 | /*! |
wamae | 0:7bfeb237e600 | 262 | * RegFifoRxNbBytes (Read Only) |
wamae | 0:7bfeb237e600 | 263 | */ |
wamae | 0:7bfeb237e600 | 264 | |
wamae | 0:7bfeb237e600 | 265 | /*! |
wamae | 0:7bfeb237e600 | 266 | * RegRxHeaderCntValueMsb (Read Only) |
wamae | 0:7bfeb237e600 | 267 | */ |
wamae | 0:7bfeb237e600 | 268 | |
wamae | 0:7bfeb237e600 | 269 | /*! |
wamae | 0:7bfeb237e600 | 270 | * RegRxHeaderCntValueLsb (Read Only) |
wamae | 0:7bfeb237e600 | 271 | */ |
wamae | 0:7bfeb237e600 | 272 | |
wamae | 0:7bfeb237e600 | 273 | /*! |
wamae | 0:7bfeb237e600 | 274 | * RegRxPacketCntValueMsb (Read Only) |
wamae | 0:7bfeb237e600 | 275 | */ |
wamae | 0:7bfeb237e600 | 276 | |
wamae | 0:7bfeb237e600 | 277 | /*! |
wamae | 0:7bfeb237e600 | 278 | * RegRxPacketCntValueLsb (Read Only) |
wamae | 0:7bfeb237e600 | 279 | */ |
wamae | 0:7bfeb237e600 | 280 | |
wamae | 0:7bfeb237e600 | 281 | /*! |
wamae | 0:7bfeb237e600 | 282 | * RegModemStat (Read Only) |
wamae | 0:7bfeb237e600 | 283 | */ |
wamae | 0:7bfeb237e600 | 284 | #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F |
wamae | 0:7bfeb237e600 | 285 | #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 |
wamae | 0:7bfeb237e600 | 286 | |
wamae | 0:7bfeb237e600 | 287 | /*! |
wamae | 0:7bfeb237e600 | 288 | * RegPktSnrValue (Read Only) |
wamae | 0:7bfeb237e600 | 289 | */ |
wamae | 0:7bfeb237e600 | 290 | |
wamae | 0:7bfeb237e600 | 291 | /*! |
wamae | 0:7bfeb237e600 | 292 | * RegPktRssiValue (Read Only) |
wamae | 0:7bfeb237e600 | 293 | */ |
wamae | 0:7bfeb237e600 | 294 | |
wamae | 0:7bfeb237e600 | 295 | /*! |
wamae | 0:7bfeb237e600 | 296 | * RegRssiValue (Read Only) |
wamae | 0:7bfeb237e600 | 297 | */ |
wamae | 0:7bfeb237e600 | 298 | |
wamae | 0:7bfeb237e600 | 299 | /*! |
wamae | 0:7bfeb237e600 | 300 | * RegHopChannel (Read Only) |
wamae | 0:7bfeb237e600 | 301 | */ |
wamae | 0:7bfeb237e600 | 302 | #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F |
wamae | 0:7bfeb237e600 | 303 | #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 |
wamae | 0:7bfeb237e600 | 304 | #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default |
wamae | 0:7bfeb237e600 | 305 | |
wamae | 0:7bfeb237e600 | 306 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF |
wamae | 0:7bfeb237e600 | 307 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 |
wamae | 0:7bfeb237e600 | 308 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 309 | |
wamae | 0:7bfeb237e600 | 310 | #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F |
wamae | 0:7bfeb237e600 | 311 | |
wamae | 0:7bfeb237e600 | 312 | /*! |
wamae | 0:7bfeb237e600 | 313 | * RegModemConfig1 |
wamae | 0:7bfeb237e600 | 314 | */ |
wamae | 0:7bfeb237e600 | 315 | #define RFLR_MODEMCONFIG1_BW_MASK 0x3F |
wamae | 0:7bfeb237e600 | 316 | #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default |
wamae | 0:7bfeb237e600 | 317 | #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 |
wamae | 0:7bfeb237e600 | 318 | #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 |
wamae | 0:7bfeb237e600 | 319 | |
wamae | 0:7bfeb237e600 | 320 | #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 |
wamae | 0:7bfeb237e600 | 321 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 |
wamae | 0:7bfeb237e600 | 322 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default |
wamae | 0:7bfeb237e600 | 323 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 |
wamae | 0:7bfeb237e600 | 324 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 |
wamae | 0:7bfeb237e600 | 325 | |
wamae | 0:7bfeb237e600 | 326 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB |
wamae | 0:7bfeb237e600 | 327 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 |
wamae | 0:7bfeb237e600 | 328 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 329 | |
wamae | 0:7bfeb237e600 | 330 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD |
wamae | 0:7bfeb237e600 | 331 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 |
wamae | 0:7bfeb237e600 | 332 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 333 | |
wamae | 0:7bfeb237e600 | 334 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE |
wamae | 0:7bfeb237e600 | 335 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 |
wamae | 0:7bfeb237e600 | 336 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 337 | |
wamae | 0:7bfeb237e600 | 338 | /*! |
wamae | 0:7bfeb237e600 | 339 | * RegModemConfig2 |
wamae | 0:7bfeb237e600 | 340 | */ |
wamae | 0:7bfeb237e600 | 341 | #define RFLR_MODEMCONFIG2_SF_MASK 0x0F |
wamae | 0:7bfeb237e600 | 342 | #define RFLR_MODEMCONFIG2_SF_6 0x60 |
wamae | 0:7bfeb237e600 | 343 | #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default |
wamae | 0:7bfeb237e600 | 344 | #define RFLR_MODEMCONFIG2_SF_8 0x80 |
wamae | 0:7bfeb237e600 | 345 | #define RFLR_MODEMCONFIG2_SF_9 0x90 |
wamae | 0:7bfeb237e600 | 346 | #define RFLR_MODEMCONFIG2_SF_10 0xA0 |
wamae | 0:7bfeb237e600 | 347 | #define RFLR_MODEMCONFIG2_SF_11 0xB0 |
wamae | 0:7bfeb237e600 | 348 | #define RFLR_MODEMCONFIG2_SF_12 0xC0 |
wamae | 0:7bfeb237e600 | 349 | |
wamae | 0:7bfeb237e600 | 350 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 |
wamae | 0:7bfeb237e600 | 351 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 |
wamae | 0:7bfeb237e600 | 352 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 |
wamae | 0:7bfeb237e600 | 353 | |
wamae | 0:7bfeb237e600 | 354 | #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB |
wamae | 0:7bfeb237e600 | 355 | #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default |
wamae | 0:7bfeb237e600 | 356 | #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 |
wamae | 0:7bfeb237e600 | 357 | |
wamae | 0:7bfeb237e600 | 358 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC |
wamae | 0:7bfeb237e600 | 359 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default |
wamae | 0:7bfeb237e600 | 360 | |
wamae | 0:7bfeb237e600 | 361 | /*! |
wamae | 0:7bfeb237e600 | 362 | * RegSymbTimeoutLsb |
wamae | 0:7bfeb237e600 | 363 | */ |
wamae | 0:7bfeb237e600 | 364 | #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default |
wamae | 0:7bfeb237e600 | 365 | |
wamae | 0:7bfeb237e600 | 366 | /*! |
wamae | 0:7bfeb237e600 | 367 | * RegPreambleLengthMsb |
wamae | 0:7bfeb237e600 | 368 | */ |
wamae | 0:7bfeb237e600 | 369 | #define RFLR_PREAMBLELENGTHMSB 0x00 // Default |
wamae | 0:7bfeb237e600 | 370 | |
wamae | 0:7bfeb237e600 | 371 | /*! |
wamae | 0:7bfeb237e600 | 372 | * RegPreambleLengthLsb |
wamae | 0:7bfeb237e600 | 373 | */ |
wamae | 0:7bfeb237e600 | 374 | #define RFLR_PREAMBLELENGTHLSB 0x08 // Default |
wamae | 0:7bfeb237e600 | 375 | |
wamae | 0:7bfeb237e600 | 376 | /*! |
wamae | 0:7bfeb237e600 | 377 | * RegPayloadLength |
wamae | 0:7bfeb237e600 | 378 | */ |
wamae | 0:7bfeb237e600 | 379 | #define RFLR_PAYLOADLENGTH 0x0E // Default |
wamae | 0:7bfeb237e600 | 380 | |
wamae | 0:7bfeb237e600 | 381 | /*! |
wamae | 0:7bfeb237e600 | 382 | * RegPayloadMaxLength |
wamae | 0:7bfeb237e600 | 383 | */ |
wamae | 0:7bfeb237e600 | 384 | #define RFLR_PAYLOADMAXLENGTH 0xFF // Default |
wamae | 0:7bfeb237e600 | 385 | |
wamae | 0:7bfeb237e600 | 386 | /*! |
wamae | 0:7bfeb237e600 | 387 | * RegHopPeriod |
wamae | 0:7bfeb237e600 | 388 | */ |
wamae | 0:7bfeb237e600 | 389 | #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default |
wamae | 0:7bfeb237e600 | 390 | |
wamae | 0:7bfeb237e600 | 391 | /*! |
wamae | 0:7bfeb237e600 | 392 | * RegFifoRxByteAddr (Read Only) |
wamae | 0:7bfeb237e600 | 393 | */ |
wamae | 0:7bfeb237e600 | 394 | |
wamae | 0:7bfeb237e600 | 395 | /*! |
wamae | 0:7bfeb237e600 | 396 | * RegFeiMsb (Read Only) |
wamae | 0:7bfeb237e600 | 397 | */ |
wamae | 0:7bfeb237e600 | 398 | |
wamae | 0:7bfeb237e600 | 399 | /*! |
wamae | 0:7bfeb237e600 | 400 | * RegFeiMid (Read Only) |
wamae | 0:7bfeb237e600 | 401 | */ |
wamae | 0:7bfeb237e600 | 402 | |
wamae | 0:7bfeb237e600 | 403 | /*! |
wamae | 0:7bfeb237e600 | 404 | * RegFeiLsb (Read Only) |
wamae | 0:7bfeb237e600 | 405 | */ |
wamae | 0:7bfeb237e600 | 406 | |
wamae | 0:7bfeb237e600 | 407 | /*! |
wamae | 0:7bfeb237e600 | 408 | * RegRssiWideband (Read Only) |
wamae | 0:7bfeb237e600 | 409 | */ |
wamae | 0:7bfeb237e600 | 410 | |
wamae | 0:7bfeb237e600 | 411 | /*! |
wamae | 0:7bfeb237e600 | 412 | * RegDetectOptimize |
wamae | 0:7bfeb237e600 | 413 | */ |
wamae | 0:7bfeb237e600 | 414 | #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 |
wamae | 0:7bfeb237e600 | 415 | #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default |
wamae | 0:7bfeb237e600 | 416 | #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 |
wamae | 0:7bfeb237e600 | 417 | |
wamae | 0:7bfeb237e600 | 418 | /*! |
wamae | 0:7bfeb237e600 | 419 | * RegInvertIQ |
wamae | 0:7bfeb237e600 | 420 | */ |
wamae | 0:7bfeb237e600 | 421 | #define RFLR_INVERTIQ_RX_MASK 0xBF |
wamae | 0:7bfeb237e600 | 422 | #define RFLR_INVERTIQ_RX_OFF 0x00 |
wamae | 0:7bfeb237e600 | 423 | #define RFLR_INVERTIQ_RX_ON 0x40 |
wamae | 0:7bfeb237e600 | 424 | #define RFLR_INVERTIQ_TX_MASK 0xFE |
wamae | 0:7bfeb237e600 | 425 | #define RFLR_INVERTIQ_TX_OFF 0x01 |
wamae | 0:7bfeb237e600 | 426 | #define RFLR_INVERTIQ_TX_ON 0x00 |
wamae | 0:7bfeb237e600 | 427 | |
wamae | 0:7bfeb237e600 | 428 | /*! |
wamae | 0:7bfeb237e600 | 429 | * RegDetectionThreshold |
wamae | 0:7bfeb237e600 | 430 | */ |
wamae | 0:7bfeb237e600 | 431 | #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default |
wamae | 0:7bfeb237e600 | 432 | #define RFLR_DETECTIONTHRESH_SF6 0x0C |
wamae | 0:7bfeb237e600 | 433 | |
wamae | 0:7bfeb237e600 | 434 | /*! |
wamae | 0:7bfeb237e600 | 435 | * RegInvertIQ2 |
wamae | 0:7bfeb237e600 | 436 | */ |
wamae | 0:7bfeb237e600 | 437 | #define RFLR_INVERTIQ2_ON 0x19 |
wamae | 0:7bfeb237e600 | 438 | #define RFLR_INVERTIQ2_OFF 0x1D |
wamae | 0:7bfeb237e600 | 439 | |
wamae | 0:7bfeb237e600 | 440 | /*! |
wamae | 0:7bfeb237e600 | 441 | * RegDioMapping1 |
wamae | 0:7bfeb237e600 | 442 | */ |
wamae | 0:7bfeb237e600 | 443 | #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F |
wamae | 0:7bfeb237e600 | 444 | #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 445 | #define RFLR_DIOMAPPING1_DIO0_01 0x40 |
wamae | 0:7bfeb237e600 | 446 | #define RFLR_DIOMAPPING1_DIO0_10 0x80 |
wamae | 0:7bfeb237e600 | 447 | #define RFLR_DIOMAPPING1_DIO0_11 0xC0 |
wamae | 0:7bfeb237e600 | 448 | |
wamae | 0:7bfeb237e600 | 449 | #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF |
wamae | 0:7bfeb237e600 | 450 | #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 451 | #define RFLR_DIOMAPPING1_DIO1_01 0x10 |
wamae | 0:7bfeb237e600 | 452 | #define RFLR_DIOMAPPING1_DIO1_10 0x20 |
wamae | 0:7bfeb237e600 | 453 | #define RFLR_DIOMAPPING1_DIO1_11 0x30 |
wamae | 0:7bfeb237e600 | 454 | |
wamae | 0:7bfeb237e600 | 455 | #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 |
wamae | 0:7bfeb237e600 | 456 | #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 457 | #define RFLR_DIOMAPPING1_DIO2_01 0x04 |
wamae | 0:7bfeb237e600 | 458 | #define RFLR_DIOMAPPING1_DIO2_10 0x08 |
wamae | 0:7bfeb237e600 | 459 | #define RFLR_DIOMAPPING1_DIO2_11 0x0C |
wamae | 0:7bfeb237e600 | 460 | |
wamae | 0:7bfeb237e600 | 461 | #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC |
wamae | 0:7bfeb237e600 | 462 | #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 463 | #define RFLR_DIOMAPPING1_DIO3_01 0x01 |
wamae | 0:7bfeb237e600 | 464 | #define RFLR_DIOMAPPING1_DIO3_10 0x02 |
wamae | 0:7bfeb237e600 | 465 | #define RFLR_DIOMAPPING1_DIO3_11 0x03 |
wamae | 0:7bfeb237e600 | 466 | |
wamae | 0:7bfeb237e600 | 467 | /*! |
wamae | 0:7bfeb237e600 | 468 | * RegDioMapping2 |
wamae | 0:7bfeb237e600 | 469 | */ |
wamae | 0:7bfeb237e600 | 470 | #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F |
wamae | 0:7bfeb237e600 | 471 | #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 472 | #define RFLR_DIOMAPPING2_DIO4_01 0x40 |
wamae | 0:7bfeb237e600 | 473 | #define RFLR_DIOMAPPING2_DIO4_10 0x80 |
wamae | 0:7bfeb237e600 | 474 | #define RFLR_DIOMAPPING2_DIO4_11 0xC0 |
wamae | 0:7bfeb237e600 | 475 | |
wamae | 0:7bfeb237e600 | 476 | #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF |
wamae | 0:7bfeb237e600 | 477 | #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default |
wamae | 0:7bfeb237e600 | 478 | #define RFLR_DIOMAPPING2_DIO5_01 0x10 |
wamae | 0:7bfeb237e600 | 479 | #define RFLR_DIOMAPPING2_DIO5_10 0x20 |
wamae | 0:7bfeb237e600 | 480 | #define RFLR_DIOMAPPING2_DIO5_11 0x30 |
wamae | 0:7bfeb237e600 | 481 | |
wamae | 0:7bfeb237e600 | 482 | #define RFLR_DIOMAPPING2_MAP_MASK 0xFE |
wamae | 0:7bfeb237e600 | 483 | #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 |
wamae | 0:7bfeb237e600 | 484 | #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default |
wamae | 0:7bfeb237e600 | 485 | |
wamae | 0:7bfeb237e600 | 486 | /*! |
wamae | 0:7bfeb237e600 | 487 | * RegVersion (Read Only) |
wamae | 0:7bfeb237e600 | 488 | */ |
wamae | 0:7bfeb237e600 | 489 | |
wamae | 0:7bfeb237e600 | 490 | /*! |
wamae | 0:7bfeb237e600 | 491 | * RegAgcRef |
wamae | 0:7bfeb237e600 | 492 | */ |
wamae | 0:7bfeb237e600 | 493 | |
wamae | 0:7bfeb237e600 | 494 | /*! |
wamae | 0:7bfeb237e600 | 495 | * RegAgcThresh1 |
wamae | 0:7bfeb237e600 | 496 | */ |
wamae | 0:7bfeb237e600 | 497 | |
wamae | 0:7bfeb237e600 | 498 | /*! |
wamae | 0:7bfeb237e600 | 499 | * RegAgcThresh2 |
wamae | 0:7bfeb237e600 | 500 | */ |
wamae | 0:7bfeb237e600 | 501 | |
wamae | 0:7bfeb237e600 | 502 | /*! |
wamae | 0:7bfeb237e600 | 503 | * RegAgcThresh3 |
wamae | 0:7bfeb237e600 | 504 | */ |
wamae | 0:7bfeb237e600 | 505 | |
wamae | 0:7bfeb237e600 | 506 | /*! |
wamae | 0:7bfeb237e600 | 507 | * RegPllHop |
wamae | 0:7bfeb237e600 | 508 | */ |
wamae | 0:7bfeb237e600 | 509 | #define RFLR_PLLHOP_FASTHOP_MASK 0x7F |
wamae | 0:7bfeb237e600 | 510 | #define RFLR_PLLHOP_FASTHOP_ON 0x80 |
wamae | 0:7bfeb237e600 | 511 | #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 512 | |
wamae | 0:7bfeb237e600 | 513 | /*! |
wamae | 0:7bfeb237e600 | 514 | * RegTcxo |
wamae | 0:7bfeb237e600 | 515 | */ |
wamae | 0:7bfeb237e600 | 516 | #define RFLR_TCXO_TCXOINPUT_MASK 0xEF |
wamae | 0:7bfeb237e600 | 517 | #define RFLR_TCXO_TCXOINPUT_ON 0x10 |
wamae | 0:7bfeb237e600 | 518 | #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default |
wamae | 0:7bfeb237e600 | 519 | |
wamae | 0:7bfeb237e600 | 520 | /*! |
wamae | 0:7bfeb237e600 | 521 | * RegPaDac |
wamae | 0:7bfeb237e600 | 522 | */ |
wamae | 0:7bfeb237e600 | 523 | #define RFLR_PADAC_20DBM_MASK 0xF8 |
wamae | 0:7bfeb237e600 | 524 | #define RFLR_PADAC_20DBM_ON 0x07 |
wamae | 0:7bfeb237e600 | 525 | #define RFLR_PADAC_20DBM_OFF 0x04 // Default |
wamae | 0:7bfeb237e600 | 526 | |
wamae | 0:7bfeb237e600 | 527 | /*! |
wamae | 0:7bfeb237e600 | 528 | * RegPll |
wamae | 0:7bfeb237e600 | 529 | */ |
wamae | 0:7bfeb237e600 | 530 | #define RFLR_PLL_BANDWIDTH_MASK 0x3F |
wamae | 0:7bfeb237e600 | 531 | #define RFLR_PLL_BANDWIDTH_75 0x00 |
wamae | 0:7bfeb237e600 | 532 | #define RFLR_PLL_BANDWIDTH_150 0x40 |
wamae | 0:7bfeb237e600 | 533 | #define RFLR_PLL_BANDWIDTH_225 0x80 |
wamae | 0:7bfeb237e600 | 534 | #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default |
wamae | 0:7bfeb237e600 | 535 | |
wamae | 0:7bfeb237e600 | 536 | /*! |
wamae | 0:7bfeb237e600 | 537 | * RegPllLowPn |
wamae | 0:7bfeb237e600 | 538 | */ |
wamae | 0:7bfeb237e600 | 539 | #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F |
wamae | 0:7bfeb237e600 | 540 | #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 |
wamae | 0:7bfeb237e600 | 541 | #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 |
wamae | 0:7bfeb237e600 | 542 | #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 |
wamae | 0:7bfeb237e600 | 543 | #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default |
wamae | 0:7bfeb237e600 | 544 | |
wamae | 0:7bfeb237e600 | 545 | /*! |
wamae | 0:7bfeb237e600 | 546 | * RegFormerTemp |
wamae | 0:7bfeb237e600 | 547 | */ |
wamae | 0:7bfeb237e600 | 548 | |
wamae | 0:7bfeb237e600 | 549 | #endif // __SX1272_REGS_LORA_H__ |