stephen mathenge
Level measurement using range finder and lora technology
Dependencies: Cayenne-LPP SDBlockDevice
Revision 0:f930f0440fd5, committed 2019-06-26
- Comitter:
- wamae
- Date:
- Wed Jun 26 10:35:50 2019 +0000
- Commit message:
- better copy
Changed in this revision
diff -r 000000000000 -r f930f0440fd5 Cayenne-LPP.lib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Cayenne-LPP.lib Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,1 @@ +https://os.mbed.com/users/wamae/code/Cayenne-LPP/#24701c1d2b70
diff -r 000000000000 -r f930f0440fd5 HCSR04/hcsr04.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/HCSR04/hcsr04.cpp Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,98 @@
+/* Copyright (c) 2013 Prabhu Desai
+ * pdtechworld@gmail.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include "hcsr04.h"
+
+
+HCSR04::HCSR04(PinName TrigPin,PinName EchoPin):
+ trigger(TrigPin), echo(EchoPin)
+{
+ pulsetime.stop();
+ pulsetime.reset();
+ echo.rise(this,&HCSR04::isr_rise);
+ echo.fall(this,&HCSR04::isr_fall);
+ trigger=0;
+}
+
+HCSR04::~HCSR04()
+{
+}
+
+void HCSR04::isr_rise(void)
+{
+ pulsetime.start();
+}
+void HCSR04::start(void)
+{
+ trigger=1;
+ wait_us(10);
+ trigger=0;
+}
+
+void HCSR04::isr_fall(void)
+{
+ pulsetime.stop();
+ pulsedur = pulsetime.read_us();
+ distance= (pulsedur*343)/20000;
+ pulsetime.reset();
+}
+
+void HCSR04::rise (void (*fptr)(void))
+{
+ echo.rise(fptr);
+}
+void HCSR04::fall (void (*fptr)(void))
+{
+ echo.fall(fptr);
+}
+
+unsigned int HCSR04::get_dist_cm()
+{
+ return distance;
+}
+unsigned int HCSR04::get_pulse_us()
+{
+ return pulsedur;
+}
+
+
+
+/*******************************************************
+ Here is a sample code usage
+*********************************************************
+#include "hcsr04.h"
+HCSR04 usensor(p25,p6);
+int main()
+{
+ unsigned char count=0;
+ while(1) {
+ usensor.start();
+ wait_ms(500);
+ dist=usensor.get_dist_cm();
+ lcd.cls();
+ lcd.locate(0,0);
+ lcd.printf("cm:%ld",dist );
+
+ count++;
+ lcd.locate(0,1);
+ lcd.printf("Distance =%d",count);
+
+ }
+*/
\ No newline at end of file
diff -r 000000000000 -r f930f0440fd5 HCSR04/hcsr04.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/HCSR04/hcsr04.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,68 @@
+/* Copyright (c) 2013 Prabhu Desai
+ * pdtechworld@gmail.com
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * For more details on the sensor :
+ * http://www.elecfreaks.com/store/hcsr04-ultrasonic-sensor-distance-measuring-module-p-91.html?zenid=pgm8pgnvaodbe36dibq5s1soi3
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef MBED_HCSR04_H
+#define MBED_HCSR04_H
+
+#include "mbed.h"
+
+/** HCSR04 Class(es)
+ */
+
+class HCSR04
+{
+public:
+ /** Create a HCSR04 object connected to the specified pin
+ * @param pin i/o pin to connect to
+ */
+ HCSR04(PinName TrigPin,PinName EchoPin);
+ ~HCSR04();
+
+ /** Return the distance from obstacle in cm
+ * @param distance in cms and returns -1, in case of failure
+ */
+ unsigned int get_dist_cm(void);
+ /** Return the pulse duration equal to sonic waves travelling to obstacle and back to receiver.
+ * @param pulse duration in microseconds.
+ */
+ unsigned int get_pulse_us(void);
+ /** Generates the trigger pulse of 10us on the trigger PIN.
+ */
+ void start(void );
+ void isr_rise(void);
+ void isr_fall(void);
+ void fall (void (*fptr)(void));
+ void rise (void (*fptr)(void));
+
+
+
+private:
+
+ Timer pulsetime;
+ DigitalOut trigger;
+ InterruptIn echo;
+ unsigned int pulsedur;
+ unsigned int distance;
+};
+
+#endif
\ No newline at end of file
diff -r 000000000000 -r f930f0440fd5 SDBlockDevice.lib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/SDBlockDevice.lib Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,1 @@ +https://os.mbed.com/users/Swabey89/code/SDBlockDevice/#3fd460dac21f
diff -r 000000000000 -r f930f0440fd5 inc/dust_sensor.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/dust_sensor.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,64 @@
+#ifndef _DUST_SENSOR_H
+#define _DUST_SENSOR_H
+
+#include "mbed.h"
+
+class DustSensor : public NonCopyable<DustSensor> {
+public:
+ DustSensor(PinName pin) : _input(pin), _cb(NULL), _busy(false) {
+
+ }
+
+ bool measure(Callback<void(int, float, float)> cb) {
+ if (_busy) {
+ return false;
+ }
+
+ _cb = cb;
+
+ _busy = true;
+
+ m.attach(callback(this, &DustSensor::calculate), 30.0f);
+ t.reset(); // reset mesurement every 30 seconds
+ _input.fall(callback(this, &DustSensor::start)); // start measuring when signal is low
+ _input.rise(callback(this, &DustSensor::stop)); // stop measuring when signal is high
+
+ return true;
+ }
+
+ bool is_busy() {
+ return _busy;
+ }
+
+private:
+ // Start Timer
+ void start(void) {
+ t.start();
+ }
+
+ // Stop Timer
+ void stop(void) {
+ t.stop();
+ }
+
+ // calculate sensor value
+ void calculate() {
+ // run measurements
+ int lpo = t.read_us();
+ float ratio = t.read_us() / (30000 * 10.0);
+ float concentration = 1.1 * pow(ratio,3) -3.8 * pow(ratio, 2) + 520 * ratio + 0.62;
+ _cb(lpo, ratio, concentration);
+
+ _busy = false;
+ }
+
+ InterruptIn _input;
+ Callback<void(int, float, float)> _cb;
+
+ bool _busy;
+
+ Timer t; // measure amount of time signal is low
+ Timeout m; // every 30 seconds calculate measurement
+};
+
+#endif // _DUST_SENSOR_H
diff -r 000000000000 -r f930f0440fd5 inc/lora_radio_helper.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lora_radio_helper.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,76 @@ +/** + * Copyright (c) 2017, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lorawan/LoRaRadio.h" + +#ifndef APP_LORA_RADIO_HELPER_H_ +#define APP_LORA_RADIO_HELPER_H_ + +#include "SX1272_LoRaRadio.h" +#include "SX1276_LoRaRadio.h" + +#define SX1272 0xFF +#define SX1276 0xEE + +#if (MBED_CONF_APP_LORA_RADIO == SX1272) + + SX1272_LoRaRadio radio(MBED_CONF_APP_LORA_SPI_MOSI, + MBED_CONF_APP_LORA_SPI_MISO, + MBED_CONF_APP_LORA_SPI_SCLK, + MBED_CONF_APP_LORA_CS, + MBED_CONF_APP_LORA_RESET, + MBED_CONF_APP_LORA_DIO0, + MBED_CONF_APP_LORA_DIO1, + MBED_CONF_APP_LORA_DIO2, + MBED_CONF_APP_LORA_DIO3, + MBED_CONF_APP_LORA_DIO4, + MBED_CONF_APP_LORA_DIO5, + MBED_CONF_APP_LORA_RF_SWITCH_CTL1, + MBED_CONF_APP_LORA_RF_SWITCH_CTL2, + MBED_CONF_APP_LORA_TXCTL, + MBED_CONF_APP_LORA_RXCTL, + MBED_CONF_APP_LORA_ANT_SWITCH, + MBED_CONF_APP_LORA_PWR_AMP_CTL, + MBED_CONF_APP_LORA_TCXO); + +#elif (MBED_CONF_APP_LORA_RADIO == SX1276) + + SX1276_LoRaRadio radio(MBED_CONF_APP_LORA_SPI_MOSI, + MBED_CONF_APP_LORA_SPI_MISO, + MBED_CONF_APP_LORA_SPI_SCLK, + MBED_CONF_APP_LORA_CS, + MBED_CONF_APP_LORA_RESET, + MBED_CONF_APP_LORA_DIO0, + MBED_CONF_APP_LORA_DIO1, + MBED_CONF_APP_LORA_DIO2, + MBED_CONF_APP_LORA_DIO3, + MBED_CONF_APP_LORA_DIO4, + MBED_CONF_APP_LORA_DIO5, + MBED_CONF_APP_LORA_RF_SWITCH_CTL1, + MBED_CONF_APP_LORA_RF_SWITCH_CTL2, + MBED_CONF_APP_LORA_TXCTL, + MBED_CONF_APP_LORA_RXCTL, + MBED_CONF_APP_LORA_ANT_SWITCH, + MBED_CONF_APP_LORA_PWR_AMP_CTL, + MBED_CONF_APP_LORA_TCXO); + +#else + #error "Unknown LoRa radio specified (SX1272,SX1276 are valid)" +#endif + + +#endif /* APP_LORA_RADIO_HELPER_H_ */
diff -r 000000000000 -r f930f0440fd5 inc/lorawan_network.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/lorawan_network.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,112 @@
+#ifndef _LORAWAN_NETWORK_H_
+#define _LORAWAN_NETWORK_H_
+
+#include "mbed.h"
+#include "mbed_trace.h"
+#include "mbed_events.h"
+#include "LoRaWANInterface.h"
+#include "SX1276_LoRaRadio.h"
+#include "CayenneLPP.h"
+#include "lora_radio_helper.h"
+
+#define MBED_CONF_LORA_APP_PORT 15
+
+// EventQueue is required to dispatch events around
+EventQueue ev_queue;
+
+// Constructing Mbed LoRaWANInterface and passing it down the radio object.
+static LoRaWANInterface lorawan(radio);
+
+// Application specific callbacks
+static lorawan_app_callbacks_t callbacks;
+
+// LoRaWAN stack event handler
+static void lora_event_handler(lorawan_event_t event);
+
+static void lorawan_setup(uint32_t devAddr, uint8_t nwkSKey[16], uint8_t appSKey[16], Callback<void(lorawan_event_t)> lw_event_handler) {
+ if (devAddr == 0x0) {
+ printf("Set your LoRaWAN credentials first!\n");
+ return;
+ }
+
+ // Enable trace output for this demo, so we can see what the LoRaWAN stack does
+ mbed_trace_init();
+
+ if (lorawan.initialize(&ev_queue) != LORAWAN_STATUS_OK) {
+ printf("[LNWK][ERR ] LoRa initialization failed!\n");
+ return;
+ }
+
+ // prepare application callbacks
+ callbacks.events = lw_event_handler;
+ lorawan.add_app_callbacks(&callbacks);
+
+ // Disable adaptive data rating
+ if (lorawan.disable_adaptive_datarate() != LORAWAN_STATUS_OK) {
+ printf("[LNWK][ERR ] disable_adaptive_datarate failed!\n");
+ return;
+ }
+
+ lorawan.set_datarate(0); // SF12BW125
+
+ lorawan_connect_t connect_params;
+ connect_params.connect_type = LORAWAN_CONNECTION_ABP;
+ // connect_params.connection_u.otaa.dev_eui = DEV_EUI;
+ // connect_params.connection_u.otaa.app_eui = APP_EUI;
+ // connect_params.connection_u.otaa.app_key = APP_KEY;
+ // connect_params.connection_u.otaa.nb_trials = 3;
+
+ connect_params.connection_u.abp.dev_addr = devAddr;
+ connect_params.connection_u.abp.nwk_skey = nwkSKey;
+ connect_params.connection_u.abp.app_skey = appSKey;
+
+ lorawan_status_t retcode = lorawan.connect(connect_params);
+
+ if (retcode == LORAWAN_STATUS_OK ||
+ retcode == LORAWAN_STATUS_CONNECT_IN_PROGRESS) {
+ } else {
+ printf("[LNWK][ERR ] Connection error, code = %d\n", retcode);
+ return;
+ }
+
+ printf("[LNWK][INFO] Connection - In Progress...\n");
+}
+
+// This is called from RX_DONE, so whenever a message came in
+static void receive_message()
+{
+ uint8_t rx_buffer[50] = { 0 };
+ int16_t retcode;
+ retcode = lorawan.receive(MBED_CONF_LORA_APP_PORT, rx_buffer,
+ sizeof(rx_buffer),
+ MSG_UNCONFIRMED_FLAG);
+
+ if (retcode < 0) {
+ printf("[LNWK][WARN] receive() - Error code %d\n", retcode);
+ return;
+ }
+
+ printf("[LNWK][INFO] Data received on port %d (length %d): ", MBED_CONF_LORA_APP_PORT, retcode);
+
+ for (uint8_t i = 0; i < retcode; i++) {
+ printf("%02x ", rx_buffer[i]);
+ }
+ printf("\n");
+}
+
+// Event handler
+bool lorawan_send(CayenneLPP *payload) {
+ int16_t retcode = lorawan.send(MBED_CONF_LORA_APP_PORT, payload->getBuffer(), payload->getSize(), MSG_UNCONFIRMED_FLAG);
+
+ // for some reason send() ret\urns -1... I cannot find out why, the stack returns the right number. I feel that this is some weird Emscripten quirk
+ if (retcode < 0) {
+ retcode == LORAWAN_STATUS_WOULD_BLOCK ? printf("[LNWK][WARN] send - duty cycle violation\n")
+ : printf("[LNWK][WARN] send() - Error code %d\n", retcode);
+ return false;
+ }
+
+ printf("[LNWK][INFO] %d bytes scheduled for transmission\n", retcode);
+ return true;
+}
+
+#endif // _LORAWAN_NETWORK_H_
diff -r 000000000000 -r f930f0440fd5 inc/mbedtls_lora_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/mbedtls_lora_config.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,2694 @@
+/**
+ * \file config.h
+ *
+ * \brief Configuration options (set of defines)
+ *
+ * This set of compile-time options may be used to enable
+ * or disable features selectively, and reduce the global
+ * memory footprint.
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_LORA_CONFIG_H
+#define MBEDTLS_LORA_CONFIG_H
+
+/**
+ * \name SECTION: System support
+ *
+ * This section sets system specific settings.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_HAVE_ASM
+ *
+ * The compiler has support for asm().
+ *
+ * Requires support for asm() in compiler.
+ *
+ * Used in:
+ * library/timing.c
+ * library/padlock.c
+ * include/mbedtls/bn_mul.h
+ *
+ * Comment to disable the use of assembly code.
+ */
+#define MBEDTLS_HAVE_ASM
+
+/**
+ * \def MBEDTLS_NO_UDBL_DIVISION
+ *
+ * The platform lacks support for double-width integer division (64-bit
+ * division on a 32-bit platform, 128-bit division on a 64-bit platform).
+ *
+ * Used in:
+ * include/mbedtls/bignum.h
+ * library/bignum.c
+ *
+ * The bignum code uses double-width division to speed up some operations.
+ * Double-width division is often implemented in software that needs to
+ * be linked with the program. The presence of a double-width integer
+ * type is usually detected automatically through preprocessor macros,
+ * but the automatic detection cannot know whether the code needs to
+ * and can be linked with an implementation of division for that type.
+ * By default division is assumed to be usable if the type is present.
+ * Uncomment this option to prevent the use of double-width division.
+ *
+ * Note that division for the native integer type is always required.
+ * Furthermore, a 64-bit type is always required even on a 32-bit
+ * platform, but it need not support multiplication or division. In some
+ * cases it is also desirable to disable some double-width operations. For
+ * example, if double-width division is implemented in software, disabling
+ * it can reduce code size in some embedded targets.
+ */
+//#define MBEDTLS_NO_UDBL_DIVISION
+
+/**
+ * \def MBEDTLS_HAVE_SSE2
+ *
+ * CPU supports SSE2 instruction set.
+ *
+ * Uncomment if the CPU supports SSE2 (IA-32 specific).
+ */
+//#define MBEDTLS_HAVE_SSE2
+
+/**
+ * \def MBEDTLS_HAVE_TIME
+ *
+ * System has time.h and time().
+ * The time does not need to be correct, only time differences are used,
+ * by contrast with MBEDTLS_HAVE_TIME_DATE
+ *
+ * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT,
+ * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and
+ * MBEDTLS_PLATFORM_STD_TIME.
+ *
+ * Comment if your system does not support time functions
+ */
+//#define MBEDTLS_HAVE_TIME
+
+/**
+ * \def MBEDTLS_HAVE_TIME_DATE
+ *
+ * System has time.h and time(), gmtime() and the clock is correct.
+ * The time needs to be correct (not necesarily very accurate, but at least
+ * the date should be correct). This is used to verify the validity period of
+ * X.509 certificates.
+ *
+ * Comment if your system does not have a correct clock.
+ */
+//#define MBEDTLS_HAVE_TIME_DATE
+
+/**
+ * \def MBEDTLS_PLATFORM_MEMORY
+ *
+ * Enable the memory allocation layer.
+ *
+ * By default mbed TLS uses the system-provided calloc() and free().
+ * This allows different allocators (self-implemented or provided) to be
+ * provided to the platform abstraction layer.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY without the
+ * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
+ * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
+ * free() function pointer at runtime.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
+ * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
+ * alternate function at compile time.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Enable this layer to allow use of alternative memory allocators.
+ */
+//#define MBEDTLS_PLATFORM_MEMORY
+
+/**
+ * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+ *
+ * Do not assign standard functions in the platform layer (e.g. calloc() to
+ * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
+ *
+ * This makes sure there are no linking errors on platforms that do not support
+ * these functions. You will HAVE to provide alternatives, either at runtime
+ * via the platform_set_xxx() functions or at compile time by setting
+ * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
+ * MBEDTLS_PLATFORM_XXX_MACRO.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Uncomment to prevent default assignment of standard functions in the
+ * platform layer.
+ */
+//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+/**
+ * \def MBEDTLS_PLATFORM_EXIT_ALT
+ *
+ * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
+ * function in the platform abstraction layer.
+ *
+ * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
+ * provide a function "mbedtls_platform_set_printf()" that allows you to set an
+ * alternative printf function pointer.
+ *
+ * All these define require MBEDTLS_PLATFORM_C to be defined!
+ *
+ * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
+ * it will be enabled automatically by check_config.h
+ *
+ * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
+ * MBEDTLS_PLATFORM_XXX_MACRO!
+ *
+ * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME
+ *
+ * Uncomment a macro to enable alternate implementation of specific base
+ * platform function
+ */
+//#define MBEDTLS_PLATFORM_EXIT_ALT
+//#define MBEDTLS_PLATFORM_TIME_ALT
+//#define MBEDTLS_PLATFORM_FPRINTF_ALT
+//#define MBEDTLS_PLATFORM_PRINTF_ALT
+//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+//#define MBEDTLS_PLATFORM_NV_SEED_ALT
+//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT
+
+/**
+ * \def MBEDTLS_DEPRECATED_WARNING
+ *
+ * Mark deprecated functions so that they generate a warning if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * This only works with GCC and Clang. With other compilers, you may want to
+ * use MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Uncomment to get warnings on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_WARNING
+
+/**
+ * \def MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Remove deprecated functions so that they generate an error if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * Uncomment to get errors on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_REMOVED
+
+/* \} name SECTION: System support */
+
+/**
+ * \name SECTION: mbed TLS feature support
+ *
+ * This section sets support for features that are or are not needed
+ * within the modules that are enabled.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_TIMING_ALT
+ *
+ * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
+ * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
+ *
+ * Only works if you have MBEDTLS_TIMING_C enabled.
+ *
+ * You will need to provide a header "timing_alt.h" and an implementation at
+ * compile time.
+ */
+//#define MBEDTLS_TIMING_ALT
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternate core implementation of a symmetric crypto, an arithmetic or hash
+ * module (e.g. platform specific assembly optimized implementations). Keep
+ * in mind that the function prototypes should remain the same.
+ *
+ * This replaces the whole module. If you only want to replace one of the
+ * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
+ * provide the "struct mbedtls_aes_context" definition and omit the base
+ * function declarations and implementations. "aes_alt.h" will be included from
+ * "aes.h" to include the new function definitions.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * module.
+ */
+//#define MBEDTLS_AES_ALT
+//#define MBEDTLS_ARC4_ALT
+//#define MBEDTLS_BLOWFISH_ALT
+//#define MBEDTLS_CAMELLIA_ALT
+//#define MBEDTLS_DES_ALT
+//#define MBEDTLS_XTEA_ALT
+//#define MBEDTLS_MD2_ALT
+//#define MBEDTLS_MD4_ALT
+//#define MBEDTLS_MD5_ALT
+//#define MBEDTLS_RIPEMD160_ALT
+//#define MBEDTLS_SHA1_ALT
+//#define MBEDTLS_SHA256_ALT
+//#define MBEDTLS_SHA512_ALT
+/*
+ * When replacing the elliptic curve module, pleace consider, that it is
+ * implemented with two .c files:
+ * - ecp.c
+ * - ecp_curves.c
+ * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT
+ * macros as described above. The only difference is that you have to make sure
+ * that you provide functionality for both .c files.
+ */
+//#define MBEDTLS_ECP_ALT
+
+/**
+ * \def MBEDTLS_MD2_PROCESS_ALT
+ *
+ * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
+ * alternate core implementation of symmetric crypto or hash function. Keep in
+ * mind that function prototypes should remain the same.
+ *
+ * This replaces only one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
+ * no longer provide the mbedtls_sha1_process() function, but it will still provide
+ * the other function (using your mbedtls_sha1_process() function) and the definition
+ * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
+ * with this definition.
+ *
+ * \note Because of a signature change, the core AES encryption and decryption routines are
+ * currently named mbedtls_aes_internal_encrypt and mbedtls_aes_internal_decrypt,
+ * respectively. When setting up alternative implementations, these functions should
+ * be overriden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt
+ * must stay untouched.
+ *
+ * \note If you use the AES_xxx_ALT macros, then is is recommended to also set
+ * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
+ * tables.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+//#define MBEDTLS_MD2_PROCESS_ALT
+//#define MBEDTLS_MD4_PROCESS_ALT
+//#define MBEDTLS_MD5_PROCESS_ALT
+//#define MBEDTLS_RIPEMD160_PROCESS_ALT
+//#define MBEDTLS_SHA1_PROCESS_ALT
+//#define MBEDTLS_SHA256_PROCESS_ALT
+//#define MBEDTLS_SHA512_PROCESS_ALT
+//#define MBEDTLS_DES_SETKEY_ALT
+//#define MBEDTLS_DES_CRYPT_ECB_ALT
+//#define MBEDTLS_DES3_CRYPT_ECB_ALT
+//#define MBEDTLS_AES_SETKEY_ENC_ALT
+//#define MBEDTLS_AES_SETKEY_DEC_ALT
+//#define MBEDTLS_AES_ENCRYPT_ALT
+//#define MBEDTLS_AES_DECRYPT_ALT
+
+/**
+ * \def MBEDTLS_ECP_INTERNAL_ALT
+ *
+ * Expose a part of the internal interface of the Elliptic Curve Point module.
+ *
+ * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternative core implementation of elliptic curve arithmetic. Keep in mind
+ * that function prototypes should remain the same.
+ *
+ * This partially replaces one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation
+ * is still present and it is used for group structures not supported by the
+ * alternative.
+ *
+ * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT
+ * and implementing the following functions:
+ * unsigned char mbedtls_internal_ecp_grp_capable(
+ * const mbedtls_ecp_group *grp )
+ * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
+ * void mbedtls_internal_ecp_deinit( const mbedtls_ecp_group *grp )
+ * The mbedtls_internal_ecp_grp_capable function should return 1 if the
+ * replacement functions implement arithmetic for the given group and 0
+ * otherwise.
+ * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_deinit are
+ * called before and after each point operation and provide an opportunity to
+ * implement optimized set up and tear down instructions.
+ *
+ * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and
+ * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac
+ * function, but will use your mbedtls_internal_ecp_double_jac if the group is
+ * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when
+ * receives it as an argument). If the group is not supported then the original
+ * implementation is used. The other functions and the definition of
+ * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your
+ * implementation of mbedtls_internal_ecp_double_jac and
+ * mbedtls_internal_ecp_grp_capable must be compatible with this definition.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+/* Required for all the functions in this section */
+//#define MBEDTLS_ECP_INTERNAL_ALT
+/* Support for Weierstrass curves with Jacobi representation */
+//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
+//#define MBEDTLS_ECP_ADD_MIXED_ALT
+//#define MBEDTLS_ECP_DOUBLE_JAC_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT
+/* Support for curves with Montgomery arithmetic */
+//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT
+//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT
+//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT
+
+/**
+ * \def MBEDTLS_TEST_NULL_ENTROPY
+ *
+ * Enables testing and use of mbed TLS without any configured entropy sources.
+ * This permits use of the library on platforms before an entropy source has
+ * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the
+ * MBEDTLS_ENTROPY_NV_SEED switches).
+ *
+ * WARNING! This switch MUST be disabled in production builds, and is suitable
+ * only for development.
+ * Enabling the switch negates any security provided by the library.
+ *
+ * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ */
+//#define MBEDTLS_TEST_NULL_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_HARDWARE_ALT
+ *
+ * Uncomment this macro to let mbed TLS use your own implementation of a
+ * hardware entropy collector.
+ *
+ * Your function must be called \c mbedtls_hardware_poll(), have the same
+ * prototype as declared in entropy_poll.h, and accept NULL as first argument.
+ *
+ * Uncomment to use your own hardware entropy collector.
+ */
+//#define MBEDTLS_ENTROPY_HARDWARE_ALT
+
+/**
+ * \def MBEDTLS_AES_ROM_TABLES
+ *
+ * Store the AES tables in ROM.
+ *
+ * Uncomment this macro to store the AES tables in ROM.
+ */
+#define MBEDTLS_AES_ROM_TABLES
+
+/**
+ * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
+ *
+ * Use less ROM for the Camellia implementation (saves about 768 bytes).
+ *
+ * Uncomment this macro to use less memory for Camellia.
+ */
+//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CBC
+ *
+ * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
+ */
+//#define MBEDTLS_CIPHER_MODE_CBC
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CFB
+ *
+ * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
+ */
+//#define MBEDTLS_CIPHER_MODE_CFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CTR
+ *
+ * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
+ */
+//#define MBEDTLS_CIPHER_MODE_CTR
+
+/**
+ * \def MBEDTLS_CIPHER_NULL_CIPHER
+ *
+ * Enable NULL cipher.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * encryption or channels without any security!
+ *
+ * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
+ * the following ciphersuites:
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA
+ *
+ * Uncomment this macro to enable the NULL cipher and ciphersuites
+ */
+//#define MBEDTLS_CIPHER_NULL_CIPHER
+
+/**
+ * \def MBEDTLS_CIPHER_PADDING_PKCS7
+ *
+ * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
+ * specific padding modes in the cipher layer with cipher modes that support
+ * padding (e.g. CBC)
+ *
+ * If you disable all padding modes, only full blocks can be used with CBC.
+ *
+ * Enable padding modes in the cipher layer.
+ */
+//#define MBEDTLS_CIPHER_PADDING_PKCS7
+//#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+//#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+//#define MBEDTLS_CIPHER_PADDING_ZEROS
+
+/**
+ * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+ *
+ * Enable weak ciphersuites in SSL / TLS.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * channels with virtually no security at all!
+ *
+ * This enables the following ciphersuites:
+ * MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+ *
+ * Uncomment this macro to enable weak ciphersuites
+ */
+//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+ *
+ * Remove RC4 ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on RC4 from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
+ * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
+ * explicitly.
+ *
+ * Uncomment this macro to remove RC4 ciphersuites by default.
+ */
+//#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
+ *
+ * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
+ * module. By default all supported curves are enabled.
+ *
+ * Comment macros to disable the curve and functions for it
+ */
+//#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+//#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+//#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+//#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+//#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+//#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+
+/**
+ * \def MBEDTLS_ECP_NIST_OPTIM
+ *
+ * Enable specific 'modulo p' routines for each NIST prime.
+ * Depending on the prime and architecture, makes operations 4 to 8 times
+ * faster on the corresponding curve.
+ *
+ * Comment this macro to disable NIST curves optimisation.
+ */
+//#define MBEDTLS_ECP_NIST_OPTIM
+
+/**
+ * \def MBEDTLS_ECDSA_DETERMINISTIC
+ *
+ * Enable deterministic ECDSA (RFC 6979).
+ * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
+ * may result in a compromise of the long-term signing key. This is avoided by
+ * the deterministic variant.
+ *
+ * Requires: MBEDTLS_HMAC_DRBG_C
+ *
+ * Comment this macro to disable deterministic ECDSA.
+ */
+//#define MBEDTLS_ECDSA_DETERMINISTIC
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+ *
+ * Enable the PSK based ciphersuite modes in SSL / TLS.
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+ *
+ * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+ *
+ * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+ *
+ * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+ *
+ * Enable the RSA-only based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ */
+//#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+ *
+ * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+ *
+ * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+ *
+ * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+ *
+ * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+ *
+ * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+ *
+ * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Requires: MBEDTLS_ECJPAKE_C
+ * MBEDTLS_SHA256_C
+ * MBEDTLS_ECP_DP_SECP256R1_ENABLED
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+/**
+ * \def MBEDTLS_PK_PARSE_EC_EXTENDED
+ *
+ * Enhance support for reading EC keys using variants of SEC1 not allowed by
+ * RFC 5915 and RFC 5480.
+ *
+ * Currently this means parsing the SpecifiedECDomain choice of EC
+ * parameters (only known groups are supported, not arbitrary domains, to
+ * avoid validation issues).
+ *
+ * Disable if you only need to support RFC 5915 + 5480 key formats.
+ */
+//#define MBEDTLS_PK_PARSE_EC_EXTENDED
+
+/**
+ * \def MBEDTLS_ERROR_STRERROR_DUMMY
+ *
+ * Enable a dummy error function to make use of mbedtls_strerror() in
+ * third party libraries easier when MBEDTLS_ERROR_C is disabled
+ * (no effect when MBEDTLS_ERROR_C is enabled).
+ *
+ * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
+ * not using mbedtls_strerror() or error_strerror() in your application.
+ *
+ * Disable if you run into name conflicts and want to really remove the
+ * mbedtls_strerror()
+ */
+//#define MBEDTLS_ERROR_STRERROR_DUMMY
+
+/**
+ * \def MBEDTLS_GENPRIME
+ *
+ * Enable the prime-number generation code.
+ *
+ * Requires: MBEDTLS_BIGNUM_C
+ */
+//#define MBEDTLS_GENPRIME
+
+/**
+ * \def MBEDTLS_FS_IO
+ *
+ * Enable functions that use the filesystem.
+ */
+//#define MBEDTLS_FS_IO
+
+/**
+ * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ * Do not add default entropy sources. These are the platform specific,
+ * mbedtls_timing_hardclock and HAVEGE based poll functions.
+ *
+ * This is useful to have more control over the added entropy sources in an
+ * application.
+ *
+ * Uncomment this macro to prevent loading of default entropy functions.
+ */
+//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+/**
+ * \def MBEDTLS_NO_PLATFORM_ENTROPY
+ *
+ * Do not use built-in platform entropy functions.
+ * This is useful if your platform does not support
+ * standards like the /dev/urandom or Windows CryptoAPI.
+ *
+ * Uncomment this macro to disable the built-in platform entropy functions.
+ */
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_FORCE_SHA256
+ *
+ * Force the entropy accumulator to use a SHA-256 accumulator instead of the
+ * default SHA-512 based one (if both are available).
+ *
+ * Requires: MBEDTLS_SHA256_C
+ *
+ * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
+ * if you have performance concerns.
+ *
+ * This option is only useful if both MBEDTLS_SHA256_C and
+ * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
+ */
+//#define MBEDTLS_ENTROPY_FORCE_SHA256
+
+/**
+ * \def MBEDTLS_ENTROPY_NV_SEED
+ *
+ * Enable the non-volatile (NV) seed file-based entropy source.
+ * (Also enables the NV seed read/write functions in the platform layer)
+ *
+ * This is crucial (if not required) on systems that do not have a
+ * cryptographic entropy source (in hardware or kernel) available.
+ *
+ * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C
+ *
+ * \note The read/write functions that are used by the entropy source are
+ * determined in the platform layer, and can be modified at runtime and/or
+ * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used.
+ *
+ * \note If you use the default implementation functions that read a seedfile
+ * with regular fopen(), please make sure you make a seedfile with the
+ * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at
+ * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from
+ * and written to or you will get an entropy source error! The default
+ * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE
+ * bytes from the file.
+ *
+ * \note The entropy collector will write to the seed file before entropy is
+ * given to an external source, to update it.
+ */
+//#define MBEDTLS_ENTROPY_NV_SEED
+
+/**
+ * \def MBEDTLS_MEMORY_DEBUG
+ *
+ * Enable debugging of buffer allocator memory issues. Automatically prints
+ * (to stderr) all (fatal) messages on memory allocation issues. Enables
+ * function for 'debug output' of allocated memory.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Uncomment this macro to let the buffer allocator print out error messages.
+ */
+//#define MBEDTLS_MEMORY_DEBUG
+
+/**
+ * \def MBEDTLS_MEMORY_BACKTRACE
+ *
+ * Include backtrace information with each allocated block.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ * GLIBC-compatible backtrace() an backtrace_symbols() support
+ *
+ * Uncomment this macro to include backtrace information
+ */
+//#define MBEDTLS_MEMORY_BACKTRACE
+
+/**
+ * \def MBEDTLS_PK_RSA_ALT_SUPPORT
+ *
+ * Support external private RSA keys (eg from a HSM) in the PK layer.
+ *
+ * Comment this macro to disable support for external private RSA keys.
+ */
+//#define MBEDTLS_PK_RSA_ALT_SUPPORT
+
+/**
+ * \def MBEDTLS_PKCS1_V15
+ *
+ * Enable support for PKCS#1 v1.5 encoding.
+ *
+ * Requires: MBEDTLS_RSA_C
+ *
+ * This enables support for PKCS#1 v1.5 operations.
+ */
+//#define MBEDTLS_PKCS1_V15
+
+/**
+ * \def MBEDTLS_PKCS1_V21
+ *
+ * Enable support for PKCS#1 v2.1 encoding.
+ *
+ * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
+ *
+ * This enables support for RSAES-OAEP and RSASSA-PSS operations.
+ */
+//#define MBEDTLS_PKCS1_V21
+
+/**
+ * \def MBEDTLS_RSA_NO_CRT
+ *
+ * Do not use the Chinese Remainder Theorem for the RSA private operation.
+ *
+ * Uncomment this macro to disable the use of CRT in RSA.
+ *
+ */
+//#define MBEDTLS_RSA_NO_CRT
+
+/**
+ * \def MBEDTLS_SELF_TEST
+ *
+ * Enable the checkup functions (*_self_test).
+ */
+//#define MBEDTLS_SELF_TEST
+
+/**
+ * \def MBEDTLS_SHA256_SMALLER
+ *
+ * Enable an implementation of SHA-256 that has lower ROM footprint but also
+ * lower performance.
+ *
+ * The default implementation is meant to be a reasonnable compromise between
+ * performance and size. This version optimizes more aggressively for size at
+ * the expense of performance. Eg on Cortex-M4 it reduces the size of
+ * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
+ * 30%.
+ *
+ * Uncomment to enable the smaller implementation of SHA256.
+ */
+//#define MBEDTLS_SHA256_SMALLER
+
+/**
+ * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
+ *
+ * Enable sending of alert messages in case of encountered errors as per RFC.
+ * If you choose not to send the alert messages, mbed TLS can still communicate
+ * with other servers, only debugging of failures is harder.
+ *
+ * The advantage of not sending alert messages, is that no information is given
+ * about reasons for failures thus preventing adversaries of gaining intel.
+ *
+ * Enable sending of all alert messages
+ */
+//#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+
+/**
+ * \def MBEDTLS_SSL_DEBUG_ALL
+ *
+ * Enable the debug messages in SSL module for all issues.
+ * Debug messages have been disabled in some places to prevent timing
+ * attacks due to (unbalanced) debugging function calls.
+ *
+ * If you need all error reporting you should enable this during debugging,
+ * but remove this for production servers that should log as well.
+ *
+ * Uncomment this macro to report all debug messages on errors introducing
+ * a timing side-channel.
+ *
+ */
+//#define MBEDTLS_SSL_DEBUG_ALL
+
+/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
+ *
+ * Enable support for Encrypt-then-MAC, RFC 7366.
+ *
+ * This allows peers that both support it to use a more robust protection for
+ * ciphersuites using CBC, providing deep resistance against timing attacks
+ * on the padding or underlying cipher.
+ *
+ * This only affects CBC ciphersuites, and is useless if none is defined.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Encrypt-then-MAC
+ */
+//#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+
+/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+ *
+ * Enable support for Extended Master Secret, aka Session Hash
+ * (draft-ietf-tls-session-hash-02).
+ *
+ * This was introduced as "the proper fix" to the Triple Handshake familiy of
+ * attacks, but it is recommended to always use it (even if you disable
+ * renegotiation), since it actually fixes a more fundamental issue in the
+ * original SSL/TLS design, and has implications beyond Triple Handshake.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Extended Master Secret.
+ */
+//#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+
+/**
+ * \def MBEDTLS_SSL_FALLBACK_SCSV
+ *
+ * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
+ *
+ * For servers, it is recommended to always enable this, unless you support
+ * only one version of TLS, or know for sure that none of your clients
+ * implements a fallback strategy.
+ *
+ * For clients, you only need this if you're using a fallback strategy, which
+ * is not recommended in the first place, unless you absolutely need it to
+ * interoperate with buggy (version-intolerant) servers.
+ *
+ * Comment this macro to disable support for FALLBACK_SCSV
+ */
+//#define MBEDTLS_SSL_FALLBACK_SCSV
+
+/**
+ * \def MBEDTLS_SSL_HW_RECORD_ACCEL
+ *
+ * Enable hooking functions in SSL module for hardware acceleration of
+ * individual records.
+ *
+ * Uncomment this macro to enable hooking functions.
+ */
+//#define MBEDTLS_SSL_HW_RECORD_ACCEL
+
+/**
+ * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
+ *
+ * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
+ *
+ * This is a countermeasure to the BEAST attack, which also minimizes the risk
+ * of interoperability issues compared to sending 0-length records.
+ *
+ * Comment this macro to disable 1/n-1 record splitting.
+ */
+//#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
+
+/**
+ * \def MBEDTLS_SSL_RENEGOTIATION
+ *
+ * Disable support for TLS renegotiation.
+ *
+ * The two main uses of renegotiation are (1) refresh keys on long-lived
+ * connections and (2) client authentication after the initial handshake.
+ * If you don't need renegotiation, it's probably better to disable it, since
+ * it has been associated with security issues in the past and is easy to
+ * misuse/misunderstand.
+ *
+ * Comment this to disable support for renegotiation.
+ */
+//#define MBEDTLS_SSL_RENEGOTIATION
+
+/**
+ * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+ *
+ * Enable support for receiving and parsing SSLv2 Client Hello messages for the
+ * SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to enable support for SSLv2 Client Hello messages.
+ */
+//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+
+/**
+ * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+ *
+ * Pick the ciphersuite according to the client's preferences rather than ours
+ * in the SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to respect client's ciphersuite order
+ */
+//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+
+/**
+ * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+ *
+ * Enable support for RFC 6066 max_fragment_length extension in SSL.
+ *
+ * Comment this macro to disable support for the max_fragment_length extension
+ */
+//#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+
+/**
+ * \def MBEDTLS_SSL_PROTO_SSL3
+ *
+ * Enable support for SSL 3.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for SSL 3.0
+ */
+//#define MBEDTLS_SSL_PROTO_SSL3
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1
+ *
+ * Enable support for TLS 1.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.0
+ */
+//#define MBEDTLS_SSL_PROTO_TLS1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_1
+ *
+ * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
+ */
+//#define MBEDTLS_SSL_PROTO_TLS1_1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
+ * (Depends on ciphersuites)
+ *
+ * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
+ */
+//#define MBEDTLS_SSL_PROTO_TLS1_2
+
+/**
+ * \def MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Enable support for DTLS (all available versions).
+ *
+ * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
+ * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1_1
+ * or MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for DTLS
+ */
+//#define MBEDTLS_SSL_PROTO_DTLS
+
+/**
+ * \def MBEDTLS_SSL_ALPN
+ *
+ * Enable support for RFC 7301 Application Layer Protocol Negotiation.
+ *
+ * Comment this macro to disable support for ALPN.
+ */
+//#define MBEDTLS_SSL_ALPN
+
+/**
+ * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
+ *
+ * Enable support for the anti-replay mechanism in DTLS.
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ * MBEDTLS_SSL_PROTO_DTLS
+ *
+ * \warning Disabling this is often a security risk!
+ * See mbedtls_ssl_conf_dtls_anti_replay() for details.
+ *
+ * Comment this to disable anti-replay in DTLS.
+ */
+//#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Enable support for HelloVerifyRequest on DTLS servers.
+ *
+ * This feature is highly recommended to prevent DTLS servers being used as
+ * amplifiers in DoS attacks against other hosts. It should always be enabled
+ * unless you know for sure amplification cannot be a problem in the
+ * environment in which your server operates.
+ *
+ * \warning Disabling this can ba a security risk! (see above)
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Comment this to disable support for HelloVerifyRequest.
+ */
+//#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+ *
+ * Enable server-side support for clients that reconnect from the same port.
+ *
+ * Some clients unexpectedly close the connection and try to reconnect using the
+ * same source port. This needs special support from the server to handle the
+ * new connection securely, as described in section 4.2.8 of RFC 6347. This
+ * flag enables that support.
+ *
+ * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Comment this to disable support for clients reusing the source port.
+ */
+//#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+
+/**
+ * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+ *
+ * Enable support for a limit of records with bad MAC.
+ *
+ * See mbedtls_ssl_conf_dtls_badmac_limit().
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ */
+//#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+
+/**
+ * \def MBEDTLS_SSL_SESSION_TICKETS
+ *
+ * Enable support for RFC 5077 session tickets in SSL.
+ * Client-side, provides full support for session tickets (maintainance of a
+ * session store remains the responsibility of the application, though).
+ * Server-side, you also need to provide callbacks for writing and parsing
+ * tickets, including authenticated encryption and key management. Example
+ * callbacks are provided by MBEDTLS_SSL_TICKET_C.
+ *
+ * Comment this macro to disable support for SSL session tickets
+ */
+//#define MBEDTLS_SSL_SESSION_TICKETS
+
+/**
+ * \def MBEDTLS_SSL_EXPORT_KEYS
+ *
+ * Enable support for exporting key block and master secret.
+ * This is required for certain users of TLS, e.g. EAP-TLS.
+ *
+ * Comment this macro to disable support for key export
+ */
+//#define MBEDTLS_SSL_EXPORT_KEYS
+
+/**
+ * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
+ *
+ * Enable support for RFC 6066 server name indication (SNI) in SSL.
+ *
+ * Requires: MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Comment this macro to disable support for server name indication in SSL
+ */
+//#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC
+ *
+ * Enable support for RFC 6066 truncated HMAC in SSL.
+ *
+ * Comment this macro to disable support for truncated HMAC in SSL
+ */
+//#define MBEDTLS_SSL_TRUNCATED_HMAC
+
+/**
+ * \def MBEDTLS_THREADING_ALT
+ *
+ * Provide your own alternate threading implementation.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to allow your own alternate threading implementation.
+ */
+//#define MBEDTLS_THREADING_ALT
+
+/**
+ * \def MBEDTLS_THREADING_PTHREAD
+ *
+ * Enable the pthread wrapper layer for the threading layer.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to enable pthread mutexes.
+ */
+//#define MBEDTLS_THREADING_PTHREAD
+
+/**
+ * \def MBEDTLS_VERSION_FEATURES
+ *
+ * Allow run-time checking of compile-time enabled features. Thus allowing users
+ * to check at run-time if the library is for instance compiled with threading
+ * support via mbedtls_version_check_feature().
+ *
+ * Requires: MBEDTLS_VERSION_C
+ *
+ * Comment this to disable run-time checking and save ROM space
+ */
+//#define MBEDTLS_VERSION_FEATURES
+
+/**
+ * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an extension in a v1 or v2 certificate.
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+
+/**
+ * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an unknown critical extension.
+ *
+ * \warning Depending on your PKI use, enabling this can be a security risk!
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+
+/**
+ * \def MBEDTLS_X509_CHECK_KEY_USAGE
+ *
+ * Enable verification of the keyUsage extension (CA and leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused
+ * (intermediate) CA and leaf certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip keyUsage checking for both CA and leaf certificates.
+ */
+//#define MBEDTLS_X509_CHECK_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+ *
+ * Enable verification of the extendedKeyUsage extension (leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip extendedKeyUsage checking for certificates.
+ */
+//#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
+ *
+ * Enable parsing and verification of X.509 certificates, CRLs and CSRS
+ * signed with RSASSA-PSS (aka PKCS#1 v2.1).
+ *
+ * Comment this macro to disallow using RSASSA-PSS in certificates.
+ */
+//#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+
+/**
+ * \def MBEDTLS_ZLIB_SUPPORT
+ *
+ * If set, the SSL/TLS module uses ZLIB to support compression and
+ * decompression of packet data.
+ *
+ * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
+ * CRIME attack. Before enabling this option, you should examine with care if
+ * CRIME or similar exploits may be a applicable to your use case.
+ *
+ * \note Currently compression can't be used with DTLS.
+ *
+ * Used in: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This feature requires zlib library and headers to be present.
+ *
+ * Uncomment to enable use of ZLIB
+ */
+//#define MBEDTLS_ZLIB_SUPPORT
+/* \} name SECTION: mbed TLS feature support */
+
+/**
+ * \name SECTION: mbed TLS modules
+ *
+ * This section enables or disables entire modules in mbed TLS
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_AESNI_C
+ *
+ * Enable AES-NI support on x86-64.
+ *
+ * Module: library/aesni.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the AES-NI instructions on x86-64
+ */
+//#define MBEDTLS_AESNI_C
+
+/**
+ * \def MBEDTLS_AES_C
+ *
+ * Enable the AES block cipher.
+ *
+ * Module: library/aes.c
+ * Caller: library/ssl_tls.c
+ * library/pem.c
+ * library/ctr_drbg.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *
+ * PEM_PARSE uses AES for decrypting encrypted keys.
+ */
+#define MBEDTLS_AES_C
+
+/**
+ * \def MBEDTLS_ARC4_C
+ *
+ * Enable the ARCFOUR stream cipher.
+ *
+ * Module: library/arc4.c
+ * Caller: library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+//#define MBEDTLS_ARC4_C
+
+/**
+ * \def MBEDTLS_ASN1_PARSE_C
+ *
+ * Enable the generic ASN1 parser.
+ *
+ * Module: library/asn1.c
+ * Caller: library/x509.c
+ * library/dhm.c
+ * library/pkcs12.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ */
+//#define MBEDTLS_ASN1_PARSE_C
+
+/**
+ * \def MBEDTLS_ASN1_WRITE_C
+ *
+ * Enable the generic ASN1 writer.
+ *
+ * Module: library/asn1write.c
+ * Caller: library/ecdsa.c
+ * library/pkwrite.c
+ * library/x509_create.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ */
+//#define MBEDTLS_ASN1_WRITE_C
+
+/**
+ * \def MBEDTLS_BASE64_C
+ *
+ * Enable the Base64 module.
+ *
+ * Module: library/base64.c
+ * Caller: library/pem.c
+ *
+ * This module is required for PEM support (required by X.509).
+ */
+#define MBEDTLS_BASE64_C
+
+/**
+ * \def MBEDTLS_BIGNUM_C
+ *
+ * Enable the multi-precision integer library.
+ *
+ * Module: library/bignum.c
+ * Caller: library/dhm.c
+ * library/ecp.c
+ * library/ecdsa.c
+ * library/rsa.c
+ * library/ssl_tls.c
+ *
+ * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
+ */
+//#define MBEDTLS_BIGNUM_C
+
+/**
+ * \def MBEDTLS_BLOWFISH_C
+ *
+ * Enable the Blowfish block cipher.
+ *
+ * Module: library/blowfish.c
+ */
+//#define MBEDTLS_BLOWFISH_C
+
+/**
+ * \def MBEDTLS_CAMELLIA_C
+ *
+ * Enable the Camellia block cipher.
+ *
+ * Module: library/camellia.c
+ * Caller: library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ */
+//#define MBEDTLS_CAMELLIA_C
+
+/**
+ * \def MBEDTLS_CCM_C
+ *
+ * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
+ *
+ * Module: library/ccm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-CCM ciphersuites, if other requisites are
+ * enabled as well.
+ */
+//#define MBEDTLS_CCM_C
+
+/**
+ * \def MBEDTLS_CERTS_C
+ *
+ * Enable the test certificates.
+ *
+ * Module: library/certs.c
+ * Caller:
+ *
+ * This module is used for testing (ssl_client/server).
+ */
+//#define MBEDTLS_CERTS_C
+
+/**
+ * \def MBEDTLS_CIPHER_C
+ *
+ * Enable the generic cipher layer.
+ *
+ * Module: library/cipher.c
+ * Caller: library/ssl_tls.c
+ *
+ * Uncomment to enable generic cipher wrappers.
+ */
+#define MBEDTLS_CIPHER_C
+
+/**
+ * \def MBEDTLS_CMAC_C
+ *
+ * Enable the CMAC (Cipher-based Message Authentication Code) mode for block
+ * ciphers.
+ *
+ * Module: library/cmac.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C
+ *
+ */
+#define MBEDTLS_CMAC_C
+
+/**
+ * \def MBEDTLS_CTR_DRBG_C
+ *
+ * Enable the CTR_DRBG AES-256-based random generator.
+ *
+ * Module: library/ctr_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_AES_C
+ *
+ * This module provides the CTR_DRBG AES-256 random number generator.
+ */
+//#define MBEDTLS_CTR_DRBG_C
+
+/**
+ * \def MBEDTLS_DEBUG_C
+ *
+ * Enable the debug functions.
+ *
+ * Module: library/debug.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module provides debugging functions.
+ */
+//#define MBEDTLS_DEBUG_C
+
+/**
+ * \def MBEDTLS_DES_C
+ *
+ * Enable the DES block cipher.
+ *
+ * Module: library/des.c
+ * Caller: library/pem.c
+ * library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *
+ * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
+ */
+//#define MBEDTLS_DES_C
+
+/**
+ * \def MBEDTLS_DHM_C
+ *
+ * Enable the Diffie-Hellman-Merkle module.
+ *
+ * Module: library/dhm.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * DHE-RSA, DHE-PSK
+ */
+//#define MBEDTLS_DHM_C
+
+/**
+ * \def MBEDTLS_ECDH_C
+ *
+ * Enable the elliptic curve Diffie-Hellman library.
+ *
+ * Module: library/ecdh.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
+ *
+ * Requires: MBEDTLS_ECP_C
+ */
+//#define MBEDTLS_ECDH_C
+
+/**
+ * \def MBEDTLS_ECDSA_C
+ *
+ * Enable the elliptic curve DSA library.
+ *
+ * Module: library/ecdsa.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
+ */
+//#define MBEDTLS_ECDSA_C
+
+/**
+ * \def MBEDTLS_ECJPAKE_C
+ *
+ * Enable the elliptic curve J-PAKE library.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Module: library/ecjpake.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECJPAKE
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
+ */
+//#define MBEDTLS_ECJPAKE_C
+
+/**
+ * \def MBEDTLS_ECP_C
+ *
+ * Enable the elliptic curve over GF(p) library.
+ *
+ * Module: library/ecp.c
+ * Caller: library/ecdh.c
+ * library/ecdsa.c
+ * library/ecjpake.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
+ */
+//#define MBEDTLS_ECP_C
+
+/**
+ * \def MBEDTLS_ENTROPY_C
+ *
+ * Enable the platform-specific entropy code.
+ *
+ * Module: library/entropy.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
+ *
+ * This module provides a generic entropy pool
+ */
+//#define MBEDTLS_ENTROPY_C
+
+/**
+ * \def MBEDTLS_ERROR_C
+ *
+ * Enable error code to error string conversion.
+ *
+ * Module: library/error.c
+ * Caller:
+ *
+ * This module enables mbedtls_strerror().
+ */
+//#define MBEDTLS_ERROR_C
+
+/**
+ * \def MBEDTLS_GCM_C
+ *
+ * Enable the Galois/Counter Mode (GCM) for AES.
+ *
+ * Module: library/gcm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
+ * requisites are enabled as well.
+ */
+//#define MBEDTLS_GCM_C
+
+/**
+ * \def MBEDTLS_HAVEGE_C
+ *
+ * Enable the HAVEGE random generator.
+ *
+ * Warning: the HAVEGE random generator is not suitable for virtualized
+ * environments
+ *
+ * Warning: the HAVEGE random generator is dependent on timing and specific
+ * processor traits. It is therefore not advised to use HAVEGE as
+ * your applications primary random generator or primary entropy pool
+ * input. As a secondary input to your entropy pool, it IS able add
+ * the (limited) extra entropy it provides.
+ *
+ * Module: library/havege.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_TIMING_C
+ *
+ * Uncomment to enable the HAVEGE random generator.
+ */
+//#define MBEDTLS_HAVEGE_C
+
+/**
+ * \def MBEDTLS_HMAC_DRBG_C
+ *
+ * Enable the HMAC_DRBG random generator.
+ *
+ * Module: library/hmac_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * Uncomment to enable the HMAC_DRBG random number geerator.
+ */
+//#define MBEDTLS_HMAC_DRBG_C
+
+/**
+ * \def MBEDTLS_MD_C
+ *
+ * Enable the generic message digest layer.
+ *
+ * Module: library/md.c
+ * Caller:
+ *
+ * Uncomment to enable generic message digest wrappers.
+ */
+//#define MBEDTLS_MD_C
+
+/**
+ * \def MBEDTLS_MD2_C
+ *
+ * Enable the MD2 hash algorithm.
+ *
+ * Module: library/md2.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD2-signed X.509 certs.
+ */
+//#define MBEDTLS_MD2_C
+
+/**
+ * \def MBEDTLS_MD4_C
+ *
+ * Enable the MD4 hash algorithm.
+ *
+ * Module: library/md4.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD4-signed X.509 certs.
+ */
+//#define MBEDTLS_MD4_C
+
+/**
+ * \def MBEDTLS_MD5_C
+ *
+ * Enable the MD5 hash algorithm.
+ *
+ * Module: library/md5.c
+ * Caller: library/md.c
+ * library/pem.c
+ * library/ssl_tls.c
+ *
+ * This module is required for SSL/TLS and X.509.
+ * PEM_PARSE uses MD5 for decrypting encrypted keys.
+ */
+//#define MBEDTLS_MD5_C
+
+/**
+ * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Enable the buffer allocator implementation that makes use of a (stack)
+ * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
+ * calls)
+ *
+ * Module: library/memory_buffer_alloc.c
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
+ *
+ * Enable this module to enable the buffer memory allocator.
+ */
+//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+
+/**
+ * \def MBEDTLS_NET_C
+ *
+ * Enable the TCP and UDP over IPv6/IPv4 networking routines.
+ *
+ * \note This module only works on POSIX/Unix (including Linux, BSD and OS X)
+ * and Windows. For other platforms, you'll want to disable it, and write your
+ * own networking callbacks to be passed to \c mbedtls_ssl_set_bio().
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/net_sockets.c
+ *
+ * This module provides networking routines.
+ */
+//#define MBEDTLS_NET_C
+
+/**
+ * \def MBEDTLS_OID_C
+ *
+ * Enable the OID database.
+ *
+ * Module: library/oid.c
+ * Caller: library/asn1write.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ * library/pkwrite.c
+ * library/rsa.c
+ * library/x509.c
+ * library/x509_create.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * This modules translates between OIDs and internal values.
+ */
+//#define MBEDTLS_OID_C
+
+/**
+ * \def MBEDTLS_PADLOCK_C
+ *
+ * Enable VIA Padlock support on x86.
+ *
+ * Module: library/padlock.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the VIA PadLock on x86.
+ */
+//#define MBEDTLS_PADLOCK_C
+
+/**
+ * \def MBEDTLS_PEM_PARSE_C
+ *
+ * Enable PEM decoding / parsing.
+ *
+ * Module: library/pem.c
+ * Caller: library/dhm.c
+ * library/pkparse.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for decoding / parsing PEM files.
+ */
+//#define MBEDTLS_PEM_PARSE_C
+
+/**
+ * \def MBEDTLS_PEM_WRITE_C
+ *
+ * Enable PEM encoding / writing.
+ *
+ * Module: library/pem.c
+ * Caller: library/pkwrite.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for encoding / writing PEM files.
+ */
+//#define MBEDTLS_PEM_WRITE_C
+
+/**
+ * \def MBEDTLS_PK_C
+ *
+ * Enable the generic public (asymetric) key layer.
+ *
+ * Module: library/pk.c
+ * Caller: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
+ *
+ * Uncomment to enable generic public key wrappers.
+ */
+//#define MBEDTLS_PK_C
+
+/**
+ * \def MBEDTLS_PK_PARSE_C
+ *
+ * Enable the generic public (asymetric) key parser.
+ *
+ * Module: library/pkparse.c
+ * Caller: library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key parse functions.
+ */
+//#define MBEDTLS_PK_PARSE_C
+
+/**
+ * \def MBEDTLS_PK_WRITE_C
+ *
+ * Enable the generic public (asymetric) key writer.
+ *
+ * Module: library/pkwrite.c
+ * Caller: library/x509write.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key write functions.
+ */
+//#define MBEDTLS_PK_WRITE_C
+
+/**
+ * \def MBEDTLS_PKCS5_C
+ *
+ * Enable PKCS#5 functions.
+ *
+ * Module: library/pkcs5.c
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the PKCS#5 functions.
+ */
+//#define MBEDTLS_PKCS5_C
+
+/**
+ * \def MBEDTLS_PKCS11_C
+ *
+ * Enable wrapper for PKCS#11 smartcard support.
+ *
+ * Module: library/pkcs11.c
+ * Caller: library/pk.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * This module enables SSL/TLS PKCS #11 smartcard support.
+ * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
+ */
+//#define MBEDTLS_PKCS11_C
+
+/**
+ * \def MBEDTLS_PKCS12_C
+ *
+ * Enable PKCS#12 PBE functions.
+ * Adds algorithms for parsing PKCS#8 encrypted private keys
+ *
+ * Module: library/pkcs12.c
+ * Caller: library/pkparse.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * Can use: MBEDTLS_ARC4_C
+ *
+ * This module enables PKCS#12 functions.
+ */
+//#define MBEDTLS_PKCS12_C
+
+/**
+ * \def MBEDTLS_PLATFORM_C
+ *
+ * Enable the platform abstraction layer that allows you to re-assign
+ * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
+ *
+ * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
+ * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
+ * above to be specified at runtime or compile time respectively.
+ *
+ * \note This abstraction layer must be enabled on Windows (including MSYS2)
+ * as other module rely on it for a fixed snprintf implementation.
+ *
+ * Module: library/platform.c
+ * Caller: Most other .c files
+ *
+ * This module enables abstraction of common (libc) functions.
+ */
+//#define MBEDTLS_PLATFORM_C
+
+/**
+ * \def MBEDTLS_RIPEMD160_C
+ *
+ * Enable the RIPEMD-160 hash algorithm.
+ *
+ * Module: library/ripemd160.c
+ * Caller: library/md.c
+ *
+ */
+//#define MBEDTLS_RIPEMD160_C
+
+/**
+ * \def MBEDTLS_RSA_C
+ *
+ * Enable the RSA public-key cryptosystem.
+ *
+ * Module: library/rsa.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509.c
+ *
+ * This module is used by the following key exchanges:
+ * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
+ */
+//#define MBEDTLS_RSA_C
+
+/**
+ * \def MBEDTLS_SHA1_C
+ *
+ * Enable the SHA1 cryptographic hash algorithm.
+ *
+ * Module: library/sha1.c
+ * Caller: library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509write_crt.c
+ *
+ * This module is required for SSL/TLS up to version 1.1, for TLS 1.2
+ * depending on the handshake parameters, and for SHA1-signed certificates.
+ */
+//#define MBEDTLS_SHA1_C
+
+/**
+ * \def MBEDTLS_SHA256_C
+ *
+ * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
+ *
+ * Module: library/sha256.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module adds support for SHA-224 and SHA-256.
+ * This module is required for the SSL/TLS 1.2 PRF function.
+ */
+//#define MBEDTLS_SHA256_C
+
+/**
+ * \def MBEDTLS_SHA512_C
+ *
+ * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
+ *
+ * Module: library/sha512.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module adds support for SHA-384 and SHA-512.
+ */
+//#define MBEDTLS_SHA512_C
+
+/**
+ * \def MBEDTLS_SSL_CACHE_C
+ *
+ * Enable simple SSL cache implementation.
+ *
+ * Module: library/ssl_cache.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_CACHE_C
+ */
+//#define MBEDTLS_SSL_CACHE_C
+
+/**
+ * \def MBEDTLS_SSL_COOKIE_C
+ *
+ * Enable basic implementation of DTLS cookies for hello verification.
+ *
+ * Module: library/ssl_cookie.c
+ * Caller:
+ */
+//#define MBEDTLS_SSL_COOKIE_C
+
+/**
+ * \def MBEDTLS_SSL_TICKET_C
+ *
+ * Enable an implementation of TLS server-side callbacks for session tickets.
+ *
+ * Module: library/ssl_ticket.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_CIPHER_C
+ */
+//#define MBEDTLS_SSL_TICKET_C
+
+/**
+ * \def MBEDTLS_SSL_CLI_C
+ *
+ * Enable the SSL/TLS client code.
+ *
+ * Module: library/ssl_cli.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS client support.
+ */
+//#define MBEDTLS_SSL_CLI_C
+
+/**
+ * \def MBEDTLS_SSL_SRV_C
+ *
+ * Enable the SSL/TLS server code.
+ *
+ * Module: library/ssl_srv.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS server support.
+ */
+//#define MBEDTLS_SSL_SRV_C
+
+/**
+ * \def MBEDTLS_SSL_TLS_C
+ *
+ * Enable the generic SSL/TLS code.
+ *
+ * Module: library/ssl_tls.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * and at least one of the MBEDTLS_SSL_PROTO_XXX defines
+ *
+ * This module is required for SSL/TLS.
+ */
+//#define MBEDTLS_SSL_TLS_C
+
+/**
+ * \def MBEDTLS_THREADING_C
+ *
+ * Enable the threading abstraction layer.
+ * By default mbed TLS assumes it is used in a non-threaded environment or that
+ * contexts are not shared between threads. If you do intend to use contexts
+ * between threads, you will need to enable this layer to prevent race
+ * conditions. See also our Knowledge Base article about threading:
+ * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
+ *
+ * Module: library/threading.c
+ *
+ * This allows different threading implementations (self-implemented or
+ * provided).
+ *
+ * You will have to enable either MBEDTLS_THREADING_ALT or
+ * MBEDTLS_THREADING_PTHREAD.
+ *
+ * Enable this layer to allow use of mutexes within mbed TLS
+ */
+//#define MBEDTLS_THREADING_C
+
+/**
+ * \def MBEDTLS_TIMING_C
+ *
+ * Enable the semi-portable timing interface.
+ *
+ * \note The provided implementation only works on POSIX/Unix (including Linux,
+ * BSD and OS X) and Windows. On other platforms, you can either disable that
+ * module and provide your own implementations of the callbacks needed by
+ * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide
+ * your own implementation of the whole module by setting
+ * \c MBEDTLS_TIMING_ALT in the current file.
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/timing.c
+ * Caller: library/havege.c
+ *
+ * This module is used by the HAVEGE random number generator.
+ */
+//#define MBEDTLS_TIMING_C
+
+/**
+ * \def MBEDTLS_VERSION_C
+ *
+ * Enable run-time version information.
+ *
+ * Module: library/version.c
+ *
+ * This module provides run-time version information.
+ */
+//#define MBEDTLS_VERSION_C
+
+/**
+ * \def MBEDTLS_X509_USE_C
+ *
+ * Enable X.509 core for using certificates.
+ *
+ * Module: library/x509.c
+ * Caller: library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
+ * MBEDTLS_PK_PARSE_C
+ *
+ * This module is required for the X.509 parsing modules.
+ */
+//#define MBEDTLS_X509_USE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Enable X.509 certificate parsing.
+ *
+ * Module: library/x509_crt.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 certificate parsing.
+ */
+//#define MBEDTLS_X509_CRT_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CRL_PARSE_C
+ *
+ * Enable X.509 CRL parsing.
+ *
+ * Module: library/x509_crl.c
+ * Caller: library/x509_crt.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 CRL parsing.
+ */
+//#define MBEDTLS_X509_CRL_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_PARSE_C
+ *
+ * Enable X.509 Certificate Signing Request (CSR) parsing.
+ *
+ * Module: library/x509_csr.c
+ * Caller: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is used for reading X.509 certificate request.
+ */
+//#define MBEDTLS_X509_CSR_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CREATE_C
+ *
+ * Enable X.509 core for creating certificates.
+ *
+ * Module: library/x509_create.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
+ *
+ * This module is the basis for creating X.509 certificates and CSRs.
+ */
+//#define MBEDTLS_X509_CREATE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_WRITE_C
+ *
+ * Enable creating X.509 certificates.
+ *
+ * Module: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate creation.
+ */
+//#define MBEDTLS_X509_CRT_WRITE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_WRITE_C
+ *
+ * Enable creating X.509 Certificate Signing Requests (CSR).
+ *
+ * Module: library/x509_csr_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate request writing.
+ */
+//#define MBEDTLS_X509_CSR_WRITE_C
+
+/**
+ * \def MBEDTLS_XTEA_C
+ *
+ * Enable the XTEA block cipher.
+ *
+ * Module: library/xtea.c
+ * Caller:
+ */
+//#define MBEDTLS_XTEA_C
+
+/* \} name SECTION: mbed TLS modules */
+
+/**
+ * \name SECTION: Module configuration options
+ *
+ * This section allows for the setting of module specific sizes and
+ * configuration options. The default values are already present in the
+ * relevant header files and should suffice for the regular use cases.
+ *
+ * Our advice is to enable options and change their values here
+ * only if you have a good reason and know the consequences.
+ *
+ * Please check the respective header file for documentation on these
+ * parameters (to prevent duplicate documentation).
+ * \{
+ */
+
+/* MPI / BIGNUM options */
+//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */
+//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */
+
+/* CTR_DRBG options */
+//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+
+/* HMAC_DRBG options */
+//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+
+/* ECP options */
+//#define MBEDTLS_ECP_MAX_BITS 521 /**< Maximum bit size of groups */
+//#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< Maximum window size used */
+//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
+
+/* Entropy options */
+//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */
+//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */
+//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */
+
+/* Memory buffer allocator options */
+//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */
+
+/* Platform options */
+//#define MBEDTLS_PLATFORM_STD_MEM_HDR <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
+//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */
+
+/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
+/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
+//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */
+
+/* SSL options */
+//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */
+//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */
+//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
+//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+
+/**
+ * Complete list of ciphersuites to use, in order of preference.
+ *
+ * \warning No dependency checking is done on that field! This option can only
+ * be used to restrict the set of available ciphersuites. It is your
+ * responsibility to make sure the needed modules are active.
+ *
+ * Use this to save a few hundred bytes of ROM (default ordering of all
+ * available ciphersuites) and a few to a few hundred bytes of RAM.
+ *
+ * The value below is only an example, not the default.
+ */
+//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+
+/* X509 options */
+//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */
+//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */
+
+/**
+ * Allow SHA-1 in the default TLS configuration for certificate signing.
+ * Without this build-time option, SHA-1 support must be activated explicitly
+ * through mbedtls_ssl_conf_cert_profile. Turning on this option is not
+ * recommended because of it is possible to generte SHA-1 collisions, however
+ * this may be safe for legacy infrastructure where additional controls apply.
+ */
+// #define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES
+
+/**
+ * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake
+ * signature and ciphersuite selection. Without this build-time option, SHA-1
+ * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes.
+ * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by
+ * default. At the time of writing, there is no practical attack on the use
+ * of SHA-1 in handshake signatures, hence this option is turned on by default
+ * for compatibility with existing peers.
+ */
+//#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
+
+
+#include "check_config.h"
+
+#endif /* MBEDTLS_LORA_CONFIG_H */
diff -r 000000000000 -r f930f0440fd5 inc/standby.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/standby.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,72 @@
+#ifndef _DSA_STANDBY_H_
+#define _DSA_STANDBY_H_
+
+#include "mbed.h"
+#include "rtc_api_hal.h"
+
+enum WakeupType {
+ WAKEUP_RESET,
+ WAKEUP_TIMER,
+ WAKEUP_PIN
+};
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_set_wake_up_timer_s(uint32_t delta)
+{
+ uint32_t clock = RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
+
+ // HAL_RTCEx_SetWakeUpTimer_IT will assert that delta is 0xFFFF at max
+ if (delta > 0xFFFF) {
+ delta -= 0x10000;
+ clock = RTC_WAKEUPCLOCK_CK_SPRE_17BITS;
+ }
+
+ RtcHandle.Instance = RTC;
+
+ HAL_StatusTypeDef status = HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, delta, clock);
+
+ if (status != HAL_OK) {
+ printf("Set wake up timer failed: %d\n", status);
+ NVIC_SystemReset();
+ }
+}
+
+WakeupType get_wakeup_type() {
+
+ if(READ_BIT(RTC->ISR, RTC_ISR_WUTF))
+ return WAKEUP_TIMER;
+
+ // this is set by timer too, but that's checked already
+ // above.
+ if(READ_BIT(PWR->CSR, PWR_CSR_WUF))
+ return WAKEUP_PIN;
+
+ return WAKEUP_RESET;
+}
+
+void standby(int seconds) {
+ printf("Going to sleep!\n");
+
+ core_util_critical_section_enter();
+
+ // Clear wakeup flag, just in case.
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+
+ // Enable wakeup timer.
+ rtc_set_wake_up_timer_s(seconds);
+
+ // Enable debug interface working in standby. Causes power consumption to increase drastically while in standby.
+ //HAL_DBGMCU_EnableDBGStandbyMode();
+
+ HAL_PWR_EnterSTANDBYMode();
+
+ // this should not happen...
+ rtc_deactivate_wake_up_timer();
+ core_util_critical_section_exit();
+
+ // something went wrong, let's reset
+ NVIC_SystemReset();
+}
+
+#endif // _DSA_STANDBY_H_
diff -r 000000000000 -r f930f0440fd5 inc/trace_helper.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/trace_helper.cpp Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,90 @@
+/**
+ * Copyright (c) 2017, Arm Limited and affiliates.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "drivers/Serial.h"
+
+/**
+ * Serial object for console tracing
+ */
+mbed::Serial pc(USBTX, USBRX, MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+/**
+ * If we have tracing library available, we can see traces from within the
+ * stack. The library could be made unavailable by removing FEATURE_COMMON_PAL
+ * from the mbed_app.json to save RAM.
+ */
+#if defined(FEATURE_COMMON_PAL)
+
+ #include "platform/PlatformMutex.h"
+ #include "mbed_trace.h"
+
+ /**
+ * Local mutex object for synchronization
+ */
+ static PlatformMutex mutex;
+
+ static void serial_lock();
+ static void serial_unlock();
+ static void trace_printer(const char* str);
+
+ /**
+ * Sets up trace for the application
+ * Wouldn't do anything if the FEATURE_COMMON_PAL is not added
+ * or if the trace is disabled using mbed_app.json
+ */
+ void setup_trace()
+ {
+ // setting up Mbed trace.
+ mbed_trace_mutex_wait_function_set(serial_lock);
+ mbed_trace_mutex_release_function_set(serial_unlock);
+ mbed_trace_init();
+ mbed_trace_print_function_set(trace_printer);
+ }
+
+ /**
+ * Lock provided for serial printing used by trace library
+ */
+ static void serial_lock()
+ {
+ mutex.lock();
+ }
+
+ /**
+ * Releasing lock provided for serial printing used by trace library
+ */
+ static void serial_unlock()
+ {
+ mutex.unlock();
+ }
+
+ /**
+ * Prints the Mbed trace, used by trace library.
+ * Not intended for local use.
+ */
+ static void trace_printer(const char* str)
+ {
+ pc.printf("%s\r\n", str);
+ }
+
+#else
+
+ void setup_trace()
+ {
+ }
+
+#endif
+
diff -r 000000000000 -r f930f0440fd5 inc/trace_helper.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/trace_helper.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,28 @@ +/** + * Copyright (c) 2017, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_TRACE_HELPER_H_ +#define APP_TRACE_HELPER_H_ + +/** + * Helper function for the application to setup Mbed trace. + * It Wouldn't do anything if the FEATURE_COMMON_PAL is not added + * or if the trace is disabled using mbed_app.json + */ +void setup_trace(); + +#endif /* APP_TRACE_HELPER_H_ */
diff -r 000000000000 -r f930f0440fd5 main.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,228 @@
+#include "mbed.h"
+#include "hcsr04.h"
+#include "SDBlockDevice.h"
+#include "FATFileSystem.h"
+//#include "MQTTTimer.h"
+//#include "CayenneMQTTClient.h"
+//#include "MQTTNetworkIDW01M1.h"
+#include "lorawan_network.h"
+#include "CayenneLPP.h"
+#include "mbed_events.h"
+#include "mbed_trace.h"
+#include "lora_radio_helper.h"
+#include "SX1276_LoRaRadio.h"
+#include "LoRaWANInterface.h"
+//#include "stm32_standby.h"
+
+
+
+
+//#define STANDBY_TIME_S 1* 60
+
+extern EventQueue ev_queue;
+
+static uint32_t DEV_ADDR_1 = 0x260118FA;
+static uint8_t NWK_S_KEY_1[] = { 0x5D, 0xD5, 0xC9, 0x84, 0xB9, 0xCE, 0x26, 0x05, 0xB7, 0x61, 0xBF, 0x9F, 0x3C, 0x2D, 0x4E, 0x14 };
+static uint8_t APP_S_KEY_1[] = { 0xF0, 0xE4, 0xA1, 0xEB, 0x1F, 0xB5, 0x6E, 0xBA, 0x31, 0x69, 0x80, 0x9D, 0x85, 0x92, 0x68, 0xB4 };
+SDBlockDevice sd(PC_12, PC_11, PC_10, D10);// mosi, miso, sclk, cs
+FATFileSystem fs("sd");
+FlashIAP flash;
+
+void apply_update(FILE *file, uint32_t address);
+
+HCSR04 sensor(D4, D3);
+//Serial pc(USBTX, USBRX);
+//FILE *fp; // File pointer declear
+
+
+int dw,d,M,y,h,m,s; //VARIABLES FOR TIME AND YEAR
+
+
+//global variable
+long distance;
+
+ bool dist_updated = false;
+ float volume;
+
+
+
+void dist_measure(){
+ sensor.start();
+ wait_ms(100);
+ distance=sensor.get_dist_cm();
+ volume = 6*6*(2-(distance*0.01));
+ dist_updated = true;
+
+ }
+
+void check_for_updated_dist() {
+
+ if (dist_updated){
+ dist_updated = false ;
+ printf("Measure Distance = %ld ",distance);
+ printf("Volume=%3.0f\n", volume);
+
+ CayenneLPP payload(50);
+ float volume_value = volume;
+ printf("Volume_value=%f\n", volume_value);
+ payload.addAnalogInput(4, volume_value);
+
+ if (!lorawan_send(&payload)){
+ // delete distance;
+ // standby(STANDBY_TIME_S);
+
+ }
+ }
+ }
+/*void SetDateTime(int year = 2019, int mon = 1, int day = 1, int hour = 0, int min = 0, int sec = 0) {
+ struct tm Clock;
+ Clock.tm_year = year - 1900;
+ Clock.tm_mon = mon - 1; // note: subtract 1
+ Clock.tm_mday = day;
+ Clock.tm_hour = hour;
+ Clock.tm_min = min;
+ Clock.tm_sec = sec;
+ time_t epoch = mktime(&Clock);
+ if (epoch == (time_t) -1) {
+ error("Error in clock setting\n");
+ // Stop here
+ }
+ set_time(epoch);
+}*/
+
+static void lora_event_handler(lorawan_event_t event) {
+ switch (event) {
+ case CONNECTED:
+ printf("[LNWK][INFO] Connection - Successful\n");
+ break;
+ case DISCONNECTED:
+ ev_queue.break_dispatch();
+ printf("[LNWK][INFO] Disconnected Successfully\n");
+ break;
+ case TX_DONE:
+ printf("[LNWK][INFO] Message Sent to Network Server\n");
+
+ // delete distance;
+ //standby(STANDBY_TIME_S);
+
+ break;
+ case TX_TIMEOUT:
+ case TX_ERROR:
+ case TX_CRYPTO_ERROR:
+ case TX_SCHEDULING_ERROR:
+ printf("[LNWK][INFO] Transmission Error - EventCode = %d\n", event);
+
+
+ //delete distance;
+ // standby(STANDBY_TIME_S);
+
+ break;
+ case RX_DONE:
+ printf("[LNWK][INFO] Received message from Network Server\n");
+ receive_message();
+ break;
+ case RX_TIMEOUT:
+ case RX_ERROR:
+ printf("[LNWK][INFO] Error in reception - Code = %d\n", event);
+ break;
+ case JOIN_FAILURE:
+ printf("[LNWK][INFO] ABP Failed - Check Keys\n");
+ break;
+ default:
+ MBED_ASSERT("Unknown Event");
+ }
+}
+
+void sd_write(){
+
+ //END OF CODE USED FOR OBTAINING TIME
+ sensor.start();
+ wait_ms(100);
+ long distance=sensor.get_dist_cm();
+ printf("distance is %dcm\n", distance);
+ wait_ms(1000);
+
+ }
+ int main() {
+
+ printf("=========================================\n");
+ printf(" Water Level Monitoring System \n");
+ printf("=========================================\n");
+ char date[64]; //string for storing the current date
+ char timeofday[64]; //string for storing the current time
+
+ struct tm t; //time structure for setting the time
+
+ //set time structure to 20 Sep 2016 00:31:01
+ time_t rawtime;
+ //time_t seconds; //time_t variable to read the number of seconds since January 1, 1970 for time calculations
+ //set_time(rawtime);
+ struct tm * timeinfo;
+
+ time ( &rawtime );
+ timeinfo = localtime ( &rawtime );
+
+ printf ( "Current local time and date: %s", asctime (timeinfo) );
+ t.tm_year = 2019 - 1900;
+ t.tm_mon = 6 - 1;
+ t.tm_mday = 19;
+ t.tm_hour = 14;
+ t.tm_min = 23;
+ t.tm_sec = 8;
+
+
+ //use the time structure and set the real-time clock (RTC) time
+ set_time(mktime(&t));
+ while (true)
+ {
+ lorawan_setup(DEV_ADDR_1, NWK_S_KEY_1, APP_S_KEY_1, lora_event_handler);
+
+ printf("Measuring Distance...\n");
+
+ //immediately measure the distance
+ sensor.start();
+ wait_ms(100);
+ distance = sensor.get_dist_cm();
+ printf("Measuring Dist =%ld...\n",distance);
+
+
+ // Try to mount the filesystem.
+ printf("Mounting the filesystem... ");
+
+ int err = fs.mount(&sd);
+ printf("%s\r\n", (err ? "Failed :(\r\n" : "OK\r\n"));
+ if (err)
+ return err;
+
+ // Open a file.
+ printf("Opening file '/sd/mylogger.txt'... ");
+ FILE* fp = fopen("/sd/mylogger.txt", "a"); // File open for "a"ppend
+ if (fp == NULL) { // Error!
+ // printf("Unable to write the file\r\n");
+
+ }
+ else {
+ char buffer[64];
+ strftime(buffer, 64, "%I:%M %p\n", localtime(&rawtime));
+ // printf("Time as a custom formatted string = %s", buffer);
+ time_t seconds = time(NULL); //read the new time value
+ strftime(date, 64, "%d/%m/%y", localtime(&rawtime)); //create a date string from the time value
+ strftime(timeofday, 64, "%H:%M:%S", localtime(&rawtime)); //create a time string from the time value
+ fprintf(fp, "%s %s %dcm\r\n", date, timeofday, distance); //write the date string, time string, and analog integer value to the file
+ //the /r/n combination puts the entries on different lines in the file
+ //printf("%dcm ",distance); // Append data to SD card.
+ //fprintf(fp, "%dcm\r\n",distance); // Serial monitor.
+ }
+ fclose(fp);
+ // Cloce file.
+ wait(20);
+ printf("File successfully written!\r\n"); // Serial monitor.
+ dist_measure();
+ ev_queue.call_every(3000, &check_for_updated_dist);
+ ev_queue.dispatch_forever();
+
+ printf ( "Current local time and date: %s", asctime (timeinfo) );
+
+ }
+
+}
\ No newline at end of file
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1272/SX1272_LoRaRadio.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1272/SX1272_LoRaRadio.cpp Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,2174 @@
+/**
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C)2013 Semtech
+ ___ _____ _ ___ _ _____ ___ ___ ___ ___
+/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __|
+\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _|
+|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___|
+embedded.connectivity.solutions===============
+
+Description: Radio driver for Semtech SX1272 LoRa radio chip. Implements LoRaRadio class.
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE )
+
+
+Copyright (c) 2017, Arm Limited and affiliates.
+
+SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include <stdio.h>
+#include <math.h> //rint
+#include <string.h>
+#include "mbed.h"
+
+#include "SX1272_LoRaRadio.h"
+#include "sx1272Regs-Fsk.h"
+#include "sx1272Regs-LoRa.h"
+
+#ifdef DEVICE_SPI
+
+#if defined(FEATURE_COMMON_PAL)
+#include "mbed_trace.h"
+#define TRACE_GROUP "LRAD"
+#else
+#define tr_debug(...) (void(0)) //dummies if feature common pal is not added
+#define tr_info(...) (void(0)) //dummies if feature common pal is not added
+#define tr_error(...) (void(0)) //dummies if feature common pal is not added
+#endif //defined(FEATURE_COMMON_PAL)
+
+#ifdef MBED_SX1272_LORA_RADIO_SPI_FREQUENCY
+#define SPI_FREQUENCY MBED_SX1272_LORA_RADIO_SPI_FREQUENCY
+#else
+#define SPI_FREQUENCY 8000000
+#endif
+
+// Sync word for Private LoRa networks
+#define LORA_MAC_PRIVATE_SYNCWORD 0x12
+// Sync word for Public LoRa networks
+#define LORA_MAC_PUBLIC_SYNCWORD 0x34
+
+// SX1272 definitions
+#define XTAL_FREQ 32000000
+#define FREQ_STEP 61.03515625
+
+
+
+enum RadioVariant {
+ SX1272UNDEFINED = 0,
+ SX1272MB2XAS,
+ SX1272MB1DCS
+};
+
+/*!
+ * FSK bandwidth definition
+ */
+typedef struct
+{
+ uint32_t bandwidth;
+ uint8_t register_value;
+} fsk_bw_t;
+
+/*!
+ * Radio registers definition
+ */
+typedef struct
+{
+ modem_type modem;
+ uint8_t addr;
+ uint8_t value;
+} radio_registers_t;
+
+/*!
+ * Constant values need to compute the RSSI value
+ */
+#define RSSI_OFFSET -139
+
+#define RADIO_INIT_REGISTERS_VALUE \
+{ \
+ { MODEM_FSK , REG_LNA , 0x23 },\
+ { MODEM_FSK , REG_RXCONFIG , 0x1E },\
+ { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
+ { MODEM_FSK , REG_AFCFEI , 0x01 },\
+ { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
+ { MODEM_FSK , REG_OSC , 0x07 },\
+ { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
+ { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
+ { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
+ { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
+ { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
+ { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
+ { MODEM_FSK , REG_IMAGECAL , 0x02 },\
+ { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
+ { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
+ { MODEM_LORA, REG_LR_DETECTOPTIMIZE , 0x43 },\
+ { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
+}
+
+const fsk_bw_t fsk_bandwidths[] =
+{
+ { 2600 , 0x17 },
+ { 3100 , 0x0F },
+ { 3900 , 0x07 },
+ { 5200 , 0x16 },
+ { 6300 , 0x0E },
+ { 7800 , 0x06 },
+ { 10400 , 0x15 },
+ { 12500 , 0x0D },
+ { 15600 , 0x05 },
+ { 20800 , 0x14 },
+ { 25000 , 0x0C },
+ { 31300 , 0x04 },
+ { 41700 , 0x13 },
+ { 50000 , 0x0B },
+ { 62500 , 0x03 },
+ { 83333 , 0x12 },
+ { 100000, 0x0A },
+ { 125000, 0x02 },
+ { 166700, 0x11 },
+ { 200000, 0x09 },
+ { 250000, 0x01 },
+ { 300000, 0x00 }, // Invalid bandwidth
+};
+
+/**
+ * SPI read/write masks
+ */
+#define SPI_WRITE_CMD 0x80
+#define SPI_READ_CMD 0x7F
+
+/**
+ * Signals
+ */
+#define SIG_DIO0 0x01
+#define SIG_DIO1 0x02
+#define SIG_DIO2 0x04
+#define SIG_DIO3 0x08
+#define SIG_DIO4 0x10
+#define SIG_DIO5 0x20
+#define SIG_TIMOUT 0x40
+
+/**
+ * Radio hardware registers initialization
+ */
+static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE;
+
+
+/**
+ * Constructor
+ */
+SX1272_LoRaRadio::SX1272_LoRaRadio(PinName spi_mosi,
+ PinName spi_miso,
+ PinName spi_sclk,
+ PinName nss,
+ PinName reset,
+ PinName dio0,
+ PinName dio1,
+ PinName dio2,
+ PinName dio3,
+ PinName dio4,
+ PinName dio5,
+ PinName rf_switch_ctl1,
+ PinName rf_switch_ctl2,
+ PinName txctl,
+ PinName rxctl,
+ PinName antswitch,
+ PinName pwr_amp_ctl,
+ PinName tcxo)
+ : _spi(spi_mosi, spi_miso, spi_sclk),
+ _chip_select(nss, 1),
+ _reset_ctl(reset),
+ _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5),
+ _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0), _txctl(txctl, 0), _rxctl(rxctl, 0),
+ _ant_switch(antswitch, PIN_INPUT, PullUp, 0),
+ _pwr_amp_ctl(pwr_amp_ctl),
+ _tcxo(tcxo)
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ , irq_thread(osPriorityRealtime, 1024)
+#endif
+{
+ _rf_ctrls.ant_switch = antswitch;
+ _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl;
+ _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1;
+ _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2;
+ _rf_ctrls.rxctl = rxctl;
+ _rf_ctrls.txctl = txctl;
+
+ _dio4_pin = dio4;
+ _dio5_pin = dio5;
+
+ _radio_events = NULL;
+
+ if (tcxo != NC) {
+ _tcxo = 1;
+ }
+
+ radio_is_active = false;
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.start(mbed::callback(this, &SX1272_LoRaRadio::rf_irq_task));
+#endif
+}
+
+/**
+ * Destructor
+ */
+SX1272_LoRaRadio::~SX1272_LoRaRadio()
+{
+
+}
+
+/*****************************************************************************
+ * Public APIs *
+ ****************************************************************************/
+
+/**
+ * Acquire lock
+ */
+void SX1272_LoRaRadio::lock(void)
+{
+ mutex.lock();
+}
+
+/**
+ * Release lock
+ */
+void SX1272_LoRaRadio::unlock(void)
+{
+ mutex.unlock();
+}
+
+/**
+ * Initializes radio module
+ */
+void SX1272_LoRaRadio::init_radio(radio_events_t *events)
+{
+ _radio_events = events;
+
+ // Reset the radio transceiver
+ radio_reset();
+
+ // Setup radio variant type
+ set_sx1272_variant_type();
+
+ // setup SPI frequency
+ // default is 8MHz although, configurable through
+ // SPI_FREQUENCY macro
+ setup_spi();
+
+ // set radio mode to sleep
+ set_operation_mode(RF_OPMODE_SLEEP);
+
+ // Setup radio registers to defaults
+ setup_registers();
+
+ // set modem type - defaults to FSK here
+ set_modem(MODEM_FSK);
+
+ // set state to be idle
+ _rf_settings.state = RF_IDLE;
+
+ // Setup interrupts on DIO pins
+ setup_interrupts();
+}
+
+/**
+ * TODO: The purpose of this API is unclear.
+ * Need to start an internal discussion.
+ */
+bool SX1272_LoRaRadio::check_rf_frequency(uint32_t frequency)
+{
+ // Implement check. Currently all frequencies are supported ? What band ?
+ return true;
+}
+
+/**
+ * Sets up carrier frequency
+ */
+void SX1272_LoRaRadio::set_channel(uint32_t freq)
+{
+ _rf_settings.channel = freq;
+ freq = (uint32_t) ((double) freq / (double) FREQ_STEP);
+ write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF));
+ write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF));
+ write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF));
+}
+
+/**
+ * Returns current status of the radio state machine
+ */
+uint8_t SX1272_LoRaRadio::get_status(void)
+{
+ return _rf_settings.state;
+}
+
+/**
+ * sets the radio module to sleep
+ */
+
+void SX1272_LoRaRadio::sleep()
+{
+ // stop timers
+ tx_timeout_timer.detach();
+ rx_timeout_timer.detach();
+
+ // put module in sleep mode
+ set_operation_mode(RF_OPMODE_SLEEP);
+}
+
+/**
+ * Sets up operation mode
+ */
+void SX1272_LoRaRadio::set_operation_mode(uint8_t mode)
+{
+ if (mode == RF_OPMODE_SLEEP) {
+ set_low_power_mode(true);
+ } else {
+ set_low_power_mode(false);
+ set_antenna_switch(mode);
+ }
+
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode);
+}
+
+/**
+ * Sets the modem type to use
+ *
+ * At initialization FSK is chosen. Later stack or application
+ * can choose to change.
+ */
+void SX1272_LoRaRadio::set_modem(uint8_t modem )
+{
+ if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) {
+ _rf_settings.modem = MODEM_LORA;
+ } else {
+ _rf_settings.modem = MODEM_FSK;
+ }
+
+ if(_rf_settings.modem == modem ) {
+ // if the modem is already set
+ return;
+ }
+
+ _rf_settings.modem = modem;
+
+ switch(_rf_settings.modem)
+ {
+ default:
+ case MODEM_FSK:
+ // before changing modem mode, put the module to sleep
+ sleep();
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
+ | RFLR_OPMODE_LONGRANGEMODE_OFF);
+
+ // Datasheet Tables 28, 29 DIO mapping
+ write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode
+ write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e.,
+ // DIO5 and DIO4=ModeReady
+ break;
+ case MODEM_LORA:
+ sleep();
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
+ | RFLR_OPMODE_LONGRANGEMODE_ON);
+
+ // Datasheet Tables 17 DIO mapping for LoRa
+ // set to defaults
+ write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults
+ write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults
+
+ break;
+ }
+}
+
+/**
+ * Can be used by application/stack or the driver itself
+ * Ref: Datasheet 7.2.2 Manual Reset
+ */
+void SX1272_LoRaRadio::radio_reset()
+{
+ _reset_ctl.output();
+ _reset_ctl = 0;
+ wait_ms(2);
+ _reset_ctl.input();
+ wait_ms(6);
+}
+
+/**
+ * Sets up receiver related configurations
+ *
+ * Must be called before setting the radio in rx mode
+ */
+void SX1272_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidth_afc, uint16_t preamble_len,
+ uint16_t symb_timeout, bool fix_len,
+ uint8_t payload_len,
+ bool crc_on, bool freq_hop_on, uint8_t hop_period,
+ bool iq_inverted, bool rx_continuous)
+{
+ set_modem(modem);
+
+ switch (modem) {
+ case MODEM_FSK:
+ _rf_settings.fsk.bandwidth = bandwidth;
+ _rf_settings.fsk.datarate = datarate;
+ _rf_settings.fsk.bandwidth_afc = bandwidth_afc;
+ _rf_settings.fsk.fix_len = fix_len;
+ _rf_settings.fsk.payload_len = payload_len;
+ _rf_settings.fsk.crc_on = crc_on;
+ _rf_settings.fsk.iq_inverted = iq_inverted;
+ _rf_settings.fsk.rx_continuous = rx_continuous;
+ _rf_settings.fsk.preamble_len = preamble_len;
+ _rf_settings.fsk.rx_single_timeout =
+ symb_timeout * ((1.0 / (double) datarate) * 8.0) * 1e3;
+
+ datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate);
+ write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8));
+ write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
+
+ write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth));
+ write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc));
+
+ write_to_register(REG_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF));
+ write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
+
+ if (fix_len == 1) {
+ write_to_register(REG_PAYLOADLENGTH, payload_len);
+ } else {
+ write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum
+ }
+
+ write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1) & RF_PACKETCONFIG1_CRC_MASK
+ & RF_PACKETCONFIG1_PACKETFORMAT_MASK)
+ | ((fix_len == 1) ?
+ RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
+ RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
+ | (crc_on << 4));
+
+ // TODO why packet mode 2 ?
+ write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET));
+
+ break;
+
+ case MODEM_LORA:
+ _rf_settings.lora.bandwidth = bandwidth;
+ _rf_settings.lora.datarate = datarate;
+ _rf_settings.lora.coderate = coderate;
+ _rf_settings.lora.preamble_len = preamble_len;
+ _rf_settings.lora.fix_len = fix_len;
+ _rf_settings.lora.payload_len = payload_len;
+ _rf_settings.lora.crc_on = crc_on;
+ _rf_settings.lora.freq_hop_on = freq_hop_on;
+ _rf_settings.lora.hop_period = hop_period;
+ _rf_settings.lora.iq_inverted = iq_inverted;
+ _rf_settings.lora.rx_continuous = rx_continuous;
+
+ if (datarate > 12) {
+ datarate = 12;
+ } else if (datarate < 6) {
+ datarate = 6;
+ }
+
+ if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12)))
+ || ((bandwidth == 1) && (datarate == 12))) {
+ _rf_settings.lora.low_datarate_optimize = 0x01;
+ } else {
+ _rf_settings.lora.low_datarate_optimize = 0x00;
+ }
+
+ write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) & RFLR_MODEMCONFIG1_BW_MASK
+ & RFLR_MODEMCONFIG1_CODINGRATE_MASK
+ & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK
+ & RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK)
+ | (bandwidth << 6)
+ | (coderate << 3) | (fix_len << 2) | (crc_on << 1)
+ | _rf_settings.lora.low_datarate_optimize);
+
+ write_to_register(REG_LR_MODEMCONFIG2, (read_register(REG_LR_MODEMCONFIG2) & RFLR_MODEMCONFIG2_SF_MASK
+ & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)
+ | (datarate << 4)
+ | ((symb_timeout >> 8)
+ & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK));
+
+ write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF));
+
+ write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF));
+ write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
+
+ if (fix_len == 1) {
+ write_to_register(REG_LR_PAYLOADLENGTH, payload_len);
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register( REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK)
+ | RFLR_PLLHOP_FASTHOP_ON);
+ write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period);
+ }
+
+ if (datarate == 6) {
+ write_to_register( REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK)
+ | RFLR_DETECTIONOPTIMIZE_SF6);
+ write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6);
+ } else {
+ write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK)
+ | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * Sets up transmitter related configuration
+ *
+ * Must be called before putting the radio module in Tx mode or trying
+ * to send
+ */
+void SX1272_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power,
+ uint32_t fdev, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint16_t preamble_len, bool fix_len,
+ bool crc_on, bool freq_hop_on,
+ uint8_t hop_period, bool iq_inverted,
+ uint32_t timeout)
+{
+ set_modem(modem);
+ set_rf_tx_power(power);
+
+ switch (modem) {
+ case MODEM_FSK:
+ _rf_settings.fsk.power = power;
+ _rf_settings.fsk.f_dev = fdev;
+ _rf_settings.fsk.bandwidth = bandwidth;
+ _rf_settings.fsk.datarate = datarate;
+ _rf_settings.fsk.preamble_len = preamble_len;
+ _rf_settings.fsk.fix_len = fix_len;
+ _rf_settings.fsk.crc_on = crc_on;
+ _rf_settings.fsk.iq_inverted = iq_inverted;
+ _rf_settings.fsk.tx_timeout = timeout;
+
+ fdev = (uint16_t) ((double) fdev / (double) FREQ_STEP);
+ write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8));
+ write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF));
+
+ datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate);
+ write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8));
+ write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
+
+ write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
+ write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF);
+
+
+ write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1)
+ & RF_PACKETCONFIG1_CRC_MASK
+ & RF_PACKETCONFIG1_PACKETFORMAT_MASK)
+ | ((fix_len == 1) ?
+ RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
+ RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
+ | (crc_on << 4));
+
+ //cfg_mode = read_register(REG_PACKETCONFIG2);
+ write_to_register(REG_PACKETCONFIG2, read_register(REG_PACKETCONFIG2)
+ | RF_PACKETCONFIG2_DATAMODE_PACKET);
+
+ break;
+
+ case MODEM_LORA:
+ _rf_settings.lora.power = power;
+ _rf_settings.lora.bandwidth = bandwidth;
+ _rf_settings.lora.datarate = datarate;
+ _rf_settings.lora.coderate = coderate;
+ _rf_settings.lora.preamble_len = preamble_len;
+ _rf_settings.lora.fix_len = fix_len;
+ _rf_settings.lora.freq_hop_on = freq_hop_on;
+ _rf_settings.lora.hop_period = hop_period;
+ _rf_settings.lora.crc_on = crc_on;
+ _rf_settings.lora.iq_inverted = iq_inverted;
+ _rf_settings.lora.tx_timeout = timeout;
+
+ if (datarate > 12) {
+ datarate = 12;
+ } else if (datarate < 6) {
+ datarate = 6;
+ }
+ if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12)))
+ || ((bandwidth == 1) && (datarate == 12))) {
+ _rf_settings.lora.low_datarate_optimize = 0x01;
+ } else {
+ _rf_settings.lora.low_datarate_optimize = 0x00;
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP)
+ & RFLR_PLLHOP_FASTHOP_MASK)
+ | RFLR_PLLHOP_FASTHOP_ON);
+ write_to_register(REG_LR_HOPPERIOD, _rf_settings.lora.hop_period);
+ }
+
+ write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) &
+ RFLR_MODEMCONFIG1_BW_MASK &
+ RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+ RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
+ RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
+ RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK)
+ | (bandwidth << 6) | (coderate << 3)
+ | (fix_len << 2) | (crc_on << 1)
+ | _rf_settings.lora.low_datarate_optimize);
+
+ write_to_register(REG_LR_MODEMCONFIG2,
+ (read_register(REG_LR_MODEMCONFIG2) &
+ RFLR_MODEMCONFIG2_SF_MASK) | (datarate << 4));
+
+ write_to_register( REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
+ write_to_register( REG_LR_PREAMBLELSB, preamble_len & 0xFF);
+
+ if (datarate == 6) {
+ write_to_register(REG_LR_DETECTOPTIMIZE,
+ (read_register(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF6);
+ write_to_register( REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF6);
+ } else {
+ write_to_register(REG_LR_DETECTOPTIMIZE,
+ (read_register(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ write_to_register(REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+
+ break;
+ }
+}
+
+/**
+ * Calculates time on Air i.e., dwell time for a single packet
+ *
+ * Crucial for the stack in order to calculate dwell time so as to control
+ * duty cycling.
+ */
+uint32_t SX1272_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len)
+{
+ uint32_t airtime = 0;
+
+ switch (modem) {
+ case MODEM_FSK: {
+ airtime = rint((8 * (_rf_settings.fsk.preamble_len
+ + ((read_register( REG_SYNCCONFIG)
+ & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1)
+ + ((_rf_settings.fsk.fix_len == 0x01) ?
+ 0.0 : 1.0)
+ + (((read_register( REG_PACKETCONFIG1)
+ & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK)
+ != 0x00) ? 1.0 : 0) + pkt_len
+ + ((_rf_settings.fsk.crc_on == 0x01) ?
+ 2.0 : 0))
+ / _rf_settings.fsk.datarate) * 1e3);
+ }
+ break;
+ case MODEM_LORA: {
+ double bw = 0.0;
+ switch (_rf_settings.lora.bandwidth) {
+ case 0: // 125 kHz
+ bw = 125e3;
+ break;
+ case 1: // 250 kHz
+ bw = 250e3;
+ break;
+ case 2: // 500 kHz
+ bw = 500e3;
+ break;
+ }
+
+ // Symbol rate : time for one symbol (secs)
+ double rs = bw / (1 << _rf_settings.lora.datarate);
+ double ts = 1 / rs;
+ // time of preamble
+ double preamble_time = (_rf_settings.lora.preamble_len + 4.25) * ts;
+ // Symbol length of payload and time
+ double tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28
+ + 16 * _rf_settings.lora.crc_on -
+ (_rf_settings.lora.fix_len ? 20 : 0))
+ / (double) (4 * (_rf_settings.lora.datarate -
+ ((_rf_settings.lora.low_datarate_optimize
+ > 0) ? 2 : 0)))) *
+ (_rf_settings.lora.coderate + 4);
+ double n_payload = 8 + ((tmp > 0) ? tmp : 0);
+ double t_payload = n_payload * ts;
+ // Time on air
+ double t_onair = preamble_time + t_payload;
+ // return ms secs
+ airtime = floor(t_onair * 1e3 + 0.999);
+ }
+ break;
+ }
+ return airtime;
+}
+
+/**
+ * Prepares and sends the radio packet out in the air
+ */
+void SX1272_LoRaRadio::send(uint8_t *buffer, uint8_t size)
+{
+ uint32_t tx_timeout = 0;
+
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = size;
+
+ // FIFO operations can not take place in Sleep mode
+ if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) {
+ standby();
+ wait_ms(1);
+ }
+
+ if (_rf_settings.fsk.fix_len == false) {
+ write_fifo((uint8_t *) &size, 1);
+ } else {
+ write_to_register(REG_PAYLOADLENGTH, size);
+ }
+
+ if ((size > 0) && (size <= 64)) {
+ _rf_settings.fsk_packet_handler.chunk_size = size;
+ } else {
+ memcpy(_data_buffer, buffer, size);
+ _rf_settings.fsk_packet_handler.chunk_size = 32;
+ }
+
+ // write payload buffer
+ write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ _rf_settings.fsk_packet_handler.chunk_size;
+ tx_timeout = _rf_settings.fsk.tx_timeout;
+
+ break;
+ case MODEM_LORA:
+ if (_rf_settings.lora.iq_inverted == true) {
+ write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
+ RFLR_INVERTIQ_TX_MASK &
+ RFLR_INVERTIQ_RX_MASK) |
+ RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON));
+ write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ } else {
+ write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
+ RFLR_INVERTIQ_TX_MASK &
+ RFLR_INVERTIQ_RX_MASK) |
+ RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ _rf_settings.lora_packet_handler.size = size;
+
+ // Initializes the payload size
+ write_to_register(REG_LR_PAYLOADLENGTH, size);
+
+ // Full buffer used for Tx
+ write_to_register(REG_LR_FIFOTXBASEADDR, 0);
+ write_to_register(REG_LR_FIFOADDRPTR, 0);
+
+ // FIFO operations can not take place in Sleep mode
+ if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) {
+ standby();
+ wait_ms(1);
+ }
+ // write payload buffer
+ write_fifo(buffer, size);
+ tx_timeout = _rf_settings.lora.tx_timeout;
+
+ break;
+ }
+
+ // transmit
+ transmit(tx_timeout);
+}
+
+/**
+ * Actual TX - Transmit routine
+ *
+ * A DIO0 interrupt let the state machine know that a a packet is
+ * successfully sent, otherwise a TxTimeout is invoked.
+ * TxTimeout should never happen in normal circumstances as the radio should
+ * be able to send a packet out in the air no matter what.
+ */
+void SX1272_LoRaRadio::transmit(uint32_t timeout)
+{
+ switch (_rf_settings.modem) {
+
+ case MODEM_FSK:
+ // DIO0=PacketSent
+ // DIO1=FifoEmpty
+ // DIO2=FifoFull
+ // DIO3=FifoEmpty
+ // DIO4=LowBat
+ // DIO5=ModeReady
+ write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
+ RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO1_MASK &
+ RF_DIOMAPPING1_DIO2_MASK) |
+ RF_DIOMAPPING1_DIO1_01);
+
+ write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) &
+ RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK));
+ _rf_settings.fsk_packet_handler.fifo_thresh =
+ read_register(REG_FIFOTHRESH) & 0x3F;
+
+ break;
+
+ case MODEM_LORA:
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=tx_done, DIO2=fhss_change_channel
+
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK &
+ RFLR_DIOMAPPING1_DIO2_MASK) |
+ RFLR_DIOMAPPING1_DIO0_01 |
+ RFLR_DIOMAPPING1_DIO2_00);
+ } else {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=tx_done
+ write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK) |
+ RFLR_DIOMAPPING1_DIO0_01);
+ }
+
+ break;
+ }
+
+ _rf_settings.state = RF_TX_RUNNING;
+ tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), timeout*1e3);
+ set_operation_mode(RF_OPMODE_TRANSMITTER);
+}
+
+/**
+ * Sets the radio module in receive mode
+ *
+ * A DIO4 interrupt let's the state machine know that a preamble is detected
+ * and finally a DIO0 interrupt let's the state machine know that a packet is
+ * ready to be read from the FIFO
+ */
+void SX1272_LoRaRadio::receive(uint32_t timeout)
+{
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ if (timeout == 0 && _rf_settings.fsk.rx_continuous == false) {
+ // user messed up probably timeout was 0 but mode was not
+ // continuous, force it to be continuous
+ _rf_settings.fsk.rx_continuous = true;
+ }
+
+ // DIO0=PayloadReady
+ // DIO1=FifoLevel
+ // DIO2=SyncAddr
+ // DIO3=FifoEmpty
+ // DIO4=Preamble
+ // DIO5=ModeReady
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
+ RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO1_MASK &
+ RF_DIOMAPPING1_DIO2_MASK) |
+ RF_DIOMAPPING1_DIO0_00 |
+ RF_DIOMAPPING1_DIO1_00 |
+ RF_DIOMAPPING1_DIO2_11);
+
+ write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) &
+ RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK) |
+ RF_DIOMAPPING2_DIO4_11 |
+ RF_DIOMAPPING2_MAP_PREAMBLEDETECT);
+
+ _rf_settings.fsk_packet_handler.fifo_thresh =
+ read_register(REG_FIFOTHRESH) & 0x3F;
+
+ write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON |
+ RF_RXCONFIG_AGCAUTO_ON |
+ RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT);
+
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+
+ break;
+
+ case MODEM_LORA:
+ if (timeout == 0 && _rf_settings.lora.rx_continuous == false) {
+ // user messed up probably timeout was 0 but mode was not
+ // continuous, force it to be continuous
+ _rf_settings.lora.rx_continuous = true;
+ }
+
+ if (_rf_settings.lora.iq_inverted == true) {
+ write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
+ RFLR_INVERTIQ_TX_MASK &
+ RFLR_INVERTIQ_RX_MASK) |
+ RFLR_INVERTIQ_RX_ON |
+ RFLR_INVERTIQ_TX_OFF));
+ write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ } else {
+ write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
+ RFLR_INVERTIQ_TX_MASK &
+ RFLR_INVERTIQ_RX_MASK) |
+ RFLR_INVERTIQ_RX_OFF |
+ RFLR_INVERTIQ_TX_OFF));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=rx_done, DIO2=fhss_change_channel
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK &
+ RFLR_DIOMAPPING1_DIO2_MASK) |
+ RFLR_DIOMAPPING1_DIO0_00 |
+ RFLR_DIOMAPPING1_DIO2_00);
+ } else {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=rx_done
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK) |
+ RFLR_DIOMAPPING1_DIO0_00);
+ }
+
+ write_to_register(REG_LR_FIFORXBASEADDR, 0);
+ write_to_register(REG_LR_FIFOADDRPTR, 0);
+
+ break;
+ }
+
+ memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX172);
+
+ _rf_settings.state = RF_RX_RUNNING;
+
+ if (timeout != 0) {
+ rx_timeout_timer.attach_us(callback(this,
+ &SX1272_LoRaRadio::timeout_irq_isr),
+ timeout*1e3);
+ }
+
+ if (_rf_settings.modem == MODEM_FSK) {
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.attach_us(callback(this,
+ &SX1272_LoRaRadio::timeout_irq_isr),
+ _rf_settings.fsk.rx_single_timeout * 1e3);
+ }
+
+ return;
+ }
+
+ // If mode is LoRa set mode
+ if (_rf_settings.lora.rx_continuous == true) {
+ set_operation_mode(RFLR_OPMODE_RECEIVER);
+ } else {
+ set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE);
+ }
+}
+
+/**
+ * Puts a limit on the size of payload the module can handle
+ * By default it is MAX, i.e., 256 bytes
+ */
+void SX1272_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max)
+{
+ set_modem(modem);
+
+ switch (modem) {
+ case MODEM_FSK:
+ if (_rf_settings.fsk.fix_len == false) {
+ write_to_register(REG_PAYLOADLENGTH, max);
+ }
+ break;
+ case MODEM_LORA:
+ write_to_register(REG_LR_PAYLOADMAXLENGTH, max);
+ break;
+ }
+}
+
+/**
+ * TODO: Making sure if this API is valid only for LoRa modulation ?
+ *
+ * Indicates if the node is part of a private or public network
+ */
+void SX1272_LoRaRadio::set_public_network(bool enable)
+{
+ set_modem(MODEM_LORA);
+
+ _rf_settings.lora.public_network = enable;
+ if (enable == true) {
+ // Change lora modem SyncWord
+ write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD);
+ } else {
+ // Change lora modem SyncWord
+ write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD);
+ }
+
+}
+
+/**
+ * Perform carrier sensing
+ *
+ * Checks for a certain time if the RSSI is above a given threshold.
+ * This threshold determines if there is already a transmission going on
+ * in the channel or not.
+ *
+ */
+bool SX1272_LoRaRadio::perform_carrier_sense(radio_modems_t modem,
+ uint32_t freq,
+ int16_t rssi_threshold,
+ uint32_t max_carrier_sense_time)
+{
+ bool status = true;
+ int16_t rssi = 0;
+
+ set_modem(modem);
+ set_channel(freq);
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ // hold on a bit, radio turn-around time
+ wait_ms(1);
+
+ Timer elapsed_time;
+ elapsed_time.start();
+
+ // Perform carrier sense for maxCarrierSenseTime
+ while (elapsed_time.read_ms() < (int)max_carrier_sense_time) {
+ rssi = get_rssi(modem);
+
+ if (rssi > rssi_threshold) {
+ status = false;
+ break;
+ }
+ }
+
+ sleep();
+ return status;
+}
+
+/**
+ * Channel Activity detection (can be done only in LoRa mode)
+ *
+ * If any activity on the channel is detected, an interrupt is asserted on
+ * DIO3. A callback will be generated to the stack/application upon the
+ * assertion of DIO3.
+ */
+void SX1272_LoRaRadio::start_cad()
+{
+ uint8_t reg_val;
+
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ // DIO3=CADDone
+ reg_val = read_register(REG_DIOMAPPING1);
+ write_to_register(REG_DIOMAPPING1, (reg_val &
+ RFLR_DIOMAPPING1_DIO3_MASK) |
+ RFLR_DIOMAPPING1_DIO3_00);
+
+ set_operation_mode(RFLR_OPMODE_CAD);
+
+ _rf_settings.state = RF_CAD;
+
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Set transmission in continuous wave mode
+ */
+void SX1272_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power,
+ uint16_t time)
+{
+ uint8_t reg_val;
+
+ set_channel(freq);
+ set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time);
+ reg_val = read_register(REG_PACKETCONFIG2);
+
+ write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) );
+ // Disable radio interrupts
+ write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
+ write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
+
+ _rf_settings.state = RF_TX_RUNNING;
+ tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), time*1e3);
+ set_operation_mode(RF_OPMODE_TRANSMITTER);
+}
+
+/**
+ * Put radio in Standby mode
+ */
+void SX1272_LoRaRadio::standby( void )
+{
+ tx_timeout_timer.detach();
+ rx_timeout_timer.detach();
+
+ set_operation_mode(RF_OPMODE_STANDBY);
+ _rf_settings.state = RF_IDLE;
+}
+
+/**
+ * Generates 32 bit random number based upon RSSI monitoring
+ * Used for various calculation by the stack for example dev nonce
+ *
+ * When this API is used modem is set in LoRa mode and all interrupts are
+ * masked. If the user had been using FSK mode, it should be noted that a
+ * change of mode is required again because the registers have changed.
+ * In addition to that RX and TX configuration APIs should be called again in
+ * order to have correct desires setup.
+ */
+uint32_t SX1272_LoRaRadio::random()
+{
+ uint8_t i;
+ uint32_t rnd = 0;
+
+ // Set LoRa modem ON
+ set_modem(MODEM_LORA);
+
+ // Disable LoRa modem interrupts, i.e., mask all interrupts
+ write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE
+ | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER
+ | RFLR_IRQFLAGS_TXDONE | RFLR_IRQFLAGS_CADDONE
+ | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | RFLR_IRQFLAGS_CADDETECTED);
+
+ // Set radio in continuous reception
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ for (i = 0; i < 32; i++) {
+ wait_ms(1);
+ // Unfiltered RSSI value reading. Only takes the LSB value
+ rnd |= ((uint32_t) read_register(REG_LR_RSSIWIDEBAND) & 0x01) << i;
+ }
+
+ sleep();
+
+ return rnd;
+}
+
+
+/*****************************************************************************
+ * Private APIs *
+ ****************************************************************************/
+#ifdef MBED_CONF_RTOS_PRESENT
+/**
+ * Thread task handling IRQs
+ */
+void SX1272_LoRaRadio::rf_irq_task(void)
+{
+ for (;;) {
+ osEvent event = irq_thread.signal_wait(0, osWaitForever);
+ if (event.status != osEventSignal) {
+ continue;
+ }
+
+ lock();
+ if (event.value.signals & SIG_DIO0) {
+ handle_dio0_irq();
+ }
+ if (event.value.signals & SIG_DIO1) {
+ handle_dio1_irq();
+ }
+ if (event.value.signals & SIG_DIO2) {
+ handle_dio2_irq();
+ }
+ if (event.value.signals & SIG_DIO3) {
+ handle_dio3_irq();
+ }
+ if (event.value.signals & SIG_DIO4) {
+ handle_dio4_irq();
+ }
+ if (event.value.signals & SIG_DIO5) {
+ handle_dio5_irq();
+ }
+ if (event.value.signals & SIG_TIMOUT) {
+ handle_timeout_irq();
+ }
+ unlock();
+ }
+}
+#endif
+
+/**
+ * Writes a single byte to a given register
+ */
+void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t data)
+{
+ write_to_register(addr, &data, 1);
+}
+
+/**
+ * Writes multiple bytes to a given register
+ */
+void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size)
+{
+ // set chip-select low
+ _chip_select = 0;
+
+ // set write command
+ _spi.write(addr | SPI_WRITE_CMD);
+
+ // write data
+ for (uint8_t i = 0; i < size; i++) {
+ _spi.write(data[i]);
+ }
+
+ // set chip-select high
+ _chip_select = 1;
+}
+
+/**
+ * Reads the value of a single register
+ */
+uint8_t SX1272_LoRaRadio::read_register(uint8_t addr)
+{
+ uint8_t data;
+ read_register(addr, &data, 1);
+ return data;
+}
+
+/**
+ * Reads multiple values from a given register
+ */
+void SX1272_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+ // set chip-select low
+ _chip_select = 0;
+
+ // set read command
+ _spi.write(addr & SPI_READ_CMD);
+
+ // read buffers
+ for (uint8_t i = 0; i < size; i++) {
+ buffer[i] = _spi.write(0);
+ }
+
+ // set chip-select high
+ _chip_select = 1;
+}
+
+/**
+ * Writes to FIIO provided by the chip
+ */
+void SX1272_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size)
+{
+ write_to_register(0, buffer, size);
+}
+
+/**
+ * Reads from the FIFO provided by the chip
+ */
+void SX1272_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size)
+{
+ read_register(0, buffer, size);
+}
+
+/**
+ * Gets FSK bandwidth values
+ *
+ * Gives either normal bandwidths or bandwidths for
+ * AFC (auto frequency correction)
+ */
+uint8_t SX1272_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth)
+{
+ uint8_t i;
+
+ for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) {
+ if ((bandwidth >= fsk_bandwidths[i].bandwidth)
+ && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) {
+ return fsk_bandwidths[i].register_value;
+ }
+ }
+ // ERROR: Value not found
+ // This should never happen
+ while (1);
+}
+
+/**
+ * Sets the radio modules to default position (off)
+ *
+ * Historically they were being called as Antenna switches, so we kept the name.
+ * In essence these are control latches over duplexer which either let
+ * TX submodule or RX submodule circuitry enabled at a time.
+ */
+void SX1272_LoRaRadio::default_antenna_switch_ctrls()
+{
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ _pwr_amp_ctl = 0;
+ }
+
+ if (_rf_ctrls.rf_switch_ctl1 != NC && _rf_ctrls.rf_switch_ctl2 != NC) {
+ _rf_switch_ctl1 = 0;
+ _rf_switch_ctl2 = 0;
+ }
+
+ if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ _txctl = 0;
+ _rxctl = 0;
+ }
+}
+
+/**
+ * Gets the power amplifier configuration register
+ */
+uint8_t SX1272_LoRaRadio::get_pa_conf_reg()
+{
+ if (radio_variant == SX1272UNDEFINED) {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ } else if (radio_variant == SX1272MB1DCS) {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ } else {
+ return RF_PACONFIG_PASELECT_RFO;
+ }
+}
+
+/**
+ * Get RSSI from the module
+ */
+int16_t SX1272_LoRaRadio::get_rssi(radio_modems_t modem)
+{
+ int16_t rssi = 0;
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ rssi = -(read_register(REG_RSSIVALUE) >> 1 );
+ break;
+ case MODEM_LORA:
+ rssi = RSSI_OFFSET + read_register(REG_LR_RSSIVALUE);
+ break;
+ default:
+ rssi = -1;
+ break;
+ }
+ return rssi;
+}
+
+/**
+ * Sets the transmit power for the module
+ */
+#if defined ( TARGET_MOTE_L152RC )
+static const uint8_t pa_boost_table[20] = {0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15};
+static const uint8_t RFO_table[11] = {1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9};
+#endif
+
+void SX1272_LoRaRadio::set_rf_tx_power(int8_t power)
+{
+ uint8_t pa_config = 0;
+ uint8_t pa_dac = 0;
+
+ pa_config = read_register(REG_PACONFIG);
+ pa_dac = read_register(REG_PADAC);
+
+#if defined ( TARGET_MOTE_L152RC )
+ if(power > 19) {
+ pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_RFO;
+ pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | RFO_table[power - 20];
+ }
+ else
+ {
+ pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_PABOOST;
+ pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | pa_boost_table[power];
+ }
+#else
+ pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg();
+
+ if ((pa_config & RF_PACONFIG_PASELECT_PABOOST)
+ == RF_PACONFIG_PASELECT_PABOOST) {
+ if (power > 17) {
+ pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON;
+ } else {
+ pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF;
+ }
+ if ((pa_dac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) {
+ if (power < 5) {
+ power = 5;
+ }
+ if (power > 20) {
+ power = 20;
+ }
+ pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power - 5) & 0x0F);
+ } else {
+ if (power < 2) {
+ power = 2;
+ }
+ if (power > 17) {
+ power = 17;
+ }
+ pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power - 2) & 0x0F);
+ }
+ } else {
+ if (power < -1) {
+ power = -1;
+ }
+ if (power > 14) {
+ power = 14;
+ }
+ pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power + 1) & 0x0F);
+ }
+#endif
+ write_to_register(REG_PACONFIG, pa_config);
+ write_to_register(REG_PADAC, pa_dac);
+}
+
+/**
+ * Sets the radio registers to defaults
+ */
+void SX1272_LoRaRadio::setup_registers()
+{
+ for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) {
+ set_modem(radio_reg_init[i].modem);
+ write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value);
+ }
+}
+
+/**
+ * Set the radio module variant
+ */
+void SX1272_LoRaRadio::set_sx1272_variant_type()
+{
+ if (_rf_ctrls.ant_switch != NC){
+ _ant_switch.input();
+ wait_ms(1);
+ if (_ant_switch == 1) {
+ radio_variant = SX1272MB1DCS;
+ } else {
+ radio_variant = SX1272MB2XAS;
+ }
+ _ant_switch.output();
+ wait_ms(1);
+ } else {
+ radio_variant = SX1272UNDEFINED;
+ }
+}
+
+/**
+ * Sets up radio latch position according to the
+ * radio mode
+ */
+void SX1272_LoRaRadio::set_antenna_switch(uint8_t mode)
+{
+ // here we got to do ifdef for changing controls
+ // as some pins might be NC
+ switch (mode) {
+ case RFLR_OPMODE_TRANSMITTER:
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // module is in transmit mode and RF latch switches
+ // are connected. Check if power amplifier boost is
+ // setup or not
+ if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST)
+ == RF_PACONFIG_PASELECT_PABOOST) {
+ _rf_switch_ctl1 = 1;
+ _rf_switch_ctl2 = 0;
+ } else {
+ // power amplifier not selected
+ _rf_switch_ctl1 = 0;
+ _rf_switch_ctl2 = 1;
+ }
+ } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ // module is in transmit mode and tx/rx submodule control
+ // pins are connected
+ _txctl = 1;
+ _rxctl = 0;
+ } else if (_rf_ctrls.ant_switch != NC){
+ _ant_switch = 1;
+ } else {
+ // None of the control pins are connected.
+ }
+ break;
+ case RFLR_OPMODE_RECEIVER:
+ case RFLR_OPMODE_RECEIVER_SINGLE:
+ case RFLR_OPMODE_CAD:
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // radio is in reception or CAD mode and RF latch switches
+ // are connected
+ _rf_switch_ctl1 = 1;
+ _rf_switch_ctl2 = 1;
+ } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ _txctl = 0;
+ _rxctl = 1;
+ } else if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ } else {
+ // None of the control pins are connected.
+ }
+ break;
+ default:
+ // Enforce default case when any connected control pin is kept low.
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // radio is in reception or CAD mode and RF latch switches
+ // are connected
+ _rf_switch_ctl1 = 0;
+ _rf_switch_ctl2 = 0;
+ } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ _txctl = 0;
+ _rxctl = 0;
+ } else if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ } else {
+ // None of the control pins are connected.
+ }
+ break;
+ }
+}
+
+/**
+ * Sets up frequency for SPI module
+ * Reference DataSheet: 4.3 SPI Interface
+ */
+void SX1272_LoRaRadio::setup_spi()
+{
+ // SPI bus frequency
+ uint32_t spi_freq = SPI_FREQUENCY;
+
+ // Hold chip-select high
+ _chip_select = 1;
+ _spi.format(8, 0);
+
+#if defined (TARGET_KL25Z)
+ //bus-clock frequency is halved -> double the SPI frequency to compensate
+ _spi.frequency(spi_freq * 2);
+#else
+ // otherwise use default SPI frequency which is 8 MHz
+ _spi.frequency(spi_freq);
+#endif
+ // 100 us wait to settle down
+ wait(0.1);
+}
+
+/**
+ * Attaches ISRs to interrupt pins
+ */
+void SX1272_LoRaRadio::setup_interrupts()
+{
+ _dio0_ctl.rise(callback(this, &SX1272_LoRaRadio::dio0_irq_isr));
+ _dio1_ctl.rise(callback(this, &SX1272_LoRaRadio::dio1_irq_isr));
+ _dio2_ctl.rise(callback(this, &SX1272_LoRaRadio::dio2_irq_isr));
+ _dio3_ctl.rise(callback(this, &SX1272_LoRaRadio::dio3_irq_isr));
+ if (_dio4_pin != NC) {
+ _dio4_ctl.rise(callback(this, &SX1272_LoRaRadio::dio4_irq_isr));
+ }
+ if (_dio5_pin != NC) {
+ _dio5_ctl.rise(callback(this, &SX1272_LoRaRadio::dio5_irq_isr));
+ }
+}
+
+/**
+ * Sets the module in low power mode by disconnecting
+ * TX and RX submodules, turning off power amplifier etc.
+ */
+void SX1272_LoRaRadio::set_low_power_mode(bool status)
+{
+ if (radio_is_active != status) {
+ radio_is_active = status;
+
+ if (status == false) {
+ if (_rf_ctrls.rf_switch_ctl1 != NC) {
+ _rf_switch_ctl1 = 0;
+ }
+ if (_rf_ctrls.rf_switch_ctl2 != NC) {
+ _rf_switch_ctl2 = 0;
+ }
+
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ _pwr_amp_ctl = 0;
+ }
+
+ if (_rf_ctrls.txctl != NC) {
+ _txctl = 0;
+ }
+
+ if (_rf_ctrls.txctl != NC) {
+ _rxctl = 0;
+ }
+
+ if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ }
+ } else {
+ default_antenna_switch_ctrls();
+ }
+ }
+}
+
+/*****************************************************************************
+ * Interrupt service routines (ISRs) - set signals to the irq_thread *
+ ****************************************************************************/
+void SX1272_LoRaRadio::dio0_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO0);
+#else
+ handle_dio0_irq();
+#endif
+}
+
+void SX1272_LoRaRadio::dio1_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO1);
+#else
+ handle_dio1_irq();
+#endif
+}
+
+void SX1272_LoRaRadio::dio2_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO2);
+#else
+ handle_dio2_irq();
+#endif
+}
+
+void SX1272_LoRaRadio::dio3_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO3);
+#else
+ handle_dio3_irq();
+#endif
+}
+
+void SX1272_LoRaRadio::dio4_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO4);
+#else
+ handle_dio4_irq();
+#endif
+}
+
+void SX1272_LoRaRadio::dio5_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO5);
+#else
+ handle_dio5_irq();
+#endif
+}
+
+// This is not a hardware interrupt
+// we invoke it ourselves based upon
+// our timers
+void SX1272_LoRaRadio::timeout_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_TIMOUT);
+#else
+ handle_timeout_irq();
+#endif
+}
+
+/******************************************************************************
+ * Interrupt Handlers *
+ *****************************************************************************/
+
+void SX1272_LoRaRadio::handle_dio0_irq()
+{
+ volatile uint8_t irqFlags = 0;
+
+ switch (_rf_settings.state) {
+ case RF_RX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ if (_rf_settings.fsk.crc_on == true) {
+ irqFlags = read_register(REG_IRQFLAGS2);
+ if ((irqFlags & RF_IRQFLAGS2_CRCOK)
+ != RF_IRQFLAGS2_CRCOK) {
+ // Clear Irqs
+ write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.detach();
+ _rf_settings.state = RF_IDLE;
+ } else {
+ // Continuous mode restart Rx chain
+ write_to_register(REG_RXCONFIG,
+ read_register(REG_RXCONFIG) |
+ RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ }
+
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_error)) {
+ _radio_events->rx_error();
+ }
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+ // break from here, a CRC error happened, RX_ERROR
+ // was notified. No need to go any further
+ break;
+ }
+ }
+
+ // Read received packet size
+ if ((_rf_settings.fsk_packet_handler.size == 0)
+ && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) {
+ if (_rf_settings.fsk.fix_len == false) {
+ read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1);
+ } else {
+ _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH);
+ }
+ read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
+ _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ } else {
+ read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
+ _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ }
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ rx_timeout_sync_word.detach();
+ } else {
+ // Continuous mode restart Rx chain
+ write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG)
+ | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ }
+
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL) && (_radio_events->rx_done)) {
+ _radio_events->rx_done(
+ _data_buffer,
+ _rf_settings.fsk_packet_handler.size,
+ _rf_settings.fsk_packet_handler.rssi_value, 0);
+ }
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+ break;
+ case MODEM_LORA: {
+ int8_t snr = 0;
+
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
+
+ irqFlags = read_register(REG_LR_IRQFLAGS);
+ if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)
+ == RFLR_IRQFLAGS_PAYLOADCRCERROR) {
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS,
+ RFLR_IRQFLAGS_PAYLOADCRCERROR);
+
+ if (_rf_settings.lora.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ }
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_error)) {
+ _radio_events->rx_error();
+ }
+ break;
+ }
+
+ _rf_settings.lora_packet_handler.snr_value = read_register(REG_LR_PKTSNRVALUE);
+ if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1
+ {
+ // Invert and divide by 4
+ snr = ((~_rf_settings.lora_packet_handler.snr_value + 1) & 0xFF) >> 2;
+ snr = -snr;
+ } else {
+ // Divide by 4
+ snr =(_rf_settings.lora_packet_handler.snr_value & 0xFF) >> 2;
+ }
+
+ int16_t rssi = read_register(REG_LR_PKTRSSIVALUE);
+ if (snr < 0) {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET + rssi + (rssi >> 4) + snr;
+ } else {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET + rssi + (rssi >> 4);
+ }
+
+ _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES);
+ read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size);
+
+ if (_rf_settings.lora.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ }
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_done)) {
+ _radio_events->rx_done(
+ _data_buffer,
+ _rf_settings.lora_packet_handler.size,
+ _rf_settings.lora_packet_handler.rssi_value,
+ _rf_settings.lora_packet_handler.snr_value);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ tx_timeout_timer.detach();
+ // TxDone interrupt
+ switch (_rf_settings.modem) {
+ case MODEM_LORA:
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
+ // Intentional fall through
+ case MODEM_FSK:
+ default:
+ _rf_settings.state = RF_IDLE;
+ if ((_radio_events != NULL)
+ && (_radio_events->tx_done)) {
+ _radio_events->tx_done();
+ }
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272_LoRaRadio::handle_dio1_irq()
+{
+
+ switch(_rf_settings.state )
+ {
+ case RF_RX_RUNNING:
+ switch(_rf_settings.modem ) {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ // Read received packet size
+ if( ( _rf_settings.fsk_packet_handler.size == 0 ) && ( _rf_settings.fsk_packet_handler.nb_bytes == 0 ) )
+ {
+ if( _rf_settings.fsk.fix_len == false )
+ {
+ read_fifo( ( uint8_t* )&_rf_settings.fsk_packet_handler.size, 1 );
+ }
+ else
+ {
+ _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH);
+ }
+ }
+
+ if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.fifo_thresh )
+ {
+ read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.fifo_thresh );
+ _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.fifo_thresh;
+ }
+ else
+ {
+ read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
+ _rf_settings.fsk_packet_handler.nb_bytes += ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
+ }
+ break;
+ case MODEM_LORA:
+ // Sync time out
+ rx_timeout_timer.detach( );
+ _rf_settings.state = RF_IDLE;
+ if ((_radio_events != NULL) && (_radio_events->rx_timeout)) {
+ _radio_events->rx_timeout();
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch( _rf_settings.modem )
+ {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.chunk_size )
+ {
+ write_fifo(( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.chunk_size );
+ _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.chunk_size;
+ }
+ else
+ {
+ // Write the last chunk of data
+ write_fifo( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
+ _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes;
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272_LoRaRadio::handle_dio2_irq(void)
+{
+ switch(_rf_settings.state )
+ {
+ case RF_RX_RUNNING:
+ switch( _rf_settings.modem )
+ {
+ case MODEM_FSK:
+
+ // DIO4 must have been asserted to set preamble_detected to true
+ if( ( _rf_settings.fsk_packet_handler.preamble_detected == 1 ) && ( _rf_settings.fsk_packet_handler.sync_word_detected == 0 ) )
+ {
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.detach( );
+ }
+
+ _rf_settings.fsk_packet_handler.sync_word_detected = 1;
+
+ _rf_settings.fsk_packet_handler.rssi_value = -( read_register( REG_RSSIVALUE ) >> 1 );
+
+ _rf_settings.fsk_packet_handler.afc_value = ( int32_t )( double )( ( ( uint16_t )read_register( REG_AFCMSB ) << 8 ) |
+ ( uint16_t )read_register( REG_AFCLSB ) ) *
+ ( double )FREQ_STEP;
+ _rf_settings.fsk_packet_handler.rx_gain = ( read_register( REG_LNA ) >> 5 ) & 0x07;
+ }
+ break;
+ case MODEM_LORA:
+ if( _rf_settings.lora.freq_hop_on == true )
+ {
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+ if( ( _radio_events != NULL ) && (_radio_events->fhss_change_channel ) )
+ {
+ _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch( _rf_settings.modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if( _rf_settings.lora.freq_hop_on == true )
+ {
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+ if( (_radio_events != NULL ) && ( _radio_events->fhss_change_channel ) )
+ {
+ _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272_LoRaRadio::handle_dio3_irq( void )
+{
+ switch( _rf_settings.modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if( ( read_register( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
+ {
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
+ if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) )
+ {
+ _radio_events->cad_done( true );
+ }
+ }
+ else
+ {
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
+ if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) )
+ {
+ _radio_events->cad_done( false );
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272_LoRaRadio::handle_dio4_irq(void)
+{
+ // is asserted when a preamble is detected (FSK modem only)
+ switch (_rf_settings.modem) {
+ case MODEM_FSK: {
+ if (_rf_settings.fsk_packet_handler.preamble_detected == 0) {
+ _rf_settings.fsk_packet_handler.preamble_detected = 1;
+ }
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272_LoRaRadio::handle_dio5_irq()
+{
+ switch( _rf_settings.modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+
+void SX1272_LoRaRadio::handle_timeout_irq()
+{
+ switch(_rf_settings.state )
+ {
+ case RF_RX_RUNNING:
+ if( _rf_settings.modem == MODEM_FSK ) {
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+
+ // Clear Irqs
+ write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+ if( _rf_settings.fsk.rx_continuous == true )
+ {
+ // Continuous mode restart Rx chain
+ write_to_register( REG_RXCONFIG, read_register(REG_RXCONFIG) |
+ RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ }
+ else
+ {
+ _rf_settings.state = RF_IDLE;
+ rx_timeout_sync_word.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr),
+ _rf_settings.fsk.rx_single_timeout * 1e3);
+ }
+ }
+
+ if((_radio_events != NULL) && (_radio_events->rx_timeout)) {
+ _radio_events->rx_timeout();
+ }
+
+ break;
+
+ case RF_TX_RUNNING:
+ // Tx timeout shouldn't happen.
+ // But it has been observed that when it happens it is a result of a
+ // corrupted SPI transfer
+ // The workaround is to put the radio in a known state.
+ // Thus, we re-initialize it.
+
+ // Reset the radio
+ radio_reset( );
+
+ // Initialize radio default values
+ set_operation_mode( RF_OPMODE_SLEEP );
+
+ setup_registers();
+
+ set_modem(MODEM_FSK);
+
+ // Restore previous network type setting.
+ set_public_network(_rf_settings.lora.public_network);
+
+ _rf_settings.state = RF_IDLE;
+ if( ( _radio_events != NULL ) && ( _radio_events->tx_timeout ) )
+ {
+ _radio_events->tx_timeout( );
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+#endif //DEVICE_SPI
+
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1272/SX1272_LoRaRadio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1272/SX1272_LoRaRadio.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,431 @@
+/**
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C)2013 Semtech
+ ___ _____ _ ___ _ _____ ___ ___ ___ ___
+/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __|
+\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _|
+|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___|
+embedded.connectivity.solutions===============
+
+Description: Radio driver for Semtech SX1272 radio. Implements LoRaRadio class.
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE )
+
+
+Copyright (c) 2017, Arm Limited and affiliates.
+
+SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef SX1272_LORARADIO_H_
+#define SX1272_LORARADIO_H_
+
+#include "PinNames.h"
+#include "InterruptIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "SPI.h"
+#include "Timeout.h"
+#include "platform/PlatformMutex.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+ #include "rtos/Thread.h"
+#endif
+
+#include "lorawan/LoRaRadio.h"
+
+#ifdef DEVICE_SPI
+
+#ifdef MBED_CONF_SX1272_LORA_DRIVER_BUFFER_SIZE
+#define MAX_DATA_BUFFER_SIZE_SX172 MBED_CONF_SX1272_LORA_DRIVER_BUFFER_SIZE
+#else
+#define MAX_DATA_BUFFER_SIZE_SX172 256
+#endif
+
+/**
+ * Radio driver implementation for Semtech SX1272 plus variants.
+ * Supports only SPI at the moment. Implements pure virtual LoRaRadio class.
+ */
+class SX1272_LoRaRadio: public LoRaRadio {
+public:
+ /**
+ * Use this constructor if pin definitions are provided manually.
+ * The pins that are marked NC are optional. It is assumed that these
+ * pins are not connected until/unless configured otherwise.
+ */
+ SX1272_LoRaRadio(PinName mosi,
+ PinName miso,
+ PinName sclk,
+ PinName nss,
+ PinName reset,
+ PinName dio0,
+ PinName dio1,
+ PinName dio2,
+ PinName dio3,
+ PinName dio4,
+ PinName dio5,
+ PinName rf_switch_ctl1 = NC,
+ PinName rf_switch_ctl2 = NC,
+ PinName txctl = NC,
+ PinName rxctl = NC,
+ PinName ant_switch = NC,
+ PinName pwr_amp_ctl = NC,
+ PinName tcxo = NC);
+
+ /**
+ * Destructor
+ */
+ virtual ~SX1272_LoRaRadio();
+
+ /**
+ * Registers radio events with the Mbed LoRaWAN stack and
+ * undergoes initialization steps if any
+ *
+ * @param events Structure containing the driver callback functions
+ */
+ virtual void init_radio(radio_events_t *events);
+
+ /**
+ * Resets the radio module
+ */
+ virtual void radio_reset();
+
+ /**
+ * Put the RF module in sleep mode
+ */
+ virtual void sleep(void);
+
+ /**
+ * Sets the radio in standby mode
+ */
+ virtual void standby(void);
+
+ /**
+ * Sets the reception parameters
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param bandwidth Sets the bandwidth
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param bandwidth_afc Sets the AFC Bandwidth ( FSK only )
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: N/A ( set to 0 )
+ * @param preamble_len Sets the Preamble length ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: Length in symbols ( the hardware adds 4 more symbols )
+ * @param symb_timeout Sets the RxSingle timeout value
+ * FSK : timeout number of bytes
+ * LoRa: timeout in symbols
+ * @param fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param payload_len Sets payload length when fixed lenght is used
+ * @param crc_on Enables/Disables the CRC [0: OFF, 1: ON]
+ * @param freq_hop_on Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param hop_period Number of symbols bewteen each hop (LoRa only)
+ * @param iq_inverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param rx_continuous Sets the reception in continuous mode
+ * [false: single mode, true: continuous mode]
+ */
+ virtual void set_rx_config (radio_modems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidth_afc, uint16_t preamble_len,
+ uint16_t symb_timeout, bool fix_len,
+ uint8_t payload_len,
+ bool crc_on, bool freq_hop_on, uint8_t hop_period,
+ bool iq_inverted, bool rx_continuous);
+
+ /**
+ * Sets the transmission parameters
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param power Sets the output power [dBm]
+ * @param fdev Sets the frequency deviation ( FSK only )
+ * FSK : [Hz]
+ * LoRa: 0
+ * @param bandwidth Sets the bandwidth ( LoRa only )
+ * FSK : 0
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param preamble_len Sets the preamble length
+ * @param fix_len Fixed length packets [0: variable, 1: fixed]
+ * @param crc_on Enables disables the CRC [0: OFF, 1: ON]
+ * @param freq_hop_on Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param hop_period Number of symbols bewteen each hop (LoRa only)
+ * @param iq_inverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param timeout Transmission timeout [us]
+ */
+ virtual void set_tx_config(radio_modems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preamble_len,
+ bool fix_len, bool crc_on, bool freq_hop_on,
+ uint8_t hop_period, bool iq_inverted, uint32_t timeout);
+
+ /**
+ * Sends the buffer of size
+ *
+ * Prepares the packet to be sent and sets the radio in transmission
+ *
+ * @param buffer Buffer pointer
+ * @param size Buffer size
+ */
+ virtual void send(uint8_t *buffer, uint8_t size);
+
+ /**
+ * Sets the radio in reception mode for the given time
+ *
+ * It should be noted that if the timeout is set to 0, it essentially
+ * puts the receiver in continuous mode and hence from thereon it should
+ * be treated as if in continuous mode. However, an appropriate way of
+ * setting the receiver in continuous mode is by using set_rx_config()
+ * API.
+ *
+ * @param timeout Reception timeout [ms]
+ *
+ */
+ virtual void receive(uint32_t timeout);
+
+ /**
+ * Sets the carrier frequency
+ *
+ * @param freq Channel RF frequency
+ */
+ virtual void set_channel(uint32_t freq);
+
+ /**
+ * Generates a 32 bits random value based on the RSSI readings
+ *
+ * Remark this function sets the radio in LoRa modem mode and disables
+ * all interrupts.
+ * After calling this function either Radio.SetRxConfig or
+ * Radio.SetTxConfig functions must be called.
+ *
+ * @return 32 bits random value
+ */
+ virtual uint32_t random(void);
+
+ /**
+ * Get radio status
+ *
+ * @param status Radio status [RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+ * @return Return current radio status
+ */
+ virtual uint8_t get_status(void);
+
+ /**
+ * Sets the maximum payload length
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param max Maximum payload length in bytes
+ */
+ virtual void set_max_payload_length(radio_modems_t modem, uint8_t max);
+
+ /**
+ * Sets the network to public or private
+ *
+ * Updates the sync byte. Applies to LoRa modem only
+ *
+ * @param enable if true, it enables a public network
+ */
+ virtual void set_public_network(bool enable);
+
+ /**
+ * Computes the packet time on air for the given payload
+ *
+ * Remark can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param pkt_len Packet payload length
+ * @return Computed airTime for the given packet payload length
+ */
+ virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len);
+
+ /**
+ * Perform carrier sensing
+ *
+ * Checks for a certain time if the RSSI is above a given threshold.
+ * This threshold determines if there is already a transmission going on
+ * in the channel or not.
+ *
+ * @param modem Type of the radio modem
+ * @param freq Carrier frequency
+ * @param rssi_threshold Threshold value of RSSI
+ * @param max_carrier_sense_time time to sense the channel
+ *
+ * @return true if there is no active transmission
+ * in the channel, false otherwise
+ */
+ virtual bool perform_carrier_sense(radio_modems_t modem,
+ uint32_t freq,
+ int16_t rssi_threshold,
+ uint32_t max_carrier_sense_time);
+
+ /**
+ * Sets the radio in CAD mode
+ *
+ */
+ virtual void start_cad(void);
+
+ /**
+ * Check if the given RF is in range
+ *
+ * @param frequency frequency needed to be checked
+ */
+ virtual bool check_rf_frequency(uint32_t frequency);
+
+ /** Sets the radio in continuous wave transmission mode
+ *
+ * @param freq Channel RF frequency
+ * @param power Sets the output power [dBm]
+ * @param time Transmission mode timeout [s]
+ */
+ virtual void set_tx_continuous_wave(uint32_t freq, int8_t power, uint16_t time);
+
+ /**
+ * Acquire exclusive access
+ */
+ virtual void lock(void);
+
+ /**
+ * Release exclusive access
+ */
+ virtual void unlock(void);
+
+private:
+
+ // SPI and chip select control
+ mbed::SPI _spi;
+ mbed::DigitalOut _chip_select;
+
+ // module rest control
+ mbed::DigitalInOut _reset_ctl;
+
+ // Interrupt controls
+ mbed::InterruptIn _dio0_ctl;
+ mbed::InterruptIn _dio1_ctl;
+ mbed::InterruptIn _dio2_ctl;
+ mbed::InterruptIn _dio3_ctl;
+ mbed::InterruptIn _dio4_ctl;
+ mbed::InterruptIn _dio5_ctl;
+
+ // Radio specific controls
+ mbed::DigitalOut _rf_switch_ctl1;
+ mbed::DigitalOut _rf_switch_ctl2;
+ mbed::DigitalOut _txctl;
+ mbed::DigitalOut _rxctl;
+ mbed::DigitalInOut _ant_switch;
+ mbed::DigitalOut _pwr_amp_ctl;
+ mbed::DigitalOut _tcxo;
+
+ // Contains all RF control pin names
+ // This storage is needed even after assigning the
+ // pins to corresponding object, as the driver needs to know
+ // which control pins are connected and which are not. This
+ // variation is inherent to driver because of target configuration.
+ rf_ctrls _rf_ctrls;
+
+ // We need these PinNames as not all modules have those connected
+ PinName _dio4_pin;
+ PinName _dio5_pin;
+
+ // Structure containing all user and network specified settings
+ // for radio module
+ radio_settings_t _rf_settings;
+
+ // Structure containing function pointers to the stack callbacks
+ radio_events_t *_radio_events;
+
+ // Data buffer used for both TX and RX
+ // Size of this buffer is configurable via Mbed config system
+ // Default is 256 bytes
+ uint8_t _data_buffer[MAX_DATA_BUFFER_SIZE_SX172];
+
+ // TX/RX Timers - all use milisecond units
+ mbed::Timeout tx_timeout_timer;
+ mbed::Timeout rx_timeout_timer;
+ mbed::Timeout rx_timeout_sync_word;
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ // Thread to handle interrupts
+ rtos::Thread irq_thread;
+#endif
+
+ // Access protection
+ PlatformMutex mutex;
+
+ uint8_t radio_variant;
+
+ /**
+ * Flag used to set the RF switch control pins in low power mode when the radio is not active.
+ */
+ bool radio_is_active;
+
+ // helper functions
+ void setup_registers();
+ void default_antenna_switch_ctrls();
+ void set_antenna_switch(uint8_t operation_mode);
+ void setup_spi();
+ void gpio_init();
+ void gpio_deinit();
+ void setup_interrupts();
+ void set_modem(uint8_t modem);
+ void set_operation_mode(uint8_t mode);
+ void set_low_power_mode(bool status);
+ void set_sx1272_variant_type();
+ uint8_t get_pa_conf_reg();
+ void set_rf_tx_power(int8_t power);
+ int16_t get_rssi(radio_modems_t modem);
+ uint8_t get_fsk_bw_reg_val(uint32_t bandwidth);
+ void write_to_register(uint8_t addr, uint8_t data);
+ void write_to_register(uint8_t addr, uint8_t *data, uint8_t size);
+ uint8_t read_register(uint8_t addr);
+ void read_register(uint8_t addr, uint8_t *buffer, uint8_t size);
+ void write_fifo(uint8_t *buffer, uint8_t size);
+ void read_fifo(uint8_t *buffer, uint8_t size);
+ void transmit(uint32_t timeout);
+ void rf_irq_task(void);
+
+ // ISRs
+ void dio0_irq_isr();
+ void dio1_irq_isr();
+ void dio2_irq_isr();
+ void dio3_irq_isr();
+ void dio4_irq_isr();
+ void dio5_irq_isr();
+ void timeout_irq_isr();
+
+ // Handlers called by thread in response to signal
+ void handle_dio0_irq();
+ void handle_dio1_irq();
+ void handle_dio2_irq();
+ void handle_dio3_irq();
+ void handle_dio4_irq();
+ void handle_dio5_irq();
+ void handle_timeout_irq();
+};
+
+#endif //DEVICE_SPI
+
+#endif /* SX1272_LORARADIO_H_ */
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1272/mbed_lib.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1272/mbed_lib.json Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,13 @@
+{
+ "name": "sx1272-lora-driver",
+ "config": {
+ "spi-frequency": {
+ "help": "SPI frequency, Default: 8 MHz",
+ "value": 8000000
+ },
+ "buffer-size": {
+ "help": "Max. buffer size the radio can handle, Default: 256 B",
+ "value": 256
+ }
+ }
+}
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1272/registers/sx1272Regs-Fsk.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-lora-radio-drv/SX1272/registers/sx1272Regs-Fsk.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,1138 @@ +/** + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2015 Semtech + +Description: SX1272 FSK modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian + +Copyright (c) 2017, Arm Limited and affiliates. + +SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef __SX1272_REGS_FSK_H__ +#define __SX1272_REGS_FSK_H__ + +/*! + * ============================================================================ + * SX1272 Internal registers Address + * ============================================================================ + */ +#define REG_FIFO 0x00 +// Common settings +#define REG_OPMODE 0x01 +#define REG_BITRATEMSB 0x02 +#define REG_BITRATELSB 0x03 +#define REG_FDEVMSB 0x04 +#define REG_FDEVLSB 0x05 +#define REG_FRFMSB 0x06 +#define REG_FRFMID 0x07 +#define REG_FRFLSB 0x08 +// Tx settings +#define REG_PACONFIG 0x09 +#define REG_PARAMP 0x0A +#define REG_OCP 0x0B +// Rx settings +#define REG_LNA 0x0C +#define REG_RXCONFIG 0x0D +#define REG_RSSICONFIG 0x0E +#define REG_RSSICOLLISION 0x0F +#define REG_RSSITHRESH 0x10 +#define REG_RSSIVALUE 0x11 +#define REG_RXBW 0x12 +#define REG_AFCBW 0x13 +#define REG_OOKPEAK 0x14 +#define REG_OOKFIX 0x15 +#define REG_OOKAVG 0x16 +#define REG_RES17 0x17 +#define REG_RES18 0x18 +#define REG_RES19 0x19 +#define REG_AFCFEI 0x1A +#define REG_AFCMSB 0x1B +#define REG_AFCLSB 0x1C +#define REG_FEIMSB 0x1D +#define REG_FEILSB 0x1E +#define REG_PREAMBLEDETECT 0x1F +#define REG_RXTIMEOUT1 0x20 +#define REG_RXTIMEOUT2 0x21 +#define REG_RXTIMEOUT3 0x22 +#define REG_RXDELAY 0x23 +// Oscillator settings +#define REG_OSC 0x24 +// Packet handler settings +#define REG_PREAMBLEMSB 0x25 +#define REG_PREAMBLELSB 0x26 +#define REG_SYNCCONFIG 0x27 +#define REG_SYNCVALUE1 0x28 +#define REG_SYNCVALUE2 0x29 +#define REG_SYNCVALUE3 0x2A +#define REG_SYNCVALUE4 0x2B +#define REG_SYNCVALUE5 0x2C +#define REG_SYNCVALUE6 0x2D +#define REG_SYNCVALUE7 0x2E +#define REG_SYNCVALUE8 0x2F +#define REG_PACKETCONFIG1 0x30 +#define REG_PACKETCONFIG2 0x31 +#define REG_PAYLOADLENGTH 0x32 +#define REG_NODEADRS 0x33 +#define REG_BROADCASTADRS 0x34 +#define REG_FIFOTHRESH 0x35 +// SM settings +#define REG_SEQCONFIG1 0x36 +#define REG_SEQCONFIG2 0x37 +#define REG_TIMERRESOL 0x38 +#define REG_TIMER1COEF 0x39 +#define REG_TIMER2COEF 0x3A +// Service settings +#define REG_IMAGECAL 0x3B +#define REG_TEMP 0x3C +#define REG_LOWBAT 0x3D +// Status +#define REG_IRQFLAGS1 0x3E +#define REG_IRQFLAGS2 0x3F +// I/O settings +#define REG_DIOMAPPING1 0x40 +#define REG_DIOMAPPING2 0x41 +// Version +#define REG_VERSION 0x42 +// Additional settings +#define REG_AGCREF 0x43 +#define REG_AGCTHRESH1 0x44 +#define REG_AGCTHRESH2 0x45 +#define REG_AGCTHRESH3 0x46 +#define REG_PLLHOP 0x4B +#define REG_TCXO 0x58 +#define REG_PADAC 0x5A +#define REG_PLL 0x5C +#define REG_PLLLOWPN 0x5E +#define REG_FORMERTEMP 0x6C +#define REG_BITRATEFRAC 0x70 + +/*! + * ============================================================================ + * SX1272 FSK bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00 +#define RF_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20 + +#define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 +#define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default +#define RF_OPMODE_MODULATIONSHAPING_01 0x08 +#define RF_OPMODE_MODULATIONSHAPING_10 0x10 +#define RF_OPMODE_MODULATIONSHAPING_11 0x18 + +#define RF_OPMODE_MASK 0xF8 +#define RF_OPMODE_SLEEP 0x00 +#define RF_OPMODE_STANDBY 0x01 // Default +#define RF_OPMODE_SYNTHESIZER_TX 0x02 +#define RF_OPMODE_TRANSMITTER 0x03 +#define RF_OPMODE_SYNTHESIZER_RX 0x04 +#define RF_OPMODE_RECEIVER 0x05 + +/*! + * RegBitRate (bits/sec) + */ +#define RF_BITRATEMSB_1200_BPS 0x68 +#define RF_BITRATELSB_1200_BPS 0x2B +#define RF_BITRATEMSB_2400_BPS 0x34 +#define RF_BITRATELSB_2400_BPS 0x15 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default +#define RF_BITRATELSB_4800_BPS 0x0B // Default +#define RF_BITRATEMSB_9600_BPS 0x0D +#define RF_BITRATELSB_9600_BPS 0x05 +#define RF_BITRATEMSB_15000_BPS 0x08 +#define RF_BITRATELSB_15000_BPS 0x55 +#define RF_BITRATEMSB_19200_BPS 0x06 +#define RF_BITRATELSB_19200_BPS 0x83 +#define RF_BITRATEMSB_38400_BPS 0x03 +#define RF_BITRATELSB_38400_BPS 0x41 +#define RF_BITRATEMSB_76800_BPS 0x01 +#define RF_BITRATELSB_76800_BPS 0xA1 +#define RF_BITRATEMSB_153600_BPS 0x00 +#define RF_BITRATELSB_153600_BPS 0xD0 +#define RF_BITRATEMSB_57600_BPS 0x02 +#define RF_BITRATELSB_57600_BPS 0x2C +#define RF_BITRATEMSB_115200_BPS 0x01 +#define RF_BITRATELSB_115200_BPS 0x16 +#define RF_BITRATEMSB_12500_BPS 0x0A +#define RF_BITRATELSB_12500_BPS 0x00 +#define RF_BITRATEMSB_25000_BPS 0x05 +#define RF_BITRATELSB_25000_BPS 0x00 +#define RF_BITRATEMSB_50000_BPS 0x02 +#define RF_BITRATELSB_50000_BPS 0x80 +#define RF_BITRATEMSB_100000_BPS 0x01 +#define RF_BITRATELSB_100000_BPS 0x40 +#define RF_BITRATEMSB_150000_BPS 0x00 +#define RF_BITRATELSB_150000_BPS 0xD5 +#define RF_BITRATEMSB_200000_BPS 0x00 +#define RF_BITRATELSB_200000_BPS 0xA0 +#define RF_BITRATEMSB_250000_BPS 0x00 +#define RF_BITRATELSB_250000_BPS 0x80 +#define RF_BITRATEMSB_32768_BPS 0x03 +#define RF_BITRATELSB_32768_BPS 0xD1 + +/*! + * RegFdev (Hz) + */ +#define RF_FDEVMSB_2000_HZ 0x00 +#define RF_FDEVLSB_2000_HZ 0x21 +#define RF_FDEVMSB_5000_HZ 0x00 // Default +#define RF_FDEVLSB_5000_HZ 0x52 // Default +#define RF_FDEVMSB_10000_HZ 0x00 +#define RF_FDEVLSB_10000_HZ 0xA4 +#define RF_FDEVMSB_15000_HZ 0x00 +#define RF_FDEVLSB_15000_HZ 0xF6 +#define RF_FDEVMSB_20000_HZ 0x01 +#define RF_FDEVLSB_20000_HZ 0x48 +#define RF_FDEVMSB_25000_HZ 0x01 +#define RF_FDEVLSB_25000_HZ 0x9A +#define RF_FDEVMSB_30000_HZ 0x01 +#define RF_FDEVLSB_30000_HZ 0xEC +#define RF_FDEVMSB_35000_HZ 0x02 +#define RF_FDEVLSB_35000_HZ 0x3D +#define RF_FDEVMSB_40000_HZ 0x02 +#define RF_FDEVLSB_40000_HZ 0x8F +#define RF_FDEVMSB_45000_HZ 0x02 +#define RF_FDEVLSB_45000_HZ 0xE1 +#define RF_FDEVMSB_50000_HZ 0x03 +#define RF_FDEVLSB_50000_HZ 0x33 +#define RF_FDEVMSB_55000_HZ 0x03 +#define RF_FDEVLSB_55000_HZ 0x85 +#define RF_FDEVMSB_60000_HZ 0x03 +#define RF_FDEVLSB_60000_HZ 0xD7 +#define RF_FDEVMSB_65000_HZ 0x04 +#define RF_FDEVLSB_65000_HZ 0x29 +#define RF_FDEVMSB_70000_HZ 0x04 +#define RF_FDEVLSB_70000_HZ 0x7B +#define RF_FDEVMSB_75000_HZ 0x04 +#define RF_FDEVLSB_75000_HZ 0xCD +#define RF_FDEVMSB_80000_HZ 0x05 +#define RF_FDEVLSB_80000_HZ 0x1F +#define RF_FDEVMSB_85000_HZ 0x05 +#define RF_FDEVLSB_85000_HZ 0x71 +#define RF_FDEVMSB_90000_HZ 0x05 +#define RF_FDEVLSB_90000_HZ 0xC3 +#define RF_FDEVMSB_95000_HZ 0x06 +#define RF_FDEVLSB_95000_HZ 0x14 +#define RF_FDEVMSB_100000_HZ 0x06 +#define RF_FDEVLSB_100000_HZ 0x66 +#define RF_FDEVMSB_110000_HZ 0x07 +#define RF_FDEVLSB_110000_HZ 0x0A +#define RF_FDEVMSB_120000_HZ 0x07 +#define RF_FDEVLSB_120000_HZ 0xAE +#define RF_FDEVMSB_130000_HZ 0x08 +#define RF_FDEVLSB_130000_HZ 0x52 +#define RF_FDEVMSB_140000_HZ 0x08 +#define RF_FDEVLSB_140000_HZ 0xF6 +#define RF_FDEVMSB_150000_HZ 0x09 +#define RF_FDEVLSB_150000_HZ 0x9A +#define RF_FDEVMSB_160000_HZ 0x0A +#define RF_FDEVLSB_160000_HZ 0x3D +#define RF_FDEVMSB_170000_HZ 0x0A +#define RF_FDEVLSB_170000_HZ 0xE1 +#define RF_FDEVMSB_180000_HZ 0x0B +#define RF_FDEVLSB_180000_HZ 0x85 +#define RF_FDEVMSB_190000_HZ 0x0C +#define RF_FDEVLSB_190000_HZ 0x29 +#define RF_FDEVMSB_200000_HZ 0x0C +#define RF_FDEVLSB_200000_HZ 0xCD + +/*! + * RegFrf (MHz) + */ +#define RF_FRFMSB_863_MHZ 0xD7 +#define RF_FRFMID_863_MHZ 0xC0 +#define RF_FRFLSB_863_MHZ 0x00 +#define RF_FRFMSB_864_MHZ 0xD8 +#define RF_FRFMID_864_MHZ 0x00 +#define RF_FRFLSB_864_MHZ 0x00 +#define RF_FRFMSB_865_MHZ 0xD8 +#define RF_FRFMID_865_MHZ 0x40 +#define RF_FRFLSB_865_MHZ 0x00 +#define RF_FRFMSB_866_MHZ 0xD8 +#define RF_FRFMID_866_MHZ 0x80 +#define RF_FRFLSB_866_MHZ 0x00 +#define RF_FRFMSB_867_MHZ 0xD8 +#define RF_FRFMID_867_MHZ 0xC0 +#define RF_FRFLSB_867_MHZ 0x00 +#define RF_FRFMSB_868_MHZ 0xD9 +#define RF_FRFMID_868_MHZ 0x00 +#define RF_FRFLSB_868_MHZ 0x00 +#define RF_FRFMSB_869_MHZ 0xD9 +#define RF_FRFMID_869_MHZ 0x40 +#define RF_FRFLSB_869_MHZ 0x00 +#define RF_FRFMSB_870_MHZ 0xD9 +#define RF_FRFMID_870_MHZ 0x80 +#define RF_FRFLSB_870_MHZ 0x00 + +#define RF_FRFMSB_902_MHZ 0xE1 +#define RF_FRFMID_902_MHZ 0x80 +#define RF_FRFLSB_902_MHZ 0x00 +#define RF_FRFMSB_903_MHZ 0xE1 +#define RF_FRFMID_903_MHZ 0xC0 +#define RF_FRFLSB_903_MHZ 0x00 +#define RF_FRFMSB_904_MHZ 0xE2 +#define RF_FRFMID_904_MHZ 0x00 +#define RF_FRFLSB_904_MHZ 0x00 +#define RF_FRFMSB_905_MHZ 0xE2 +#define RF_FRFMID_905_MHZ 0x40 +#define RF_FRFLSB_905_MHZ 0x00 +#define RF_FRFMSB_906_MHZ 0xE2 +#define RF_FRFMID_906_MHZ 0x80 +#define RF_FRFLSB_906_MHZ 0x00 +#define RF_FRFMSB_907_MHZ 0xE2 +#define RF_FRFMID_907_MHZ 0xC0 +#define RF_FRFLSB_907_MHZ 0x00 +#define RF_FRFMSB_908_MHZ 0xE3 +#define RF_FRFMID_908_MHZ 0x00 +#define RF_FRFLSB_908_MHZ 0x00 +#define RF_FRFMSB_909_MHZ 0xE3 +#define RF_FRFMID_909_MHZ 0x40 +#define RF_FRFLSB_909_MHZ 0x00 +#define RF_FRFMSB_910_MHZ 0xE3 +#define RF_FRFMID_910_MHZ 0x80 +#define RF_FRFLSB_910_MHZ 0x00 +#define RF_FRFMSB_911_MHZ 0xE3 +#define RF_FRFMID_911_MHZ 0xC0 +#define RF_FRFLSB_911_MHZ 0x00 +#define RF_FRFMSB_912_MHZ 0xE4 +#define RF_FRFMID_912_MHZ 0x00 +#define RF_FRFLSB_912_MHZ 0x00 +#define RF_FRFMSB_913_MHZ 0xE4 +#define RF_FRFMID_913_MHZ 0x40 +#define RF_FRFLSB_913_MHZ 0x00 +#define RF_FRFMSB_914_MHZ 0xE4 +#define RF_FRFMID_914_MHZ 0x80 +#define RF_FRFLSB_914_MHZ 0x00 +#define RF_FRFMSB_915_MHZ 0xE4 // Default +#define RF_FRFMID_915_MHZ 0xC0 // Default +#define RF_FRFLSB_915_MHZ 0x00 // Default +#define RF_FRFMSB_916_MHZ 0xE5 +#define RF_FRFMID_916_MHZ 0x00 +#define RF_FRFLSB_916_MHZ 0x00 +#define RF_FRFMSB_917_MHZ 0xE5 +#define RF_FRFMID_917_MHZ 0x40 +#define RF_FRFLSB_917_MHZ 0x00 +#define RF_FRFMSB_918_MHZ 0xE5 +#define RF_FRFMID_918_MHZ 0x80 +#define RF_FRFLSB_918_MHZ 0x00 +#define RF_FRFMSB_919_MHZ 0xE5 +#define RF_FRFMID_919_MHZ 0xC0 +#define RF_FRFLSB_919_MHZ 0x00 +#define RF_FRFMSB_920_MHZ 0xE6 +#define RF_FRFMID_920_MHZ 0x00 +#define RF_FRFLSB_920_MHZ 0x00 +#define RF_FRFMSB_921_MHZ 0xE6 +#define RF_FRFMID_921_MHZ 0x40 +#define RF_FRFLSB_921_MHZ 0x00 +#define RF_FRFMSB_922_MHZ 0xE6 +#define RF_FRFMID_922_MHZ 0x80 +#define RF_FRFLSB_922_MHZ 0x00 +#define RF_FRFMSB_923_MHZ 0xE6 +#define RF_FRFMID_923_MHZ 0xC0 +#define RF_FRFLSB_923_MHZ 0x00 +#define RF_FRFMSB_924_MHZ 0xE7 +#define RF_FRFMID_924_MHZ 0x00 +#define RF_FRFLSB_924_MHZ 0x00 +#define RF_FRFMSB_925_MHZ 0xE7 +#define RF_FRFMID_925_MHZ 0x40 +#define RF_FRFLSB_925_MHZ 0x00 +#define RF_FRFMSB_926_MHZ 0xE7 +#define RF_FRFMID_926_MHZ 0x80 +#define RF_FRFLSB_926_MHZ 0x00 +#define RF_FRFMSB_927_MHZ 0xE7 +#define RF_FRFMID_927_MHZ 0xC0 +#define RF_FRFLSB_927_MHZ 0x00 +#define RF_FRFMSB_928_MHZ 0xE8 +#define RF_FRFMID_928_MHZ 0x00 +#define RF_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RF_PACONFIG_PASELECT_MASK 0x7F +#define RF_PACONFIG_PASELECT_PABOOST 0x80 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RF_PARAMP_LOWPNTXPLL_MASK 0xEF +#define RF_PARAMP_LOWPNTXPLL_OFF 0x10 // Default +#define RF_PARAMP_LOWPNTXPLL_ON 0x00 + +#define RF_PARAMP_MASK 0xF0 +#define RF_PARAMP_3400_US 0x00 +#define RF_PARAMP_2000_US 0x01 +#define RF_PARAMP_1000_US 0x02 +#define RF_PARAMP_0500_US 0x03 +#define RF_PARAMP_0250_US 0x04 +#define RF_PARAMP_0125_US 0x05 +#define RF_PARAMP_0100_US 0x06 +#define RF_PARAMP_0062_US 0x07 +#define RF_PARAMP_0050_US 0x08 +#define RF_PARAMP_0040_US 0x09 // Default +#define RF_PARAMP_0031_US 0x0A +#define RF_PARAMP_0025_US 0x0B +#define RF_PARAMP_0020_US 0x0C +#define RF_PARAMP_0015_US 0x0D +#define RF_PARAMP_0012_US 0x0E +#define RF_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RF_OCP_MASK 0xDF +#define RF_OCP_ON 0x20 // Default +#define RF_OCP_OFF 0x00 + +#define RF_OCP_TRIM_MASK 0xE0 +#define RF_OCP_TRIM_045_MA 0x00 +#define RF_OCP_TRIM_050_MA 0x01 +#define RF_OCP_TRIM_055_MA 0x02 +#define RF_OCP_TRIM_060_MA 0x03 +#define RF_OCP_TRIM_065_MA 0x04 +#define RF_OCP_TRIM_070_MA 0x05 +#define RF_OCP_TRIM_075_MA 0x06 +#define RF_OCP_TRIM_080_MA 0x07 +#define RF_OCP_TRIM_085_MA 0x08 +#define RF_OCP_TRIM_090_MA 0x09 +#define RF_OCP_TRIM_095_MA 0x0A +#define RF_OCP_TRIM_100_MA 0x0B // Default +#define RF_OCP_TRIM_105_MA 0x0C +#define RF_OCP_TRIM_110_MA 0x0D +#define RF_OCP_TRIM_115_MA 0x0E +#define RF_OCP_TRIM_120_MA 0x0F +#define RF_OCP_TRIM_130_MA 0x10 +#define RF_OCP_TRIM_140_MA 0x11 +#define RF_OCP_TRIM_150_MA 0x12 +#define RF_OCP_TRIM_160_MA 0x13 +#define RF_OCP_TRIM_170_MA 0x14 +#define RF_OCP_TRIM_180_MA 0x15 +#define RF_OCP_TRIM_190_MA 0x16 +#define RF_OCP_TRIM_200_MA 0x17 +#define RF_OCP_TRIM_210_MA 0x18 +#define RF_OCP_TRIM_220_MA 0x19 +#define RF_OCP_TRIM_230_MA 0x1A +#define RF_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RF_LNA_GAIN_MASK 0x1F +#define RF_LNA_GAIN_G1 0x20 // Default +#define RF_LNA_GAIN_G2 0x40 +#define RF_LNA_GAIN_G3 0x60 +#define RF_LNA_GAIN_G4 0x80 +#define RF_LNA_GAIN_G5 0xA0 +#define RF_LNA_GAIN_G6 0xC0 + +#define RF_LNA_BOOST_MASK 0xFC +#define RF_LNA_BOOST_OFF 0x00 // Default +#define RF_LNA_BOOST_ON 0x03 + +/*! + * RegRxConfig + */ +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default + +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only + +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only + +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF +#define RF_RXCONFIG_AFCAUTO_ON 0x10 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default + +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default +#define RF_RXCONFIG_AGCAUTO_OFF 0x00 + +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 + +/*! + * RegRssiConfig + */ +#define RF_RSSICONFIG_OFFSET_MASK 0x07 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 + +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 +#define RF_RSSICONFIG_SMOOTHING_2 0x00 +#define RF_RSSICONFIG_SMOOTHING_4 0x01 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default +#define RF_RSSICONFIG_SMOOTHING_16 0x03 +#define RF_RSSICONFIG_SMOOTHING_32 0x04 +#define RF_RSSICONFIG_SMOOTHING_64 0x05 +#define RF_RSSICONFIG_SMOOTHING_128 0x06 +#define RF_RSSICONFIG_SMOOTHING_256 0x07 + +/*! + * RegRssiCollision + */ +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default + +/*! + * RegRssiThresh + */ +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegRxBw + */ +#define RF_RXBW_MANT_MASK 0xE7 +#define RF_RXBW_MANT_16 0x00 +#define RF_RXBW_MANT_20 0x08 +#define RF_RXBW_MANT_24 0x10 // Default + +#define RF_RXBW_EXP_MASK 0xF8 +#define RF_RXBW_EXP_0 0x00 +#define RF_RXBW_EXP_1 0x01 +#define RF_RXBW_EXP_2 0x02 +#define RF_RXBW_EXP_3 0x03 +#define RF_RXBW_EXP_4 0x04 +#define RF_RXBW_EXP_5 0x05 // Default +#define RF_RXBW_EXP_6 0x06 +#define RF_RXBW_EXP_7 0x07 + +/*! + * RegAfcBw + */ +#define RF_AFCBW_MANTAFC_MASK 0xE7 +#define RF_AFCBW_MANTAFC_16 0x00 +#define RF_AFCBW_MANTAFC_20 0x08 // Default +#define RF_AFCBW_MANTAFC_24 0x10 + +#define RF_AFCBW_EXPAFC_MASK 0xF8 +#define RF_AFCBW_EXPAFC_0 0x00 +#define RF_AFCBW_EXPAFC_1 0x01 +#define RF_AFCBW_EXPAFC_2 0x02 +#define RF_AFCBW_EXPAFC_3 0x03 // Default +#define RF_AFCBW_EXPAFC_4 0x04 +#define RF_AFCBW_EXPAFC_5 0x05 +#define RF_AFCBW_EXPAFC_6 0x06 +#define RF_AFCBW_EXPAFC_7 0x07 + +/*! + * RegOokPeak + */ +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default +#define RF_OOKPEAK_BITSYNC_OFF 0x00 + +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 + +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 + +/*! + * RegOokFix + */ +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default + +/*! + * RegOokAvg + */ +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 + +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C + +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 + +/*! + * RegAfcFei + */ +#define RF_AFCFEI_AGCSTART 0x10 + +#define RF_AFCFEI_AFCCLEAR 0x02 + +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default + +/*! + * RegAfcMsb (Read Only) + */ + +/*! + * RegAfcLsb (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegPreambleDetect + */ +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 + +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 + +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F + +/*! + * RegRxTimeout1 + */ +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default + +/*! + * RegRxTimeout2 + */ +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default + +/*! + * RegRxTimeout3 + */ +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default + +/*! + * RegRxDelay + */ +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default + +/*! + * RegOsc + */ +#define RF_OSC_RCCALSTART 0x08 + +#define RF_OSC_CLKOUT_MASK 0xF8 +#define RF_OSC_CLKOUT_32_MHZ 0x00 +#define RF_OSC_CLKOUT_16_MHZ 0x01 +#define RF_OSC_CLKOUT_8_MHZ 0x02 +#define RF_OSC_CLKOUT_4_MHZ 0x03 +#define RF_OSC_CLKOUT_2_MHZ 0x04 +#define RF_OSC_CLKOUT_1_MHZ 0x05 +#define RF_OSC_CLKOUT_RC 0x06 +#define RF_OSC_CLKOUT_OFF 0x07 // Default + +/*! + * RegPreambleMsb/RegPreambleLsb + */ +#define RF_PREAMBLEMSB_SIZE 0x00 // Default +#define RF_PREAMBLELSB_SIZE 0x03 // Default + +/*! + * RegSyncConfig + */ +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 + + +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default + +#define RF_SYNCCONFIG_SYNC_MASK 0xEF +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default +#define RF_SYNCCONFIG_SYNC_OFF 0x00 + +#define RF_SYNCCONFIG_FIFOFILLCONDITION_MASK 0xF7 +#define RF_SYNCCONFIG_FIFOFILLCONDITION_AUTO 0x00 // Default +#define RF_SYNCCONFIG_FIFOFILLCONDITION_MANUAL 0x08 + +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07 + +/*! + * RegSyncValue1-8 + */ +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default + +/*! + * RegPacketConfig1 + */ +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default + +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 + +#define RF_PACKETCONFIG1_CRC_MASK 0xEF +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default +#define RF_PACKETCONFIG1_CRC_OFF 0x00 + +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 + +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 + +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 + +/*! + * RegPacketConfig2 + */ +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default + +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF +#define RF_PACKETCONFIG2_IOHOME_ON 0x20 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7 +#define RF_PACKETCONFIG2_BEACON_ON 0x08 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 + +/*! + * RegPayloadLength + */ +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default + +/*! + * RegNodeAdrs + */ +#define RF_NODEADDRESS_ADDRESS 0x00 + +/*! + * RegBroadcastAdrs + */ +#define RF_BROADCASTADDRESS_ADDRESS 0x00 + +/*! + * RegFifoThresh + */ +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 // Default + +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default + +/*! + * RegSeqConfig1 + */ +#define RF_SEQCONFIG1_SEQUENCER_START 0x80 + +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 + +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default + +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 + +#define RF_SEQCONFIG1_LPS_MASK 0xFB +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default +#define RF_SEQCONFIG1_LPS_IDLE 0x04 + +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 + +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMTX_TORX 0x01 + +/*! + * RegSeqConfig2 + */ +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 + +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 + +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 + +/*! + * RegTimerResol + */ +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C + +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 + +/*! + * RegTimer1Coef + */ +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default + +/*! + * RegTimer2Coef + */ +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default + +/*! + * RegImageCal + */ +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default + +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF +#define RF_IMAGECAL_IMAGECAL_START 0x40 + +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default + +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 + +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 + +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 + +/*! + * RegTemp (Read Only) + */ + +/*! + * RegLowBat + */ +#define RF_LOWBAT_MASK 0xF7 +#define RF_LOWBAT_ON 0x08 +#define RF_LOWBAT_OFF 0x00 // Default + +#define RF_LOWBAT_TRIM_MASK 0xF8 +#define RF_LOWBAT_TRIM_1695 0x00 +#define RF_LOWBAT_TRIM_1764 0x01 +#define RF_LOWBAT_TRIM_1835 0x02 // Default +#define RF_LOWBAT_TRIM_1905 0x03 +#define RF_LOWBAT_TRIM_1976 0x04 +#define RF_LOWBAT_TRIM_2045 0x05 +#define RF_LOWBAT_TRIM_2116 0x06 +#define RF_LOWBAT_TRIM_2185 0x07 + +/*! + * RegIrqFlags1 + */ +#define RF_IRQFLAGS1_MODEREADY 0x80 + +#define RF_IRQFLAGS1_RXREADY 0x40 + +#define RF_IRQFLAGS1_TXREADY 0x20 + +#define RF_IRQFLAGS1_PLLLOCK 0x10 + +#define RF_IRQFLAGS1_RSSI 0x08 + +#define RF_IRQFLAGS1_TIMEOUT 0x04 + +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 + +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 + +/*! + * RegIrqFlags2 + */ +#define RF_IRQFLAGS2_FIFOFULL 0x80 + +#define RF_IRQFLAGS2_FIFOEMPTY 0x40 + +#define RF_IRQFLAGS2_FIFOLEVEL 0x20 + +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10 + +#define RF_IRQFLAGS2_PACKETSENT 0x08 + +#define RF_IRQFLAGS2_PAYLOADREADY 0x04 + +#define RF_IRQFLAGS2_CRCOK 0x02 + +#define RF_IRQFLAGS2_LOWBAT 0x01 + +/*! + * RegDioMapping1 + */ +#define RF_DIOMAPPING1_DIO0_MASK 0x3F +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default +#define RF_DIOMAPPING1_DIO0_01 0x40 +#define RF_DIOMAPPING1_DIO0_10 0x80 +#define RF_DIOMAPPING1_DIO0_11 0xC0 + +#define RF_DIOMAPPING1_DIO1_MASK 0xCF +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default +#define RF_DIOMAPPING1_DIO1_01 0x10 +#define RF_DIOMAPPING1_DIO1_10 0x20 +#define RF_DIOMAPPING1_DIO1_11 0x30 + +#define RF_DIOMAPPING1_DIO2_MASK 0xF3 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default +#define RF_DIOMAPPING1_DIO2_01 0x04 +#define RF_DIOMAPPING1_DIO2_10 0x08 +#define RF_DIOMAPPING1_DIO2_11 0x0C + +#define RF_DIOMAPPING1_DIO3_MASK 0xFC +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default +#define RF_DIOMAPPING1_DIO3_01 0x01 +#define RF_DIOMAPPING1_DIO3_10 0x02 +#define RF_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RF_DIOMAPPING2_DIO4_MASK 0x3F +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default +#define RF_DIOMAPPING2_DIO4_01 0x40 +#define RF_DIOMAPPING2_DIO4_10 0x80 +#define RF_DIOMAPPING2_DIO4_11 0xC0 + +#define RF_DIOMAPPING2_DIO5_MASK 0xCF +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default +#define RF_DIOMAPPING2_DIO5_01 0x10 +#define RF_DIOMAPPING2_DIO5_10 0x20 +#define RF_DIOMAPPING2_DIO5_11 0x30 + +#define RF_DIOMAPPING2_MAP_MASK 0xFE +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPllHop + */ +#define RF_PLLHOP_FASTHOP_MASK 0x7F +#define RF_PLLHOP_FASTHOP_ON 0x80 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RF_TCXO_TCXOINPUT_MASK 0xEF +#define RF_TCXO_TCXOINPUT_ON 0x10 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RF_PADAC_20DBM_MASK 0xF8 +#define RF_PADAC_20DBM_ON 0x07 +#define RF_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RF_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RF_PLLLOWPN_BANDWIDTH_75 0x00 +#define RF_PLLLOWPN_BANDWIDTH_150 0x40 +#define RF_PLLLOWPN_BANDWIDTH_225 0x80 +#define RF_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +#endif // __SX1272_REGS_FSK_H__
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1272/registers/sx1272Regs-LoRa.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-lora-radio-drv/SX1272/registers/sx1272Regs-LoRa.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,549 @@ +/** + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2015 Semtech + +Description: SX1272 LoRa modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian + +Copyright (c) 2017, Arm Limited and affiliates. + +SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef __SX1272_REGS_LORA_H__ +#define __SX1272_REGS_LORA_H__ + +/*! + * ============================================================================ + * SX1272 Internal registers Address + * ============================================================================ + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_RXNBBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_FEIMSB 0x28 +#define REG_LR_FEIMID 0x29 +#define REG_LR_FEILSB 0x2A +#define REG_LR_RSSIWIDEBAND 0x2C +#define REG_LR_DETECTOPTIMIZE 0x31 +#define REG_LR_INVERTIQ 0x33 +#define REG_LR_DETECTIONTHRESHOLD 0x37 +#define REG_LR_SYNCWORD 0x39 +#define REG_LR_INVERTIQ2 0x3B + +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_AGCREF 0x43 +#define REG_LR_AGCTHRESH1 0x44 +#define REG_LR_AGCTHRESH2 0x45 +#define REG_LR_AGCTHRESH3 0x46 +#define REG_LR_PLLHOP 0x4B +#define REG_LR_TCXO 0x58 +#define REG_LR_PADAC 0x5A +#define REG_LR_PLL 0x5C +#define REG_LR_PLLLOWPN 0x5E +#define REG_LR_FORMERTEMP 0x6C + +/*! + * ============================================================================ + * SX1272 LoRa bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegFrf (MHz) + */ +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 +#define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default +#define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_MASK 0xFC +#define RFLR_LNA_BOOST_OFF 0x00 // Default +#define RFLR_LNA_BOOST_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + +/*! + * RegFifoRxNbBytes (Read Only) + */ + +/*! + * RegRxHeaderCntValueMsb (Read Only) + */ + +/*! + * RegRxHeaderCntValueLsb (Read Only) + */ + +/*! + * RegRxPacketCntValueMsb (Read Only) + */ + +/*! + * RegRxPacketCntValueLsb (Read Only) + */ + +/*! + * RegModemStat (Read Only) + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) + */ + +/*! + * RegPktRssiValue (Read Only) + */ + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + +/*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x3F +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +/*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiMid (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegRssiWideband (Read Only) + */ + +/*! + * RegDetectOptimize + */ +#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 +#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default +#define RFLR_DETECTIONOPTIMIZE_SF6 0x05 + +/*! + * RegInvertIQ + */ +#define RFLR_INVERTIQ_RX_MASK 0xBF +#define RFLR_INVERTIQ_RX_OFF 0x00 +#define RFLR_INVERTIQ_RX_ON 0x40 +#define RFLR_INVERTIQ_TX_MASK 0xFE +#define RFLR_INVERTIQ_TX_OFF 0x01 +#define RFLR_INVERTIQ_TX_ON 0x00 + +/*! + * RegDetectionThreshold + */ +#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default +#define RFLR_DETECTIONTHRESH_SF6 0x0C + +/*! + * RegInvertIQ2 + */ +#define RFLR_INVERTIQ2_ON 0x19 +#define RFLR_INVERTIQ2_OFF 0x1D + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegFormerTemp + */ + +#endif // __SX1272_REGS_LORA_H__
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1276/SX1276_LoRaRadio.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1276/SX1276_LoRaRadio.cpp Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,2326 @@
+/**
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C)2013 Semtech
+ ___ _____ _ ___ _ _____ ___ ___ ___ ___
+/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __|
+\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _|
+|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___|
+embedded.connectivity.solutions===============
+
+Description: LoRaWAN stack layer that controls both MAC and PHY underneath
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE )
+
+Copyright (c) 2017, Arm Limited and affiliates.
+
+SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include <stdio.h>
+#include <math.h> //rint
+#include <string.h>
+#include "mbed.h"
+#include "SX1276_LoRaRadio.h"
+#include "sx1276Regs-Fsk.h"
+#include "sx1276Regs-LoRa.h"
+
+#ifdef DEVICE_SPI
+
+/*!
+ * Sync word for Private LoRa networks
+ */
+#define LORA_MAC_PRIVATE_SYNCWORD 0x12
+
+/*!
+ * Sync word for Public LoRa networks
+ */
+#define LORA_MAC_PUBLIC_SYNCWORD 0x34
+
+/*!
+ * SX1276 definitions
+ */
+#define XTAL_FREQ 32000000
+#define FREQ_STEP 61.03515625
+
+/*!
+ * Constant values need to compute the RSSI value
+ */
+#define RSSI_OFFSET_LF -164.0
+#define RSSI_OFFSET_HF -157.0
+#define RF_MID_BAND_THRESH 525000000
+
+
+/*!
+ * FSK bandwidth definition
+ */
+typedef struct
+{
+ uint32_t bandwidth;
+ uint8_t register_value;
+} fsk_bw_t;
+
+/*!
+ * Radio registers definition
+ */
+typedef struct
+{
+ uint8_t modem;
+ uint8_t addr;
+ uint8_t value;
+} radio_registers_t;
+
+#define RADIO_INIT_REGISTERS_VALUE \
+{ \
+ { MODEM_FSK , REG_LNA , 0x23 },\
+ { MODEM_FSK , REG_RXCONFIG , 0x1E },\
+ { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
+ { MODEM_FSK , REG_AFCFEI , 0x01 },\
+ { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
+ { MODEM_FSK , REG_OSC , 0x07 },\
+ { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
+ { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
+ { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
+ { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
+ { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
+ { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
+ { MODEM_FSK , REG_IMAGECAL , 0x02 },\
+ { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
+ { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
+ { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
+}
+
+static const fsk_bw_t fsk_bandwidths[] =
+{
+ { 2600 , 0x17 },
+ { 3100 , 0x0F },
+ { 3900 , 0x07 },
+ { 5200 , 0x16 },
+ { 6300 , 0x0E },
+ { 7800 , 0x06 },
+ { 10400 , 0x15 },
+ { 12500 , 0x0D },
+ { 15600 , 0x05 },
+ { 20800 , 0x14 },
+ { 25000 , 0x0C },
+ { 31300 , 0x04 },
+ { 41700 , 0x13 },
+ { 50000 , 0x0B },
+ { 62500 , 0x03 },
+ { 83333 , 0x12 },
+ { 100000, 0x0A },
+ { 125000, 0x02 },
+ { 166700, 0x11 },
+ { 200000, 0x09 },
+ { 250000, 0x01 },
+ { 300000, 0x00 }, // Invalid bandwidth
+};
+
+/**
+ * SPI read/write masks
+ */
+#define SPI_WRITE_CMD 0x80
+#define SPI_READ_CMD 0x7F
+
+/**
+ * Signals
+ */
+#define SIG_DIO0 0x01
+#define SIG_DIO1 0x02
+#define SIG_DIO2 0x04
+#define SIG_DIO3 0x08
+#define SIG_DIO4 0x10
+#define SIG_DIO5 0x20
+#define SIG_TIMOUT 0x40
+
+/**
+ * Radio hardware registers initialization
+ */
+static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE;
+
+enum RadioVariant {
+ SX1276UNDEFINED = 0,
+ SX1276MB1LAS,
+ SX1276MB1MAS
+};
+
+#ifdef MBED_SX1276_LORA_RADIO_SPI_FREQUENCY
+#define SPI_FREQUENCY MBED_SX1276_LORA_RADIO_SPI_FREQUENCY
+#else
+#define SPI_FREQUENCY 8000000
+#endif
+
+/**
+ * Constructor
+ */
+SX1276_LoRaRadio::SX1276_LoRaRadio(PinName spi_mosi,
+ PinName spi_miso,
+ PinName spi_sclk,
+ PinName nss,
+ PinName reset,
+ PinName dio0,
+ PinName dio1,
+ PinName dio2,
+ PinName dio3,
+ PinName dio4,
+ PinName dio5,
+ PinName rf_switch_ctl1,
+ PinName rf_switch_ctl2,
+ PinName txctl,
+ PinName rxctl,
+ PinName antswitch,
+ PinName pwr_amp_ctl,
+ PinName tcxo)
+ : _spi(spi_mosi, spi_miso, spi_sclk),
+ _chip_select(nss, 1),
+ _reset_ctl(reset),
+ _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5),
+ _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0),
+ _txctl(txctl, 0), _rxctl(rxctl, 0),
+ _ant_switch(antswitch, PIN_INPUT, PullUp, 0),
+ _pwr_amp_ctl(pwr_amp_ctl),
+ _tcxo(tcxo)
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ , irq_thread(osPriorityRealtime, 1024)
+#endif
+{
+ _rf_ctrls.ant_switch = antswitch;
+ _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl;
+ _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1;
+ _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2;
+ _rf_ctrls.rxctl = rxctl;
+ _rf_ctrls.txctl = txctl;
+ _rf_ctrls.tcxo = tcxo;
+
+ _dio4_pin = dio4;
+ _dio5_pin = dio5;
+
+ _radio_events = NULL;
+
+ if (tcxo != NC) {
+ _tcxo = 1;
+ }
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.start(mbed::callback(this, &SX1276_LoRaRadio::rf_irq_task));
+#endif
+}
+
+/**
+ * Destructor
+ */
+SX1276_LoRaRadio::~SX1276_LoRaRadio()
+{
+
+}
+
+/*****************************************************************************
+ * Public APIs *
+ ****************************************************************************/
+/**
+ * Acquire lock
+ */
+void SX1276_LoRaRadio::lock(void)
+{
+ mutex.lock();
+}
+
+/**
+ * Release lock
+ */
+void SX1276_LoRaRadio::unlock(void)
+{
+ mutex.unlock();
+}
+
+/**
+ * Initializes radio module
+ */
+void SX1276_LoRaRadio::init_radio(radio_events_t *events)
+{
+ _radio_events = events;
+
+ // Reset the radio transceiver
+ radio_reset();
+
+ // Setup radio variant type
+ set_sx1276_variant_type();
+
+ // setup SPI frequency
+ // default is 8MHz although, configurable through
+ // SPI_FREQUENCY macro
+ setup_spi();
+
+ // Calibrate radio receiver chain
+ rx_chain_calibration();
+
+ // set radio mode to sleep
+ set_operation_mode(RF_OPMODE_SLEEP);
+
+ // Setup radio registers to defaults
+ setup_registers();
+
+ // set modem type - defaults to FSK here
+ set_modem(MODEM_FSK);
+
+ // set state to be idle
+ _rf_settings.state = RF_IDLE;
+
+ // Setup interrupts on DIO pins
+ setup_interrupts();
+}
+
+/**
+ * Can be used by application/stack or the driver itself
+ */
+void SX1276_LoRaRadio::radio_reset()
+{
+ _reset_ctl.output();
+ _reset_ctl = 0;
+ wait_ms(2);
+ _reset_ctl.input();
+ wait_ms(6);
+}
+
+/**
+ * TODO: The purpose of this API is unclear.
+ * Need to start an internal discussion.
+ */
+bool SX1276_LoRaRadio::check_rf_frequency(uint32_t frequency)
+{
+ // Implement check. Currently all frequencies are supported ? What band ?
+ return true;
+}
+
+/**
+ * Returns current status of the radio state machine
+ */
+uint8_t SX1276_LoRaRadio::get_status(void)
+{
+ return _rf_settings.state;
+}
+
+/**
+ * Sets up carrier frequency
+ */
+void SX1276_LoRaRadio::set_channel(uint32_t freq)
+{
+ _rf_settings.channel = freq;
+ freq = (uint32_t) ((double) freq / (double) FREQ_STEP);
+ write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF));
+ write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF));
+ write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF));
+}
+
+/**
+ * Generates 32 bit random number based upon RSSI monitoring
+ * Used for various calculation by the stack for example dev nonce
+ *
+ * When this API is used modem is set in LoRa mode and all interrupts are
+ * masked. If the user had been using FSK mode, it should be noted that a
+ * change of mode is required again because the registers have changed.
+ * In addition to that RX and TX configuration APIs should be called again in
+ * order to have correct desires setup.
+ */
+uint32_t SX1276_LoRaRadio::random( void )
+{
+ uint8_t i;
+ uint32_t rnd = 0;
+
+ /*
+ * Radio setup for random number generation
+ */
+ set_modem( MODEM_LORA );
+
+ // Disable LoRa modem interrupts
+ write_to_register( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // Set radio in continuous reception
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ for (i = 0; i < 32; i++) {
+ wait_ms(1);
+ // Unfiltered RSSI value reading. Only takes the LSB value
+ rnd |= ((uint32_t) read_register( REG_LR_RSSIWIDEBAND) & 0x01) << i;
+ }
+
+ sleep();
+
+ return rnd;
+}
+
+/**
+ * Sets up receiver related configurations
+ *
+ * Must be called before setting the radio in rx mode
+ */
+void SX1276_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidth_afc,
+ uint16_t preamble_len,
+ uint16_t symb_timeout, bool fix_len,
+ uint8_t payload_len, bool crc_on,
+ bool freq_hop_on, uint8_t hop_period,
+ bool iq_inverted, bool rx_continuous)
+{
+ set_modem(modem);
+
+ switch (modem) {
+ case MODEM_FSK:
+ _rf_settings.fsk.bandwidth = bandwidth;
+ _rf_settings.fsk.datarate = datarate;
+ _rf_settings.fsk.bandwidth_afc = bandwidth_afc;
+ _rf_settings.fsk.fix_len = fix_len;
+ _rf_settings.fsk.payload_len = payload_len;
+ _rf_settings.fsk.crc_on = crc_on;
+ _rf_settings.fsk.iq_inverted = iq_inverted;
+ _rf_settings.fsk.rx_continuous = rx_continuous;
+ _rf_settings.fsk.preamble_len = preamble_len;
+ _rf_settings.fsk.rx_single_timeout = symb_timeout
+ * ((1.0 / (double) datarate) * 8.0) * 1e3;
+
+ datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate);
+ write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8));
+ write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
+
+ write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth));
+ write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc));
+
+ write_to_register(REG_PREAMBLEMSB,
+ (uint8_t) ((preamble_len >> 8) & 0xFF));
+ write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
+
+ if (fix_len == 1) {
+ write_to_register(REG_PAYLOADLENGTH, payload_len);
+ } else {
+ write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum
+ }
+
+ write_to_register(
+ REG_PACKETCONFIG1,
+ (read_register(REG_PACKETCONFIG1)
+ & RF_PACKETCONFIG1_CRC_MASK
+ & RF_PACKETCONFIG1_PACKETFORMAT_MASK)
+ | ((fix_len == 1) ?
+ RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
+ RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
+ | (crc_on << 4));
+
+ // TODO why packet mode 2 ?
+ write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2)
+ | RF_PACKETCONFIG2_DATAMODE_PACKET));
+
+ break;
+
+ case MODEM_LORA:
+
+ if (bandwidth > 2) {
+ // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ while (1)
+ ;
+ // TODO Return a proper error from here
+ }
+
+ // stupid hack. TODO think something better
+ bandwidth+=7;
+
+ _rf_settings.lora.bandwidth = bandwidth;
+ _rf_settings.lora.datarate = datarate;
+ _rf_settings.lora.coderate = coderate;
+ _rf_settings.lora.preamble_len = preamble_len;
+ _rf_settings.lora.fix_len = fix_len;
+ _rf_settings.lora.payload_len = payload_len;
+ _rf_settings.lora.crc_on = crc_on;
+ _rf_settings.lora.freq_hop_on = freq_hop_on;
+ _rf_settings.lora.hop_period = hop_period;
+ _rf_settings.lora.iq_inverted = iq_inverted;
+ _rf_settings.lora.rx_continuous = rx_continuous;
+
+ if (datarate > 12) {
+ datarate = 12;
+ } else if (datarate < 6) {
+ datarate = 6;
+ }
+
+ if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12)))
+ || ((bandwidth == 8) && (datarate == 12))) {
+ _rf_settings.lora.low_datarate_optimize = 0x01;
+ } else {
+ _rf_settings.lora.low_datarate_optimize = 0x00;
+ }
+
+ write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1)
+ & RFLR_MODEMCONFIG1_BW_MASK
+ & RFLR_MODEMCONFIG1_CODINGRATE_MASK
+ & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK)
+ | (bandwidth << 4)
+ | (coderate << 1) | fix_len);
+
+ write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2)
+ & RFLR_MODEMCONFIG2_SF_MASK
+ & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK
+ & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)
+ | (datarate << 4)
+ | (crc_on << 2)
+ | ((symb_timeout >> 8)
+ & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK));
+
+ write_to_register(REG_LR_MODEMCONFIG3, (read_register( REG_LR_MODEMCONFIG3)
+ & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK)
+ | (_rf_settings.lora.low_datarate_optimize << 3));
+
+ write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF));
+
+ write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF));
+ write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
+
+ if (fix_len == 1) {
+ write_to_register(REG_LR_PAYLOADLENGTH, payload_len);
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_PLLHOP, (read_register( REG_LR_PLLHOP)
+ & RFLR_PLLHOP_FASTHOP_MASK)
+ | RFLR_PLLHOP_FASTHOP_ON);
+ write_to_register(REG_LR_HOPPERIOD,_rf_settings.lora.hop_period);
+ }
+
+ if ((bandwidth == 9) && (_rf_settings.channel > RF_MID_BAND_THRESH)) {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ write_to_register(REG_LR_TEST36, 0x02);
+ write_to_register(REG_LR_TEST3A, 0x64);
+ } else if (bandwidth == 9) {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ write_to_register(REG_LR_TEST36, 0x02);
+ write_to_register(REG_LR_TEST3A, 0x7F);
+ } else {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ write_to_register(REG_LR_TEST36, 0x03);
+ }
+
+ if (datarate == 6) {
+ write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE)
+ & RFLR_DETECTIONOPTIMIZE_MASK)
+ | RFLR_DETECTIONOPTIMIZE_SF6);
+ write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6);
+ } else {
+ write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE)
+ & RFLR_DETECTIONOPTIMIZE_MASK)
+ | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * Sets up transmitter related configuration
+ *
+ * Must be called before putting the radio module in Tx mode or trying
+ * to send
+ */
+void SX1276_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power,
+ uint32_t fdev, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint16_t preamble_len, bool fix_len,
+ bool crc_on, bool freq_hop_on,
+ uint8_t hop_period, bool iq_inverted,
+ uint32_t timeout)
+{
+ set_modem(modem);
+ set_rf_tx_power(power);
+
+ switch (modem) {
+ case MODEM_FSK:
+ _rf_settings.fsk.power = power;
+ _rf_settings.fsk.f_dev = fdev;
+ _rf_settings.fsk.bandwidth = bandwidth;
+ _rf_settings.fsk.datarate = datarate;
+ _rf_settings.fsk.preamble_len = preamble_len;
+ _rf_settings.fsk.fix_len = fix_len;
+ _rf_settings.fsk.crc_on = crc_on;
+ _rf_settings.fsk.iq_inverted = iq_inverted;
+ _rf_settings.fsk.tx_timeout = timeout;
+
+ fdev = (uint16_t) ((double) fdev / (double) FREQ_STEP);
+ write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8));
+ write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF));
+
+ datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate);
+ write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8));
+ write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
+
+ write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
+ write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF);
+
+ write_to_register(REG_PACKETCONFIG1,
+ (read_register( REG_PACKETCONFIG1) &
+ RF_PACKETCONFIG1_CRC_MASK &
+ RF_PACKETCONFIG1_PACKETFORMAT_MASK)
+ | ((fix_len == 1) ?
+ RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
+ RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
+ | (crc_on << 4));
+ write_to_register(REG_PACKETCONFIG2,
+ (read_register( REG_PACKETCONFIG2)
+ | RF_PACKETCONFIG2_DATAMODE_PACKET));
+
+ break;
+
+ case MODEM_LORA:
+ _rf_settings.lora.power = power;
+ if (bandwidth > 2) {
+ // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ while (1)
+ ;
+ }
+ bandwidth += 7;
+ _rf_settings.lora.bandwidth = bandwidth;
+ _rf_settings.lora.datarate = datarate;
+ _rf_settings.lora.coderate = coderate;
+ _rf_settings.lora.preamble_len = preamble_len;
+ _rf_settings.lora.fix_len = fix_len;
+ _rf_settings.lora.freq_hop_on = freq_hop_on;
+ _rf_settings.lora.hop_period = hop_period;
+ _rf_settings.lora.crc_on = crc_on;
+ _rf_settings.lora.iq_inverted = iq_inverted;
+ _rf_settings.lora.tx_timeout = timeout;
+
+ if (datarate > 12) {
+ datarate = 12;
+ } else if (datarate < 6) {
+ datarate = 6;
+ }
+ if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12)))
+ || ((bandwidth == 8) && (datarate == 12))) {
+ _rf_settings.lora.low_datarate_optimize = 0x01;
+ } else {
+ _rf_settings.lora.low_datarate_optimize = 0x00;
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP)
+ & RFLR_PLLHOP_FASTHOP_MASK)
+ | RFLR_PLLHOP_FASTHOP_ON);
+ write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period);
+ }
+
+ write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1)
+ & RFLR_MODEMCONFIG1_BW_MASK
+ & RFLR_MODEMCONFIG1_CODINGRATE_MASK
+ & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) | (bandwidth << 4)
+ | (coderate << 1) | fix_len);
+
+ write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2)
+ & RFLR_MODEMCONFIG2_SF_MASK
+ & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK)
+ | (datarate << 4)
+ | (crc_on << 2));
+
+ write_to_register(REG_LR_MODEMCONFIG3, (read_register(REG_LR_MODEMCONFIG3)
+ & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK)
+ | (_rf_settings.lora.low_datarate_optimize << 3));
+
+ write_to_register(REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
+ write_to_register(REG_LR_PREAMBLELSB, preamble_len & 0xFF);
+
+ if (datarate == 6) {
+ write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE)
+ & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF6);
+ write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6);
+ } else {
+ write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE)
+ & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+
+ break;
+ }
+}
+
+/**
+ * Calculates time on Air i.e., dwell time for a single packet
+ *
+ * Crucial for the stack in order to calculate dwell time so as to control
+ * duty cycling.
+ */
+uint32_t SX1276_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len)
+{
+ uint32_t airTime = 0;
+
+ switch (modem) {
+ case MODEM_FSK:
+ airTime =
+ rint((8 * (_rf_settings.fsk.preamble_len
+ + ((read_register( REG_SYNCCONFIG)
+ & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1)
+ + ((_rf_settings.fsk.fix_len == 0x01) ?
+ 0.0 : 1.0)
+ + (((read_register( REG_PACKETCONFIG1)
+ & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK)
+ != 0x00) ? 1.0 : 0) + pkt_len
+ + ((_rf_settings.fsk.crc_on == 0x01) ?
+ 2.0 : 0))
+ / _rf_settings.fsk.datarate) * 1e3);
+
+ break;
+ case MODEM_LORA:
+ double bw = 0.0;
+ // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ switch (_rf_settings.lora.bandwidth) {
+ //case 0: // 7.8 kHz
+ // bw = 78e2;
+ // break;
+ //case 1: // 10.4 kHz
+ // bw = 104e2;
+ // break;
+ //case 2: // 15.6 kHz
+ // bw = 156e2;
+ // break;
+ //case 3: // 20.8 kHz
+ // bw = 208e2;
+ // break;
+ //case 4: // 31.2 kHz
+ // bw = 312e2;
+ // break;
+ //case 5: // 41.4 kHz
+ // bw = 414e2;
+ // break;
+ //case 6: // 62.5 kHz
+ // bw = 625e2;
+ // break;
+ case 7: // 125 kHz
+ bw = 125e3;
+ break;
+ case 8: // 250 kHz
+ bw = 250e3;
+ break;
+ case 9: // 500 kHz
+ bw = 500e3;
+ break;
+ }
+
+ // Symbol rate : time for one symbol (secs)
+ double rs = bw / (1 << _rf_settings.lora.datarate);
+ double ts = 1 / rs;
+ // time of preamble
+ double tPreamble = (_rf_settings.lora.preamble_len + 4.25) * ts;
+ // Symbol length of payload and time
+ double tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28
+ + 16 * _rf_settings.lora.crc_on
+ - (_rf_settings.lora.fix_len ? 20 : 0))
+ / (double) (4
+ * (_rf_settings.lora.datarate
+ - ((_rf_settings.lora.low_datarate_optimize > 0)
+ ? 2 : 0))))
+ * (_rf_settings.lora.coderate + 4);
+ double nPayload = 8 + ((tmp > 0) ? tmp : 0);
+ double tPayload = nPayload * ts;
+ // Time on air
+ double tOnAir = tPreamble + tPayload;
+ // return ms secs
+ airTime = floor(tOnAir * 1e3 + 0.999);
+
+ break;
+ }
+
+ return airTime;
+}
+
+/**
+ * Prepares and sends the radio packet out in the air
+ */
+void SX1276_LoRaRadio::send(uint8_t *buffer, uint8_t size)
+{
+ uint32_t tx_timeout = 0;
+
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = size;
+
+ if (_rf_settings.fsk.fix_len == false) {
+ write_fifo((uint8_t*) &size, 1);
+ } else {
+ write_to_register(REG_PAYLOADLENGTH, size);
+ }
+
+ if ((size > 0) && (size <= 64)) {
+ _rf_settings.fsk_packet_handler.chunk_size = size;
+ } else {
+ memcpy(_data_buffer, buffer, size);
+ _rf_settings.fsk_packet_handler.chunk_size = 32;
+ }
+
+ // Write payload buffer
+ write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ _rf_settings.fsk_packet_handler.chunk_size;
+ tx_timeout = _rf_settings.fsk.tx_timeout;
+
+ break;
+
+ case MODEM_LORA:
+ if (_rf_settings.lora.iq_inverted == true) {
+ write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ)
+ & RFLR_INVERTIQ_TX_MASK
+ & RFLR_INVERTIQ_RX_MASK)
+ | RFLR_INVERTIQ_RX_OFF
+ | RFLR_INVERTIQ_TX_ON));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ } else {
+ write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ)
+ & RFLR_INVERTIQ_TX_MASK
+ & RFLR_INVERTIQ_RX_MASK)
+ | RFLR_INVERTIQ_RX_OFF
+ | RFLR_INVERTIQ_TX_OFF));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ _rf_settings.lora_packet_handler.size = size;
+
+ // Initializes the payload size
+ write_to_register(REG_LR_PAYLOADLENGTH, size);
+
+ // Full buffer used for Tx
+ write_to_register(REG_LR_FIFOTXBASEADDR, 0);
+ write_to_register(REG_LR_FIFOADDRPTR, 0);
+
+ // FIFO operations can not take place in Sleep mode
+ if ((read_register( REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) {
+ standby();
+ wait_ms(1);
+ }
+ // write_to_register payload buffer
+ write_fifo(buffer, size);
+ tx_timeout = _rf_settings.lora.tx_timeout;
+
+ break;
+ }
+
+ transmit(tx_timeout);
+}
+
+/**
+ * sets the radio module to sleep
+ */
+
+void SX1276_LoRaRadio::sleep()
+{
+ // stop timers
+ tx_timeout_timer.detach();
+ rx_timeout_timer.detach();
+
+ // put module in sleep mode
+ set_operation_mode(RF_OPMODE_SLEEP);
+}
+
+/**
+ * Put radio in Standby mode
+ */
+void SX1276_LoRaRadio::standby( void )
+{
+ tx_timeout_timer.detach();
+ rx_timeout_timer.detach();
+
+ set_operation_mode(RF_OPMODE_STANDBY);
+ _rf_settings.state = RF_IDLE;
+}
+
+/**
+ * Sets the radio module in receive mode
+ *
+ * A DIO4 interrupt let's the state machine know that a preamble is detected
+ * and finally a DIO0 interrupt let's the state machine know that a packet is
+ * ready to be read from the FIFO
+ */
+void SX1276_LoRaRadio::receive(uint32_t timeout)
+{
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ if (timeout == 0 && _rf_settings.fsk.rx_continuous == false) {
+ // user messed up probably timeout was 0 but mode was not
+ // continuous, force it to be continuous
+ _rf_settings.fsk.rx_continuous = true;
+ }
+
+ // DIO0=PayloadReady
+ // DIO1=FifoLevel
+ // DIO2=SyncAddr
+ // DIO3=FifoEmpty
+ // DIO4=Preamble
+ // DIO5=ModeReady
+ write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1)
+ & RF_DIOMAPPING1_DIO0_MASK
+ & RF_DIOMAPPING1_DIO1_MASK
+ & RF_DIOMAPPING1_DIO2_MASK)
+ | RF_DIOMAPPING1_DIO0_00
+ | RF_DIOMAPPING1_DIO1_00
+ | RF_DIOMAPPING1_DIO2_11);
+
+ write_to_register(REG_DIOMAPPING2, (read_register( REG_DIOMAPPING2)
+ & RF_DIOMAPPING2_DIO4_MASK
+ & RF_DIOMAPPING2_MAP_MASK)
+ | RF_DIOMAPPING2_DIO4_11
+ | RF_DIOMAPPING2_MAP_PREAMBLEDETECT);
+
+ _rf_settings.fsk_packet_handler.fifo_thresh =
+ read_register(REG_FIFOTHRESH) & 0x3F;
+
+ write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON
+ | RF_RXCONFIG_AGCAUTO_ON
+ | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT);
+
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+
+ break;
+
+ case MODEM_LORA:
+ if (timeout == 0 && _rf_settings.lora.rx_continuous == false) {
+ // user messed up probably timeout was 0 but mode was not
+ // continuous, force it to be continuous
+ _rf_settings.lora.rx_continuous = true;
+ }
+ if (_rf_settings.lora.iq_inverted == true) {
+ write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ)
+ & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK)
+ | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ } else {
+ write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ)
+ & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK)
+ | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF));
+ write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
+ if (_rf_settings.lora.bandwidth < 9) {
+ write_to_register(REG_LR_DETECTOPTIMIZE,
+ read_register(REG_LR_DETECTOPTIMIZE) & 0x7F);
+ write_to_register(REG_LR_TEST30, 0x00);
+ switch (_rf_settings.lora.bandwidth) {
+ case 0: // 7.8 kHz
+ write_to_register( REG_LR_TEST2F, 0x48);
+ set_channel(_rf_settings.channel + 7.81e3);
+ break;
+ case 1: // 10.4 kHz
+ write_to_register( REG_LR_TEST2F, 0x44);
+ set_channel(_rf_settings.channel + 10.42e3);
+ break;
+ case 2: // 15.6 kHz
+ write_to_register( REG_LR_TEST2F, 0x44);
+ set_channel(_rf_settings.channel + 15.62e3);
+ break;
+ case 3: // 20.8 kHz
+ write_to_register( REG_LR_TEST2F, 0x44);
+ set_channel(_rf_settings.channel + 20.83e3);
+ break;
+ case 4: // 31.2 kHz
+ write_to_register( REG_LR_TEST2F, 0x44);
+ set_channel(_rf_settings.channel + 31.25e3);
+ break;
+ case 5: // 41.4 kHz
+ write_to_register( REG_LR_TEST2F, 0x44);
+ set_channel(_rf_settings.channel + 41.67e3);
+ break;
+ case 6: // 62.5 kHz
+ write_to_register( REG_LR_TEST2F, 0x40);
+ break;
+ case 7: // 125 kHz
+ write_to_register( REG_LR_TEST2F, 0x40);
+ break;
+ case 8: // 250 kHz
+ write_to_register( REG_LR_TEST2F, 0x40);
+ break;
+ }
+ } else {
+ write_to_register( REG_LR_DETECTOPTIMIZE,
+ read_register( REG_LR_DETECTOPTIMIZE) | 0x80);
+ }
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER
+ | RFLR_IRQFLAGS_TXDONE
+ | RFLR_IRQFLAGS_CADDONE
+ | RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=RxDone, DIO2=FhssChangeChannel
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1)
+ & RFLR_DIOMAPPING1_DIO0_MASK
+ & RFLR_DIOMAPPING1_DIO2_MASK)
+ | RFLR_DIOMAPPING1_DIO0_00
+ | RFLR_DIOMAPPING1_DIO2_00);
+ } else {
+ write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER
+ | RFLR_IRQFLAGS_TXDONE
+ | RFLR_IRQFLAGS_CADDONE
+ | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL
+ | RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=RxDone
+ write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1)
+ & RFLR_DIOMAPPING1_DIO0_MASK)
+ | RFLR_DIOMAPPING1_DIO0_00);
+ }
+ write_to_register(REG_LR_FIFORXBASEADDR, 0);
+ write_to_register(REG_LR_FIFOADDRPTR, 0);
+
+ break;
+ }
+
+ memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX1276);
+
+ _rf_settings.state = RF_RX_RUNNING;
+
+ if (timeout != 0) {
+ rx_timeout_timer.attach_us(
+ callback(this, &SX1276_LoRaRadio::timeout_irq_isr),
+ timeout * 1e3);
+ }
+
+ if (_rf_settings.modem == MODEM_FSK) {
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.attach_us(
+ callback(this, &SX1276_LoRaRadio::timeout_irq_isr),
+ _rf_settings.fsk.rx_single_timeout * 1e3);
+ }
+
+ return;
+ }
+
+ // If mode is LoRa set mode
+ if (_rf_settings.lora.rx_continuous == true) {
+ set_operation_mode(RFLR_OPMODE_RECEIVER);
+ } else {
+ set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE);
+ }
+}
+
+
+/**
+ * Perform carrier sensing
+ *
+ * Checks for a certain time if the RSSI is above a given threshold.
+ * This threshold determines if there is already a transmission going on
+ * in the channel or not.
+ *
+ */
+bool SX1276_LoRaRadio::perform_carrier_sense(radio_modems_t modem,
+ uint32_t freq,
+ int16_t rssi_threshold,
+ uint32_t max_carrier_sense_time)
+{
+ bool status = true;
+ int16_t rssi = 0;
+
+ set_modem(modem);
+ set_channel(freq);
+ set_operation_mode(RF_OPMODE_RECEIVER);
+
+ // hold on a bit, radio turn-around time
+ wait_ms(1);
+
+ Timer elapsed_time;
+ elapsed_time.start();
+
+ // Perform carrier sense for maxCarrierSenseTime
+ while (elapsed_time.read_ms() < (int)max_carrier_sense_time) {
+ rssi = get_rssi(modem);
+
+ if (rssi > rssi_threshold) {
+ status = false;
+ break;
+ }
+ }
+
+ sleep();
+ return status;
+}
+
+/**
+ * TODO: Making sure if this API is valid only for LoRa modulation ?
+ *
+ * Indicates if the node is part of a private or public network
+ */
+void SX1276_LoRaRadio::set_public_network(bool enable)
+{
+ set_modem(MODEM_LORA);
+
+ _rf_settings.lora.public_network = enable;
+ if (enable == true) {
+ // Change lora modem SyncWord
+ write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD);
+ } else {
+ // Change lora modem SyncWord
+ write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD);
+ }
+
+}
+
+/**
+ * Puts a limit on the size of payload the module can handle
+ * By default it is MAX, i.e., 256 bytes
+ */
+void SX1276_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max)
+{
+ set_modem(modem);
+
+ switch (modem) {
+ case MODEM_FSK:
+ if (_rf_settings.fsk.fix_len == false) {
+ write_to_register(REG_PAYLOADLENGTH, max);
+ }
+ break;
+ case MODEM_LORA:
+ write_to_register(REG_LR_PAYLOADMAXLENGTH, max);
+ break;
+ }
+}
+
+/**
+ * Channel Activity detection (can be done only in LoRa mode)
+ *
+ * If any activity on the channel is detected, an interrupt is asserted on
+ * DIO3. A callback will be generated to the stack/application upon the
+ * assertion of DIO3.
+ */
+void SX1276_LoRaRadio::start_cad()
+{
+ uint8_t reg_val;
+
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ // DIO3=CADDone
+ reg_val = read_register(REG_DIOMAPPING1);
+ write_to_register(REG_DIOMAPPING1, (reg_val &
+ RFLR_DIOMAPPING1_DIO3_MASK) |
+ RFLR_DIOMAPPING1_DIO3_00);
+
+ set_operation_mode(RFLR_OPMODE_CAD);
+
+ _rf_settings.state = RF_CAD;
+
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Set transmission in continuous wave mode
+ */
+void SX1276_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power,
+ uint16_t time)
+{
+ uint8_t reg_val;
+
+ set_channel(freq);
+ set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time);
+ reg_val = read_register(REG_PACKETCONFIG2);
+
+ write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) );
+ // Disable radio interrupts
+ write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
+ write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
+
+ _rf_settings.state = RF_TX_RUNNING;
+ tx_timeout_timer.attach_us(callback(this, &SX1276_LoRaRadio::timeout_irq_isr), time*1e3);
+ set_operation_mode(RF_OPMODE_TRANSMITTER);
+}
+
+/*****************************************************************************
+ * Private APIs *
+ ****************************************************************************/
+#ifdef MBED_CONF_RTOS_PRESENT
+/**
+ * Thread task handling IRQs
+ */
+void SX1276_LoRaRadio::rf_irq_task(void)
+{
+ for (;;) {
+ osEvent event = irq_thread.signal_wait(0, osWaitForever);
+ if (event.status != osEventSignal) {
+ continue;
+ }
+
+ lock();
+ if (event.value.signals & SIG_DIO0) {
+ handle_dio0_irq();
+ }
+ if (event.value.signals & SIG_DIO1) {
+ handle_dio1_irq();
+ }
+ if (event.value.signals & SIG_DIO2) {
+ handle_dio2_irq();
+ }
+ if (event.value.signals & SIG_DIO3) {
+ handle_dio3_irq();
+ }
+ if (event.value.signals & SIG_DIO4) {
+ handle_dio4_irq();
+ }
+ if (event.value.signals & SIG_DIO5) {
+ handle_dio5_irq();
+ }
+ if (event.value.signals & SIG_TIMOUT) {
+ handle_timeout_irq();
+ }
+ unlock();
+ }
+}
+#endif
+
+/**
+ * Writes a single byte to a given register
+ */
+void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t data)
+{
+ write_to_register(addr, &data, 1);
+}
+
+/**
+ * Writes multiple bytes to a given register
+ */
+void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size)
+{
+ // set chip-select low
+ _chip_select = 0;
+
+ // set write command
+ _spi.write(addr | SPI_WRITE_CMD);
+
+ // write data
+ for (uint8_t i = 0; i < size; i++) {
+ _spi.write(data[i]);
+ }
+
+ // set chip-select high
+ _chip_select = 1;
+}
+
+/**
+ * Reads the value of a single register
+ */
+uint8_t SX1276_LoRaRadio::read_register(uint8_t addr)
+{
+ uint8_t data;
+ read_register(addr, &data, 1);
+ return data;
+}
+
+/**
+ * Reads multiple values from a given register
+ */
+void SX1276_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+ // set chip-select low
+ _chip_select = 0;
+
+ // set read command
+ _spi.write(addr & SPI_READ_CMD);
+
+ // read buffers
+ for (uint8_t i = 0; i < size; i++) {
+ buffer[i] = _spi.write(0);
+ }
+
+ // set chip-select high
+ _chip_select = 1;
+}
+
+/**
+ * Writes to FIIO provided by the chip
+ */
+void SX1276_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size)
+{
+ write_to_register(0, buffer, size);
+}
+
+/**
+ * Reads from the FIFO provided by the chip
+ */
+void SX1276_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size)
+{
+ read_register(0, buffer, size);
+}
+
+/**
+ * Sets up operation mode
+ */
+void SX1276_LoRaRadio::set_operation_mode(uint8_t mode)
+{
+ if (mode == RF_OPMODE_SLEEP) {
+ set_low_power_mode();
+ } else {
+ set_low_power_mode();
+ set_antenna_switch(mode);
+ }
+
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode);
+}
+
+/**
+ * Sets the modem type to use
+ *
+ * At initialization FSK is chosen. Later stack or application
+ * can choose to change.
+ */
+void SX1276_LoRaRadio::set_modem(uint8_t modem )
+{
+ if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) {
+ _rf_settings.modem = MODEM_LORA;
+ } else {
+ _rf_settings.modem = MODEM_FSK;
+ }
+
+ if(_rf_settings.modem == modem ) {
+ // if the modem is already set
+ return;
+ }
+
+ _rf_settings.modem = modem;
+
+ switch(_rf_settings.modem)
+ {
+ default:
+ case MODEM_FSK:
+ // before changing modem mode, put the module to sleep
+ sleep();
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
+ | RFLR_OPMODE_LONGRANGEMODE_OFF);
+
+ // Datasheet Tables 28, 29 DIO mapping
+ write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode
+ write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e.,
+ // DIO5 and DIO4=ModeReady
+ break;
+ case MODEM_LORA:
+ sleep();
+ write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
+ | RFLR_OPMODE_LONGRANGEMODE_ON);
+
+ // Datasheet Tables 17 DIO mapping for LoRa
+ // set to defaults
+ write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults
+ write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults
+
+ break;
+ }
+}
+
+/**
+ * Set the radio module variant
+ */
+void SX1276_LoRaRadio::set_sx1276_variant_type()
+{
+ if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch.input();
+ wait_ms(1);
+ if (_ant_switch == 1) {
+ radio_variant = SX1276MB1LAS;
+ } else {
+ radio_variant = SX1276MB1MAS;
+ }
+ _ant_switch.output();
+ wait_ms(1);
+ } else {
+ radio_variant = SX1276UNDEFINED;
+ }
+}
+
+/**
+ * Sets up frequency for SPI module
+ * Reference DataSheet: 4.3 SPI Interface
+ */
+void SX1276_LoRaRadio::setup_spi()
+{
+ // SPI bus frequency
+ uint32_t spi_freq = SPI_FREQUENCY;
+
+ // Hold chip-select high
+ _chip_select = 1;
+ _spi.format(8, 0);
+
+#if defined (TARGET_KL25Z)
+ //bus-clock frequency is halved -> double the SPI frequency to compensate
+ _spi.frequency(spi_freq * 2);
+#else
+ // otherwise use default SPI frequency which is 8 MHz
+ _spi.frequency(spi_freq);
+#endif
+ // 100 us wait to settle down
+ wait(0.1);
+}
+
+/**
+ * Sets the radio registers to defaults
+ */
+void SX1276_LoRaRadio::setup_registers()
+{
+ for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) {
+ set_modem(radio_reg_init[i].modem);
+ write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value);
+ }
+}
+
+/**
+ * Performs the Rx chain calibration for LF and HF bands
+ *
+ * Must be called just after the reset so all registers are at their
+ * default values.
+ */
+void SX1276_LoRaRadio::rx_chain_calibration(void)
+{
+ uint8_t regPaConfigInitVal;
+ uint32_t initialFreq;
+
+ // Save context
+ regPaConfigInitVal = read_register( REG_PACONFIG );
+ initialFreq = ( double )( ( ( uint32_t )this->read_register( REG_FRFMSB ) << 16 ) |
+ ( ( uint32_t )this->read_register( REG_FRFMID ) << 8 ) |
+ ( ( uint32_t )this->read_register( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
+
+ // Cut the PA just in case, RFO output, power = -1 dBm
+ write_to_register( REG_PACONFIG, 0x00 );
+
+ // Launch Rx chain calibration for LF band
+ write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL)
+ & RF_IMAGECAL_IMAGECAL_MASK)
+ | RF_IMAGECAL_IMAGECAL_START);
+ while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING )
+ == RF_IMAGECAL_IMAGECAL_RUNNING )
+ {
+ }
+
+ // Sets a Frequency in HF band
+ set_channel(868000000);
+
+ // Launch Rx chain calibration for HF band
+ write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL)
+ & RF_IMAGECAL_IMAGECAL_MASK )
+ | RF_IMAGECAL_IMAGECAL_START );
+ while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING )
+ == RF_IMAGECAL_IMAGECAL_RUNNING )
+ {
+ // do nothing, just wait while rf image frequency calibration is done
+ }
+
+ // Restore context
+ write_to_register( REG_PACONFIG, regPaConfigInitVal );
+ set_channel(initialFreq);
+}
+
+/**
+ * Gets FSK bandwidth values
+ *
+ * Gives either normal bandwidths or bandwidths for
+ * AFC (auto frequency correction)
+ */
+uint8_t SX1276_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth)
+{
+ uint8_t i;
+
+ for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) {
+ if ((bandwidth >= fsk_bandwidths[i].bandwidth)
+ && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) {
+ return fsk_bandwidths[i].register_value;
+ }
+ }
+ // ERROR: Value not found
+ // This should never happen
+ while (1);
+}
+
+uint8_t SX1276_LoRaRadio::get_pa_conf_reg(uint32_t channel)
+{
+ if (radio_variant == SX1276UNDEFINED) {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ } else if (channel > RF_MID_BAND_THRESH) {
+ if (radio_variant == SX1276MB1LAS) {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ } else {
+ return RF_PACONFIG_PASELECT_RFO;
+ }
+ } else {
+ return RF_PACONFIG_PASELECT_RFO;
+ }
+}
+
+/**
+ * Sets the transmit power for the module
+ */
+void SX1276_LoRaRadio::set_rf_tx_power(int8_t power)
+{
+
+ uint8_t paConfig = 0;
+ uint8_t paDac = 0;
+
+ paConfig = read_register(REG_PACONFIG);
+ paDac = read_register(REG_PADAC);
+
+ paConfig = (paConfig & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg(_rf_settings.channel);
+ paConfig = (paConfig & RF_PACONFIG_MAX_POWER_MASK) | 0x70;
+
+ if ((paConfig & RF_PACONFIG_PASELECT_PABOOST) == RF_PACONFIG_PASELECT_PABOOST) {
+ if (power > 17) {
+ paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON;
+ } else {
+ paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF;
+ }
+ if ((paDac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) {
+ if (power < 5) {
+ power = 5;
+ }
+ if (power > 20) {
+ power = 20;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power - 5) & 0x0F);
+ } else {
+ if (power < 2) {
+ power = 2;
+ }
+ if (power > 17) {
+ power = 17;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power - 2) & 0x0F);
+ }
+ } else {
+ if (power < -1) {
+ power = -1;
+ }
+ if (power > 14) {
+ power = 14;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK)
+ | (uint8_t) ((uint16_t) (power + 1) & 0x0F);
+ }
+ write_to_register( REG_PACONFIG, paConfig);
+ write_to_register( REG_PADAC, paDac);
+}
+
+/**
+ * Actual TX - Transmit routine
+ *
+ * A DIO0 interrupt let the state machine know that a a packet is
+ * successfully sent, otherwise a TxTimeout is invoked.
+ * TxTimeout should never happen in normal circumstances as the radio should
+ * be able to send a packet out in the air no matter what.
+ */
+void SX1276_LoRaRadio::transmit(uint32_t timeout)
+{
+ switch (_rf_settings.modem) {
+
+ case MODEM_FSK:
+ // DIO0=PacketSent
+ // DIO1=FifoEmpty
+ // DIO2=FifoFull
+ // DIO3=FifoEmpty
+ // DIO4=LowBat
+ // DIO5=ModeReady
+ write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
+ RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO1_MASK &
+ RF_DIOMAPPING1_DIO2_MASK) |
+ RF_DIOMAPPING1_DIO1_01);
+
+ write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) &
+ RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK));
+ _rf_settings.fsk_packet_handler.fifo_thresh =
+ read_register(REG_FIFOTHRESH) & 0x3F;
+
+ break;
+
+ case MODEM_LORA:
+
+ if (_rf_settings.lora.freq_hop_on == true) {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=tx_done, DIO2=fhss_change_channel
+
+ write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK &
+ RFLR_DIOMAPPING1_DIO2_MASK) |
+ RFLR_DIOMAPPING1_DIO0_01 |
+ RFLR_DIOMAPPING1_DIO2_00);
+ } else {
+ write_to_register(REG_LR_IRQFLAGSMASK,
+ RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=tx_done
+ write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
+ RFLR_DIOMAPPING1_DIO0_MASK) |
+ RFLR_DIOMAPPING1_DIO0_01);
+ }
+
+ break;
+ }
+
+ _rf_settings.state = RF_TX_RUNNING;
+ tx_timeout_timer.attach_us(callback(this,
+ &SX1276_LoRaRadio::timeout_irq_isr), timeout*1e3);
+ set_operation_mode(RF_OPMODE_TRANSMITTER);
+}
+
+/**
+ * Get RSSI from the module
+ */
+int16_t SX1276_LoRaRadio::get_rssi(radio_modems_t modem)
+{
+ int16_t rssi = 0;
+
+ switch (modem) {
+ case MODEM_FSK:
+ rssi = -(read_register(REG_RSSIVALUE) >> 1);
+ break;
+ case MODEM_LORA:
+ if (_rf_settings.channel > RF_MID_BAND_THRESH) {
+ rssi = RSSI_OFFSET_HF + read_register(REG_LR_RSSIVALUE);
+ } else {
+ rssi = RSSI_OFFSET_LF + read_register(REG_LR_RSSIVALUE);
+ }
+ break;
+ default:
+ rssi = -1;
+ break;
+ }
+ return rssi;
+}
+
+/**
+ * Sets the module in low power mode by disconnecting
+ * TX and RX submodules, turning off power amplifier etc.
+ */
+void SX1276_LoRaRadio::set_low_power_mode()
+{
+
+ if (_rf_ctrls.rf_switch_ctl1 != NC) {
+ _rf_switch_ctl1 = 0;
+ }
+
+ if (_rf_ctrls.rf_switch_ctl2 != NC) {
+ _rf_switch_ctl2 = 0;
+ }
+
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ _pwr_amp_ctl = 0;
+ }
+
+ if (_rf_ctrls.txctl != NC) {
+ _txctl = 0;
+ }
+
+ if (_rf_ctrls.txctl != NC) {
+ _rxctl = 0;
+ }
+
+ if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ }
+}
+
+/**
+ * Attaches ISRs to interrupt pins
+ */
+void SX1276_LoRaRadio::setup_interrupts()
+{
+ _dio0_ctl.rise(callback(this, &SX1276_LoRaRadio::dio0_irq_isr));
+ _dio1_ctl.rise(callback(this, &SX1276_LoRaRadio::dio1_irq_isr));
+ _dio2_ctl.rise(callback(this, &SX1276_LoRaRadio::dio2_irq_isr));
+ _dio3_ctl.rise(callback(this, &SX1276_LoRaRadio::dio3_irq_isr));
+ if (_dio4_pin != NC) {
+ _dio4_ctl.rise(callback(this, &SX1276_LoRaRadio::dio4_irq_isr));
+ }
+ if (_dio5_pin != NC) {
+ _dio5_ctl.rise(callback(this, &SX1276_LoRaRadio::dio5_irq_isr));
+ }
+}
+
+/**
+ * Sets up radio latch position according to the
+ * radio mode
+ */
+void SX1276_LoRaRadio::set_antenna_switch(uint8_t mode)
+{
+ // here we got to do ifdef for changing controls
+ // as some pins might be NC
+ switch (mode) {
+ case RFLR_OPMODE_TRANSMITTER:
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // module is in transmit mode and RF latch switches
+ // are connected. Check if power amplifier boost is
+ // setup or not
+ if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST)
+ == RF_PACONFIG_PASELECT_PABOOST) {
+ _rf_switch_ctl1 = 1;
+ _rf_switch_ctl2 = 0;
+ } else {
+ // power amplifier not selected
+ _rf_switch_ctl1 = 0;
+ _rf_switch_ctl2 = 1;
+ }
+ }
+ if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ // module is in transmit mode and tx/rx submodule control
+ // pins are connected
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ if (read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) {
+ _pwr_amp_ctl = 1;
+ _txctl = 0;
+ } else {
+ _pwr_amp_ctl = 0;
+ _txctl = 1;
+ }
+ } else {
+ _txctl = 1;
+ }
+ _rxctl = 0;
+ }
+ if (_rf_ctrls.ant_switch != NC){
+ _ant_switch = 1;
+ }
+ break;
+ case RFLR_OPMODE_RECEIVER:
+ case RFLR_OPMODE_RECEIVER_SINGLE:
+ case RFLR_OPMODE_CAD:
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // radio is in reception or CAD mode and RF latch switches
+ // are connected
+ _rf_switch_ctl1 = 1;
+ _rf_switch_ctl2 = 1;
+ }
+ if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ _txctl = 0;
+ _rxctl = 1;
+ }
+ if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ }
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ _pwr_amp_ctl = 0;
+ }
+ break;
+ default:
+ // Enforce default case when any connected control pin is kept low.
+ if (_rf_ctrls.rf_switch_ctl1 != NC
+ && _rf_ctrls.rf_switch_ctl2 != NC) {
+ // radio is in reception or CAD mode and RF latch switches
+ // are connected
+ _rf_switch_ctl1 = 0;
+ _rf_switch_ctl2 = 0;
+ }
+ if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
+ _txctl = 0;
+ _rxctl = 0;
+ }
+ if (_rf_ctrls.ant_switch != NC) {
+ _ant_switch = 0;
+ }
+ if (_rf_ctrls.pwr_amp_ctl != NC) {
+ _pwr_amp_ctl = 0;
+ }
+ break;
+ }
+}
+
+/*****************************************************************************
+ * Interrupt service routines (ISRs) - set signals to the irq_thread *
+ ****************************************************************************/
+void SX1276_LoRaRadio::dio0_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO0);
+#else
+ handle_dio0_irq();
+#endif
+}
+
+void SX1276_LoRaRadio::dio1_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO1);
+#else
+ handle_dio1_irq();
+#endif
+}
+
+void SX1276_LoRaRadio::dio2_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO2);
+#else
+ handle_dio2_irq();
+#endif
+}
+
+void SX1276_LoRaRadio::dio3_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO3);
+#else
+ handle_dio3_irq();
+#endif
+}
+
+void SX1276_LoRaRadio::dio4_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO4);
+#else
+ handle_dio4_irq();
+#endif
+}
+
+void SX1276_LoRaRadio::dio5_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_DIO5);
+#else
+ handle_dio5_irq();
+#endif
+}
+
+// This is not a hardware interrupt
+// we invoke it ourselves based upon
+// our timers
+void SX1276_LoRaRadio::timeout_irq_isr()
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ irq_thread.signal_set(SIG_TIMOUT);
+#else
+ handle_timeout_irq();
+#endif
+}
+
+/******************************************************************************
+ * Interrupt Handlers *
+ *****************************************************************************/
+
+void SX1276_LoRaRadio::handle_dio0_irq()
+{
+ volatile uint8_t irqFlags = 0;
+
+ switch (_rf_settings.state) {
+ case RF_RX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ if (_rf_settings.fsk.crc_on == true) {
+ irqFlags = read_register(REG_IRQFLAGS2);
+ if ((irqFlags & RF_IRQFLAGS2_CRCOK)
+ != RF_IRQFLAGS2_CRCOK) {
+ // Clear Irqs
+ write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.detach();
+ _rf_settings.state = RF_IDLE;
+ } else {
+ // Continuous mode restart Rx chain
+ write_to_register(REG_RXCONFIG,
+ read_register(REG_RXCONFIG) |
+ RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ }
+
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_error)) {
+ _radio_events->rx_error();
+ }
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+ // break from here, a CRC error happened, RX_ERROR
+ // was notified. No need to go any further
+ break;
+ }
+ }
+
+ // Read received packet size
+ if ((_rf_settings.fsk_packet_handler.size == 0)
+ && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) {
+ if (_rf_settings.fsk.fix_len == false) {
+ read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1);
+ } else {
+ _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH);
+ }
+ read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
+ _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ } else {
+ read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
+ _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
+ }
+
+ if (_rf_settings.fsk.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ rx_timeout_sync_word.detach();
+ } else {
+ // Continuous mode restart Rx chain
+ write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG)
+ | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ }
+
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL) && (_radio_events->rx_done)) {
+ _radio_events->rx_done(
+ _data_buffer,
+ _rf_settings.fsk_packet_handler.size,
+ _rf_settings.fsk_packet_handler.rssi_value, 0);
+ }
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+ break;
+
+ case MODEM_LORA: {
+ int8_t snr = 0;
+
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
+
+ irqFlags = read_register(REG_LR_IRQFLAGS);
+ if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)
+ == RFLR_IRQFLAGS_PAYLOADCRCERROR) {
+ // Clear Irq
+ write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR);
+
+ if (_rf_settings.lora.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ }
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_error)) {
+ _radio_events->rx_error();
+ }
+ break;
+ }
+
+ _rf_settings.lora_packet_handler.snr_value = read_register(
+ REG_LR_PKTSNRVALUE);
+ if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1
+ {
+ // Invert and divide by 4
+ snr = ((~_rf_settings.lora_packet_handler.snr_value + 1)
+ & 0xFF) >> 2;
+ snr = -snr;
+ } else {
+ // Divide by 4
+ snr =
+ (_rf_settings.lora_packet_handler.snr_value
+ & 0xFF) >> 2;
+ }
+
+ int16_t rssi = read_register( REG_LR_PKTRSSIVALUE);
+ if (snr < 0) {
+ if (_rf_settings.channel > RF_MID_BAND_THRESH) {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET_HF + rssi + (rssi >> 4) + snr;
+ } else {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET_LF + rssi + (rssi >> 4) + snr;
+ }
+ } else {
+ if (_rf_settings.channel > RF_MID_BAND_THRESH) {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET_HF + rssi + (rssi >> 4);
+ } else {
+ _rf_settings.lora_packet_handler.rssi_value =
+ RSSI_OFFSET_LF + rssi + (rssi >> 4);
+ }
+ }
+
+ _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES);
+ read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size);
+
+ if (_rf_settings.lora.rx_continuous == false) {
+ _rf_settings.state = RF_IDLE;
+ }
+ rx_timeout_timer.detach();
+
+ if ((_radio_events != NULL) && (_radio_events->rx_done)) {
+ _radio_events->rx_done(_data_buffer,
+ _rf_settings.lora_packet_handler.size,
+ _rf_settings.lora_packet_handler.rssi_value,
+ _rf_settings.lora_packet_handler.snr_value);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ tx_timeout_timer.detach();
+ // TxDone interrupt
+ switch (_rf_settings.modem) {
+ case MODEM_LORA:
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
+ // Intentional fall through
+ case MODEM_FSK:
+ default:
+ _rf_settings.state = RF_IDLE;
+ if ((_radio_events != NULL)
+ && (_radio_events->tx_done)) {
+ _radio_events->tx_done();
+ }
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1276_LoRaRadio::handle_dio1_irq()
+{
+ switch (_rf_settings.state) {
+ case RF_RX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ // Read received packet size
+ if ((_rf_settings.fsk_packet_handler.size == 0)
+ && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) {
+ if (_rf_settings.fsk.fix_len == false) {
+ read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1);
+ } else {
+ _rf_settings.fsk_packet_handler.size =
+ read_register(REG_PAYLOADLENGTH);
+ }
+ }
+
+ if ((_rf_settings.fsk_packet_handler.size
+ - _rf_settings.fsk_packet_handler.nb_bytes)
+ > _rf_settings.fsk_packet_handler.fifo_thresh) {
+ read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes),
+ _rf_settings.fsk_packet_handler.fifo_thresh);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ _rf_settings.fsk_packet_handler.fifo_thresh;
+ } else {
+ read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes),
+ _rf_settings.fsk_packet_handler.size
+ - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ (_rf_settings.fsk_packet_handler.size
+ - _rf_settings.fsk_packet_handler.nb_bytes);
+ }
+
+ break;
+
+ case MODEM_LORA:
+ // Sync time out
+ rx_timeout_timer.detach();
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT);
+ _rf_settings.state = RF_IDLE;
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_timeout)) {
+ _radio_events->rx_timeout();
+ }
+ break;
+ default:
+ break;
+ }
+
+ break;
+
+ case RF_TX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ if ((_rf_settings.fsk_packet_handler.size
+ - _rf_settings.fsk_packet_handler.nb_bytes)
+ > _rf_settings.fsk_packet_handler.chunk_size) {
+ write_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes),
+ _rf_settings.fsk_packet_handler.chunk_size);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ _rf_settings.fsk_packet_handler.chunk_size;
+ } else {
+ // Write the last chunk of data
+ write_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
+ _rf_settings.fsk_packet_handler.size
+ - _rf_settings.fsk_packet_handler.nb_bytes);
+ _rf_settings.fsk_packet_handler.nb_bytes +=
+ _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes;
+ }
+
+ break;
+
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1276_LoRaRadio::handle_dio2_irq(void)
+{
+ switch (_rf_settings.state) {
+ case RF_RX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ // DIO4 must have been asserted to set preamble_detected to true
+ if ((_rf_settings.fsk_packet_handler.preamble_detected == 1)
+ && (_rf_settings.fsk_packet_handler.sync_word_detected == 0)) {
+ if (_rf_settings.fsk.rx_continuous == false) {
+ rx_timeout_sync_word.detach();
+ }
+
+ _rf_settings.fsk_packet_handler.sync_word_detected = 1;
+
+ _rf_settings.fsk_packet_handler.rssi_value =
+ -(read_register(REG_RSSIVALUE) >> 1);
+
+ _rf_settings.fsk_packet_handler.afc_value =
+ (int32_t) (double) (((uint16_t) read_register(
+ REG_AFCMSB) << 8)
+ | (uint16_t) read_register( REG_AFCLSB))
+ * (double) FREQ_STEP;
+ _rf_settings.fsk_packet_handler.rx_gain =
+ (read_register( REG_LNA) >> 5) & 0x07;
+ }
+
+ break;
+
+ case MODEM_LORA:
+ if (_rf_settings.lora.freq_hop_on == true) {
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS,
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ if ((_radio_events != NULL)
+ && (_radio_events->fhss_change_channel)) {
+ _radio_events->fhss_change_channel(
+ (read_register(REG_LR_HOPCHANNEL)
+ & RFLR_HOPCHANNEL_CHANNEL_MASK));
+ }
+ }
+
+ break;
+
+ default:
+ break;
+ }
+
+ break;
+
+ case RF_TX_RUNNING:
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if (_rf_settings.lora.freq_hop_on == true) {
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS,
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ if ((_radio_events != NULL)
+ && (_radio_events->fhss_change_channel)) {
+ _radio_events->fhss_change_channel(
+ (read_register(REG_LR_HOPCHANNEL)
+ & RFLR_HOPCHANNEL_CHANNEL_MASK));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1276_LoRaRadio::handle_dio3_irq(void)
+{
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if ((read_register(REG_LR_IRQFLAGS) & RFLR_IRQFLAGS_CADDETECTED)
+ == RFLR_IRQFLAGS_CADDETECTED) {
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS,
+ RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE);
+ if ((_radio_events != NULL)
+ && (_radio_events->cad_done)) {
+ _radio_events->cad_done(true);
+ }
+ } else {
+ // Clear Irq
+ write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE);
+ if ((_radio_events != NULL)
+ && (_radio_events->cad_done)) {
+ _radio_events->cad_done(false);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1276_LoRaRadio::handle_dio4_irq(void)
+{
+ // is asserted when a preamble is detected (FSK modem only)
+ switch (_rf_settings.modem) {
+ case MODEM_FSK: {
+ if (_rf_settings.fsk_packet_handler.preamble_detected == 0) {
+ _rf_settings.fsk_packet_handler.preamble_detected = 1;
+ }
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1276_LoRaRadio::handle_dio5_irq()
+{
+ switch (_rf_settings.modem) {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+
+void SX1276_LoRaRadio::handle_timeout_irq()
+{
+ switch (_rf_settings.state) {
+ case RF_RX_RUNNING:
+ if (_rf_settings.modem == MODEM_FSK) {
+ _rf_settings.fsk_packet_handler.preamble_detected = 0;
+ _rf_settings.fsk_packet_handler.sync_word_detected = 0;
+ _rf_settings.fsk_packet_handler.nb_bytes = 0;
+ _rf_settings.fsk_packet_handler.size = 0;
+
+ // Clear Irqs
+ write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+ if (_rf_settings.fsk.rx_continuous == true) {
+ // Continuous mode restart Rx chain
+ write_to_register( REG_RXCONFIG,
+ read_register(REG_RXCONFIG) |
+ RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ } else {
+ _rf_settings.state = RF_IDLE;
+ rx_timeout_sync_word.attach_us(
+ callback(this, &SX1276_LoRaRadio::timeout_irq_isr),
+ _rf_settings.fsk.rx_single_timeout * 1e3);
+ }
+ }
+
+ if ((_radio_events != NULL)
+ && (_radio_events->rx_timeout)) {
+ _radio_events->rx_timeout();
+ }
+
+ break;
+
+ case RF_TX_RUNNING:
+ // Tx timeout shouldn't happen.
+ // But it has been observed that when it happens it is a result of a
+ // corrupted SPI transfer
+ // The workaround is to put the radio in a known state.
+ // Thus, we re-initialize it.
+
+ // Reset the radio
+ radio_reset();
+
+ // Initialize radio default values
+ set_operation_mode(RF_OPMODE_SLEEP);
+
+ setup_registers();
+
+ set_modem(MODEM_FSK);
+
+ // Restore previous network type setting.
+ set_public_network(_rf_settings.lora.public_network);
+
+ _rf_settings.state = RF_IDLE;
+ if ((_radio_events != NULL)
+ && (_radio_events->tx_timeout)) {
+ _radio_events->tx_timeout();
+ }
+ break;
+ default:
+ break;
+ }
+}
+// EOF
+
+#endif //DEVICE_SPI
+
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1276/SX1276_LoRaRadio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1276/SX1276_LoRaRadio.h Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,442 @@
+/**
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C)2013 Semtech
+ ___ _____ _ ___ _ _____ ___ ___ ___ ___
+/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __|
+\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _|
+|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___|
+embedded.connectivity.solutions===============
+
+Description: LoRaWAN stack layer that controls both MAC and PHY underneath
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE )
+
+
+Copyright (c) 2017, Arm Limited and affiliates.
+
+SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef SX1276_LORARADIO_H_
+#define SX1276_LORARADIO_H_
+
+#include "PinNames.h"
+#include "InterruptIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "SPI.h"
+#include "Timeout.h"
+#include "platform/PlatformMutex.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+ #include "rtos/Thread.h"
+#endif
+
+#include "lorawan/LoRaRadio.h"
+
+#ifdef MBED_CONF_SX1276_LORA_DRIVER_BUFFER_SIZE
+#define MAX_DATA_BUFFER_SIZE_SX1276 MBED_CONF_SX1276_LORA_DRIVER_BUFFER_SIZE
+#else
+#define MAX_DATA_BUFFER_SIZE_SX1276 256
+#endif
+
+#ifdef DEVICE_SPI
+
+/**
+ * Radio driver implementation for Semtech SX1272 plus variants.
+ * Supports only SPI at the moment. Implements pure virtual LoRaRadio class.
+ */
+class SX1276_LoRaRadio: public LoRaRadio {
+public:
+ /**
+ * Use this constructor if pin definitions are provided manually.
+ * The pins that are marked NC are optional. It is assumed that these
+ * pins are not connected until/unless configured otherwise.
+ *
+ * Note: Pin ant_switch is equivalent to RxTx pin at
+ * https://developer.mbed.org/components/SX1276MB1xAS/.
+ * Reading the state of this pin indicates if the radio module type is
+ * SX1276MB1LAS(North American frequency band supported) or SX1276MAS
+ * (European frequency band supported).
+ * Pin dio4 can be mapped to multiple pins on the board, please refer to
+ * schematic of your board. For reference look at
+ * https://developer.mbed.org/components/SX1276MB1xAS/
+ *
+ * Most of the radio module control pins are not being used at the moment as
+ * the SX1276MB1xAS shield has not connected them. For consistency and future
+ * use we are leaving the pins in the constructor. For example, if in some
+ * setting SX1276 radio module gets connected to an external power amplifier
+ * or radio latch controls are connected.
+ */
+ SX1276_LoRaRadio(PinName mosi,
+ PinName miso,
+ PinName sclk,
+ PinName nss,
+ PinName reset,
+ PinName dio0,
+ PinName dio1,
+ PinName dio2,
+ PinName dio3,
+ PinName dio4,
+ PinName dio5,
+ PinName rf_switch_ctl1 = NC,
+ PinName rf_switch_ctl2 = NC,
+ PinName txctl = NC,
+ PinName rxctl = NC,
+ PinName ant_switch = NC,
+ PinName pwr_amp_ctl = NC,
+ PinName tcxo = NC);
+
+ /**
+ * Destructor
+ */
+ virtual ~SX1276_LoRaRadio();
+
+ /**
+ * Registers radio events with the Mbed LoRaWAN stack and
+ * undergoes initialization steps if any
+ *
+ * @param events Structure containing the driver callback functions
+ */
+ virtual void init_radio(radio_events_t *events);
+
+ /**
+ * Resets the radio module
+ */
+ virtual void radio_reset();
+
+ /**
+ * Put the RF module in sleep mode
+ */
+ virtual void sleep(void);
+
+ /**
+ * Sets the radio in standby mode
+ */
+ virtual void standby(void);
+
+ /**
+ * Sets the reception parameters
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param bandwidth Sets the bandwidth
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param bandwidth_afc Sets the AFC Bandwidth ( FSK only )
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: N/A ( set to 0 )
+ * @param preamble_len Sets the Preamble length ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: Length in symbols ( the hardware adds 4 more symbols )
+ * @param symb_timeout Sets the RxSingle timeout value
+ * FSK : timeout number of bytes
+ * LoRa: timeout in symbols
+ * @param fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param payload_len Sets payload length when fixed lenght is used
+ * @param crc_on Enables/Disables the CRC [0: OFF, 1: ON]
+ * @param freq_hop_on Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param hop_period Number of symbols bewteen each hop (LoRa only)
+ * @param iq_inverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param rx_continuous Sets the reception in continuous mode
+ * [false: single mode, true: continuous mode]
+ */
+ virtual void set_rx_config (radio_modems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidth_afc, uint16_t preamble_len,
+ uint16_t symb_timeout, bool fix_len,
+ uint8_t payload_len,
+ bool crc_on, bool freq_hop_on, uint8_t hop_period,
+ bool iq_inverted, bool rx_continuous);
+
+ /**
+ * Sets the transmission parameters
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param power Sets the output power [dBm]
+ * @param fdev Sets the frequency deviation ( FSK only )
+ * FSK : [Hz]
+ * LoRa: 0
+ * @param bandwidth Sets the bandwidth ( LoRa only )
+ * FSK : 0
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param preamble_len Sets the preamble length
+ * @param fix_len Fixed length packets [0: variable, 1: fixed]
+ * @param crc_on Enables disables the CRC [0: OFF, 1: ON]
+ * @param freq_hop_on Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param hop_period Number of symbols bewteen each hop (LoRa only)
+ * @param iq_inverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param timeout Transmission timeout [us]
+ */
+ virtual void set_tx_config(radio_modems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preamble_len,
+ bool fix_len, bool crc_on, bool freq_hop_on,
+ uint8_t hop_period, bool iq_inverted, uint32_t timeout);
+
+ /**
+ * Sends the buffer of size
+ *
+ * Prepares the packet to be sent and sets the radio in transmission
+ *
+ * @param buffer Buffer pointer
+ * @param size Buffer size
+ */
+ virtual void send(uint8_t *buffer, uint8_t size);
+
+ /**
+ * Sets the radio in reception mode for the given time
+ *
+ * It should be noted that if the timeout is set to 0, it essentially
+ * puts the receiver in continuous mode and hence from thereon it should
+ * be treated as if in continuous mode. However, an appropriate way of
+ * setting the receiver in continuous mode is by using set_rx_config()
+ * API.
+ *
+ * @param timeout Reception timeout [ms]
+ *
+ */
+ virtual void receive(uint32_t timeout);
+
+ /**
+ * Sets the carrier frequency
+ *
+ * @param freq Channel RF frequency
+ */
+ virtual void set_channel(uint32_t freq);
+
+ /**
+ * Generates a 32 bits random value based on the RSSI readings
+ *
+ * Remark this function sets the radio in LoRa modem mode and disables
+ * all interrupts.
+ * After calling this function either Radio.SetRxConfig or
+ * Radio.SetTxConfig functions must be called.
+ *
+ * @return 32 bits random value
+ */
+ virtual uint32_t random(void);
+
+ /**
+ * Get radio status
+ *
+ * @param status Radio status [RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+ * @return Return current radio status
+ */
+ virtual uint8_t get_status(void);
+
+ /**
+ * Sets the maximum payload length
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param max Maximum payload length in bytes
+ */
+ virtual void set_max_payload_length(radio_modems_t modem, uint8_t max);
+
+ /**
+ * Sets the network to public or private
+ *
+ * Updates the sync byte. Applies to LoRa modem only
+ *
+ * @param enable if true, it enables a public network
+ */
+ virtual void set_public_network(bool enable);
+
+ /**
+ * Computes the packet time on air for the given payload
+ *
+ * Remark can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * @param modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param pkt_len Packet payload length
+ * @return Computed airTime for the given packet payload length
+ */
+ virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len);
+
+ /**
+ * Perform carrier sensing
+ *
+ * Checks for a certain time if the RSSI is above a given threshold.
+ * This threshold determines if there is already a transmission going on
+ * in the channel or not.
+ *
+ * @param modem Type of the radio modem
+ * @param freq Carrier frequency
+ * @param rssi_threshold Threshold value of RSSI
+ * @param max_carrier_sense_time time to sense the channel
+ *
+ * @return true if there is no active transmission
+ * in the channel, false otherwise
+ */
+ virtual bool perform_carrier_sense(radio_modems_t modem,
+ uint32_t freq,
+ int16_t rssi_threshold,
+ uint32_t max_carrier_sense_time);
+
+ /**
+ * Sets the radio in CAD mode
+ *
+ */
+ virtual void start_cad(void);
+
+ /**
+ * Check if the given RF is in range
+ *
+ * @param frequency frequency needed to be checked
+ */
+ virtual bool check_rf_frequency(uint32_t frequency);
+
+ /** Sets the radio in continuous wave transmission mode
+ *
+ * @param freq Channel RF frequency
+ * @param power Sets the output power [dBm]
+ * @param time Transmission mode timeout [s]
+ */
+ virtual void set_tx_continuous_wave(uint32_t freq, int8_t power, uint16_t time);
+
+ /**
+ * Acquire exclusive access
+ */
+ virtual void lock(void);
+
+ /**
+ * Release exclusive access
+ */
+ virtual void unlock(void);
+
+private:
+
+ // SPI and chip select control
+ mbed::SPI _spi;
+ mbed::DigitalOut _chip_select;
+
+ // module rest control
+ mbed::DigitalInOut _reset_ctl;
+
+ // Interrupt controls
+ mbed::InterruptIn _dio0_ctl;
+ mbed::InterruptIn _dio1_ctl;
+ mbed::InterruptIn _dio2_ctl;
+ mbed::InterruptIn _dio3_ctl;
+ mbed::InterruptIn _dio4_ctl;
+ mbed::InterruptIn _dio5_ctl;
+
+ // Radio specific controls
+ mbed::DigitalOut _rf_switch_ctl1;
+ mbed::DigitalOut _rf_switch_ctl2;
+ mbed::DigitalOut _txctl;
+ mbed::DigitalOut _rxctl;
+ mbed::DigitalInOut _ant_switch;
+ mbed::DigitalOut _pwr_amp_ctl;
+ mbed::DigitalOut _tcxo;
+
+ // Contains all RF control pin names
+ // This storage is needed even after assigning the
+ // pins to corresponding object, as the driver needs to know
+ // which control pins are connected and which are not. This
+ // variation is inherent to driver because of target configuration.
+ rf_ctrls _rf_ctrls;
+
+ // We need these PinNames as not all modules have those connected
+ PinName _dio4_pin;
+ PinName _dio5_pin;
+
+ // Structure containing all user and network specified settings
+ // for radio module
+ radio_settings_t _rf_settings;
+
+ // Structure containing function pointers to the stack callbacks
+ radio_events_t *_radio_events;
+
+ // Data buffer used for both TX and RX
+ // Size of this buffer is configurable via Mbed config system
+ // Default is 256 bytes
+ uint8_t _data_buffer[MAX_DATA_BUFFER_SIZE_SX1276];
+
+ // TX/RX Timers - all use milisecond units
+ mbed::Timeout tx_timeout_timer;
+ mbed::Timeout rx_timeout_timer;
+ mbed::Timeout rx_timeout_sync_word;
+
+#ifdef MBED_CONF_RTOS_PRESENT
+ // Thread to handle interrupts
+ rtos::Thread irq_thread;
+#endif
+
+ // Access protection
+ PlatformMutex mutex;
+
+ uint8_t radio_variant;
+
+ // helper functions
+ void setup_registers();
+ void default_antenna_switch_ctrls();
+ void set_antenna_switch(uint8_t operation_mode);
+ void setup_spi();
+ void gpio_init();
+ void gpio_deinit();
+ void setup_interrupts();
+ void set_operation_mode(uint8_t operation_mode);
+ void set_low_power_mode();
+ void set_sx1276_variant_type();
+ uint8_t get_pa_conf_reg(uint32_t channel);
+ void set_rf_tx_power(int8_t power);
+ int16_t get_rssi(radio_modems_t modem);
+ uint8_t get_fsk_bw_reg_val(uint32_t bandwidth);
+ void write_to_register(uint8_t addr, uint8_t data);
+ void write_to_register(uint8_t addr, uint8_t *data, uint8_t size);
+ uint8_t read_register(uint8_t addr);
+ void read_register(uint8_t addr, uint8_t *buffer, uint8_t size);
+ void write_fifo(uint8_t *buffer, uint8_t size);
+ void read_fifo(uint8_t *buffer, uint8_t size);
+ void transmit(uint32_t timeout);
+ void rf_irq_task(void);
+ void set_modem(uint8_t modem);
+ void rx_chain_calibration(void);
+
+ // ISRs
+ void dio0_irq_isr();
+ void dio1_irq_isr();
+ void dio2_irq_isr();
+ void dio3_irq_isr();
+ void dio4_irq_isr();
+ void dio5_irq_isr();
+ void timeout_irq_isr();
+
+ // Handlers called by thread in response to signal
+ void handle_dio0_irq();
+ void handle_dio1_irq();
+ void handle_dio2_irq();
+ void handle_dio3_irq();
+ void handle_dio4_irq();
+ void handle_dio5_irq();
+ void handle_timeout_irq();
+};
+
+#endif //DEVICE_SPI
+
+#endif // SX1276_LORARADIO_H_
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1276/mbed_lib.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-lora-radio-drv/SX1276/mbed_lib.json Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,13 @@
+{
+ "name": "sx1276-lora-driver",
+ "config": {
+ "spi-frequency": {
+ "help": "SPI frequency, Default: 8 MHz",
+ "value": 8000000
+ },
+ "buffer-size": {
+ "help": "Max. buffer size the radio can handle, Default: 256 B",
+ "value": 256
+ }
+ }
+}
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1276/registers/sx1276Regs-Fsk.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-lora-radio-drv/SX1276/registers/sx1276Regs-Fsk.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,1138 @@ +/** + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2014 Semtech + +Description: SX1276 FSK modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian + +Copyright (c) 2017, Arm Limited and affiliates. + +SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef __SX1276_REGS_FSK_H__ +#define __SX1276_REGS_FSK_H__ + +/*! + * ============================================================================ + * SX1276 Internal registers Address + * ============================================================================ + */ +#define REG_FIFO 0x00 +// Common settings +#define REG_OPMODE 0x01 +#define REG_BITRATEMSB 0x02 +#define REG_BITRATELSB 0x03 +#define REG_FDEVMSB 0x04 +#define REG_FDEVLSB 0x05 +#define REG_FRFMSB 0x06 +#define REG_FRFMID 0x07 +#define REG_FRFLSB 0x08 +// Tx settings +#define REG_PACONFIG 0x09 +#define REG_PARAMP 0x0A +#define REG_OCP 0x0B +// Rx settings +#define REG_LNA 0x0C +#define REG_RXCONFIG 0x0D +#define REG_RSSICONFIG 0x0E +#define REG_RSSICOLLISION 0x0F +#define REG_RSSITHRESH 0x10 +#define REG_RSSIVALUE 0x11 +#define REG_RXBW 0x12 +#define REG_AFCBW 0x13 +#define REG_OOKPEAK 0x14 +#define REG_OOKFIX 0x15 +#define REG_OOKAVG 0x16 +#define REG_RES17 0x17 +#define REG_RES18 0x18 +#define REG_RES19 0x19 +#define REG_AFCFEI 0x1A +#define REG_AFCMSB 0x1B +#define REG_AFCLSB 0x1C +#define REG_FEIMSB 0x1D +#define REG_FEILSB 0x1E +#define REG_PREAMBLEDETECT 0x1F +#define REG_RXTIMEOUT1 0x20 +#define REG_RXTIMEOUT2 0x21 +#define REG_RXTIMEOUT3 0x22 +#define REG_RXDELAY 0x23 +// Oscillator settings +#define REG_OSC 0x24 +// Packet handler settings +#define REG_PREAMBLEMSB 0x25 +#define REG_PREAMBLELSB 0x26 +#define REG_SYNCCONFIG 0x27 +#define REG_SYNCVALUE1 0x28 +#define REG_SYNCVALUE2 0x29 +#define REG_SYNCVALUE3 0x2A +#define REG_SYNCVALUE4 0x2B +#define REG_SYNCVALUE5 0x2C +#define REG_SYNCVALUE6 0x2D +#define REG_SYNCVALUE7 0x2E +#define REG_SYNCVALUE8 0x2F +#define REG_PACKETCONFIG1 0x30 +#define REG_PACKETCONFIG2 0x31 +#define REG_PAYLOADLENGTH 0x32 +#define REG_NODEADRS 0x33 +#define REG_BROADCASTADRS 0x34 +#define REG_FIFOTHRESH 0x35 +// SM settings +#define REG_SEQCONFIG1 0x36 +#define REG_SEQCONFIG2 0x37 +#define REG_TIMERRESOL 0x38 +#define REG_TIMER1COEF 0x39 +#define REG_TIMER2COEF 0x3A +// Service settings +#define REG_IMAGECAL 0x3B +#define REG_TEMP 0x3C +#define REG_LOWBAT 0x3D +// Status +#define REG_IRQFLAGS1 0x3E +#define REG_IRQFLAGS2 0x3F +// I/O settings +#define REG_DIOMAPPING1 0x40 +#define REG_DIOMAPPING2 0x41 +// Version +#define REG_VERSION 0x42 +// Additional settings +#define REG_PLLHOP 0x44 +#define REG_TCXO 0x4B +#define REG_PADAC 0x4D +#define REG_FORMERTEMP 0x5B +#define REG_BITRATEFRAC 0x5D +#define REG_AGCREF 0x61 +#define REG_AGCTHRESH1 0x62 +#define REG_AGCTHRESH2 0x63 +#define REG_AGCTHRESH3 0x64 +#define REG_PLL 0x70 + +/*! + * ============================================================================ + * SX1276 FSK bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00 +#define RF_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20 + +#define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 +#define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default +#define RF_OPMODE_MODULATIONSHAPING_01 0x08 +#define RF_OPMODE_MODULATIONSHAPING_10 0x10 +#define RF_OPMODE_MODULATIONSHAPING_11 0x18 + +#define RF_OPMODE_MASK 0xF8 +#define RF_OPMODE_SLEEP 0x00 +#define RF_OPMODE_STANDBY 0x01 // Default +#define RF_OPMODE_SYNTHESIZER_TX 0x02 +#define RF_OPMODE_TRANSMITTER 0x03 +#define RF_OPMODE_SYNTHESIZER_RX 0x04 +#define RF_OPMODE_RECEIVER 0x05 + +/*! + * RegBitRate (bits/sec) + */ +#define RF_BITRATEMSB_1200_BPS 0x68 +#define RF_BITRATELSB_1200_BPS 0x2B +#define RF_BITRATEMSB_2400_BPS 0x34 +#define RF_BITRATELSB_2400_BPS 0x15 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default +#define RF_BITRATELSB_4800_BPS 0x0B // Default +#define RF_BITRATEMSB_9600_BPS 0x0D +#define RF_BITRATELSB_9600_BPS 0x05 +#define RF_BITRATEMSB_15000_BPS 0x08 +#define RF_BITRATELSB_15000_BPS 0x55 +#define RF_BITRATEMSB_19200_BPS 0x06 +#define RF_BITRATELSB_19200_BPS 0x83 +#define RF_BITRATEMSB_38400_BPS 0x03 +#define RF_BITRATELSB_38400_BPS 0x41 +#define RF_BITRATEMSB_76800_BPS 0x01 +#define RF_BITRATELSB_76800_BPS 0xA1 +#define RF_BITRATEMSB_153600_BPS 0x00 +#define RF_BITRATELSB_153600_BPS 0xD0 +#define RF_BITRATEMSB_57600_BPS 0x02 +#define RF_BITRATELSB_57600_BPS 0x2C +#define RF_BITRATEMSB_115200_BPS 0x01 +#define RF_BITRATELSB_115200_BPS 0x16 +#define RF_BITRATEMSB_12500_BPS 0x0A +#define RF_BITRATELSB_12500_BPS 0x00 +#define RF_BITRATEMSB_25000_BPS 0x05 +#define RF_BITRATELSB_25000_BPS 0x00 +#define RF_BITRATEMSB_50000_BPS 0x02 +#define RF_BITRATELSB_50000_BPS 0x80 +#define RF_BITRATEMSB_100000_BPS 0x01 +#define RF_BITRATELSB_100000_BPS 0x40 +#define RF_BITRATEMSB_150000_BPS 0x00 +#define RF_BITRATELSB_150000_BPS 0xD5 +#define RF_BITRATEMSB_200000_BPS 0x00 +#define RF_BITRATELSB_200000_BPS 0xA0 +#define RF_BITRATEMSB_250000_BPS 0x00 +#define RF_BITRATELSB_250000_BPS 0x80 +#define RF_BITRATEMSB_32768_BPS 0x03 +#define RF_BITRATELSB_32768_BPS 0xD1 + +/*! + * RegFdev (Hz) + */ +#define RF_FDEVMSB_2000_HZ 0x00 +#define RF_FDEVLSB_2000_HZ 0x21 +#define RF_FDEVMSB_5000_HZ 0x00 // Default +#define RF_FDEVLSB_5000_HZ 0x52 // Default +#define RF_FDEVMSB_10000_HZ 0x00 +#define RF_FDEVLSB_10000_HZ 0xA4 +#define RF_FDEVMSB_15000_HZ 0x00 +#define RF_FDEVLSB_15000_HZ 0xF6 +#define RF_FDEVMSB_20000_HZ 0x01 +#define RF_FDEVLSB_20000_HZ 0x48 +#define RF_FDEVMSB_25000_HZ 0x01 +#define RF_FDEVLSB_25000_HZ 0x9A +#define RF_FDEVMSB_30000_HZ 0x01 +#define RF_FDEVLSB_30000_HZ 0xEC +#define RF_FDEVMSB_35000_HZ 0x02 +#define RF_FDEVLSB_35000_HZ 0x3D +#define RF_FDEVMSB_40000_HZ 0x02 +#define RF_FDEVLSB_40000_HZ 0x8F +#define RF_FDEVMSB_45000_HZ 0x02 +#define RF_FDEVLSB_45000_HZ 0xE1 +#define RF_FDEVMSB_50000_HZ 0x03 +#define RF_FDEVLSB_50000_HZ 0x33 +#define RF_FDEVMSB_55000_HZ 0x03 +#define RF_FDEVLSB_55000_HZ 0x85 +#define RF_FDEVMSB_60000_HZ 0x03 +#define RF_FDEVLSB_60000_HZ 0xD7 +#define RF_FDEVMSB_65000_HZ 0x04 +#define RF_FDEVLSB_65000_HZ 0x29 +#define RF_FDEVMSB_70000_HZ 0x04 +#define RF_FDEVLSB_70000_HZ 0x7B +#define RF_FDEVMSB_75000_HZ 0x04 +#define RF_FDEVLSB_75000_HZ 0xCD +#define RF_FDEVMSB_80000_HZ 0x05 +#define RF_FDEVLSB_80000_HZ 0x1F +#define RF_FDEVMSB_85000_HZ 0x05 +#define RF_FDEVLSB_85000_HZ 0x71 +#define RF_FDEVMSB_90000_HZ 0x05 +#define RF_FDEVLSB_90000_HZ 0xC3 +#define RF_FDEVMSB_95000_HZ 0x06 +#define RF_FDEVLSB_95000_HZ 0x14 +#define RF_FDEVMSB_100000_HZ 0x06 +#define RF_FDEVLSB_100000_HZ 0x66 +#define RF_FDEVMSB_110000_HZ 0x07 +#define RF_FDEVLSB_110000_HZ 0x0A +#define RF_FDEVMSB_120000_HZ 0x07 +#define RF_FDEVLSB_120000_HZ 0xAE +#define RF_FDEVMSB_130000_HZ 0x08 +#define RF_FDEVLSB_130000_HZ 0x52 +#define RF_FDEVMSB_140000_HZ 0x08 +#define RF_FDEVLSB_140000_HZ 0xF6 +#define RF_FDEVMSB_150000_HZ 0x09 +#define RF_FDEVLSB_150000_HZ 0x9A +#define RF_FDEVMSB_160000_HZ 0x0A +#define RF_FDEVLSB_160000_HZ 0x3D +#define RF_FDEVMSB_170000_HZ 0x0A +#define RF_FDEVLSB_170000_HZ 0xE1 +#define RF_FDEVMSB_180000_HZ 0x0B +#define RF_FDEVLSB_180000_HZ 0x85 +#define RF_FDEVMSB_190000_HZ 0x0C +#define RF_FDEVLSB_190000_HZ 0x29 +#define RF_FDEVMSB_200000_HZ 0x0C +#define RF_FDEVLSB_200000_HZ 0xCD + +/*! + * RegFrf (MHz) + */ +#define RF_FRFMSB_863_MHZ 0xD7 +#define RF_FRFMID_863_MHZ 0xC0 +#define RF_FRFLSB_863_MHZ 0x00 +#define RF_FRFMSB_864_MHZ 0xD8 +#define RF_FRFMID_864_MHZ 0x00 +#define RF_FRFLSB_864_MHZ 0x00 +#define RF_FRFMSB_865_MHZ 0xD8 +#define RF_FRFMID_865_MHZ 0x40 +#define RF_FRFLSB_865_MHZ 0x00 +#define RF_FRFMSB_866_MHZ 0xD8 +#define RF_FRFMID_866_MHZ 0x80 +#define RF_FRFLSB_866_MHZ 0x00 +#define RF_FRFMSB_867_MHZ 0xD8 +#define RF_FRFMID_867_MHZ 0xC0 +#define RF_FRFLSB_867_MHZ 0x00 +#define RF_FRFMSB_868_MHZ 0xD9 +#define RF_FRFMID_868_MHZ 0x00 +#define RF_FRFLSB_868_MHZ 0x00 +#define RF_FRFMSB_869_MHZ 0xD9 +#define RF_FRFMID_869_MHZ 0x40 +#define RF_FRFLSB_869_MHZ 0x00 +#define RF_FRFMSB_870_MHZ 0xD9 +#define RF_FRFMID_870_MHZ 0x80 +#define RF_FRFLSB_870_MHZ 0x00 + +#define RF_FRFMSB_902_MHZ 0xE1 +#define RF_FRFMID_902_MHZ 0x80 +#define RF_FRFLSB_902_MHZ 0x00 +#define RF_FRFMSB_903_MHZ 0xE1 +#define RF_FRFMID_903_MHZ 0xC0 +#define RF_FRFLSB_903_MHZ 0x00 +#define RF_FRFMSB_904_MHZ 0xE2 +#define RF_FRFMID_904_MHZ 0x00 +#define RF_FRFLSB_904_MHZ 0x00 +#define RF_FRFMSB_905_MHZ 0xE2 +#define RF_FRFMID_905_MHZ 0x40 +#define RF_FRFLSB_905_MHZ 0x00 +#define RF_FRFMSB_906_MHZ 0xE2 +#define RF_FRFMID_906_MHZ 0x80 +#define RF_FRFLSB_906_MHZ 0x00 +#define RF_FRFMSB_907_MHZ 0xE2 +#define RF_FRFMID_907_MHZ 0xC0 +#define RF_FRFLSB_907_MHZ 0x00 +#define RF_FRFMSB_908_MHZ 0xE3 +#define RF_FRFMID_908_MHZ 0x00 +#define RF_FRFLSB_908_MHZ 0x00 +#define RF_FRFMSB_909_MHZ 0xE3 +#define RF_FRFMID_909_MHZ 0x40 +#define RF_FRFLSB_909_MHZ 0x00 +#define RF_FRFMSB_910_MHZ 0xE3 +#define RF_FRFMID_910_MHZ 0x80 +#define RF_FRFLSB_910_MHZ 0x00 +#define RF_FRFMSB_911_MHZ 0xE3 +#define RF_FRFMID_911_MHZ 0xC0 +#define RF_FRFLSB_911_MHZ 0x00 +#define RF_FRFMSB_912_MHZ 0xE4 +#define RF_FRFMID_912_MHZ 0x00 +#define RF_FRFLSB_912_MHZ 0x00 +#define RF_FRFMSB_913_MHZ 0xE4 +#define RF_FRFMID_913_MHZ 0x40 +#define RF_FRFLSB_913_MHZ 0x00 +#define RF_FRFMSB_914_MHZ 0xE4 +#define RF_FRFMID_914_MHZ 0x80 +#define RF_FRFLSB_914_MHZ 0x00 +#define RF_FRFMSB_915_MHZ 0xE4 // Default +#define RF_FRFMID_915_MHZ 0xC0 // Default +#define RF_FRFLSB_915_MHZ 0x00 // Default +#define RF_FRFMSB_916_MHZ 0xE5 +#define RF_FRFMID_916_MHZ 0x00 +#define RF_FRFLSB_916_MHZ 0x00 +#define RF_FRFMSB_917_MHZ 0xE5 +#define RF_FRFMID_917_MHZ 0x40 +#define RF_FRFLSB_917_MHZ 0x00 +#define RF_FRFMSB_918_MHZ 0xE5 +#define RF_FRFMID_918_MHZ 0x80 +#define RF_FRFLSB_918_MHZ 0x00 +#define RF_FRFMSB_919_MHZ 0xE5 +#define RF_FRFMID_919_MHZ 0xC0 +#define RF_FRFLSB_919_MHZ 0x00 +#define RF_FRFMSB_920_MHZ 0xE6 +#define RF_FRFMID_920_MHZ 0x00 +#define RF_FRFLSB_920_MHZ 0x00 +#define RF_FRFMSB_921_MHZ 0xE6 +#define RF_FRFMID_921_MHZ 0x40 +#define RF_FRFLSB_921_MHZ 0x00 +#define RF_FRFMSB_922_MHZ 0xE6 +#define RF_FRFMID_922_MHZ 0x80 +#define RF_FRFLSB_922_MHZ 0x00 +#define RF_FRFMSB_923_MHZ 0xE6 +#define RF_FRFMID_923_MHZ 0xC0 +#define RF_FRFLSB_923_MHZ 0x00 +#define RF_FRFMSB_924_MHZ 0xE7 +#define RF_FRFMID_924_MHZ 0x00 +#define RF_FRFLSB_924_MHZ 0x00 +#define RF_FRFMSB_925_MHZ 0xE7 +#define RF_FRFMID_925_MHZ 0x40 +#define RF_FRFLSB_925_MHZ 0x00 +#define RF_FRFMSB_926_MHZ 0xE7 +#define RF_FRFMID_926_MHZ 0x80 +#define RF_FRFLSB_926_MHZ 0x00 +#define RF_FRFMSB_927_MHZ 0xE7 +#define RF_FRFMID_927_MHZ 0xC0 +#define RF_FRFLSB_927_MHZ 0x00 +#define RF_FRFMSB_928_MHZ 0xE8 +#define RF_FRFMID_928_MHZ 0x00 +#define RF_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RF_PACONFIG_PASELECT_MASK 0x7F +#define RF_PACONFIG_PASELECT_PABOOST 0x80 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RF_PACONFIG_MAX_POWER_MASK 0x8F + +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F +#define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default +#define RF_PARAMP_MODULATIONSHAPING_01 0x20 +#define RF_PARAMP_MODULATIONSHAPING_10 0x40 +#define RF_PARAMP_MODULATIONSHAPING_11 0x60 + +#define RF_PARAMP_LOWPNTXPLL_MASK 0xEF +#define RF_PARAMP_LOWPNTXPLL_OFF 0x10 +#define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default + +#define RF_PARAMP_MASK 0xF0 +#define RF_PARAMP_3400_US 0x00 +#define RF_PARAMP_2000_US 0x01 +#define RF_PARAMP_1000_US 0x02 +#define RF_PARAMP_0500_US 0x03 +#define RF_PARAMP_0250_US 0x04 +#define RF_PARAMP_0125_US 0x05 +#define RF_PARAMP_0100_US 0x06 +#define RF_PARAMP_0062_US 0x07 +#define RF_PARAMP_0050_US 0x08 +#define RF_PARAMP_0040_US 0x09 // Default +#define RF_PARAMP_0031_US 0x0A +#define RF_PARAMP_0025_US 0x0B +#define RF_PARAMP_0020_US 0x0C +#define RF_PARAMP_0015_US 0x0D +#define RF_PARAMP_0012_US 0x0E +#define RF_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RF_OCP_MASK 0xDF +#define RF_OCP_ON 0x20 // Default +#define RF_OCP_OFF 0x00 + +#define RF_OCP_TRIM_MASK 0xE0 +#define RF_OCP_TRIM_045_MA 0x00 +#define RF_OCP_TRIM_050_MA 0x01 +#define RF_OCP_TRIM_055_MA 0x02 +#define RF_OCP_TRIM_060_MA 0x03 +#define RF_OCP_TRIM_065_MA 0x04 +#define RF_OCP_TRIM_070_MA 0x05 +#define RF_OCP_TRIM_075_MA 0x06 +#define RF_OCP_TRIM_080_MA 0x07 +#define RF_OCP_TRIM_085_MA 0x08 +#define RF_OCP_TRIM_090_MA 0x09 +#define RF_OCP_TRIM_095_MA 0x0A +#define RF_OCP_TRIM_100_MA 0x0B // Default +#define RF_OCP_TRIM_105_MA 0x0C +#define RF_OCP_TRIM_110_MA 0x0D +#define RF_OCP_TRIM_115_MA 0x0E +#define RF_OCP_TRIM_120_MA 0x0F +#define RF_OCP_TRIM_130_MA 0x10 +#define RF_OCP_TRIM_140_MA 0x11 +#define RF_OCP_TRIM_150_MA 0x12 +#define RF_OCP_TRIM_160_MA 0x13 +#define RF_OCP_TRIM_170_MA 0x14 +#define RF_OCP_TRIM_180_MA 0x15 +#define RF_OCP_TRIM_190_MA 0x16 +#define RF_OCP_TRIM_200_MA 0x17 +#define RF_OCP_TRIM_210_MA 0x18 +#define RF_OCP_TRIM_220_MA 0x19 +#define RF_OCP_TRIM_230_MA 0x1A +#define RF_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RF_LNA_GAIN_MASK 0x1F +#define RF_LNA_GAIN_G1 0x20 // Default +#define RF_LNA_GAIN_G2 0x40 +#define RF_LNA_GAIN_G3 0x60 +#define RF_LNA_GAIN_G4 0x80 +#define RF_LNA_GAIN_G5 0xA0 +#define RF_LNA_GAIN_G6 0xC0 + +#define RF_LNA_BOOST_MASK 0xFC +#define RF_LNA_BOOST_OFF 0x00 // Default +#define RF_LNA_BOOST_ON 0x03 + +/*! + * RegRxConfig + */ +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default + +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only + +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only + +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF +#define RF_RXCONFIG_AFCAUTO_ON 0x10 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default + +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default +#define RF_RXCONFIG_AGCAUTO_OFF 0x00 + +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 + +/*! + * RegRssiConfig + */ +#define RF_RSSICONFIG_OFFSET_MASK 0x07 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 + +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 +#define RF_RSSICONFIG_SMOOTHING_2 0x00 +#define RF_RSSICONFIG_SMOOTHING_4 0x01 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default +#define RF_RSSICONFIG_SMOOTHING_16 0x03 +#define RF_RSSICONFIG_SMOOTHING_32 0x04 +#define RF_RSSICONFIG_SMOOTHING_64 0x05 +#define RF_RSSICONFIG_SMOOTHING_128 0x06 +#define RF_RSSICONFIG_SMOOTHING_256 0x07 + +/*! + * RegRssiCollision + */ +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default + +/*! + * RegRssiThresh + */ +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegRxBw + */ +#define RF_RXBW_MANT_MASK 0xE7 +#define RF_RXBW_MANT_16 0x00 +#define RF_RXBW_MANT_20 0x08 +#define RF_RXBW_MANT_24 0x10 // Default + +#define RF_RXBW_EXP_MASK 0xF8 +#define RF_RXBW_EXP_0 0x00 +#define RF_RXBW_EXP_1 0x01 +#define RF_RXBW_EXP_2 0x02 +#define RF_RXBW_EXP_3 0x03 +#define RF_RXBW_EXP_4 0x04 +#define RF_RXBW_EXP_5 0x05 // Default +#define RF_RXBW_EXP_6 0x06 +#define RF_RXBW_EXP_7 0x07 + +/*! + * RegAfcBw + */ +#define RF_AFCBW_MANTAFC_MASK 0xE7 +#define RF_AFCBW_MANTAFC_16 0x00 +#define RF_AFCBW_MANTAFC_20 0x08 // Default +#define RF_AFCBW_MANTAFC_24 0x10 + +#define RF_AFCBW_EXPAFC_MASK 0xF8 +#define RF_AFCBW_EXPAFC_0 0x00 +#define RF_AFCBW_EXPAFC_1 0x01 +#define RF_AFCBW_EXPAFC_2 0x02 +#define RF_AFCBW_EXPAFC_3 0x03 // Default +#define RF_AFCBW_EXPAFC_4 0x04 +#define RF_AFCBW_EXPAFC_5 0x05 +#define RF_AFCBW_EXPAFC_6 0x06 +#define RF_AFCBW_EXPAFC_7 0x07 + +/*! + * RegOokPeak + */ +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default +#define RF_OOKPEAK_BITSYNC_OFF 0x00 + +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 + +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 + +/*! + * RegOokFix + */ +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default + +/*! + * RegOokAvg + */ +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 + +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C + +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 + +/*! + * RegAfcFei + */ +#define RF_AFCFEI_AGCSTART 0x10 + +#define RF_AFCFEI_AFCCLEAR 0x02 + +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default + +/*! + * RegAfcMsb (Read Only) + */ + +/*! + * RegAfcLsb (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegPreambleDetect + */ +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 + +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 + +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F + +/*! + * RegRxTimeout1 + */ +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default + +/*! + * RegRxTimeout2 + */ +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default + +/*! + * RegRxTimeout3 + */ +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default + +/*! + * RegRxDelay + */ +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default + +/*! + * RegOsc + */ +#define RF_OSC_RCCALSTART 0x08 + +#define RF_OSC_CLKOUT_MASK 0xF8 +#define RF_OSC_CLKOUT_32_MHZ 0x00 +#define RF_OSC_CLKOUT_16_MHZ 0x01 +#define RF_OSC_CLKOUT_8_MHZ 0x02 +#define RF_OSC_CLKOUT_4_MHZ 0x03 +#define RF_OSC_CLKOUT_2_MHZ 0x04 +#define RF_OSC_CLKOUT_1_MHZ 0x05 // Default +#define RF_OSC_CLKOUT_RC 0x06 +#define RF_OSC_CLKOUT_OFF 0x07 + +/*! + * RegPreambleMsb/RegPreambleLsb + */ +#define RF_PREAMBLEMSB_SIZE 0x00 // Default +#define RF_PREAMBLELSB_SIZE 0x03 // Default + +/*! + * RegSyncConfig + */ +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 + + +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default + +#define RF_SYNCCONFIG_SYNC_MASK 0xEF +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default +#define RF_SYNCCONFIG_SYNC_OFF 0x00 + + +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07 + +/*! + * RegSyncValue1-8 + */ +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default + +/*! + * RegPacketConfig1 + */ +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default + +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 + +#define RF_PACKETCONFIG1_CRC_MASK 0xEF +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default +#define RF_PACKETCONFIG1_CRC_OFF 0x00 + +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 + +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 + +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 + +/*! + * RegPacketConfig2 + */ + +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80 +#define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default + +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default + +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF +#define RF_PACKETCONFIG2_IOHOME_ON 0x20 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7 +#define RF_PACKETCONFIG2_BEACON_ON 0x08 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 + +/*! + * RegPayloadLength + */ +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default + +/*! + * RegNodeAdrs + */ +#define RF_NODEADDRESS_ADDRESS 0x00 + +/*! + * RegBroadcastAdrs + */ +#define RF_BROADCASTADDRESS_ADDRESS 0x00 + +/*! + * RegFifoThresh + */ +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 + +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default + +/*! + * RegSeqConfig1 + */ +#define RF_SEQCONFIG1_SEQUENCER_START 0x80 + +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 + +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default + +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 + +#define RF_SEQCONFIG1_LPS_MASK 0xFB +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default +#define RF_SEQCONFIG1_LPS_IDLE 0x04 + +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 + +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMTX_TORX 0x01 + +/*! + * RegSeqConfig2 + */ +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 + +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 + +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 + +/*! + * RegTimerResol + */ +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C + +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 + +/*! + * RegTimer1Coef + */ +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default + +/*! + * RegTimer2Coef + */ +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default + +/*! + * RegImageCal + */ +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default + +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF +#define RF_IMAGECAL_IMAGECAL_START 0x40 + +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default + +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 + +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 + +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 + +/*! + * RegTemp (Read Only) + */ + +/*! + * RegLowBat + */ +#define RF_LOWBAT_MASK 0xF7 +#define RF_LOWBAT_ON 0x08 +#define RF_LOWBAT_OFF 0x00 // Default + +#define RF_LOWBAT_TRIM_MASK 0xF8 +#define RF_LOWBAT_TRIM_1695 0x00 +#define RF_LOWBAT_TRIM_1764 0x01 +#define RF_LOWBAT_TRIM_1835 0x02 // Default +#define RF_LOWBAT_TRIM_1905 0x03 +#define RF_LOWBAT_TRIM_1976 0x04 +#define RF_LOWBAT_TRIM_2045 0x05 +#define RF_LOWBAT_TRIM_2116 0x06 +#define RF_LOWBAT_TRIM_2185 0x07 + +/*! + * RegIrqFlags1 + */ +#define RF_IRQFLAGS1_MODEREADY 0x80 + +#define RF_IRQFLAGS1_RXREADY 0x40 + +#define RF_IRQFLAGS1_TXREADY 0x20 + +#define RF_IRQFLAGS1_PLLLOCK 0x10 + +#define RF_IRQFLAGS1_RSSI 0x08 + +#define RF_IRQFLAGS1_TIMEOUT 0x04 + +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 + +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 + +/*! + * RegIrqFlags2 + */ +#define RF_IRQFLAGS2_FIFOFULL 0x80 + +#define RF_IRQFLAGS2_FIFOEMPTY 0x40 + +#define RF_IRQFLAGS2_FIFOLEVEL 0x20 + +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10 + +#define RF_IRQFLAGS2_PACKETSENT 0x08 + +#define RF_IRQFLAGS2_PAYLOADREADY 0x04 + +#define RF_IRQFLAGS2_CRCOK 0x02 + +#define RF_IRQFLAGS2_LOWBAT 0x01 + +/*! + * RegDioMapping1 + */ +#define RF_DIOMAPPING1_DIO0_MASK 0x3F +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default +#define RF_DIOMAPPING1_DIO0_01 0x40 +#define RF_DIOMAPPING1_DIO0_10 0x80 +#define RF_DIOMAPPING1_DIO0_11 0xC0 + +#define RF_DIOMAPPING1_DIO1_MASK 0xCF +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default +#define RF_DIOMAPPING1_DIO1_01 0x10 +#define RF_DIOMAPPING1_DIO1_10 0x20 +#define RF_DIOMAPPING1_DIO1_11 0x30 + +#define RF_DIOMAPPING1_DIO2_MASK 0xF3 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default +#define RF_DIOMAPPING1_DIO2_01 0x04 +#define RF_DIOMAPPING1_DIO2_10 0x08 +#define RF_DIOMAPPING1_DIO2_11 0x0C + +#define RF_DIOMAPPING1_DIO3_MASK 0xFC +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default +#define RF_DIOMAPPING1_DIO3_01 0x01 +#define RF_DIOMAPPING1_DIO3_10 0x02 +#define RF_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RF_DIOMAPPING2_DIO4_MASK 0x3F +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default +#define RF_DIOMAPPING2_DIO4_01 0x40 +#define RF_DIOMAPPING2_DIO4_10 0x80 +#define RF_DIOMAPPING2_DIO4_11 0xC0 + +#define RF_DIOMAPPING2_DIO5_MASK 0xCF +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default +#define RF_DIOMAPPING2_DIO5_01 0x10 +#define RF_DIOMAPPING2_DIO5_10 0x20 +#define RF_DIOMAPPING2_DIO5_11 0x30 + +#define RF_DIOMAPPING2_MAP_MASK 0xFE +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegPllHop + */ +#define RF_PLLHOP_FASTHOP_MASK 0x7F +#define RF_PLLHOP_FASTHOP_ON 0x80 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RF_TCXO_TCXOINPUT_MASK 0xEF +#define RF_TCXO_TCXOINPUT_ON 0x10 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RF_PADAC_20DBM_MASK 0xF8 +#define RF_PADAC_20DBM_ON 0x07 +#define RF_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + +#endif // __SX1276_REGS_FSK_H__
diff -r 000000000000 -r f930f0440fd5 mbed-lora-radio-drv/SX1276/registers/sx1276Regs-LoRa.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-lora-radio-drv/SX1276/registers/sx1276Regs-LoRa.h Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,569 @@ +/** + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2014 Semtech + +Description: SX1276 LoRa modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian + +Copyright (c) 2017, Arm Limited and affiliates. + +SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef __SX1276_REGS_LORA_H__ +#define __SX1276_REGS_LORA_H__ + +/*! + * ============================================================================ + * SX1276 Internal registers Address + * ============================================================================ + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_RXNBBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +#define REG_LR_FEIMSB 0x28 +#define REG_LR_FEIMID 0x29 +#define REG_LR_FEILSB 0x2A +#define REG_LR_RSSIWIDEBAND 0x2C +#define REG_LR_TEST2F 0x2F +#define REG_LR_TEST30 0x30 +#define REG_LR_DETECTOPTIMIZE 0x31 +#define REG_LR_INVERTIQ 0x33 +#define REG_LR_TEST36 0x36 +#define REG_LR_DETECTIONTHRESHOLD 0x37 +#define REG_LR_SYNCWORD 0x39 +#define REG_LR_TEST3A 0x3A +#define REG_LR_INVERTIQ2 0x3B + +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 +#define REG_LR_PLL 0x70 + +/*! + * ============================================================================ + * SX1276 LoRa bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegFrf (MHz) + */ +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default + +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + +/*! + * RegFifoRxNbBytes (Read Only) + */ + +/*! + * RegRxHeaderCntValueMsb (Read Only) + */ + +/*! + * RegRxHeaderCntValueLsb (Read Only) + */ + +/*! + * RegRxPacketCntValueMsb (Read Only) + */ + +/*! + * RegRxPacketCntValueLsb (Read Only) + */ + +/*! + * RegModemStat (Read Only) + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) + */ + +/*! + * RegPktRssiValue (Read Only) + */ + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + +/*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + +/*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiMid (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegRssiWideband (Read Only) + */ + +/*! + * RegDetectOptimize + */ +#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 +#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default +#define RFLR_DETECTIONOPTIMIZE_SF6 0x05 + +/*! + * RegInvertIQ + */ +#define RFLR_INVERTIQ_RX_MASK 0xBF +#define RFLR_INVERTIQ_RX_OFF 0x00 +#define RFLR_INVERTIQ_RX_ON 0x40 +#define RFLR_INVERTIQ_TX_MASK 0xFE +#define RFLR_INVERTIQ_TX_OFF 0x01 +#define RFLR_INVERTIQ_TX_ON 0x00 + +/*! + * RegDetectionThreshold + */ +#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default +#define RFLR_DETECTIONTHRESH_SF6 0x0C + +/*! + * RegInvertIQ2 + */ +#define RFLR_INVERTIQ2_ON 0x19 +#define RFLR_INVERTIQ2_OFF 0x1D + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + +#endif // __SX1276_REGS_LORA_H__
diff -r 000000000000 -r f930f0440fd5 mbed-os.lib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os.lib Wed Jun 26 10:35:50 2019 +0000 @@ -0,0 +1,1 @@ +https://github.com/ARMmbed/mbed-os/#f9ee4e849f8cbd64f1ec5fdd4ad256585a208360
diff -r 000000000000 -r f930f0440fd5 mbed_app.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed_app.json Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,284 @@
+{
+ "config": {
+ "lora-radio": {
+ "help": "Which radio to use (options: SX1272,SX1276)",
+ "value": "SX1276"
+ },
+ "main_stack_size": { "value": 4096 },
+
+ "lorawan-enabled": { "value": false},
+
+ "lora-spi-mosi": { "value": "NC" },
+ "lora-spi-miso": { "value": "NC" },
+ "lora-spi-sclk": { "value": "NC" },
+ "lora-cs": { "value": "NC" },
+ "lora-reset": { "value": "NC" },
+ "lora-dio0": { "value": "NC" },
+ "lora-dio1": { "value": "NC" },
+ "lora-dio2": { "value": "NC" },
+ "lora-dio3": { "value": "NC" },
+ "lora-dio4": { "value": "NC" },
+ "lora-dio5": { "value": "NC" },
+ "lora-rf-switch-ctl1": { "value": "NC" },
+ "lora-rf-switch-ctl2": { "value": "NC" },
+ "lora-txctl": { "value": "NC" },
+ "lora-rxctl": { "value": "NC" },
+ "lora-ant-switch": { "value": "NC" },
+ "lora-pwr-amp-ctl": { "value": "NC" },
+ "lora-tcxo": { "value": "NC" }
+ },
+ "target_overrides": {
+ "*": {
+ "platform.stdio-convert-newlines": true,
+ "platform.stdio-baud-rate": 9600,
+ "platform.default-serial-baud-rate": 9600,
+ "lora.duty-cycle-on": false,
+ "lora.phy": 0,
+ "target.features_add": ["COMMON_PAL"],
+ "mbed-trace.enable": true
+ },
+
+ "NUCLEO_F446RE": {
+ "lorawan-enabled": true,
+
+ "lora-spi-mosi": "D11",
+ "lora-spi-miso": "D12",
+ "lora-spi-sclk": "D13",
+ "lora-cs": "D10",
+ "lora-reset": "A0",
+ "lora-dio0": "D2",
+ "lora-dio1": "D3",
+ "lora-dio2": "D4",
+ "lora-dio3": "D5",
+ "lora-dio4": "D8",
+ "lora-dio5": "D9",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "A4",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "DISCO_L072CZ_LRWAN1": {
+ "main_stack_size": 1024,
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1276",
+ "lora-spi-mosi": "PA_7",
+ "lora-spi-miso": "PA_6",
+ "lora-spi-sclk": "PB_3",
+ "lora-cs": "PA_15",
+ "lora-reset": "PC_0",
+ "lora-dio0": "PB_4",
+ "lora-dio1": "PB_1",
+ "lora-dio2": "PB_0",
+ "lora-dio3": "PC_13",
+ "lora-dio4": "NC",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "PC_2",
+ "lora-rxctl": "PA_1",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "PC_1",
+ "lora-tcxo": "PA_12"
+ },
+
+ "MTB_MURATA_ABZ": {
+ "main_stack_size": 1024,
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1276",
+ "lora-spi-mosi": "PA_7",
+ "lora-spi-miso": "PA_6",
+ "lora-spi-sclk": "PB_3",
+ "lora-cs": "PA_15",
+ "lora-reset": "PC_0",
+ "lora-dio0": "PB_4",
+ "lora-dio1": "PB_1",
+ "lora-dio2": "PB_0",
+ "lora-dio3": "PC_13",
+ "lora-dio4": "NC",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "PC_2",
+ "lora-rxctl": "PA_1",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "PC_1",
+ "lora-tcxo": "PA_12"
+ },
+
+ "XDOT_L151CC": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1272",
+ "lora-spi-mosi": "LORA_MOSI",
+ "lora-spi-miso": "LORA_MISO",
+ "lora-spi-sclk": "LORA_SCK",
+ "lora-cs": "LORA_NSS",
+ "lora-reset": "LORA_RESET",
+ "lora-dio0": "LORA_DIO0",
+ "lora-dio1": "LORA_DIO1",
+ "lora-dio2": "LORA_DIO2",
+ "lora-dio3": "LORA_DIO3",
+ "lora-dio4": "LORA_DIO4",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "MTB_MTS_XDOT": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1272",
+ "lora-spi-mosi": "LORA_MOSI",
+ "lora-spi-miso": "LORA_MISO",
+ "lora-spi-sclk": "LORA_SCK",
+ "lora-cs": "LORA_NSS",
+ "lora-reset": "LORA_RESET",
+ "lora-dio0": "LORA_DIO0",
+ "lora-dio1": "LORA_DIO1",
+ "lora-dio2": "LORA_DIO2",
+ "lora-dio3": "LORA_DIO3",
+ "lora-dio4": "LORA_DIO4",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "LTEK_FF1705": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1272",
+ "lora-spi-mosi": "LORA_MOSI",
+ "lora-spi-miso": "LORA_MISO",
+ "lora-spi-sclk": "LORA_SCK",
+ "lora-cs": "LORA_NSS",
+ "lora-reset": "LORA_RESET",
+ "lora-dio0": "LORA_DIO0",
+ "lora-dio1": "LORA_DIO1",
+ "lora-dio2": "LORA_DIO2",
+ "lora-dio3": "LORA_DIO3",
+ "lora-dio4": "LORA_DIO4",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "MTS_MDOT_F411RE": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1272",
+ "lora-spi-mosi": "LORA_MOSI",
+ "lora-spi-miso": "LORA_MISO",
+ "lora-spi-sclk": "LORA_SCK",
+ "lora-cs": "LORA_NSS",
+ "lora-reset": "LORA_RESET",
+ "lora-dio0": "LORA_DIO0",
+ "lora-dio1": "LORA_DIO1",
+ "lora-dio2": "LORA_DIO2",
+ "lora-dio3": "LORA_DIO3",
+ "lora-dio4": "LORA_DIO4",
+ "lora-dio5": "LORA_DIO5",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "LORA_TXCTL",
+ "lora-rxctl": "LORA_RXCTL",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "MTB_ADV_WISE_1510": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1276",
+ "lora-spi-mosi": "SPI_RF_MOSI",
+ "lora-spi-miso": "SPI_RF_MISO",
+ "lora-spi-sclk": "SPI_RF_SCK",
+ "lora-cs": "SPI_RF_CS",
+ "lora-reset": "SPI_RF_RESET",
+ "lora-dio0": "DIO0",
+ "lora-dio1": "DIO1",
+ "lora-dio2": "DIO2",
+ "lora-dio3": "DIO3",
+ "lora-dio4": "DIO4",
+ "lora-dio5": "DIO5",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "ANT_SWITCH",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ },
+
+ "MTB_RAK811": {
+ "lorawan-enabled": true,
+
+ "lora-radio": "SX1276",
+ "lora-spi-mosi": "SPI_RF_MOSI",
+ "lora-spi-miso": "SPI_RF_MISO",
+ "lora-spi-sclk": "SPI_RF_SCK",
+ "lora-cs": "SPI_RF_CS",
+ "lora-reset": "SPI_RF_RESET",
+ "lora-dio0": "DIO0",
+ "lora-dio1": "DIO1",
+ "lora-dio2": "DIO2",
+ "lora-dio3": "DIO3",
+ "lora-dio4": "DIO4",
+ "lora-dio5": "NC",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "ANT_CTX_PA",
+ "lora-rxctl": "ANT_CRX_RX",
+ "lora-ant-switch": "NC",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "RF_TCXO_EN"
+ },
+
+ "SIMULATOR": {
+ "lorawan-enabled": true,
+
+ "lora-spi-mosi": "D11",
+ "lora-spi-miso": "D12",
+ "lora-spi-sclk": "D13",
+ "lora-cs": "D10",
+ "lora-reset": "A0",
+ "lora-dio0": "D2",
+ "lora-dio1": "D3",
+ "lora-dio2": "D4",
+ "lora-dio3": "D5",
+ "lora-dio4": "D8",
+ "lora-dio5": "D9",
+ "lora-rf-switch-ctl1": "NC",
+ "lora-rf-switch-ctl2": "NC",
+ "lora-txctl": "NC",
+ "lora-rxctl": "NC",
+ "lora-ant-switch": "A4",
+ "lora-pwr-amp-ctl": "NC",
+ "lora-tcxo": "NC"
+ }
+ },
+ "macros": ["MBEDTLS_USER_CONFIG_FILE=\"mbedtls_lora_config.h\""]
+
+}
+
diff -r 000000000000 -r f930f0440fd5 ttn-devices-to-c/devices.js
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ttn-devices-to-c/devices.js Wed Jun 26 10:35:50 2019 +0000
@@ -0,0 +1,37 @@
+/**
+ * > const ttn = require('ttn')
+ * > var app; ttn.application('YOUR_APP', 'YOUR_KEY').then(a=>app=a)
+ * > var d; app.devices().then(de=>d=de)
+ * > d
+ */
+
+var devices =[
+ { appId: '12345678909876543',
+ devId: 'hc_sr04_2',
+ latitude: 0.3956° S,
+ longitude: 36.9622° E,
+ altitude: 7723,
+ description: 'water level system',
+ fCntUp: 0,
+ fCntDown: 0,
+ disableFCntCheck: true,
+ uses32BitFCnt: true,
+ activationConstraints: 'local',
+ usedDevNoncesList: [],
+ usedAppNoncesList: [],
+ lastSeen: 0,
+ appEui: '70B3D57ED0010386',
+ devEui: '00D76350D629D861',
+ appKey: '00000000000000000000000000000000',
+ appSKey: '8833967FB940B18EDD461ADE38905F2A',
+ nwkSKey: '7B2C6805B56D7B055FA31CF21F0326D2',
+ devAddr: '26011EE8',
+ attributes: {} }]
+
+
+console.log(devices.map((d) => {
+ var id = d.devId.match(/(\d+)/)[0];
+ return `static uint32_t DEVADDR_${id} = 0x${d.devAddr};
+static uint8_t NWKSKEY_${id}[] = { ${d.nwkSKey.split(/(..)/).filter(f=>!!f).map(f=>'0x'+f).join(', ')} };
+static uint8_t APPSKEY_${id}[] = { ${d.appSKey.split(/(..)/).filter(f=>!!f).map(f=>'0x'+f).join(', ')} };`
+ }).join('\n\n'));