valeria toffoli / Mbed OS COG4050_adxrs290_adxrs453

driver for gyro

Dependencies:   COG4050_ADT7420

Fork of COG4050_adxl355_adxl357-ver2 by ADI_CAC

ADXRS290/ADXRS290.h@6:45d2393ef468, 2018-08-14 (annotated)

Committer:
vtoffoli
Date:
Tue Aug 14 06:49:07 2018 +0000
Revision:
6:45d2393ef468
Parent:
4:23b53636b576
Child:
9:1afd906c5ed2
update 14.08.2018

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vtoffoli 6:45d2393ef468 1
vtoffoli 6:45d2393ef468 2 #ifndef ADXRS290_H_
vtoffoli 6:45d2393ef468 3 #define ADXRS290_H_
vtoffoli 6:45d2393ef468 4
vtoffoli 6:45d2393ef468 5 class ADXRS290
vtoffoli 6:45d2393ef468 6 {
vtoffoli 6:45d2393ef468 7 public:
vtoffoli 6:45d2393ef468 8 float gyro_sens;
vtoffoli 6:45d2393ef468 9 float t_sens;
vtoffoli 6:45d2393ef468 10 // -------------------------- //
vtoffoli 6:45d2393ef468 11 // REGISTERS //
vtoffoli 6:45d2393ef468 12 // -------------------------- //
vtoffoli 6:45d2393ef468 13 typedef enum {
vtoffoli 6:45d2393ef468 14 DEVID_AD = 0x00,
vtoffoli 6:45d2393ef468 15 DEVID_MST = 0x01,
vtoffoli 6:45d2393ef468 16 PARTID = 0x02,
vtoffoli 6:45d2393ef468 17 REVID = 0x03,
vtoffoli 6:45d2393ef468 18 SN0 = 0x04,
vtoffoli 6:45d2393ef468 19 SN1 = 0x05,
vtoffoli 6:45d2393ef468 20 SN2 = 0x06,
vtoffoli 6:45d2393ef468 21 SN3 = 0x07,
vtoffoli 6:45d2393ef468 22 DATAX0 = 0x08,
vtoffoli 6:45d2393ef468 23 DATAX1 = 0x09,
vtoffoli 6:45d2393ef468 24 DATAY0 = 0x0A,
vtoffoli 6:45d2393ef468 25 DATAY1 = 0x0B,
vtoffoli 6:45d2393ef468 26 TEMP0 = 0x0C,
vtoffoli 6:45d2393ef468 27 TEMP1 = 0x0D,
vtoffoli 6:45d2393ef468 28 POWER_CTL = 0x10,
vtoffoli 6:45d2393ef468 29 FILTER = 0x11,
vtoffoli 6:45d2393ef468 30 DATA_READY = 0x12
vtoffoli 6:45d2393ef468 31 } ADXRS290_register_t;
vtoffoli 6:45d2393ef468 32 // -------------------------- //
vtoffoli 6:45d2393ef468 33 // REGISTERS - DEFAULT VALUES //
vtoffoli 6:45d2393ef468 34 // -------------------------- //
vtoffoli 6:45d2393ef468 35 // Modes - POWER_CTL
vtoffoli 6:45d2393ef468 36 typedef enum {
vtoffoli 6:45d2393ef468 37 TEMP_ON = 0x00,
vtoffoli 6:45d2393ef468 38 TEMP_OFF = 0x01,
vtoffoli 6:45d2393ef468 39 STANDBY = 0x00,
vtoffoli 6:45d2393ef468 40 MEASUREMENT = 0x02
vtoffoli 6:45d2393ef468 41 } ADXL355_modes_t;
vtoffoli 6:45d2393ef468 42 // High-Pass and Low-Pass Filter - FILTER
vtoffoli 6:45d2393ef468 43 typedef enum {
vtoffoli 6:45d2393ef468 44 LPF480 = 0x00,
vtoffoli 6:45d2393ef468 45 LPF320 = 0x01,
vtoffoli 6:45d2393ef468 46 LPF160 = 0x02,
vtoffoli 6:45d2393ef468 47 LPF80 = 0x03,
vtoffoli 6:45d2393ef468 48 LPF56 = 0x04,
vtoffoli 6:45d2393ef468 49 LPF40 = 0x05,
vtoffoli 6:45d2393ef468 50 LPF28 = 0x06,
vtoffoli 6:45d2393ef468 51 LPF20 = 0x07,
vtoffoli 6:45d2393ef468 52 HPFOFF = 0x00,
vtoffoli 6:45d2393ef468 53 HPF001 = 0x10,
vtoffoli 6:45d2393ef468 54 HPF002 = 0x20,
vtoffoli 6:45d2393ef468 55 HPF004 = 0x30,
vtoffoli 6:45d2393ef468 56 HPF008 = 0x40,
vtoffoli 6:45d2393ef468 57 HPF017 = 0x50,
vtoffoli 6:45d2393ef468 58 HPF035 = 0x60,
vtoffoli 6:45d2393ef468 59 HPF070 = 0x70,
vtoffoli 6:45d2393ef468 60 HPF140 = 0x80,
vtoffoli 6:45d2393ef468 61 HPF280 = 0x90,
vtoffoli 6:45d2393ef468 62 HPF1130 = 0xA0
vtoffoli 6:45d2393ef468 63 } ADXRS290_filter_ctl_t;
vtoffoli 6:45d2393ef468 64 // External timing register - INT_MAP
vtoffoli 6:45d2393ef468 65 typedef enum {
vtoffoli 6:45d2393ef468 66 OVR_EN = 0x04,
vtoffoli 6:45d2393ef468 67 FULL_EN = 0x02,
vtoffoli 6:45d2393ef468 68 RDY_EN = 0x01
vtoffoli 6:45d2393ef468 69 } ADXRS290_intmap_ctl_t;
vtoffoli 6:45d2393ef468 70 // External timing register - SYNC
vtoffoli 6:45d2393ef468 71 typedef enum {
vtoffoli 6:45d2393ef468 72 ANAL_SYNC = 0x00,
vtoffoli 6:45d2393ef468 73 DIGI_SYNC = 0x01
vtoffoli 6:45d2393ef468 74 } ADXRS290_dataready_ctl_t;
vtoffoli 6:45d2393ef468 75
vtoffoli 6:45d2393ef468 76 // -------------------------- //
vtoffoli 6:45d2393ef468 77 // FUNCTIONS //
vtoffoli 6:45d2393ef468 78 // -------------------------- //
vtoffoli 6:45d2393ef468 79 // SPI configuration & constructor
vtoffoli 6:45d2393ef468 80 ADXRS290(PinName cs_pin , PinName MOSI , PinName MISO , PinName SCK );
vtoffoli 6:45d2393ef468 81 void frequency(int hz);
vtoffoli 6:45d2393ef468 82 // SPI configuration & constructor
vtoffoli 6:45d2393ef468 83 void write_reg(ADXRS290_register_t reg, uint8_t data);
vtoffoli 6:45d2393ef468 84 uint8_t read_reg(ADXRS290_register_t reg);
vtoffoli 6:45d2393ef468 85 uint16_t read_reg_u16(ADXRS290_register_t reg);
vtoffoli 6:45d2393ef468 86 // ADXRS general register R/W methods
vtoffoli 6:45d2393ef468 87 void set_power_ctl_reg(uint8_t data);
vtoffoli 6:45d2393ef468 88 void set_filter_ctl_reg(ADXRS290_filter_ctl_t hpf, ADXRS290_filter_ctl_t odr);
vtoffoli 6:45d2393ef468 89 void set_sync(ADXRS290_dataready_ctl_t data);
vtoffoli 6:45d2393ef468 90 // ADXRS X/Y/T scanning methods
vtoffoli 6:45d2393ef468 91 uint16_t scanx();
vtoffoli 6:45d2393ef468 92 uint16_t scany();
vtoffoli 6:45d2393ef468 93 uint16_t scant();
vtoffoli 6:45d2393ef468 94 // ADXRS tilt methods and calibration
vtoffoli 6:45d2393ef468 95 // TBD
vtoffoli 6:45d2393ef468 96 private:
vtoffoli 6:45d2393ef468 97 // SPI adxl355; ///< SPI instance of the ADXL
vtoffoli 6:45d2393ef468 98 SPI adxrs290; DigitalOut cs;
vtoffoli 6:45d2393ef468 99 const static uint8_t _DEVICE_AD = 0x92; // contect of DEVID_AD (only-read) register
vtoffoli 6:45d2393ef468 100 const static uint8_t _DUMMY_BYTE = 0xAA; // 10101010
vtoffoli 6:45d2393ef468 101 const static uint8_t _WRITE_REG_CMD = 0x00; // write register
vtoffoli 6:45d2393ef468 102 const static uint8_t _READ_REG_CMD = 0x80; // read register
vtoffoli 6:45d2393ef468 103 const static uint8_t _SPI_MODE = 4; // timing scheme
vtoffoli 6:45d2393ef468 104 };
vtoffoli 6:45d2393ef468 105
vtoffoli 6:45d2393ef468 106 #endif