MQTTGatewayK64 - Fork of my MQTTGateway

Users » vpcola » Code » MQTTGatewayK64

Fork of my MQTTGateway

easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:: vpcola
Date:: Sat Apr 08 14:45:51 2017 +0000
Revision:: 0:f1d3878b8dd9

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
vpcola	0:f1d3878b8dd9	1	/**
vpcola	0:f1d3878b8dd9	2	******************************************************************************
vpcola	0:f1d3878b8dd9	3	* @file SPIRIT_Regs.h
vpcola	0:f1d3878b8dd9	4	* @author VMA division - AMS
vpcola	0:f1d3878b8dd9	5	* @version 3.2.2
vpcola	0:f1d3878b8dd9	6	* @date 08-July-2015
vpcola	0:f1d3878b8dd9	7	* @brief This file contains all the SPIRIT registers address and masks.
vpcola	0:f1d3878b8dd9	8	* @details
vpcola	0:f1d3878b8dd9	9	*
vpcola	0:f1d3878b8dd9	10	* @attention
vpcola	0:f1d3878b8dd9	11	*
vpcola	0:f1d3878b8dd9	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
vpcola	0:f1d3878b8dd9	13	*
vpcola	0:f1d3878b8dd9	14	* Redistribution and use in source and binary forms, with or without modification,
vpcola	0:f1d3878b8dd9	15	* are permitted provided that the following conditions are met:
vpcola	0:f1d3878b8dd9	16	* 1. Redistributions of source code must retain the above copyright notice,
vpcola	0:f1d3878b8dd9	17	* this list of conditions and the following disclaimer.
vpcola	0:f1d3878b8dd9	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
vpcola	0:f1d3878b8dd9	19	* this list of conditions and the following disclaimer in the documentation
vpcola	0:f1d3878b8dd9	20	* and/or other materials provided with the distribution.
vpcola	0:f1d3878b8dd9	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vpcola	0:f1d3878b8dd9	22	* may be used to endorse or promote products derived from this software
vpcola	0:f1d3878b8dd9	23	* without specific prior written permission.
vpcola	0:f1d3878b8dd9	24	*
vpcola	0:f1d3878b8dd9	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vpcola	0:f1d3878b8dd9	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vpcola	0:f1d3878b8dd9	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola	0:f1d3878b8dd9	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vpcola	0:f1d3878b8dd9	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vpcola	0:f1d3878b8dd9	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vpcola	0:f1d3878b8dd9	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vpcola	0:f1d3878b8dd9	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vpcola	0:f1d3878b8dd9	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vpcola	0:f1d3878b8dd9	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola	0:f1d3878b8dd9	35	*
vpcola	0:f1d3878b8dd9	36	******************************************************************************
vpcola	0:f1d3878b8dd9	37	*/
vpcola	0:f1d3878b8dd9	38
vpcola	0:f1d3878b8dd9	39	/* Define to prevent recursive inclusion -------------------------------------*/
vpcola	0:f1d3878b8dd9	40	#ifndef __SPIRIT1_REGS_H
vpcola	0:f1d3878b8dd9	41	#define __SPIRIT1_REGS_H
vpcola	0:f1d3878b8dd9	42
vpcola	0:f1d3878b8dd9	43	#ifdef __cplusplus
vpcola	0:f1d3878b8dd9	44	extern "C" {
vpcola	0:f1d3878b8dd9	45	#endif
vpcola	0:f1d3878b8dd9	46
vpcola	0:f1d3878b8dd9	47	/**
vpcola	0:f1d3878b8dd9	48	* @addtogroup SPIRIT_Registers SPIRIT Registers
vpcola	0:f1d3878b8dd9	49	* @brief Header file containing all the SPIRIT registers address and masks.
vpcola	0:f1d3878b8dd9	50	* @details See the file <i>@ref SPIRIT_Regs.h</i> for more details.
vpcola	0:f1d3878b8dd9	51	* @{
vpcola	0:f1d3878b8dd9	52	*/
vpcola	0:f1d3878b8dd9	53
vpcola	0:f1d3878b8dd9	54	/** @defgroup General_Configuration_Registers
vpcola	0:f1d3878b8dd9	55	* @{
vpcola	0:f1d3878b8dd9	56	*/
vpcola	0:f1d3878b8dd9	57
vpcola	0:f1d3878b8dd9	58	/** @defgroup ANA_FUNC_CONF_1_Register
vpcola	0:f1d3878b8dd9	59	* @{
vpcola	0:f1d3878b8dd9	60	*/
vpcola	0:f1d3878b8dd9	61
vpcola	0:f1d3878b8dd9	62	/**
vpcola	0:f1d3878b8dd9	63	* \brief ANA_FUNC_CONF register 1
vpcola	0:f1d3878b8dd9	64	* \code
vpcola	0:f1d3878b8dd9	65	* Read Write
vpcola	0:f1d3878b8dd9	66	* Default value: 0x0C
vpcola	0:f1d3878b8dd9	67	* 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0).
vpcola	0:f1d3878b8dd9	68	* 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up:
vpcola	0:f1d3878b8dd9	69	* GM_CONF2 \| GM_CONF1 \| GM_CONF0 \| GM [mS]
vpcola	0:f1d3878b8dd9	70	* ------------------------------------------
vpcola	0:f1d3878b8dd9	71	* 0 \| 0 \| 0 \| 13.2
vpcola	0:f1d3878b8dd9	72	* 0 \| 0 \| 1 \| 18.2
vpcola	0:f1d3878b8dd9	73	* 0 \| 1 \| 0 \| 21.5
vpcola	0:f1d3878b8dd9	74	* 0 \| 1 \| 1 \| 25.6
vpcola	0:f1d3878b8dd9	75	* 1 \| 0 \| 0 \| 28.8
vpcola	0:f1d3878b8dd9	76	* 1 \| 0 \| 1 \| 33.9
vpcola	0:f1d3878b8dd9	77	* 1 \| 1 \| 0 \| 38.5
vpcola	0:f1d3878b8dd9	78	* 1 \| 1 \| 1 \| 43.0
vpcola	0:f1d3878b8dd9	79	* 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold:
vpcola	0:f1d3878b8dd9	80	* SET_BLD_LVL1 \| SET_BLD_LVL0 \| Threshold [V]
vpcola	0:f1d3878b8dd9	81	* ------------------------------------------
vpcola	0:f1d3878b8dd9	82	* 0 \| 0 \| 2.7
vpcola	0:f1d3878b8dd9	83	* 0 \| 1 \| 2.5
vpcola	0:f1d3878b8dd9	84	* 1 \| 0 \| 2.3
vpcola	0:f1d3878b8dd9	85	* 1 \| 1 \| 2.1
vpcola	0:f1d3878b8dd9	86	* \endcode
vpcola	0:f1d3878b8dd9	87	*/
vpcola	0:f1d3878b8dd9	88
vpcola	0:f1d3878b8dd9	89	#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /!< ANA_FUNC_CONF1 Address (R/W) /
vpcola	0:f1d3878b8dd9	90
vpcola	0:f1d3878b8dd9	91	#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /!< Mask for number of enabled pipes/
vpcola	0:f1d3878b8dd9	92
vpcola	0:f1d3878b8dd9	93	#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) /
vpcola	0:f1d3878b8dd9	94
vpcola	0:f1d3878b8dd9	95	#define GM_13_2 ((uint8_t)0x00) /!< Transconducatance Gm at start-up 13.2 mS /
vpcola	0:f1d3878b8dd9	96	#define GM_18_2 ((uint8_t)0x04) /!< Transconducatance Gm at start-up 18.2 mS /
vpcola	0:f1d3878b8dd9	97	#define GM_21_5 ((uint8_t)0x08) /!< Transconducatance Gm at start-up 21.5 mS /
vpcola	0:f1d3878b8dd9	98	#define GM_25_6 ((uint8_t)0x0C) /!< Transconducatance Gm at start-up 25.6 mS /
vpcola	0:f1d3878b8dd9	99	#define GM_28_8 ((uint8_t)0x10) /!< Transconducatance Gm at start-up 28.8 mS /
vpcola	0:f1d3878b8dd9	100	#define GM_33_9 ((uint8_t)0x14) /!< Transconducatance Gm at start-up 33.9 mS /
vpcola	0:f1d3878b8dd9	101	#define GM_38_5 ((uint8_t)0x18) /!< Transconducatance Gm at start-up 38.5 mS /
vpcola	0:f1d3878b8dd9	102	#define GM_43_0 ((uint8_t)0x1C) /!< Transconducatance Gm at start-up 43.0 mS /
vpcola	0:f1d3878b8dd9	103
vpcola	0:f1d3878b8dd9	104	#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) /
vpcola	0:f1d3878b8dd9	105
vpcola	0:f1d3878b8dd9	106	#define BLD_LVL_2_7 ((uint8_t)0x00) /!< Sets the Battery Level Detector threshold to 2.7V /
vpcola	0:f1d3878b8dd9	107	#define BLD_LVL_2_5 ((uint8_t)0x01) /!< Sets the Battery Level Detector threshold to 2.5V /
vpcola	0:f1d3878b8dd9	108	#define BLD_LVL_2_3 ((uint8_t)0x02) /!< Sets the Battery Level Detector threshold to 2.3V /
vpcola	0:f1d3878b8dd9	109	#define BLD_LVL_2_1 ((uint8_t)0x03) /!< Sets the Battery Level Detector threshold to 2.1V /
vpcola	0:f1d3878b8dd9	110
vpcola	0:f1d3878b8dd9	111	/**
vpcola	0:f1d3878b8dd9	112	* @}
vpcola	0:f1d3878b8dd9	113	*/
vpcola	0:f1d3878b8dd9	114
vpcola	0:f1d3878b8dd9	115
vpcola	0:f1d3878b8dd9	116	/** @defgroup ANA_FUNC_CONF_0_Register
vpcola	0:f1d3878b8dd9	117	* @{
vpcola	0:f1d3878b8dd9	118	*/
vpcola	0:f1d3878b8dd9	119
vpcola	0:f1d3878b8dd9	120	/**
vpcola	0:f1d3878b8dd9	121	* \brief ANA_FUNC_CONF register 0
vpcola	0:f1d3878b8dd9	122	* \code
vpcola	0:f1d3878b8dd9	123	* Read Write
vpcola	0:f1d3878b8dd9	124	* Default value: 0xC0
vpcola	0:f1d3878b8dd9	125	* 7 Reserved.
vpcola	0:f1d3878b8dd9	126	* 6 24_26_MHz_SELECT: 1 - 26 MHz configuration
vpcola	0:f1d3878b8dd9	127	* 0 - 24 MHz configuration
vpcola	0:f1d3878b8dd9	128	* 5 AES_ON: 1 - AES engine enabled
vpcola	0:f1d3878b8dd9	129	* 0 - AES engine disabled
vpcola	0:f1d3878b8dd9	130	* 4 EXT_REF: 1 - Reference signal from XIN pin
vpcola	0:f1d3878b8dd9	131	* 0 - Reference signal from XO circuit
vpcola	0:f1d3878b8dd9	132	* 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to
vpcola	0:f1d3878b8dd9	133	* PM_TEST register in RX state, while in TX state it
vpcola	0:f1d3878b8dd9	134	* will be fixed to 111 (which programs the SMPS output
vpcola	0:f1d3878b8dd9	135	* at max value 1.8V)
vpcola	0:f1d3878b8dd9	136	* 0 - SET_SMPS_LEVEL word will hold the value written in the
vpcola	0:f1d3878b8dd9	137	* PM_TEST register both in RX and TX state
vpcola	0:f1d3878b8dd9	138	* 2 BROWN_OUT: 1 - Brown_Out Detection enabled
vpcola	0:f1d3878b8dd9	139	* 0 - Brown_Out Detection disabled
vpcola	0:f1d3878b8dd9	140	* 1 BATTERY_LEVEL: 1 - Battery level detector enabled
vpcola	0:f1d3878b8dd9	141	* 0 - Battery level detector disabled
vpcola	0:f1d3878b8dd9	142	* 0 TS: 1 - Enable the "Temperature Sensor" function
vpcola	0:f1d3878b8dd9	143	* 0 - Disable the "Temperature Sensor" function
vpcola	0:f1d3878b8dd9	144	* \endcode
vpcola	0:f1d3878b8dd9	145	*/
vpcola	0:f1d3878b8dd9	146
vpcola	0:f1d3878b8dd9	147
vpcola	0:f1d3878b8dd9	148	#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /!< ANA_FUNC_CONF0 Address (R/W) /
vpcola	0:f1d3878b8dd9	149
vpcola	0:f1d3878b8dd9	150	#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal /
vpcola	0:f1d3878b8dd9	151	#define AES_MASK ((uint8_t)0x20) /!< AES engine on/off /
vpcola	0:f1d3878b8dd9	152	#define EXT_REF_MASK ((uint8_t)0x10) /!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)/
vpcola	0:f1d3878b8dd9	153	#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register
vpcola	0:f1d3878b8dd9	154	in RX state, while in TX state it will be fixed to 111
vpcola	0:f1d3878b8dd9	155	(which programs the SMPS output at max value, 1.8V) */
vpcola	0:f1d3878b8dd9	156	#define BROWN_OUT_MASK ((uint8_t)0x04) /!< Accurate Brown-Out detection on/off /
vpcola	0:f1d3878b8dd9	157	#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /!< Battery level detector circuit on/off /
vpcola	0:f1d3878b8dd9	158	#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /!< The Temperature Sensor (available on GPIO0) on/off /
vpcola	0:f1d3878b8dd9	159
vpcola	0:f1d3878b8dd9	160	/**
vpcola	0:f1d3878b8dd9	161	* @}
vpcola	0:f1d3878b8dd9	162	*/
vpcola	0:f1d3878b8dd9	163
vpcola	0:f1d3878b8dd9	164	/** @defgroup ANT_SELECT_CONF_Register
vpcola	0:f1d3878b8dd9	165	* @{
vpcola	0:f1d3878b8dd9	166	*/
vpcola	0:f1d3878b8dd9	167
vpcola	0:f1d3878b8dd9	168	/**
vpcola	0:f1d3878b8dd9	169	* \brief ANT_SELECT_CONF register
vpcola	0:f1d3878b8dd9	170	* \code
vpcola	0:f1d3878b8dd9	171	* Read Write
vpcola	0:f1d3878b8dd9	172	* Default value: 0x05
vpcola	0:f1d3878b8dd9	173	*
vpcola	0:f1d3878b8dd9	174	* 7:5 Reserved.
vpcola	0:f1d3878b8dd9	175	*
vpcola	0:f1d3878b8dd9	176	* 4 CS_BLANKING: Blank received data if signal is below the CS threshold
vpcola	0:f1d3878b8dd9	177	*
vpcola	0:f1d3878b8dd9	178	* 3 AS_ENABLE: Enable antenna switching
vpcola	0:f1d3878b8dd9	179	* 1 - Enable
vpcola	0:f1d3878b8dd9	180	* 0 - Disable
vpcola	0:f1d3878b8dd9	181	*
vpcola	0:f1d3878b8dd9	182	* 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 242^(EchFlt)2^AS_MEAS_TIME/fxo
vpcola	0:f1d3878b8dd9	183	* \endcode
vpcola	0:f1d3878b8dd9	184	*/
vpcola	0:f1d3878b8dd9	185	#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /!< Antenna diversity (works only in static carrier sense mode) /
vpcola	0:f1d3878b8dd9	186	#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /!< CS data blanking on/off /
vpcola	0:f1d3878b8dd9	187	#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /!< Antenna diversity on/off /
vpcola	0:f1d3878b8dd9	188
vpcola	0:f1d3878b8dd9	189	/**
vpcola	0:f1d3878b8dd9	190	* @}
vpcola	0:f1d3878b8dd9	191	*/
vpcola	0:f1d3878b8dd9	192
vpcola	0:f1d3878b8dd9	193	/** @defgroup DEVICE_INFO1_Register
vpcola	0:f1d3878b8dd9	194	* @{
vpcola	0:f1d3878b8dd9	195	*/
vpcola	0:f1d3878b8dd9	196
vpcola	0:f1d3878b8dd9	197	/**
vpcola	0:f1d3878b8dd9	198	* \brief DEVICE_INFO1[7:0] registers
vpcola	0:f1d3878b8dd9	199	* \code
vpcola	0:f1d3878b8dd9	200	* Default value: 0x01
vpcola	0:f1d3878b8dd9	201	* Read
vpcola	0:f1d3878b8dd9	202	*
vpcola	0:f1d3878b8dd9	203	* 7:0 PARTNUM[7:0]: Device part number
vpcola	0:f1d3878b8dd9	204	* \endcode
vpcola	0:f1d3878b8dd9	205	*/
vpcola	0:f1d3878b8dd9	206	#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /!< Device part number [7:0] /
vpcola	0:f1d3878b8dd9	207
vpcola	0:f1d3878b8dd9	208	/**
vpcola	0:f1d3878b8dd9	209	* @}
vpcola	0:f1d3878b8dd9	210	*/
vpcola	0:f1d3878b8dd9	211
vpcola	0:f1d3878b8dd9	212	/** @defgroup DEVICE_INFO0_Register
vpcola	0:f1d3878b8dd9	213	* @{
vpcola	0:f1d3878b8dd9	214	*/
vpcola	0:f1d3878b8dd9	215
vpcola	0:f1d3878b8dd9	216	/**
vpcola	0:f1d3878b8dd9	217	* \brief DEVICE_INFO0[7:0] registers
vpcola	0:f1d3878b8dd9	218	* \code
vpcola	0:f1d3878b8dd9	219	* Read
vpcola	0:f1d3878b8dd9	220	*
vpcola	0:f1d3878b8dd9	221	* 7:0 VERSION[7:0]: Device version number
vpcola	0:f1d3878b8dd9	222	* \endcode
vpcola	0:f1d3878b8dd9	223	*/
vpcola	0:f1d3878b8dd9	224	#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /!< Device version [7:0]; (0x55 in CUT1.0) /
vpcola	0:f1d3878b8dd9	225
vpcola	0:f1d3878b8dd9	226	/**
vpcola	0:f1d3878b8dd9	227	* @}
vpcola	0:f1d3878b8dd9	228	*/
vpcola	0:f1d3878b8dd9	229
vpcola	0:f1d3878b8dd9	230
vpcola	0:f1d3878b8dd9	231	/**
vpcola	0:f1d3878b8dd9	232	* @}
vpcola	0:f1d3878b8dd9	233	*/
vpcola	0:f1d3878b8dd9	234
vpcola	0:f1d3878b8dd9	235
vpcola	0:f1d3878b8dd9	236	/** @defgroup GPIO_Registers
vpcola	0:f1d3878b8dd9	237	* @{
vpcola	0:f1d3878b8dd9	238	*/
vpcola	0:f1d3878b8dd9	239
vpcola	0:f1d3878b8dd9	240	/** @defgroup GPIOx_CONF_Registers
vpcola	0:f1d3878b8dd9	241	* @{
vpcola	0:f1d3878b8dd9	242	*/
vpcola	0:f1d3878b8dd9	243
vpcola	0:f1d3878b8dd9	244	/**
vpcola	0:f1d3878b8dd9	245	* \brief GPIOx registers
vpcola	0:f1d3878b8dd9	246	* \code
vpcola	0:f1d3878b8dd9	247	* Read Write
vpcola	0:f1d3878b8dd9	248	* Default value: 0x03
vpcola	0:f1d3878b8dd9	249	* 7:3 GPIO_SELECT[4:0]: Specify the I/O signal.
vpcola	0:f1d3878b8dd9	250	* GPIO_SELECT[4:0] \| I/O \| Signal
vpcola	0:f1d3878b8dd9	251	* ------------------------------------------------
vpcola	0:f1d3878b8dd9	252	* 0 \| Output \| nIRQ
vpcola	0:f1d3878b8dd9	253	* 0 \| Input \| TX command
vpcola	0:f1d3878b8dd9	254	* 1 \| Output \| POR inverted
vpcola	0:f1d3878b8dd9	255	* 1 \| Input \| RX command
vpcola	0:f1d3878b8dd9	256	* 2 \| Output \| Wake-Up timer expiration
vpcola	0:f1d3878b8dd9	257	* 2 \| Input \| TX data for direct modulation
vpcola	0:f1d3878b8dd9	258	* 3 \| Output \| Low Battery Detection
vpcola	0:f1d3878b8dd9	259	* 3 \| Input \| Wake-up from external input
vpcola	0:f1d3878b8dd9	260	* 4 \| Output \| TX clock output
vpcola	0:f1d3878b8dd9	261	* 5 \| Output \| TX state
vpcola	0:f1d3878b8dd9	262	* 6 \| Output \| TX FIFO Almost Empty Flag
vpcola	0:f1d3878b8dd9	263	* 7 \| Output \| TX FIFO ALmost Full Flag
vpcola	0:f1d3878b8dd9	264	* 8 \| Output \| RX data output
vpcola	0:f1d3878b8dd9	265	* 9 \| Output \| RX clock output
vpcola	0:f1d3878b8dd9	266	* 10 \| Output \| RX state
vpcola	0:f1d3878b8dd9	267	* 11 \| Output \| RX FIFO Almost Full Flag
vpcola	0:f1d3878b8dd9	268	* 12 \| Output \| RX FIFO Almost Empty Flag
vpcola	0:f1d3878b8dd9	269	* 13 \| Output \| Antenna switch
vpcola	0:f1d3878b8dd9	270	* 14 \| Output \| Valid preamble detected
vpcola	0:f1d3878b8dd9	271	* 15 \| Output \| Sync word detected
vpcola	0:f1d3878b8dd9	272	* 16 \| Output \| RSSI above threshold
vpcola	0:f1d3878b8dd9	273	* 17 \| Output \| MCU clock
vpcola	0:f1d3878b8dd9	274	* 18 \| Output \| TX or RX mode indicator
vpcola	0:f1d3878b8dd9	275	* 19 \| Output \| VDD
vpcola	0:f1d3878b8dd9	276	* 20 \| Output \| GND
vpcola	0:f1d3878b8dd9	277	* 21 \| Output \| External SMPS enable signal
vpcola	0:f1d3878b8dd9	278	* 22-31 \| Not Used \| Not Used
vpcola	0:f1d3878b8dd9	279	* 2 Reserved
vpcola	0:f1d3878b8dd9	280	* 1:0 GpioMode[1:0]: Specify the mode:
vpcola	0:f1d3878b8dd9	281	* GPIO_MODE1 \| GPIO_MODE0 \| MODE
vpcola	0:f1d3878b8dd9	282	* ------------------------------------------------------------
vpcola	0:f1d3878b8dd9	283	* 0 \| 0 \| Analog (valid only for GPIO_0)
vpcola	0:f1d3878b8dd9	284	* 0 \| 1 \| Digital Input
vpcola	0:f1d3878b8dd9	285	* 1 \| 0 \| Digital Output Low Power
vpcola	0:f1d3878b8dd9	286	* 1 \| 1 \| Digital Output High Power
vpcola	0:f1d3878b8dd9	287	*
vpcola	0:f1d3878b8dd9	288	* Note: The Analog mode is used only for temperature sensor indication. This is available only
vpcola	0:f1d3878b8dd9	289	* on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register.
vpcola	0:f1d3878b8dd9	290	* \endcode
vpcola	0:f1d3878b8dd9	291	*/
vpcola	0:f1d3878b8dd9	292
vpcola	0:f1d3878b8dd9	293
vpcola	0:f1d3878b8dd9	294	#define GPIO3_CONF_BASE ((uint8_t)0x02) /!< GPIO_3 register address /
vpcola	0:f1d3878b8dd9	295	#define GPIO2_CONF_BASE ((uint8_t)0x03) /!< GPIO_3 register address /
vpcola	0:f1d3878b8dd9	296	#define GPIO1_CONF_BASE ((uint8_t)0x04) /!< GPIO_3 register address /
vpcola	0:f1d3878b8dd9	297	#define GPIO0_CONF_BASE ((uint8_t)0x05) /!< GPIO_3 register address /
vpcola	0:f1d3878b8dd9	298
vpcola	0:f1d3878b8dd9	299	#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /!< TX command direct from PIN (rising edge, width min=50ns) /
vpcola	0:f1d3878b8dd9	300	#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /!< RX command direct from PIN (rising edge, width min=50ns)/
vpcola	0:f1d3878b8dd9	301	#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /!< TX data input for direct modulation /
vpcola	0:f1d3878b8dd9	302	#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /!< Wake up from external input /
vpcola	0:f1d3878b8dd9	303
vpcola	0:f1d3878b8dd9	304	#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /!< nIRQ (Interrupt Request, active low) , default configuration after POR /
vpcola	0:f1d3878b8dd9	305	#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /!< POR inverted (active low) /
vpcola	0:f1d3878b8dd9	306	#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /!< Wake-Up Timer expiration: 1 when WUT has expired /
vpcola	0:f1d3878b8dd9	307	#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /!< Low battery detection: 1 when battery is below threshold setting /
vpcola	0:f1d3878b8dd9	308	#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /!< TX data internal clock output (TX data are sampled on the rising edge of it) /
vpcola	0:f1d3878b8dd9	309	#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /!< TX state indication: 1 when Spirit1 is transiting in the TX state /
vpcola	0:f1d3878b8dd9	310	#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /!< TX FIFO Almost Empty Flag /
vpcola	0:f1d3878b8dd9	311	#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /!< TX FIFO Almost Full Flag /
vpcola	0:f1d3878b8dd9	312	#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /!< RX data output /
vpcola	0:f1d3878b8dd9	313	#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /!< RX clock output (recovered from received data) /
vpcola	0:f1d3878b8dd9	314	#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /!< RX state indication: 1 when Spirit1 is transiting in the RX state /
vpcola	0:f1d3878b8dd9	315	#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /!< RX FIFO Almost Full Flag /
vpcola	0:f1d3878b8dd9	316	#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /!< RX FIFO Almost Empty Flag /
vpcola	0:f1d3878b8dd9	317	#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /!< Antenna switch used for antenna diversity /
vpcola	0:f1d3878b8dd9	318	#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /!< Valid Preamble Detected Flag /
vpcola	0:f1d3878b8dd9	319	#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /!< Sync WordSync Word Detected Flag /
vpcola	0:f1d3878b8dd9	320	#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /!< CCA Assessment Flag /
vpcola	0:f1d3878b8dd9	321	#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /!< MCU Clock /
vpcola	0:f1d3878b8dd9	322	#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /!< TX or RX mode indicator (to enable an external range extender) /
vpcola	0:f1d3878b8dd9	323	#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) /
vpcola	0:f1d3878b8dd9	324	#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) /
vpcola	0:f1d3878b8dd9	325	#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /!< External SMPS enable signal (active high) /
vpcola	0:f1d3878b8dd9	326
vpcola	0:f1d3878b8dd9	327	#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) /
vpcola	0:f1d3878b8dd9	328	#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /!< Digital Input on GPIO /
vpcola	0:f1d3878b8dd9	329	#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /!< Digital Output on GPIO (low current) /
vpcola	0:f1d3878b8dd9	330	#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /!< Digital Output on GPIO (high current) /
vpcola	0:f1d3878b8dd9	331
vpcola	0:f1d3878b8dd9	332	/**
vpcola	0:f1d3878b8dd9	333	* @}
vpcola	0:f1d3878b8dd9	334	*/
vpcola	0:f1d3878b8dd9	335
vpcola	0:f1d3878b8dd9	336
vpcola	0:f1d3878b8dd9	337	/** @defgroup MCU_CK_CONF_Register
vpcola	0:f1d3878b8dd9	338	* @{
vpcola	0:f1d3878b8dd9	339	*/
vpcola	0:f1d3878b8dd9	340
vpcola	0:f1d3878b8dd9	341	/**
vpcola	0:f1d3878b8dd9	342	* \brief MCU_CK_CONF register
vpcola	0:f1d3878b8dd9	343	* \code
vpcola	0:f1d3878b8dd9	344	* Read Write
vpcola	0:f1d3878b8dd9	345	* Default value: 0x00
vpcola	0:f1d3878b8dd9	346	* 7 Reserved.
vpcola	0:f1d3878b8dd9	347	* 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state.
vpcola	0:f1d3878b8dd9	348	* CLOCK_TAIL1 \| CLOCK_TAIL0 \| Number of Extra Cycles
vpcola	0:f1d3878b8dd9	349	* ------------------------------------------------------------
vpcola	0:f1d3878b8dd9	350	* 0 \| 0 \| 0
vpcola	0:f1d3878b8dd9	351	* 0 \| 1 \| 64
vpcola	0:f1d3878b8dd9	352	* 1 \| 0 \| 256
vpcola	0:f1d3878b8dd9	353	* 1 \| 1 \| 512
vpcola	0:f1d3878b8dd9	354	* 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source
vpcola	0:f1d3878b8dd9	355	* XO_RATIO[3:0] \| Division Ratio
vpcola	0:f1d3878b8dd9	356	* -----------------------------------
vpcola	0:f1d3878b8dd9	357	* 0 \| 1
vpcola	0:f1d3878b8dd9	358	* 1 \| 2/3
vpcola	0:f1d3878b8dd9	359	* 2 \| 1/2
vpcola	0:f1d3878b8dd9	360	* 3 \| 1/3
vpcola	0:f1d3878b8dd9	361	* 4 \| 1/4
vpcola	0:f1d3878b8dd9	362	* 5 \| 1/6
vpcola	0:f1d3878b8dd9	363	* 6 \| 1/8
vpcola	0:f1d3878b8dd9	364	* 7 \| 1/12
vpcola	0:f1d3878b8dd9	365	* 8 \| 1/16
vpcola	0:f1d3878b8dd9	366	* 9 \| 1/24
vpcola	0:f1d3878b8dd9	367	* 10 \| 1/36
vpcola	0:f1d3878b8dd9	368	* 11 \| 1/48
vpcola	0:f1d3878b8dd9	369	* 12 \| 1/64
vpcola	0:f1d3878b8dd9	370	* 13 \| 1/96
vpcola	0:f1d3878b8dd9	371	* 14 \| 1/128
vpcola	0:f1d3878b8dd9	372	* 15 \| 1/256
vpcola	0:f1d3878b8dd9	373	* 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source
vpcola	0:f1d3878b8dd9	374	* 0 - Division Ratio equal to 0
vpcola	0:f1d3878b8dd9	375	* 1 - Division Ratio equal to 1/128
vpcola	0:f1d3878b8dd9	376	* \endcode
vpcola	0:f1d3878b8dd9	377	*/
vpcola	0:f1d3878b8dd9	378
vpcola	0:f1d3878b8dd9	379
vpcola	0:f1d3878b8dd9	380	#define MCU_CK_CONF_BASE ((uint8_t)0x06) /!< MCU Clock Config register address /
vpcola	0:f1d3878b8dd9	381
vpcola	0:f1d3878b8dd9	382	#define MCU_CK_ENABLE ((uint8_t)0x80) /!< MCU clock enable bit /
vpcola	0:f1d3878b8dd9	383
vpcola	0:f1d3878b8dd9	384	#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /!< 0 extra clock cycles provided to the MCU before switching to STANDBY state /
vpcola	0:f1d3878b8dd9	385	#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /!< 64 extra clock cycles provided to the MCU before switching to STANDBY state /
vpcola	0:f1d3878b8dd9	386	#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /!< 256 extra clock cycles provided to the MCU before switching to STANDBY state /
vpcola	0:f1d3878b8dd9	387	#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /!< 512 extra clock cycles provided to the MCU before switching to STANDBY state /
vpcola	0:f1d3878b8dd9	388	#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /!< XO Clock signal available on the GPIO divided by 1 /
vpcola	0:f1d3878b8dd9	389	#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /!< XO Clock signal available on the GPIO divided by 2/3 /
vpcola	0:f1d3878b8dd9	390	#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /!< XO Clock signal available on the GPIO divided by 1/2 /
vpcola	0:f1d3878b8dd9	391	#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /!< XO Clock signal available on the GPIO divided by 1/3 /
vpcola	0:f1d3878b8dd9	392	#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /!< XO Clock signal available on the GPIO divided by 1/4 /
vpcola	0:f1d3878b8dd9	393	#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /!< XO Clock signal available on the GPIO divided by 1/6 /
vpcola	0:f1d3878b8dd9	394	#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /!< XO Clock signal available on the GPIO divided by 1/8 /
vpcola	0:f1d3878b8dd9	395	#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /!< XO Clock signal available on the GPIO divided by 1/12 /
vpcola	0:f1d3878b8dd9	396	#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /!< XO Clock signal available on the GPIO divided by 1/16 /
vpcola	0:f1d3878b8dd9	397	#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /!< XO Clock signal available on the GPIO divided by 1/24 /
vpcola	0:f1d3878b8dd9	398	#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /!< XO Clock signal available on the GPIO divided by 1/36 /
vpcola	0:f1d3878b8dd9	399	#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /!< XO Clock signal available on the GPIO divided by 1/48 /
vpcola	0:f1d3878b8dd9	400	#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /!< XO Clock signal available on the GPIO divided by 1/64 /
vpcola	0:f1d3878b8dd9	401	#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /!< XO Clock signal available on the GPIO divided by 1/96 /
vpcola	0:f1d3878b8dd9	402	#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /!< XO Clock signal available on the GPIO divided by 1/128 /
vpcola	0:f1d3878b8dd9	403	#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /!< XO Clock signal available on the GPIO divided by 1/196 /
vpcola	0:f1d3878b8dd9	404	#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /!< RCO Clock signal available on the GPIO divided by 1 /
vpcola	0:f1d3878b8dd9	405	#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /!< RCO Clock signal available on the GPIO divided by 1/128/
vpcola	0:f1d3878b8dd9	406
vpcola	0:f1d3878b8dd9	407	/**
vpcola	0:f1d3878b8dd9	408	* @}
vpcola	0:f1d3878b8dd9	409	*/
vpcola	0:f1d3878b8dd9	410
vpcola	0:f1d3878b8dd9	411	/**
vpcola	0:f1d3878b8dd9	412	* @}
vpcola	0:f1d3878b8dd9	413	*/
vpcola	0:f1d3878b8dd9	414
vpcola	0:f1d3878b8dd9	415
vpcola	0:f1d3878b8dd9	416	/** @defgroup Radio_Configuration_Registers
vpcola	0:f1d3878b8dd9	417	* @{
vpcola	0:f1d3878b8dd9	418	*/
vpcola	0:f1d3878b8dd9	419
vpcola	0:f1d3878b8dd9	420
vpcola	0:f1d3878b8dd9	421
vpcola	0:f1d3878b8dd9	422	/** @defgroup SYNT3_Register
vpcola	0:f1d3878b8dd9	423	* @{
vpcola	0:f1d3878b8dd9	424	*/
vpcola	0:f1d3878b8dd9	425
vpcola	0:f1d3878b8dd9	426	/**
vpcola	0:f1d3878b8dd9	427	* \brief SYNT3 register
vpcola	0:f1d3878b8dd9	428	* \code
vpcola	0:f1d3878b8dd9	429	* Read Write
vpcola	0:f1d3878b8dd9	430	* Default value: 0x0C
vpcola	0:f1d3878b8dd9	431	*
vpcola	0:f1d3878b8dd9	432	* 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode.
vpcola	0:f1d3878b8dd9	433	*
vpcola	0:f1d3878b8dd9	434	* VCO Frequency \| WCP2 \| WCP1 \| WCP0 \| Charge Pump Current (uA)
vpcola	0:f1d3878b8dd9	435	* ------------------------------------------------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	436	* 4644-4678 \| 0 \| 0 \| 0 \| 378.4
vpcola	0:f1d3878b8dd9	437	* 4708-4772 \| 0 \| 0 \| 1 \| 368.9
vpcola	0:f1d3878b8dd9	438	* 4772-4836 \| 0 \| 1 \| 0 \| 359.5
vpcola	0:f1d3878b8dd9	439	* 4836-4902 \| 0 \| 1 \| 1 \| 350
vpcola	0:f1d3878b8dd9	440	* 4902-4966 \| 1 \| 0 \| 0 \| 340.5
vpcola	0:f1d3878b8dd9	441	* 4966-5030 \| 1 \| 0 \| 1 \| 331.1
vpcola	0:f1d3878b8dd9	442	* 5030-5095 \| 1 \| 1 \| 0 \| 321.6
vpcola	0:f1d3878b8dd9	443	* 5095-5161 \| 1 \| 1 \| 1 \| 312.2
vpcola	0:f1d3878b8dd9	444	* 5161-5232 \| 0 \| 0 \| 0 \| 378.4
vpcola	0:f1d3878b8dd9	445	* 5232-5303 \| 0 \| 0 \| 1 \| 368.9
vpcola	0:f1d3878b8dd9	446	* 5303-5375 \| 0 \| 1 \| 0 \| 359.5
vpcola	0:f1d3878b8dd9	447	* 5375-5448 \| 0 \| 1 \| 1 \| 350
vpcola	0:f1d3878b8dd9	448	* 5448-5519 \| 1 \| 0 \| 0 \| 340.5
vpcola	0:f1d3878b8dd9	449	* 5519-5592 \| 1 \| 0 \| 1 \| 331.1
vpcola	0:f1d3878b8dd9	450	* 5592-5663 \| 1 \| 1 \| 0 \| 321.6
vpcola	0:f1d3878b8dd9	451	* 5663-5736 \| 1 \| 1 \| 1 \| 312.2
vpcola	0:f1d3878b8dd9	452	*
vpcola	0:f1d3878b8dd9	453	*
vpcola	0:f1d3878b8dd9	454	* 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider
vpcola	0:f1d3878b8dd9	455	* The valid range depends on fXO and REFDIV settings; for
vpcola	0:f1d3878b8dd9	456	* fXO=26MHz
vpcola	0:f1d3878b8dd9	457	* REFDIV = 0 - SYNT[25:21] = 11...13
vpcola	0:f1d3878b8dd9	458	* REFDIV = 1 - SYNT[25:21] = 2227
vpcola	0:f1d3878b8dd9	459	*
vpcola	0:f1d3878b8dd9	460	*
vpcola	0:f1d3878b8dd9	461	* \endcode
vpcola	0:f1d3878b8dd9	462	*/
vpcola	0:f1d3878b8dd9	463	#define SYNT3_BASE ((uint8_t)0x08) /!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider /
vpcola	0:f1d3878b8dd9	464
vpcola	0:f1d3878b8dd9	465	#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] /
vpcola	0:f1d3878b8dd9	466	#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] /
vpcola	0:f1d3878b8dd9	467	#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] /
vpcola	0:f1d3878b8dd9	468	#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] /
vpcola	0:f1d3878b8dd9	469	#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] /
vpcola	0:f1d3878b8dd9	470	#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] /
vpcola	0:f1d3878b8dd9	471	#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] /
vpcola	0:f1d3878b8dd9	472	#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] /
vpcola	0:f1d3878b8dd9	473
vpcola	0:f1d3878b8dd9	474
vpcola	0:f1d3878b8dd9	475	/**
vpcola	0:f1d3878b8dd9	476	* @}
vpcola	0:f1d3878b8dd9	477	*/
vpcola	0:f1d3878b8dd9	478
vpcola	0:f1d3878b8dd9	479
vpcola	0:f1d3878b8dd9	480	/** @defgroup SYNT2_Register
vpcola	0:f1d3878b8dd9	481	* @{
vpcola	0:f1d3878b8dd9	482	*/
vpcola	0:f1d3878b8dd9	483
vpcola	0:f1d3878b8dd9	484	/**
vpcola	0:f1d3878b8dd9	485	* \brief SYNT2 register
vpcola	0:f1d3878b8dd9	486	* \code
vpcola	0:f1d3878b8dd9	487	* Read Write
vpcola	0:f1d3878b8dd9	488	* Default value: 0x84
vpcola	0:f1d3878b8dd9	489	* 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider.
vpcola	0:f1d3878b8dd9	490	*
vpcola	0:f1d3878b8dd9	491	* \endcode
vpcola	0:f1d3878b8dd9	492	*/
vpcola	0:f1d3878b8dd9	493
vpcola	0:f1d3878b8dd9	494	#define SYNT2_BASE ((uint8_t)0x09) /!< SYNT[20:13], intermediate bits of the PLL programmable divider /
vpcola	0:f1d3878b8dd9	495
vpcola	0:f1d3878b8dd9	496	/**
vpcola	0:f1d3878b8dd9	497	* @}
vpcola	0:f1d3878b8dd9	498	*/
vpcola	0:f1d3878b8dd9	499
vpcola	0:f1d3878b8dd9	500	/** @defgroup SYNT1_Register
vpcola	0:f1d3878b8dd9	501	* @{
vpcola	0:f1d3878b8dd9	502	*/
vpcola	0:f1d3878b8dd9	503
vpcola	0:f1d3878b8dd9	504	/**
vpcola	0:f1d3878b8dd9	505	* \brief SYNT1 register
vpcola	0:f1d3878b8dd9	506	* \code
vpcola	0:f1d3878b8dd9	507	* Read Write
vpcola	0:f1d3878b8dd9	508	* Default value: 0xEC
vpcola	0:f1d3878b8dd9	509	* 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider.
vpcola	0:f1d3878b8dd9	510	*
vpcola	0:f1d3878b8dd9	511	* \endcode
vpcola	0:f1d3878b8dd9	512	*/
vpcola	0:f1d3878b8dd9	513
vpcola	0:f1d3878b8dd9	514	#define SYNT1_BASE ((uint8_t)0x0A) /!< SYNT[12:5], intermediate bits of the PLL programmable divider /
vpcola	0:f1d3878b8dd9	515
vpcola	0:f1d3878b8dd9	516	/**
vpcola	0:f1d3878b8dd9	517	* @}
vpcola	0:f1d3878b8dd9	518	*/
vpcola	0:f1d3878b8dd9	519
vpcola	0:f1d3878b8dd9	520	/** @defgroup SYNT0_Register
vpcola	0:f1d3878b8dd9	521	* @{
vpcola	0:f1d3878b8dd9	522	*/
vpcola	0:f1d3878b8dd9	523
vpcola	0:f1d3878b8dd9	524	/**
vpcola	0:f1d3878b8dd9	525	* \brief SYNT0 register
vpcola	0:f1d3878b8dd9	526	* \code
vpcola	0:f1d3878b8dd9	527	* Read Write
vpcola	0:f1d3878b8dd9	528	* Default value: 0x51
vpcola	0:f1d3878b8dd9	529	* 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider.
vpcola	0:f1d3878b8dd9	530	* 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer
vpcola	0:f1d3878b8dd9	531	* according to the formula fxo/(B/2)/D*SYNT/2^18
vpcola	0:f1d3878b8dd9	532	*
vpcola	0:f1d3878b8dd9	533	* BS2 \| BS1 \| BS0 \| value of B
vpcola	0:f1d3878b8dd9	534	* ---------------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	535	* 0 \| 0 \| 1 \| 6
vpcola	0:f1d3878b8dd9	536	* 0 \| 1 \| 0 \| 8
vpcola	0:f1d3878b8dd9	537	* 0 \| 1 \| 1 \| 12
vpcola	0:f1d3878b8dd9	538	* 1 \| 0 \| 0 \| 16
vpcola	0:f1d3878b8dd9	539	* 1 \| 0 \| 1 \| 32
vpcola	0:f1d3878b8dd9	540	*
vpcola	0:f1d3878b8dd9	541	* \endcode
vpcola	0:f1d3878b8dd9	542	*/
vpcola	0:f1d3878b8dd9	543	#define SYNT0_BASE ((uint8_t)0x0B) /!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider /
vpcola	0:f1d3878b8dd9	544
vpcola	0:f1d3878b8dd9	545	#define SYNT0_BS_6 ((uint8_t)0x01) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) /
vpcola	0:f1d3878b8dd9	546	#define SYNT0_BS_8 ((uint8_t)0x02) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)/
vpcola	0:f1d3878b8dd9	547	#define SYNT0_BS_12 ((uint8_t)0x03) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)/
vpcola	0:f1d3878b8dd9	548	#define SYNT0_BS_16 ((uint8_t)0x04) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)/
vpcola	0:f1d3878b8dd9	549	#define SYNT0_BS_32 ((uint8_t)0x05) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)/
vpcola	0:f1d3878b8dd9	550
vpcola	0:f1d3878b8dd9	551	/**
vpcola	0:f1d3878b8dd9	552	* @}
vpcola	0:f1d3878b8dd9	553	*/
vpcola	0:f1d3878b8dd9	554
vpcola	0:f1d3878b8dd9	555	/** @defgroup CHSPACE_Register
vpcola	0:f1d3878b8dd9	556	* @{
vpcola	0:f1d3878b8dd9	557	*/
vpcola	0:f1d3878b8dd9	558
vpcola	0:f1d3878b8dd9	559	/**
vpcola	0:f1d3878b8dd9	560	* \brief CHSPACE register
vpcola	0:f1d3878b8dd9	561	* \code
vpcola	0:f1d3878b8dd9	562	* Read Write
vpcola	0:f1d3878b8dd9	563	* Default value: 0xFC
vpcola	0:f1d3878b8dd9	564	* 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps
vpcola	0:f1d3878b8dd9	565	* (in general, frequency step is fXO/215=26MHz/215~793Hz).
vpcola	0:f1d3878b8dd9	566	*
vpcola	0:f1d3878b8dd9	567	* \endcode
vpcola	0:f1d3878b8dd9	568	*/
vpcola	0:f1d3878b8dd9	569
vpcola	0:f1d3878b8dd9	570	#define CHSPACE_BASE ((uint8_t)0x0C) /!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps /
vpcola	0:f1d3878b8dd9	571
vpcola	0:f1d3878b8dd9	572	/**
vpcola	0:f1d3878b8dd9	573	* @}
vpcola	0:f1d3878b8dd9	574	*/
vpcola	0:f1d3878b8dd9	575
vpcola	0:f1d3878b8dd9	576
vpcola	0:f1d3878b8dd9	577
vpcola	0:f1d3878b8dd9	578	/** @defgroup IF_OFFSET_DIG_Register
vpcola	0:f1d3878b8dd9	579	* @{
vpcola	0:f1d3878b8dd9	580	*/
vpcola	0:f1d3878b8dd9	581
vpcola	0:f1d3878b8dd9	582	/**
vpcola	0:f1d3878b8dd9	583	* \brief IF_OFFSET_DIG register
vpcola	0:f1d3878b8dd9	584	* \code
vpcola	0:f1d3878b8dd9	585	* Read Write
vpcola	0:f1d3878b8dd9	586	* Default value: 0xA3
vpcola	0:f1d3878b8dd9	587	* 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
vpcola	0:f1d3878b8dd9	588	*
vpcola	0:f1d3878b8dd9	589	* \endcode
vpcola	0:f1d3878b8dd9	590	*/
vpcola	0:f1d3878b8dd9	591	#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
vpcola	0:f1d3878b8dd9	592
vpcola	0:f1d3878b8dd9	593	/**
vpcola	0:f1d3878b8dd9	594	* @}
vpcola	0:f1d3878b8dd9	595	*/
vpcola	0:f1d3878b8dd9	596
vpcola	0:f1d3878b8dd9	597	/** @defgroup IF_OFFSET_ANA_Register
vpcola	0:f1d3878b8dd9	598	* @{
vpcola	0:f1d3878b8dd9	599	*/
vpcola	0:f1d3878b8dd9	600
vpcola	0:f1d3878b8dd9	601	/**
vpcola	0:f1d3878b8dd9	602	* \brief IF_OFFSET_ANA register
vpcola	0:f1d3878b8dd9	603	* \code
vpcola	0:f1d3878b8dd9	604	* Read Write
vpcola	0:f1d3878b8dd9	605	* Default value: 0xA3
vpcola	0:f1d3878b8dd9	606	* 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
vpcola	0:f1d3878b8dd9	607	*
vpcola	0:f1d3878b8dd9	608	* \endcode
vpcola	0:f1d3878b8dd9	609	*/
vpcola	0:f1d3878b8dd9	610	#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
vpcola	0:f1d3878b8dd9	611
vpcola	0:f1d3878b8dd9	612
vpcola	0:f1d3878b8dd9	613	/**
vpcola	0:f1d3878b8dd9	614	* @}
vpcola	0:f1d3878b8dd9	615	*/
vpcola	0:f1d3878b8dd9	616
vpcola	0:f1d3878b8dd9	617	/** @defgroup FC_OFFSET1_Register
vpcola	0:f1d3878b8dd9	618	* @{
vpcola	0:f1d3878b8dd9	619	*/
vpcola	0:f1d3878b8dd9	620
vpcola	0:f1d3878b8dd9	621	/**
vpcola	0:f1d3878b8dd9	622	* \brief FC_OFFSET1 registers
vpcola	0:f1d3878b8dd9	623	* \code
vpcola	0:f1d3878b8dd9	624	* Read Write
vpcola	0:f1d3878b8dd9	625	* Default value: 0xA3
vpcola	0:f1d3878b8dd9	626	* 7:4 Reserved.
vpcola	0:f1d3878b8dd9	627	* 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2s complement integer
vpcola	0:f1d3878b8dd9	628	* representing an offset in 99Hz(2) units added/subtracted to the
vpcola	0:f1d3878b8dd9	629	* carrier frequency set by registers SYNT3SYNT0.
vpcola	0:f1d3878b8dd9	630	* This register can be used to set a fixed correction value
vpcola	0:f1d3878b8dd9	631	* obtained e.g. from crystal measurements.
vpcola	0:f1d3878b8dd9	632	*
vpcola	0:f1d3878b8dd9	633	* \endcode
vpcola	0:f1d3878b8dd9	634	*/
vpcola	0:f1d3878b8dd9	635	#define FC_OFFSET1_BASE ((uint8_t)0x0E) /!< [3:0] -> [11:8] Carrier offset (upper part) /
vpcola	0:f1d3878b8dd9	636
vpcola	0:f1d3878b8dd9	637	/**
vpcola	0:f1d3878b8dd9	638	* @}
vpcola	0:f1d3878b8dd9	639	*/
vpcola	0:f1d3878b8dd9	640
vpcola	0:f1d3878b8dd9	641
vpcola	0:f1d3878b8dd9	642	/** @defgroup FC_OFFSET0_Register
vpcola	0:f1d3878b8dd9	643	* @{
vpcola	0:f1d3878b8dd9	644	*/
vpcola	0:f1d3878b8dd9	645
vpcola	0:f1d3878b8dd9	646	/**
vpcola	0:f1d3878b8dd9	647	* \brief FC_OFFSET0 registers
vpcola	0:f1d3878b8dd9	648	* \code
vpcola	0:f1d3878b8dd9	649	* Default value: 0x00
vpcola	0:f1d3878b8dd9	650	* Read Write
vpcola	0:f1d3878b8dd9	651	* 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2s complement integer
vpcola	0:f1d3878b8dd9	652	* representing an offset in 99Hz(2) units added/subtracted to the
vpcola	0:f1d3878b8dd9	653	* carrier frequency set by registers SYNT3SYNT0.
vpcola	0:f1d3878b8dd9	654	* This register can be used to set a fixed correction value
vpcola	0:f1d3878b8dd9	655	* obtained e.g. from crystal measurements.
vpcola	0:f1d3878b8dd9	656	*
vpcola	0:f1d3878b8dd9	657	* \endcode
vpcola	0:f1d3878b8dd9	658	*/
vpcola	0:f1d3878b8dd9	659	#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2s complement integer
vpcola	0:f1d3878b8dd9	660	representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency
vpcola	0:f1d3878b8dd9	661	set by registers SYNT3SYNT0. Range is +/-200kHz with 26 MHz XO */
vpcola	0:f1d3878b8dd9	662	/**
vpcola	0:f1d3878b8dd9	663	* @}
vpcola	0:f1d3878b8dd9	664	*/
vpcola	0:f1d3878b8dd9	665
vpcola	0:f1d3878b8dd9	666
vpcola	0:f1d3878b8dd9	667	/** @defgroup PA_LEVEL_x_Registers
vpcola	0:f1d3878b8dd9	668	* @{
vpcola	0:f1d3878b8dd9	669	*/
vpcola	0:f1d3878b8dd9	670
vpcola	0:f1d3878b8dd9	671	/**
vpcola	0:f1d3878b8dd9	672	* \brief PA_POWER_x[8:1] registers
vpcola	0:f1d3878b8dd9	673	* \code
vpcola	0:f1d3878b8dd9	674	* Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00]
vpcola	0:f1d3878b8dd9	675	* Read Write
vpcola	0:f1d3878b8dd9	676	*
vpcola	0:f1d3878b8dd9	677	* 7 Reserved.
vpcola	0:f1d3878b8dd9	678	* 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot.
vpcola	0:f1d3878b8dd9	679	* \endcode
vpcola	0:f1d3878b8dd9	680	*/
vpcola	0:f1d3878b8dd9	681
vpcola	0:f1d3878b8dd9	682	#define PA_POWER8_BASE ((uint8_t)0x10) /!< PA Power level for 8th slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	683	#define PA_POWER7_BASE ((uint8_t)0x11) /!< PA Power level for 7th slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	684	#define PA_POWER6_BASE ((uint8_t)0x12) /!< PA Power level for 6th slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	685	#define PA_POWER5_BASE ((uint8_t)0x13) /!< PA Power level for 5th slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	686	#define PA_POWER4_BASE ((uint8_t)0x14) /!< PA Power level for 4th slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	687	#define PA_POWER3_BASE ((uint8_t)0x15) /!< PA Power level for 3rd slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	688	#define PA_POWER2_BASE ((uint8_t)0x16) /!< PA Power level for 2nd slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	689	#define PA_POWER1_BASE ((uint8_t)0x17) /!< PA Power level for 1st slot of PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	690
vpcola	0:f1d3878b8dd9	691	/**
vpcola	0:f1d3878b8dd9	692	* @}
vpcola	0:f1d3878b8dd9	693	*/
vpcola	0:f1d3878b8dd9	694
vpcola	0:f1d3878b8dd9	695	/** @defgroup PA_POWER_CONF_Registers
vpcola	0:f1d3878b8dd9	696	* @{
vpcola	0:f1d3878b8dd9	697	*/
vpcola	0:f1d3878b8dd9	698
vpcola	0:f1d3878b8dd9	699	/**
vpcola	0:f1d3878b8dd9	700	* \brief PA_POWER_CONF_Registers
vpcola	0:f1d3878b8dd9	701	* \code
vpcola	0:f1d3878b8dd9	702	* Default value:0x07
vpcola	0:f1d3878b8dd9	703	* Read Write
vpcola	0:f1d3878b8dd9	704	*
vpcola	0:f1d3878b8dd9	705	* 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to
vpcola	0:f1d3878b8dd9	706	* optimize the PA for different sub-bands).
vpcola	0:f1d3878b8dd9	707	*
vpcola	0:f1d3878b8dd9	708	* CWC1 \| CWC0 \| Total capacity in pF
vpcola	0:f1d3878b8dd9	709	* ---------------------------------------------------------
vpcola	0:f1d3878b8dd9	710	* 0 \| 0 \| 0
vpcola	0:f1d3878b8dd9	711	* 0 \| 1 \| 1.2
vpcola	0:f1d3878b8dd9	712	* 1 \| 0 \| 2.4
vpcola	0:f1d3878b8dd9	713	* 1 \| 1 \| 3.6
vpcola	0:f1d3878b8dd9	714	*
vpcola	0:f1d3878b8dd9	715	* 5 PA_RAMP_ENABLE:
vpcola	0:f1d3878b8dd9	716	* 1 - Enable the power ramping
vpcola	0:f1d3878b8dd9	717	* 0 - Disable the power ramping
vpcola	0:f1d3878b8dd9	718	* 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period
vpcola	0:f1d3878b8dd9	719	*
vpcola	0:f1d3878b8dd9	720	* PA_RAMP_STEP_WIDTH1 \| PA_RAMP_STEP_WIDTH0 \| PA ramping time step
vpcola	0:f1d3878b8dd9	721	* -------------------------------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	722	* 0 \| 0 \| 1/8 Bit period
vpcola	0:f1d3878b8dd9	723	* 0 \| 1 \| 2/8 Bit period
vpcola	0:f1d3878b8dd9	724	* 1 \| 0 \| 3/8 Bit period
vpcola	0:f1d3878b8dd9	725	* 1 \| 1 \| 4/8 Bit period
vpcola	0:f1d3878b8dd9	726	*
vpcola	0:f1d3878b8dd9	727	* 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation
vpcola	0:f1d3878b8dd9	728	*
vpcola	0:f1d3878b8dd9	729	* \endcode
vpcola	0:f1d3878b8dd9	730	*/
vpcola	0:f1d3878b8dd9	731	#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used
vpcola	0:f1d3878b8dd9	732	for PA optimization in different sub bands*/
vpcola	0:f1d3878b8dd9	733	#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /!< Output stage additional load capacitors bank /
vpcola	0:f1d3878b8dd9	734	#define PA_POWER0_CWC_0 ((uint8_t)0x00) /!< No additional PA load capacitor /
vpcola	0:f1d3878b8dd9	735	#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /!< 1.2pF additional PA load capacitor /
vpcola	0:f1d3878b8dd9	736	#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /!< 2.4pF additional PA load capacitor /
vpcola	0:f1d3878b8dd9	737	#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /!< 3.6pF additional PA load capacitor /
vpcola	0:f1d3878b8dd9	738	#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /!< The PA power ramping /
vpcola	0:f1d3878b8dd9	739	#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /!< The step width /
vpcola	0:f1d3878b8dd9	740	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /!< PA ramping time step = 1/8 Bit period/
vpcola	0:f1d3878b8dd9	741	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /!< PA ramping time step = 2/8 Bit period/
vpcola	0:f1d3878b8dd9	742	#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /!< PA ramping time step = 3/8 Bit period/
vpcola	0:f1d3878b8dd9	743	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /!< PA ramping time step = 4/8 Bit period/
vpcola	0:f1d3878b8dd9	744	#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /!< Final level for power ramping /
vpcola	0:f1d3878b8dd9	745	#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /!< /
vpcola	0:f1d3878b8dd9	746	#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation /
vpcola	0:f1d3878b8dd9	747	#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /!< /
vpcola	0:f1d3878b8dd9	748	#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /!< _________ /
vpcola	0:f1d3878b8dd9	749	#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /!< PA_LVL2 _\| <--\| /
vpcola	0:f1d3878b8dd9	750	#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /!< _\| \| /
vpcola	0:f1d3878b8dd9	751	#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /!< PA_LVL1 _\| \| /
vpcola	0:f1d3878b8dd9	752	#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /!< PA_LVL0 _\| MAX_INDEX- /
vpcola	0:f1d3878b8dd9	753
vpcola	0:f1d3878b8dd9	754
vpcola	0:f1d3878b8dd9	755
vpcola	0:f1d3878b8dd9	756	/**
vpcola	0:f1d3878b8dd9	757	* @}
vpcola	0:f1d3878b8dd9	758	*/
vpcola	0:f1d3878b8dd9	759
vpcola	0:f1d3878b8dd9	760
vpcola	0:f1d3878b8dd9	761	/** @defgroup MOD1_Register
vpcola	0:f1d3878b8dd9	762	* @{
vpcola	0:f1d3878b8dd9	763	*/
vpcola	0:f1d3878b8dd9	764
vpcola	0:f1d3878b8dd9	765	/**
vpcola	0:f1d3878b8dd9	766	* \brief MOD1 register
vpcola	0:f1d3878b8dd9	767	* \code
vpcola	0:f1d3878b8dd9	768	* Read Write
vpcola	0:f1d3878b8dd9	769	* Default value: 0x83
vpcola	0:f1d3878b8dd9	770	* 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate
vpcola	0:f1d3878b8dd9	771	*
vpcola	0:f1d3878b8dd9	772	* \endcode
vpcola	0:f1d3878b8dd9	773	*/
vpcola	0:f1d3878b8dd9	774	#define MOD1_BASE ((uint8_t)0x1A) /!< The Mantissa of the specified data rate /
vpcola	0:f1d3878b8dd9	775
vpcola	0:f1d3878b8dd9	776	/**
vpcola	0:f1d3878b8dd9	777	* @}
vpcola	0:f1d3878b8dd9	778	*/
vpcola	0:f1d3878b8dd9	779
vpcola	0:f1d3878b8dd9	780	/** @defgroup MOD0_Register
vpcola	0:f1d3878b8dd9	781	* @{
vpcola	0:f1d3878b8dd9	782	*/
vpcola	0:f1d3878b8dd9	783
vpcola	0:f1d3878b8dd9	784	/**
vpcola	0:f1d3878b8dd9	785	* \brief MOD0 register
vpcola	0:f1d3878b8dd9	786	* \code
vpcola	0:f1d3878b8dd9	787	* Read Write
vpcola	0:f1d3878b8dd9	788	* Default value: 0x1A
vpcola	0:f1d3878b8dd9	789	* 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation
vpcola	0:f1d3878b8dd9	790	* 0 - CW Mode disabled
vpcola	0:f1d3878b8dd9	791	*
vpcola	0:f1d3878b8dd9	792	* 6 BT_SEL: Select BT value for GFSK
vpcola	0:f1d3878b8dd9	793	* 1 - BT=0.5
vpcola	0:f1d3878b8dd9	794	* 0 - BT=1
vpcola	0:f1d3878b8dd9	795	*
vpcola	0:f1d3878b8dd9	796	* 5:4 MOD_TYPE[1:0]: Modulation type
vpcola	0:f1d3878b8dd9	797	*
vpcola	0:f1d3878b8dd9	798	*
vpcola	0:f1d3878b8dd9	799	* MOD_TYPE1 \| MOD_TYPE0 \| Modulation
vpcola	0:f1d3878b8dd9	800	* ---------------------------------------------------------
vpcola	0:f1d3878b8dd9	801	* 0 \| 0 \| 2-FSK,MSK
vpcola	0:f1d3878b8dd9	802	* 0 \| 1 \| GFSK,GMSK
vpcola	0:f1d3878b8dd9	803	* 1 \| 0 \| ASK/OOK
vpcola	0:f1d3878b8dd9	804	*
vpcola	0:f1d3878b8dd9	805	* 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate
vpcola	0:f1d3878b8dd9	806	*
vpcola	0:f1d3878b8dd9	807	* \endcode
vpcola	0:f1d3878b8dd9	808	*/
vpcola	0:f1d3878b8dd9	809	#define MOD0_BASE ((uint8_t)0x1B) /!< Modulation Settings, Exponent of the specified data rate, CW mode/
vpcola	0:f1d3878b8dd9	810
vpcola	0:f1d3878b8dd9	811	#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) /
vpcola	0:f1d3878b8dd9	812	#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) /
vpcola	0:f1d3878b8dd9	813	#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /!< Modulation type ASK (OOK the PA is switched off for symbol "0") /
vpcola	0:f1d3878b8dd9	814	#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) /
vpcola	0:f1d3878b8dd9	815	#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) /
vpcola	0:f1d3878b8dd9	816	#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation/
vpcola	0:f1d3878b8dd9	817	#define MOD0_CW ((uint8_t)0x80) /!< Set the Continous Wave (no modulation) transmit mode /
vpcola	0:f1d3878b8dd9	818
vpcola	0:f1d3878b8dd9	819	/**
vpcola	0:f1d3878b8dd9	820	* @}
vpcola	0:f1d3878b8dd9	821	*/
vpcola	0:f1d3878b8dd9	822
vpcola	0:f1d3878b8dd9	823
vpcola	0:f1d3878b8dd9	824	/** @defgroup FDEV0_Register
vpcola	0:f1d3878b8dd9	825	* @{
vpcola	0:f1d3878b8dd9	826	*/
vpcola	0:f1d3878b8dd9	827
vpcola	0:f1d3878b8dd9	828	/**
vpcola	0:f1d3878b8dd9	829	* \brief FDEV0 register
vpcola	0:f1d3878b8dd9	830	* \code
vpcola	0:f1d3878b8dd9	831	* Read Write
vpcola	0:f1d3878b8dd9	832	* Default value: 0x45
vpcola	0:f1d3878b8dd9	833	* 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9)
vpcola	0:f1d3878b8dd9	834	*
vpcola	0:f1d3878b8dd9	835	* 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery
vpcola	0:f1d3878b8dd9	836	* 1 - DLL mode
vpcola	0:f1d3878b8dd9	837	* 0 - PLL mode
vpcola	0:f1d3878b8dd9	838	*
vpcola	0:f1d3878b8dd9	839	* 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7)
vpcola	0:f1d3878b8dd9	840	*
vpcola	0:f1d3878b8dd9	841	*
vpcola	0:f1d3878b8dd9	842	* \endcode
vpcola	0:f1d3878b8dd9	843	*/
vpcola	0:f1d3878b8dd9	844	#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2)
vpcola	0:f1d3878b8dd9	845	and PLL or DLL alogrithm from clock recovery in RX digital demod*/
vpcola	0:f1d3878b8dd9	846	#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) /
vpcola	0:f1d3878b8dd9	847	#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
vpcola	0:f1d3878b8dd9	848	#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
vpcola	0:f1d3878b8dd9	849
vpcola	0:f1d3878b8dd9	850	/**
vpcola	0:f1d3878b8dd9	851	* @}
vpcola	0:f1d3878b8dd9	852	*/
vpcola	0:f1d3878b8dd9	853
vpcola	0:f1d3878b8dd9	854	/** @defgroup CHFLT_Register
vpcola	0:f1d3878b8dd9	855	* @{
vpcola	0:f1d3878b8dd9	856	*/
vpcola	0:f1d3878b8dd9	857
vpcola	0:f1d3878b8dd9	858	/**
vpcola	0:f1d3878b8dd9	859	* \brief CHFLT register
vpcola	0:f1d3878b8dd9	860	* \code
vpcola	0:f1d3878b8dd9	861	* Read Write
vpcola	0:f1d3878b8dd9	862	* Default value: 0x23
vpcola	0:f1d3878b8dd9	863	* 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8)
vpcola	0:f1d3878b8dd9	864	*
vpcola	0:f1d3878b8dd9	865	* 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9)
vpcola	0:f1d3878b8dd9	866	*
vpcola	0:f1d3878b8dd9	867	* M\E \| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \| 8 \| 9 \|
vpcola	0:f1d3878b8dd9	868	* -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+
vpcola	0:f1d3878b8dd9	869	* 0 \| 800.1 \| 450.9 \| 224.7 \| 112.3 \| 56.1 \| 28.0 \| 14.0 \| 7.0 \| 3.5 \| 1.8 \|
vpcola	0:f1d3878b8dd9	870	* 1 \| 795.1 \| 425.9 \| 212.4 \| 106.2 \| 53.0 \| 26.5 \| 13.3 \| 6.6 \| 3.3 \| 1.7 \|
vpcola	0:f1d3878b8dd9	871	* 2 \| 768.4 \| 403.2 \| 201.1 \| 100.5 \| 50.2 \| 25.1 \| 12.6 \| 6.3 \| 3.1 \| 1.6 \|
vpcola	0:f1d3878b8dd9	872	* 3 \| 736.8 \| 380.8 \| 190.0 \| 95.0 \| 47.4 \| 23.7 \| 11.9 \| 5.9 \| 3.0 \| 1.5 \|
vpcola	0:f1d3878b8dd9	873	* 4 \| 705.1 \| 362.1 \| 180.7 \| 90.3 \| 45.1 \| 22.6 \| 11.3 \| 5.6 \| 2.8 \| 1.4 \|
vpcola	0:f1d3878b8dd9	874	* 5 \| 670.9 \| 341.7 \| 170.6 \| 85.3 \| 42.6 \| 21.3 \| 10.6 \| 5.3 \| 2.7 \| 1.3 \|
vpcola	0:f1d3878b8dd9	875	* 6 \| 642.3 \| 325.4 \| 162.4 \| 81.2 \| 40.6 \| 20.3 \| 10.1 \| 5.1 \| 2.5 \| 1.3 \|
vpcola	0:f1d3878b8dd9	876	* 7 \| 586.7 \| 294.5 \| 147.1 \| 73.5 \| 36.7 \| 18.4 \| 9.2 \| 4.6 \| 2.3 \| 1.2 \|
vpcola	0:f1d3878b8dd9	877	* 8 \| 541.4 \| 270.3 \| 135.0 \| 67.5 \| 33.7 \| 16.9 \| 8.4 \| 4.2 \| 2.1 \| 1.1 \|
vpcola	0:f1d3878b8dd9	878	*
vpcola	0:f1d3878b8dd9	879	* \endcode
vpcola	0:f1d3878b8dd9	880	*/
vpcola	0:f1d3878b8dd9	881	#define CHFLT_BASE ((uint8_t)0x1D) /!< RX Channel Filter Bandwidth /
vpcola	0:f1d3878b8dd9	882
vpcola	0:f1d3878b8dd9	883	#define CHFLT_800_1 ((uint8_t)0x00) /!< RX Channel Filter Bandwidth = 800.1 kHz /
vpcola	0:f1d3878b8dd9	884	#define CHFLT_795_1 ((uint8_t)0x10) /!< RX Channel Filter Bandwidth = 795.1 kHz /
vpcola	0:f1d3878b8dd9	885	#define CHFLT_768_4 ((uint8_t)0x20) /!< RX Channel Filter Bandwidth = 768.4 kHz /
vpcola	0:f1d3878b8dd9	886	#define CHFLT_736_8 ((uint8_t)0x30) /!< RX Channel Filter Bandwidth = 736.8 kHz /
vpcola	0:f1d3878b8dd9	887	#define CHFLT_705_1 ((uint8_t)0x40) /!< RX Channel Filter Bandwidth = 705.1 kHz /
vpcola	0:f1d3878b8dd9	888	#define CHFLT_670_9 ((uint8_t)0x50) /!< RX Channel Filter Bandwidth = 670.9 kHz /
vpcola	0:f1d3878b8dd9	889	#define CHFLT_642_3 ((uint8_t)0x60) /!< RX Channel Filter Bandwidth = 642.3 kHz /
vpcola	0:f1d3878b8dd9	890	#define CHFLT_586_7 ((uint8_t)0x70) /!< RX Channel Filter Bandwidth = 586.7 kHz /
vpcola	0:f1d3878b8dd9	891	#define CHFLT_541_4 ((uint8_t)0x80) /!< RX Channel Filter Bandwidth = 541.4 kHz /
vpcola	0:f1d3878b8dd9	892	#define CHFLT_450_9 ((uint8_t)0x01) /!< RX Channel Filter Bandwidth = 450.9 kHz /
vpcola	0:f1d3878b8dd9	893	#define CHFLT_425_9 ((uint8_t)0x11) /!< RX Channel Filter Bandwidth = 425.9 kHz /
vpcola	0:f1d3878b8dd9	894	#define CHFLT_403_2 ((uint8_t)0x21) /!< RX Channel Filter Bandwidth = 403.2 kHz /
vpcola	0:f1d3878b8dd9	895	#define CHFLT_380_8 ((uint8_t)0x31) /!< RX Channel Filter Bandwidth = 380.8 kHz /
vpcola	0:f1d3878b8dd9	896	#define CHFLT_362_1 ((uint8_t)0x41) /!< RX Channel Filter Bandwidth = 362.1 kHz /
vpcola	0:f1d3878b8dd9	897	#define CHFLT_341_7 ((uint8_t)0x51) /!< RX Channel Filter Bandwidth = 341.7 kHz /
vpcola	0:f1d3878b8dd9	898	#define CHFLT_325_4 ((uint8_t)0x61) /!< RX Channel Filter Bandwidth = 325.4 kHz /
vpcola	0:f1d3878b8dd9	899	#define CHFLT_294_5 ((uint8_t)0x71) /!< RX Channel Filter Bandwidth = 294.5 kHz /
vpcola	0:f1d3878b8dd9	900	#define CHFLT_270_3 ((uint8_t)0x81) /!< RX Channel Filter Bandwidth = 270.3 kHz /
vpcola	0:f1d3878b8dd9	901	#define CHFLT_224_7 ((uint8_t)0x02) /!< RX Channel Filter Bandwidth = 224.7 kHz /
vpcola	0:f1d3878b8dd9	902	#define CHFLT_212_4 ((uint8_t)0x12) /!< RX Channel Filter Bandwidth = 212.4 kHz /
vpcola	0:f1d3878b8dd9	903	#define CHFLT_201_1 ((uint8_t)0x22) /!< RX Channel Filter Bandwidth = 201.1 kHz /
vpcola	0:f1d3878b8dd9	904	#define CHFLT_190 ((uint8_t)0x32) /!< RX Channel Filter Bandwidth = 190.0 kHz /
vpcola	0:f1d3878b8dd9	905	#define CHFLT_180_7 ((uint8_t)0x42) /!< RX Channel Filter Bandwidth = 180.7 kHz /
vpcola	0:f1d3878b8dd9	906	#define CHFLT_170_6 ((uint8_t)0x52) /!< RX Channel Filter Bandwidth = 170.6 kHz /
vpcola	0:f1d3878b8dd9	907	#define CHFLT_162_4 ((uint8_t)0x62) /!< RX Channel Filter Bandwidth = 162.4 kHz /
vpcola	0:f1d3878b8dd9	908	#define CHFLT_147_1 ((uint8_t)0x72) /!< RX Channel Filter Bandwidth = 147.1 kHz /
vpcola	0:f1d3878b8dd9	909	#define CHFLT_135 ((uint8_t)0x82) /!< RX Channel Filter Bandwidth = 135.0 kHz /
vpcola	0:f1d3878b8dd9	910	#define CHFLT_112_3 ((uint8_t)0x03) /!< RX Channel Filter Bandwidth = 112.3 kHz /
vpcola	0:f1d3878b8dd9	911	#define CHFLT_106_2 ((uint8_t)0x13) /!< RX Channel Filter Bandwidth = 106.2 kHz /
vpcola	0:f1d3878b8dd9	912	#define CHFLT_100_5 ((uint8_t)0x23) /!< RX Channel Filter Bandwidth = 100.5 kHz /
vpcola	0:f1d3878b8dd9	913	#define CHFLT_95 ((uint8_t)0x33) /!< RX Channel Filter Bandwidth = 95.0 kHz /
vpcola	0:f1d3878b8dd9	914	#define CHFLT_90_3 ((uint8_t)0x43) /!< RX Channel Filter Bandwidth = 90.3 kHz /
vpcola	0:f1d3878b8dd9	915	#define CHFLT_85_3 ((uint8_t)0x53) /!< RX Channel Filter Bandwidth = 85.3 kHz /
vpcola	0:f1d3878b8dd9	916	#define CHFLT_81_2 ((uint8_t)0x63) /!< RX Channel Filter Bandwidth = 81.2 kHz /
vpcola	0:f1d3878b8dd9	917	#define CHFLT_73_5 ((uint8_t)0x73) /!< RX Channel Filter Bandwidth = 73.5 kHz /
vpcola	0:f1d3878b8dd9	918	#define CHFLT_67_5 ((uint8_t)0x83) /!< RX Channel Filter Bandwidth = 67.5 kHz /
vpcola	0:f1d3878b8dd9	919	#define CHFLT_56_1 ((uint8_t)0x04) /!< RX Channel Filter Bandwidth = 56.1 kHz /
vpcola	0:f1d3878b8dd9	920	#define CHFLT_53 ((uint8_t)0x14) /!< RX Channel Filter Bandwidth = 53.0 kHz /
vpcola	0:f1d3878b8dd9	921	#define CHFLT_50_2 ((uint8_t)0x24) /!< RX Channel Filter Bandwidth = 50.2 kHz /
vpcola	0:f1d3878b8dd9	922	#define CHFLT_47_4 ((uint8_t)0x34) /!< RX Channel Filter Bandwidth = 47.4 kHz /
vpcola	0:f1d3878b8dd9	923	#define CHFLT_45_1 ((uint8_t)0x44) /!< RX Channel Filter Bandwidth = 45.1 kHz /
vpcola	0:f1d3878b8dd9	924	#define CHFLT_42_6 ((uint8_t)0x54) /!< RX Channel Filter Bandwidth = 42.6 kHz /
vpcola	0:f1d3878b8dd9	925	#define CHFLT_40_6 ((uint8_t)0x64) /!< RX Channel Filter Bandwidth = 40.6 kHz /
vpcola	0:f1d3878b8dd9	926	#define CHFLT_36_7 ((uint8_t)0x74) /!< RX Channel Filter Bandwidth = 36.7 kHz /
vpcola	0:f1d3878b8dd9	927	#define CHFLT_33_7 ((uint8_t)0x84) /!< RX Channel Filter Bandwidth = 33.7 kHz /
vpcola	0:f1d3878b8dd9	928	#define CHFLT_28 ((uint8_t)0x05) /!< RX Channel Filter Bandwidth = 28.0 kHz /
vpcola	0:f1d3878b8dd9	929	#define CHFLT_26_5 ((uint8_t)0x15) /!< RX Channel Filter Bandwidth = 26.5 kHz /
vpcola	0:f1d3878b8dd9	930	#define CHFLT_25_1 ((uint8_t)0x25) /!< RX Channel Filter Bandwidth = 25.1 kHz /
vpcola	0:f1d3878b8dd9	931	#define CHFLT_23_7 ((uint8_t)0x35) /!< RX Channel Filter Bandwidth = 23.7 kHz /
vpcola	0:f1d3878b8dd9	932	#define CHFLT_22_6 ((uint8_t)0x45) /!< RX Channel Filter Bandwidth = 22.6 kHz /
vpcola	0:f1d3878b8dd9	933	#define CHFLT_21_3 ((uint8_t)0x55) /!< RX Channel Filter Bandwidth = 21.3 kHz /
vpcola	0:f1d3878b8dd9	934	#define CHFLT_20_3 ((uint8_t)0x65) /!< RX Channel Filter Bandwidth = 20.3 kHz /
vpcola	0:f1d3878b8dd9	935	#define CHFLT_18_4 ((uint8_t)0x75) /!< RX Channel Filter Bandwidth = 18.4 kHz /
vpcola	0:f1d3878b8dd9	936	#define CHFLT_16_9 ((uint8_t)0x85) /!< RX Channel Filter Bandwidth = 16.9 kHz /
vpcola	0:f1d3878b8dd9	937	#define CHFLT_14 ((uint8_t)0x06) /!< RX Channel Filter Bandwidth = 14.0 kHz /
vpcola	0:f1d3878b8dd9	938	#define CHFLT_13_3 ((uint8_t)0x16) /!< RX Channel Filter Bandwidth = 13.3 kHz /
vpcola	0:f1d3878b8dd9	939	#define CHFLT_12_6 ((uint8_t)0x26) /!< RX Channel Filter Bandwidth = 12.6 kHz /
vpcola	0:f1d3878b8dd9	940	#define CHFLT_11_9 ((uint8_t)0x36) /!< RX Channel Filter Bandwidth = 11.9 kHz /
vpcola	0:f1d3878b8dd9	941	#define CHFLT_11_3 ((uint8_t)0x46) /!< RX Channel Filter Bandwidth = 11.3 kHz /
vpcola	0:f1d3878b8dd9	942	#define CHFLT_10_6 ((uint8_t)0x56) /!< RX Channel Filter Bandwidth = 10.6 kHz /
vpcola	0:f1d3878b8dd9	943	#define CHFLT_10_1 ((uint8_t)0x66) /!< RX Channel Filter Bandwidth = 10.1 kHz /
vpcola	0:f1d3878b8dd9	944	#define CHFLT_9_2 ((uint8_t)0x76) /!< RX Channel Filter Bandwidth = 9.2 kHz /
vpcola	0:f1d3878b8dd9	945	#define CHFLT_8_4 ((uint8_t)0x86) /!< RX Channel Filter Bandwidth = 8.4 kHz /
vpcola	0:f1d3878b8dd9	946	#define CHFLT_7 ((uint8_t)0x07) /!< RX Channel Filter Bandwidth = 7.0 kHz /
vpcola	0:f1d3878b8dd9	947	#define CHFLT_6_6 ((uint8_t)0x17) /!< RX Channel Filter Bandwidth = 6.6 kHz /
vpcola	0:f1d3878b8dd9	948	#define CHFLT_6_3 ((uint8_t)0x27) /!< RX Channel Filter Bandwidth = 6.3 kHz /
vpcola	0:f1d3878b8dd9	949	#define CHFLT_5_9 ((uint8_t)0x37) /!< RX Channel Filter Bandwidth = 5.9 kHz /
vpcola	0:f1d3878b8dd9	950	#define CHFLT_5_6 ((uint8_t)0x47) /!< RX Channel Filter Bandwidth = 5.6 kHz /
vpcola	0:f1d3878b8dd9	951	#define CHFLT_5_3 ((uint8_t)0x57) /!< RX Channel Filter Bandwidth = 5.3 kHz /
vpcola	0:f1d3878b8dd9	952	#define CHFLT_5_1 ((uint8_t)0x67) /!< RX Channel Filter Bandwidth = 5.1 kHz /
vpcola	0:f1d3878b8dd9	953	#define CHFLT_4_6 ((uint8_t)0x77) /!< RX Channel Filter Bandwidth = 4.6 kHz /
vpcola	0:f1d3878b8dd9	954	#define CHFLT_4_2 ((uint8_t)0x87) /!< RX Channel Filter Bandwidth = 4.2 kHz /
vpcola	0:f1d3878b8dd9	955	#define CHFLT_3_5 ((uint8_t)0x08) /!< RX Channel Filter Bandwidth = 3.5 kHz /
vpcola	0:f1d3878b8dd9	956	#define CHFLT_3_3 ((uint8_t)0x18) /!< RX Channel Filter Bandwidth = 3.3 kHz /
vpcola	0:f1d3878b8dd9	957	#define CHFLT_3_1 ((uint8_t)0x28) /!< RX Channel Filter Bandwidth = 3.1 kHz /
vpcola	0:f1d3878b8dd9	958	#define CHFLT_3 ((uint8_t)0x38) /!< RX Channel Filter Bandwidth = 3.0 kHz /
vpcola	0:f1d3878b8dd9	959	#define CHFLT_2_8 ((uint8_t)0x48) /!< RX Channel Filter Bandwidth = 2.8 kHz /
vpcola	0:f1d3878b8dd9	960	#define CHFLT_2_7 ((uint8_t)0x58) /!< RX Channel Filter Bandwidth = 2.7 kHz /
vpcola	0:f1d3878b8dd9	961	#define CHFLT_2_5 ((uint8_t)0x68) /!< RX Channel Filter Bandwidth = 2.5 kHz /
vpcola	0:f1d3878b8dd9	962	#define CHFLT_2_3 ((uint8_t)0x78) /!< RX Channel Filter Bandwidth = 2.3 kHz /
vpcola	0:f1d3878b8dd9	963	#define CHFLT_2_1 ((uint8_t)0x88) /!< RX Channel Filter Bandwidth = 2.1 kHz /
vpcola	0:f1d3878b8dd9	964	#define CHFLT_1_8 ((uint8_t)0x09) /!< RX Channel Filter Bandwidth = 1.8 kHz /
vpcola	0:f1d3878b8dd9	965	#define CHFLT_1_7 ((uint8_t)0x19) /!< RX Channel Filter Bandwidth = 1.7 kHz /
vpcola	0:f1d3878b8dd9	966	#define CHFLT_1_6 ((uint8_t)0x29) /!< RX Channel Filter Bandwidth = 1.6 kHz /
vpcola	0:f1d3878b8dd9	967	#define CHFLT_1_5 ((uint8_t)0x39) /!< RX Channel Filter Bandwidth = 1.5 kHz /
vpcola	0:f1d3878b8dd9	968	#define CHFLT_1_4 ((uint8_t)0x49) /!< RX Channel Filter Bandwidth = 1.4 kHz /
vpcola	0:f1d3878b8dd9	969	#define CHFLT_1_3a ((uint8_t)0x59) /!< RX Channel Filter Bandwidth = 1.3 kHz /
vpcola	0:f1d3878b8dd9	970	#define CHFLT_1_3 ((uint8_t)0x69) /!< RX Channel Filter Bandwidth = 1.3 kHz /
vpcola	0:f1d3878b8dd9	971	#define CHFLT_1_2 ((uint8_t)0x79) /!< RX Channel Filter Bandwidth = 1.2 kHz /
vpcola	0:f1d3878b8dd9	972	#define CHFLT_1_1 ((uint8_t)0x89) /!< RX Channel Filter Bandwidth = 1.1 kHz /
vpcola	0:f1d3878b8dd9	973
vpcola	0:f1d3878b8dd9	974	/**
vpcola	0:f1d3878b8dd9	975	* @}
vpcola	0:f1d3878b8dd9	976	*/
vpcola	0:f1d3878b8dd9	977
vpcola	0:f1d3878b8dd9	978	/** @defgroup AFC2_Register
vpcola	0:f1d3878b8dd9	979	* @{
vpcola	0:f1d3878b8dd9	980	*/
vpcola	0:f1d3878b8dd9	981
vpcola	0:f1d3878b8dd9	982	/**
vpcola	0:f1d3878b8dd9	983	* \brief AFC2 register
vpcola	0:f1d3878b8dd9	984	* \code
vpcola	0:f1d3878b8dd9	985	* Read Write
vpcola	0:f1d3878b8dd9	986	* Default value: 0x48
vpcola	0:f1d3878b8dd9	987	* 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection.
vpcola	0:f1d3878b8dd9	988	* 1 - AFC Freeze enabled
vpcola	0:f1d3878b8dd9	989	* 0 - AFC Freeze disabled
vpcola	0:f1d3878b8dd9	990	*
vpcola	0:f1d3878b8dd9	991	* 6 AFC Enabled: Enable AFC
vpcola	0:f1d3878b8dd9	992	* 1 - AFC enabled
vpcola	0:f1d3878b8dd9	993	* 0 - AFC disabled
vpcola	0:f1d3878b8dd9	994	*
vpcola	0:f1d3878b8dd9	995	* 5 AFC Mode: Select AFC mode
vpcola	0:f1d3878b8dd9	996	* 1 - AFC Loop closed on 2nd conversion stage.
vpcola	0:f1d3878b8dd9	997	* 0 - AFC Loop closed on slicer
vpcola	0:f1d3878b8dd9	998	*
vpcola	0:f1d3878b8dd9	999	* 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register),
vpcola	0:f1d3878b8dd9	1000	* the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4.
vpcola	0:f1d3878b8dd9	1001	*
vpcola	0:f1d3878b8dd9	1002	* \endcode
vpcola	0:f1d3878b8dd9	1003	*/
vpcola	0:f1d3878b8dd9	1004	#define AFC2_BASE ((uint8_t)0x1E) /!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)/
vpcola	0:f1d3878b8dd9	1005
vpcola	0:f1d3878b8dd9	1006	#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /!< The frequency correction value is frozen when SYNC word is detected /
vpcola	0:f1d3878b8dd9	1007	#define AFC2_AFC_MASK ((uint8_t)0x40) /!< Mask of Automatic Frequency Correction /
vpcola	0:f1d3878b8dd9	1008	#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE/
vpcola	0:f1d3878b8dd9	1009	#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /!< Automatic Frequency Correction Main MODE /
vpcola	0:f1d3878b8dd9	1010	#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /!< Automatic Frequency Correction Auxiliary MODE /
vpcola	0:f1d3878b8dd9	1011
vpcola	0:f1d3878b8dd9	1012	/**
vpcola	0:f1d3878b8dd9	1013	* @}
vpcola	0:f1d3878b8dd9	1014	*/
vpcola	0:f1d3878b8dd9	1015
vpcola	0:f1d3878b8dd9	1016	/** @defgroup AFC1_Register
vpcola	0:f1d3878b8dd9	1017	* @{
vpcola	0:f1d3878b8dd9	1018	*/
vpcola	0:f1d3878b8dd9	1019
vpcola	0:f1d3878b8dd9	1020	/**
vpcola	0:f1d3878b8dd9	1021	* \brief AFC1 register
vpcola	0:f1d3878b8dd9	1022	* \code
vpcola	0:f1d3878b8dd9	1023	* Read Write
vpcola	0:f1d3878b8dd9	1024	* Default value: 0x18
vpcola	0:f1d3878b8dd9	1025	* 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed
vpcola	0:f1d3878b8dd9	1026	* is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the
vpcola	0:f1d3878b8dd9	1027	* algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble
vpcola	0:f1d3878b8dd9	1028	* symbols.
vpcola	0:f1d3878b8dd9	1029	*
vpcola	0:f1d3878b8dd9	1030	* \endcode
vpcola	0:f1d3878b8dd9	1031	*/
vpcola	0:f1d3878b8dd9	1032	#define AFC1_BASE ((uint8_t)0x1F) /!< Length of the AFC fast period /
vpcola	0:f1d3878b8dd9	1033
vpcola	0:f1d3878b8dd9	1034	/**
vpcola	0:f1d3878b8dd9	1035	* @}
vpcola	0:f1d3878b8dd9	1036	*/
vpcola	0:f1d3878b8dd9	1037
vpcola	0:f1d3878b8dd9	1038	/** @defgroup AFC0_Register
vpcola	0:f1d3878b8dd9	1039	* @{
vpcola	0:f1d3878b8dd9	1040	*/
vpcola	0:f1d3878b8dd9	1041
vpcola	0:f1d3878b8dd9	1042	/**
vpcola	0:f1d3878b8dd9	1043	* \brief AFC0 register
vpcola	0:f1d3878b8dd9	1044	* \code
vpcola	0:f1d3878b8dd9	1045	* Read Write
vpcola	0:f1d3878b8dd9	1046	* Default value: 0x25
vpcola	0:f1d3878b8dd9	1047	* 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log)
vpcola	0:f1d3878b8dd9	1048	*
vpcola	0:f1d3878b8dd9	1049	* 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log)
vpcola	0:f1d3878b8dd9	1050	*
vpcola	0:f1d3878b8dd9	1051	* \endcode
vpcola	0:f1d3878b8dd9	1052	*/
vpcola	0:f1d3878b8dd9	1053	#define AFC0_BASE ((uint8_t)0x20) /!< AFC loop gain in fast and slow modes (2's log) /
vpcola	0:f1d3878b8dd9	1054
vpcola	0:f1d3878b8dd9	1055	/**
vpcola	0:f1d3878b8dd9	1056	* @}
vpcola	0:f1d3878b8dd9	1057	*/
vpcola	0:f1d3878b8dd9	1058
vpcola	0:f1d3878b8dd9	1059	/** @defgroup CLOCKREC_Register
vpcola	0:f1d3878b8dd9	1060	* @{
vpcola	0:f1d3878b8dd9	1061	*/
vpcola	0:f1d3878b8dd9	1062
vpcola	0:f1d3878b8dd9	1063	/**
vpcola	0:f1d3878b8dd9	1064	* \brief CLOCKREC register
vpcola	0:f1d3878b8dd9	1065	* \code
vpcola	0:f1d3878b8dd9	1066	* Read Write
vpcola	0:f1d3878b8dd9	1067	* Default value: 0x58
vpcola	0:f1d3878b8dd9	1068	*
vpcola	0:f1d3878b8dd9	1069	* 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2)
vpcola	0:f1d3878b8dd9	1070	*
vpcola	0:f1d3878b8dd9	1071	* 4 PSTFLT_LEN: Set Postfilter length
vpcola	0:f1d3878b8dd9	1072	* 1 - 16 symbols
vpcola	0:f1d3878b8dd9	1073	* 0 - 8 symbols
vpcola	0:f1d3878b8dd9	1074	*
vpcola	0:f1d3878b8dd9	1075	* 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop
vpcola	0:f1d3878b8dd9	1076	* \endcode
vpcola	0:f1d3878b8dd9	1077	*/
vpcola	0:f1d3878b8dd9	1078
vpcola	0:f1d3878b8dd9	1079	#define CLOCKREC_BASE ((uint8_t)0x23) /!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols /
vpcola	0:f1d3878b8dd9	1080
vpcola	0:f1d3878b8dd9	1081	/**
vpcola	0:f1d3878b8dd9	1082	* @}
vpcola	0:f1d3878b8dd9	1083	*/
vpcola	0:f1d3878b8dd9	1084
vpcola	0:f1d3878b8dd9	1085	/** @defgroup AGCCTRL2_Register
vpcola	0:f1d3878b8dd9	1086	* @{
vpcola	0:f1d3878b8dd9	1087	*/
vpcola	0:f1d3878b8dd9	1088
vpcola	0:f1d3878b8dd9	1089	/**
vpcola	0:f1d3878b8dd9	1090	* \brief AGCCTRL2 register
vpcola	0:f1d3878b8dd9	1091	* \code
vpcola	0:f1d3878b8dd9	1092	* Read Write
vpcola	0:f1d3878b8dd9	1093	* Default value: 0x22
vpcola	0:f1d3878b8dd9	1094	*
vpcola	0:f1d3878b8dd9	1095	* 7 Reserved
vpcola	0:f1d3878b8dd9	1096	*
vpcola	0:f1d3878b8dd9	1097	* 6 FREEZE_ON_STEADY: Enable freezing on steady state
vpcola	0:f1d3878b8dd9	1098	* 1 - Enable
vpcola	0:f1d3878b8dd9	1099	* 0 - Disable
vpcola	0:f1d3878b8dd9	1100	*
vpcola	0:f1d3878b8dd9	1101	* 5 FREEZE_ON_SYNC: Enable freezing on sync detection
vpcola	0:f1d3878b8dd9	1102	* 1 - Enable
vpcola	0:f1d3878b8dd9	1103	* 0 - Disable
vpcola	0:f1d3878b8dd9	1104	*
vpcola	0:f1d3878b8dd9	1105	* 4 START_MAX_ATTENUATION: Start with max attenuation
vpcola	0:f1d3878b8dd9	1106	* 1 - Enable
vpcola	0:f1d3878b8dd9	1107	* 0 - Disable
vpcola	0:f1d3878b8dd9	1108	*
vpcola	0:f1d3878b8dd9	1109	* 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME)
vpcola	0:f1d3878b8dd9	1110	* \endcode
vpcola	0:f1d3878b8dd9	1111	*/
vpcola	0:f1d3878b8dd9	1112	#define AGCCTRL2_BASE ((uint8_t)0x24) /!< AGC freeze strategy, AGC attenuation strategy, AGC measure time /
vpcola	0:f1d3878b8dd9	1113
vpcola	0:f1d3878b8dd9	1114	#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level
vpcola	0:f1d3878b8dd9	1115	is betweeen min and max treshold (see AGCCTRL1) */
vpcola	0:f1d3878b8dd9	1116	#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /!< The attenuation settings will be frozen as soon sync word is detected /
vpcola	0:f1d3878b8dd9	1117	#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /!< The AGC algorithm can start with MAX attenuation or MIN attenuation /
vpcola	0:f1d3878b8dd9	1118
vpcola	0:f1d3878b8dd9	1119	/**
vpcola	0:f1d3878b8dd9	1120	* @}
vpcola	0:f1d3878b8dd9	1121	*/
vpcola	0:f1d3878b8dd9	1122
vpcola	0:f1d3878b8dd9	1123	/** @defgroup AGCCTRL1_Register
vpcola	0:f1d3878b8dd9	1124	* @{
vpcola	0:f1d3878b8dd9	1125	*/
vpcola	0:f1d3878b8dd9	1126
vpcola	0:f1d3878b8dd9	1127	/**
vpcola	0:f1d3878b8dd9	1128	* \brief AGCCTRL1 register
vpcola	0:f1d3878b8dd9	1129	* \code
vpcola	0:f1d3878b8dd9	1130	* Read Write
vpcola	0:f1d3878b8dd9	1131	* Default value: 0x65
vpcola	0:f1d3878b8dd9	1132	*
vpcola	0:f1d3878b8dd9	1133	* 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC
vpcola	0:f1d3878b8dd9	1134	*
vpcola	0:f1d3878b8dd9	1135	* 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC
vpcola	0:f1d3878b8dd9	1136	* \endcode
vpcola	0:f1d3878b8dd9	1137	*/
vpcola	0:f1d3878b8dd9	1138	#define AGCCTRL1_BASE ((uint8_t)0x25) /!< Sets low and high threshold for AGC /
vpcola	0:f1d3878b8dd9	1139
vpcola	0:f1d3878b8dd9	1140	/**
vpcola	0:f1d3878b8dd9	1141	* @}
vpcola	0:f1d3878b8dd9	1142	*/
vpcola	0:f1d3878b8dd9	1143
vpcola	0:f1d3878b8dd9	1144	/** @defgroup AGCCTRL0_Register
vpcola	0:f1d3878b8dd9	1145	* @{
vpcola	0:f1d3878b8dd9	1146	*/
vpcola	0:f1d3878b8dd9	1147
vpcola	0:f1d3878b8dd9	1148	/**
vpcola	0:f1d3878b8dd9	1149	* \brief AGCCTRL0 register
vpcola	0:f1d3878b8dd9	1150	* \code
vpcola	0:f1d3878b8dd9	1151	* Read Write
vpcola	0:f1d3878b8dd9	1152	* Default value: 0x8A
vpcola	0:f1d3878b8dd9	1153	*
vpcola	0:f1d3878b8dd9	1154	* 7 AGC S_ENABLE: Enable AGC
vpcola	0:f1d3878b8dd9	1155	* 1 - Enable
vpcola	0:f1d3878b8dd9	1156	* 0 - Disable
vpcola	0:f1d3878b8dd9	1157	*
vpcola	0:f1d3878b8dd9	1158	* 6 AGC_MODE: Set linear-Binary AGC mode
vpcola	0:f1d3878b8dd9	1159	* 1 - Enable
vpcola	0:f1d3878b8dd9	1160	* 0 - Disable
vpcola	0:f1d3878b8dd9	1161	*
vpcola	0:f1d3878b8dd9	1162	* 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME
vpcola	0:f1d3878b8dd9	1163	* \endcode
vpcola	0:f1d3878b8dd9	1164	*/
vpcola	0:f1d3878b8dd9	1165	#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time
vpcola	0:f1d3878b8dd9	1166	to account signal propagation through RX chain */
vpcola	0:f1d3878b8dd9	1167	#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /!< AGC on/off /
vpcola	0:f1d3878b8dd9	1168	#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode or sequential mode /
vpcola	0:f1d3878b8dd9	1169	#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /!< AGC search correct attenuation in sequential mode (recommended) /
vpcola	0:f1d3878b8dd9	1170	#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode /
vpcola	0:f1d3878b8dd9	1171
vpcola	0:f1d3878b8dd9	1172	/**
vpcola	0:f1d3878b8dd9	1173	* @}
vpcola	0:f1d3878b8dd9	1174	*/
vpcola	0:f1d3878b8dd9	1175
vpcola	0:f1d3878b8dd9	1176	/** @defgroup CHNUM_Register
vpcola	0:f1d3878b8dd9	1177	* @{
vpcola	0:f1d3878b8dd9	1178	*/
vpcola	0:f1d3878b8dd9	1179
vpcola	0:f1d3878b8dd9	1180	/**
vpcola	0:f1d3878b8dd9	1181	* \brief CHNUM registers
vpcola	0:f1d3878b8dd9	1182	* \code
vpcola	0:f1d3878b8dd9	1183	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1184	* Read Write
vpcola	0:f1d3878b8dd9	1185	* 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the
vpcola	0:f1d3878b8dd9	1186	* synthesizer base frequency to generate the actual RF carrier frequency.
vpcola	0:f1d3878b8dd9	1187	* \endcode
vpcola	0:f1d3878b8dd9	1188	*/
vpcola	0:f1d3878b8dd9	1189	#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel
vpcola	0:f1d3878b8dd9	1190	spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */
vpcola	0:f1d3878b8dd9	1191	/**
vpcola	0:f1d3878b8dd9	1192	* @}
vpcola	0:f1d3878b8dd9	1193	*/
vpcola	0:f1d3878b8dd9	1194
vpcola	0:f1d3878b8dd9	1195	/** @defgroup AFC_CORR_Register
vpcola	0:f1d3878b8dd9	1196	* @{
vpcola	0:f1d3878b8dd9	1197	*/
vpcola	0:f1d3878b8dd9	1198
vpcola	0:f1d3878b8dd9	1199	/**
vpcola	0:f1d3878b8dd9	1200	* \brief AFC_CORR registers
vpcola	0:f1d3878b8dd9	1201	* \code
vpcola	0:f1d3878b8dd9	1202	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1203	* Read
vpcola	0:f1d3878b8dd9	1204	*
vpcola	0:f1d3878b8dd9	1205	* 7:0 AFC_CORR[7:0]: AFC word of the received packet
vpcola	0:f1d3878b8dd9	1206	* \endcode
vpcola	0:f1d3878b8dd9	1207	*/
vpcola	0:f1d3878b8dd9	1208	#define AFC_CORR_BASE ((uint8_t)(0xC4)) /!< AFC word of the received packet /
vpcola	0:f1d3878b8dd9	1209
vpcola	0:f1d3878b8dd9	1210	/**
vpcola	0:f1d3878b8dd9	1211	* @}
vpcola	0:f1d3878b8dd9	1212	*/
vpcola	0:f1d3878b8dd9	1213
vpcola	0:f1d3878b8dd9	1214	/**
vpcola	0:f1d3878b8dd9	1215	* @}
vpcola	0:f1d3878b8dd9	1216	*/
vpcola	0:f1d3878b8dd9	1217
vpcola	0:f1d3878b8dd9	1218
vpcola	0:f1d3878b8dd9	1219	/** @defgroup Packet_Configuration_Registers
vpcola	0:f1d3878b8dd9	1220	* @{
vpcola	0:f1d3878b8dd9	1221	*/
vpcola	0:f1d3878b8dd9	1222
vpcola	0:f1d3878b8dd9	1223	/** @defgroup PCKTCTRL4_Register
vpcola	0:f1d3878b8dd9	1224	* @{
vpcola	0:f1d3878b8dd9	1225	*/
vpcola	0:f1d3878b8dd9	1226
vpcola	0:f1d3878b8dd9	1227	/**
vpcola	0:f1d3878b8dd9	1228	* \brief PCKTCTRL4 register
vpcola	0:f1d3878b8dd9	1229	* \code
vpcola	0:f1d3878b8dd9	1230	* Read Write
vpcola	0:f1d3878b8dd9	1231	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1232	*
vpcola	0:f1d3878b8dd9	1233	* 7:5 NOT_USED.
vpcola	0:f1d3878b8dd9	1234	*
vpcola	0:f1d3878b8dd9	1235	* 4:3 ADDRESS_LEN[1:0]: length of address field in bytes
vpcola	0:f1d3878b8dd9	1236	*
vpcola	0:f1d3878b8dd9	1237	* 2:0 control_len[2:0]: length of control field in bytes
vpcola	0:f1d3878b8dd9	1238	* \endcode
vpcola	0:f1d3878b8dd9	1239	*/
vpcola	0:f1d3878b8dd9	1240	#define PCKTCTRL4_BASE ((uint8_t)0x30) /!< lenghts of address and control field /
vpcola	0:f1d3878b8dd9	1241
vpcola	0:f1d3878b8dd9	1242	#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18)
vpcola	0:f1d3878b8dd9	1243	#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07)
vpcola	0:f1d3878b8dd9	1244
vpcola	0:f1d3878b8dd9	1245	/**
vpcola	0:f1d3878b8dd9	1246	* @}
vpcola	0:f1d3878b8dd9	1247	*/
vpcola	0:f1d3878b8dd9	1248
vpcola	0:f1d3878b8dd9	1249	/** @defgroup PCKTCTRL3_Register
vpcola	0:f1d3878b8dd9	1250	* @{
vpcola	0:f1d3878b8dd9	1251	*/
vpcola	0:f1d3878b8dd9	1252
vpcola	0:f1d3878b8dd9	1253	/**
vpcola	0:f1d3878b8dd9	1254	* \brief PCKTCTRL3 register
vpcola	0:f1d3878b8dd9	1255	* \code
vpcola	0:f1d3878b8dd9	1256	* Read Write
vpcola	0:f1d3878b8dd9	1257	* Default value: 0x07
vpcola	0:f1d3878b8dd9	1258	*
vpcola	0:f1d3878b8dd9	1259	* 7:6 PCKT_FRMT[1:0]: format of packet
vpcola	0:f1d3878b8dd9	1260	*
vpcola	0:f1d3878b8dd9	1261	* PCKT_FRMT1 \| PCKT_FRMT0 \| Format
vpcola	0:f1d3878b8dd9	1262	* ----------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	1263	* 0 \| 0 \| BASIC
vpcola	0:f1d3878b8dd9	1264	* 1 \| 0 \| MBUS
vpcola	0:f1d3878b8dd9	1265	* 1 \| 1 \| STACK
vpcola	0:f1d3878b8dd9	1266	*
vpcola	0:f1d3878b8dd9	1267	* 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes
vpcola	0:f1d3878b8dd9	1268	*
vpcola	0:f1d3878b8dd9	1269	* RX_MODE1 \| RX_MODE0 \| Rx Mode
vpcola	0:f1d3878b8dd9	1270	* --------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	1271	* 0 \| 0 \| normal
vpcola	0:f1d3878b8dd9	1272	* 0 \| 1 \| direct through FIFO
vpcola	0:f1d3878b8dd9	1273	* 1 \| 0 \| direct through GPIO
vpcola	0:f1d3878b8dd9	1274	*
vpcola	0:f1d3878b8dd9	1275	* 3:0 LEN_WID[3:0]: length of length field in bits
vpcola	0:f1d3878b8dd9	1276	* \endcode
vpcola	0:f1d3878b8dd9	1277	*/
vpcola	0:f1d3878b8dd9	1278	#define PCKTCTRL3_BASE ((uint8_t)0x31) /!< packet format, RX mode, lenght of length field /
vpcola	0:f1d3878b8dd9	1279
vpcola	0:f1d3878b8dd9	1280	#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /!< Basic Packet Format /
vpcola	0:f1d3878b8dd9	1281	#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /!< Wireless M-BUS Packet Format /
vpcola	0:f1d3878b8dd9	1282	#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /!< STack Packet Format /
vpcola	0:f1d3878b8dd9	1283
vpcola	0:f1d3878b8dd9	1284	#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /!< Normal RX Mode /
vpcola	0:f1d3878b8dd9	1285	#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /!< RX Direct Mode; data available through FIFO /
vpcola	0:f1d3878b8dd9	1286	#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /!< RX Direct Mode; data available through selected GPIO /
vpcola	0:f1d3878b8dd9	1287
vpcola	0:f1d3878b8dd9	1288	#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0)
vpcola	0:f1d3878b8dd9	1289	#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30)
vpcola	0:f1d3878b8dd9	1290	#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F)
vpcola	0:f1d3878b8dd9	1291
vpcola	0:f1d3878b8dd9	1292	/**
vpcola	0:f1d3878b8dd9	1293	* @}
vpcola	0:f1d3878b8dd9	1294	*/
vpcola	0:f1d3878b8dd9	1295
vpcola	0:f1d3878b8dd9	1296	/** @defgroup PCKTCTRL2_Register
vpcola	0:f1d3878b8dd9	1297	* @{
vpcola	0:f1d3878b8dd9	1298	*/
vpcola	0:f1d3878b8dd9	1299
vpcola	0:f1d3878b8dd9	1300	/**
vpcola	0:f1d3878b8dd9	1301	* \brief PCKTCTRL2 register
vpcola	0:f1d3878b8dd9	1302	* \code
vpcola	0:f1d3878b8dd9	1303	* Read Write
vpcola	0:f1d3878b8dd9	1304	* Default value: 0x1E
vpcola	0:f1d3878b8dd9	1305	*
vpcola	0:f1d3878b8dd9	1306	* 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31)
vpcola	0:f1d3878b8dd9	1307	*
vpcola	0:f1d3878b8dd9	1308	*
vpcola	0:f1d3878b8dd9	1309	* 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes
vpcola	0:f1d3878b8dd9	1310	*
vpcola	0:f1d3878b8dd9	1311	*
vpcola	0:f1d3878b8dd9	1312	* 0 FIX_VAR_LEN: fixed/variable packet length
vpcola	0:f1d3878b8dd9	1313	* 1 - Variable
vpcola	0:f1d3878b8dd9	1314	* 0 - Fixed
vpcola	0:f1d3878b8dd9	1315	* \endcode
vpcola	0:f1d3878b8dd9	1316	*/
vpcola	0:f1d3878b8dd9	1317	#define PCKTCTRL2_BASE ((uint8_t)0x32) /!< length of preamble and sync fields (in bytes), fix or variable packet length /
vpcola	0:f1d3878b8dd9	1318
vpcola	0:f1d3878b8dd9	1319	#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /!< Enable/disable the length mode /
vpcola	0:f1d3878b8dd9	1320	#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8)
vpcola	0:f1d3878b8dd9	1321	#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06)
vpcola	0:f1d3878b8dd9	1322
vpcola	0:f1d3878b8dd9	1323	/**
vpcola	0:f1d3878b8dd9	1324	* @}
vpcola	0:f1d3878b8dd9	1325	*/
vpcola	0:f1d3878b8dd9	1326
vpcola	0:f1d3878b8dd9	1327	/** @defgroup PCKTCTRL1_Register
vpcola	0:f1d3878b8dd9	1328	* @{
vpcola	0:f1d3878b8dd9	1329	*/
vpcola	0:f1d3878b8dd9	1330
vpcola	0:f1d3878b8dd9	1331	/**
vpcola	0:f1d3878b8dd9	1332	* \brief PCKTCTRL1 register
vpcola	0:f1d3878b8dd9	1333	* \code
vpcola	0:f1d3878b8dd9	1334	* Read Write
vpcola	0:f1d3878b8dd9	1335	* Default value: 0x20
vpcola	0:f1d3878b8dd9	1336	*
vpcola	0:f1d3878b8dd9	1337	* 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits)
vpcola	0:f1d3878b8dd9	1338	*
vpcola	0:f1d3878b8dd9	1339	* CRC_MODE2 \| CRC_MODE1 \| CRC_MODE0 \| CRC Mode (n. bits - poly)
vpcola	0:f1d3878b8dd9	1340	* -------------------------------------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	1341	* 0 \| 0 \| 1 \| 8 - 0x07
vpcola	0:f1d3878b8dd9	1342	* 0 \| 1 \| 0 \| 16 - 0x8005
vpcola	0:f1d3878b8dd9	1343	* 0 \| 1 \| 1 \| 16 - 0x1021
vpcola	0:f1d3878b8dd9	1344	* 1 \| 0 \| 0 \| 24 - 0x864CBF
vpcola	0:f1d3878b8dd9	1345	*
vpcola	0:f1d3878b8dd9	1346	* 4 WHIT_EN[0]: Enable Whitening
vpcola	0:f1d3878b8dd9	1347	* 1 - Enable
vpcola	0:f1d3878b8dd9	1348	* 0 - Disable
vpcola	0:f1d3878b8dd9	1349	*
vpcola	0:f1d3878b8dd9	1350	* 3:2 TX_SOURCE[1:0]: length of sync field in bytes
vpcola	0:f1d3878b8dd9	1351	*
vpcola	0:f1d3878b8dd9	1352	* TX_SOURCE1 \| TX_SOURCE0 \| Tx Mode
vpcola	0:f1d3878b8dd9	1353	* --------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	1354	* 0 \| 0 \| normal
vpcola	0:f1d3878b8dd9	1355	* 0 \| 1 \| direct through FIFO
vpcola	0:f1d3878b8dd9	1356	* 1 \| 0 \| direct through GPIO
vpcola	0:f1d3878b8dd9	1357	* 1 \| 1 \| pn9
vpcola	0:f1d3878b8dd9	1358	*
vpcola	0:f1d3878b8dd9	1359	* 1 NOT_USED
vpcola	0:f1d3878b8dd9	1360	*
vpcola	0:f1d3878b8dd9	1361	* 0 FEC_EN: enable FEC
vpcola	0:f1d3878b8dd9	1362	* 1 - FEC in TX , Viterbi decoding in RX
vpcola	0:f1d3878b8dd9	1363	* 0 - Disabled
vpcola	0:f1d3878b8dd9	1364	* \endcode
vpcola	0:f1d3878b8dd9	1365	*/
vpcola	0:f1d3878b8dd9	1366	#define PCKTCTRL1_BASE ((uint8_t)0x33) /!< CRC type, whitening enable, TX mode /
vpcola	0:f1d3878b8dd9	1367
vpcola	0:f1d3878b8dd9	1368	#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /!< Enable/disable the Forward Error Correction /
vpcola	0:f1d3878b8dd9	1369	#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /!< TX source mode /
vpcola	0:f1d3878b8dd9	1370	#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /!< CRC type /
vpcola	0:f1d3878b8dd9	1371	#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /!< Enable/disable the Whitening /
vpcola	0:f1d3878b8dd9	1372
vpcola	0:f1d3878b8dd9	1373	/**
vpcola	0:f1d3878b8dd9	1374	* @}
vpcola	0:f1d3878b8dd9	1375	*/
vpcola	0:f1d3878b8dd9	1376
vpcola	0:f1d3878b8dd9	1377
vpcola	0:f1d3878b8dd9	1378
vpcola	0:f1d3878b8dd9	1379	/** @defgroup PCKTLEN1_Register
vpcola	0:f1d3878b8dd9	1380	* @{
vpcola	0:f1d3878b8dd9	1381	*/
vpcola	0:f1d3878b8dd9	1382
vpcola	0:f1d3878b8dd9	1383	/**
vpcola	0:f1d3878b8dd9	1384	* \brief PCKTLEN1 register
vpcola	0:f1d3878b8dd9	1385	* \code
vpcola	0:f1d3878b8dd9	1386	* Read Write
vpcola	0:f1d3878b8dd9	1387	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1388	*
vpcola	0:f1d3878b8dd9	1389	* 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256
vpcola	0:f1d3878b8dd9	1390	* \endcode
vpcola	0:f1d3878b8dd9	1391	*/
vpcola	0:f1d3878b8dd9	1392	#define PCKTLEN1_BASE ((uint8_t)0x34) /!< lenght of packet in bytes (upper field) /
vpcola	0:f1d3878b8dd9	1393
vpcola	0:f1d3878b8dd9	1394	/**
vpcola	0:f1d3878b8dd9	1395	* @}
vpcola	0:f1d3878b8dd9	1396	*/
vpcola	0:f1d3878b8dd9	1397
vpcola	0:f1d3878b8dd9	1398	/** @defgroup PCKTLEN0_Register
vpcola	0:f1d3878b8dd9	1399	* @{
vpcola	0:f1d3878b8dd9	1400	*/
vpcola	0:f1d3878b8dd9	1401
vpcola	0:f1d3878b8dd9	1402	/**
vpcola	0:f1d3878b8dd9	1403	* \brief PCKTLEN0 register
vpcola	0:f1d3878b8dd9	1404	* \code
vpcola	0:f1d3878b8dd9	1405	* Read Write
vpcola	0:f1d3878b8dd9	1406	* Default value: 0x14
vpcola	0:f1d3878b8dd9	1407	*
vpcola	0:f1d3878b8dd9	1408	* 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256
vpcola	0:f1d3878b8dd9	1409	* \endcode
vpcola	0:f1d3878b8dd9	1410	*/
vpcola	0:f1d3878b8dd9	1411	#define PCKTLEN0_BASE ((uint8_t)0x35) /!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]/
vpcola	0:f1d3878b8dd9	1412
vpcola	0:f1d3878b8dd9	1413	/**
vpcola	0:f1d3878b8dd9	1414	* @}
vpcola	0:f1d3878b8dd9	1415	*/
vpcola	0:f1d3878b8dd9	1416
vpcola	0:f1d3878b8dd9	1417	/** @defgroup SYNCx_Registers
vpcola	0:f1d3878b8dd9	1418	* @{
vpcola	0:f1d3878b8dd9	1419	*/
vpcola	0:f1d3878b8dd9	1420	/**
vpcola	0:f1d3878b8dd9	1421	* \brief SYNCx[4:1] Registers
vpcola	0:f1d3878b8dd9	1422	* \code
vpcola	0:f1d3878b8dd9	1423	* Read Write
vpcola	0:f1d3878b8dd9	1424	* Default value: 0x88
vpcola	0:f1d3878b8dd9	1425	*
vpcola	0:f1d3878b8dd9	1426	* 7:0 SYNCx[7:0]: xth sync word
vpcola	0:f1d3878b8dd9	1427	* \endcode
vpcola	0:f1d3878b8dd9	1428	*/
vpcola	0:f1d3878b8dd9	1429	#define SYNC4_BASE ((uint8_t)0x36) /!< Sync word 4 /
vpcola	0:f1d3878b8dd9	1430	#define SYNC3_BASE ((uint8_t)0x37) /!< Sync word 3 /
vpcola	0:f1d3878b8dd9	1431	#define SYNC2_BASE ((uint8_t)0x38) /!< Sync word 2 /
vpcola	0:f1d3878b8dd9	1432	#define SYNC1_BASE ((uint8_t)0x39) /!< Sync word 1 /
vpcola	0:f1d3878b8dd9	1433
vpcola	0:f1d3878b8dd9	1434	/**
vpcola	0:f1d3878b8dd9	1435	* @}
vpcola	0:f1d3878b8dd9	1436	*/
vpcola	0:f1d3878b8dd9	1437
vpcola	0:f1d3878b8dd9	1438
vpcola	0:f1d3878b8dd9	1439	/** @defgroup MBUS_PRMBL_Register
vpcola	0:f1d3878b8dd9	1440	* @{
vpcola	0:f1d3878b8dd9	1441	*/
vpcola	0:f1d3878b8dd9	1442
vpcola	0:f1d3878b8dd9	1443	/**
vpcola	0:f1d3878b8dd9	1444	* \brief MBUS_PRMBL register
vpcola	0:f1d3878b8dd9	1445	* \code
vpcola	0:f1d3878b8dd9	1446	* Read Write
vpcola	0:f1d3878b8dd9	1447	* Default value: 0x20
vpcola	0:f1d3878b8dd9	1448	*
vpcola	0:f1d3878b8dd9	1449	* 7:0 MBUS_PRMBL[7:0]: MBUS preamble control
vpcola	0:f1d3878b8dd9	1450	* \endcode
vpcola	0:f1d3878b8dd9	1451	*/
vpcola	0:f1d3878b8dd9	1452	#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /!< MBUS preamble lenght (in 01 bit pairs) /
vpcola	0:f1d3878b8dd9	1453
vpcola	0:f1d3878b8dd9	1454	/**
vpcola	0:f1d3878b8dd9	1455	* @}
vpcola	0:f1d3878b8dd9	1456	*/
vpcola	0:f1d3878b8dd9	1457
vpcola	0:f1d3878b8dd9	1458
vpcola	0:f1d3878b8dd9	1459	/** @defgroup MBUS_PSTMBL_Register
vpcola	0:f1d3878b8dd9	1460	* @{
vpcola	0:f1d3878b8dd9	1461	*/
vpcola	0:f1d3878b8dd9	1462
vpcola	0:f1d3878b8dd9	1463	/**
vpcola	0:f1d3878b8dd9	1464	* \brief MBUS_PSTMBL register
vpcola	0:f1d3878b8dd9	1465	* \code
vpcola	0:f1d3878b8dd9	1466	* Read Write
vpcola	0:f1d3878b8dd9	1467	* Default value: 0x20
vpcola	0:f1d3878b8dd9	1468	*
vpcola	0:f1d3878b8dd9	1469	* 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control
vpcola	0:f1d3878b8dd9	1470	* \endcode
vpcola	0:f1d3878b8dd9	1471	*/
vpcola	0:f1d3878b8dd9	1472	#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /!< MBUS postamble length (in 01 bit pairs) /
vpcola	0:f1d3878b8dd9	1473
vpcola	0:f1d3878b8dd9	1474	/**
vpcola	0:f1d3878b8dd9	1475	* @}
vpcola	0:f1d3878b8dd9	1476	*/
vpcola	0:f1d3878b8dd9	1477
vpcola	0:f1d3878b8dd9	1478	/** @defgroup MBUS_CTRL_Register
vpcola	0:f1d3878b8dd9	1479	* @{
vpcola	0:f1d3878b8dd9	1480	*/
vpcola	0:f1d3878b8dd9	1481
vpcola	0:f1d3878b8dd9	1482	/**
vpcola	0:f1d3878b8dd9	1483	* \brief MBUS_CTRL register
vpcola	0:f1d3878b8dd9	1484	* \code
vpcola	0:f1d3878b8dd9	1485	* Read Write
vpcola	0:f1d3878b8dd9	1486	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1487	*
vpcola	0:f1d3878b8dd9	1488	* 7:4 NOT_USED
vpcola	0:f1d3878b8dd9	1489	*
vpcola	0:f1d3878b8dd9	1490	* 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5)
vpcola	0:f1d3878b8dd9	1491	*
vpcola	0:f1d3878b8dd9	1492	* 0 NOT_USED
vpcola	0:f1d3878b8dd9	1493	* \endcode
vpcola	0:f1d3878b8dd9	1494	*/
vpcola	0:f1d3878b8dd9	1495	#define MBUS_CTRL_BASE ((uint8_t)0x3D) /!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) /
vpcola	0:f1d3878b8dd9	1496
vpcola	0:f1d3878b8dd9	1497	#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester /
vpcola	0:f1d3878b8dd9	1498	#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester /
vpcola	0:f1d3878b8dd9	1499	#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 /
vpcola	0:f1d3878b8dd9	1500	#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester /
vpcola	0:f1d3878b8dd9	1501
vpcola	0:f1d3878b8dd9	1502	/**
vpcola	0:f1d3878b8dd9	1503	* @}
vpcola	0:f1d3878b8dd9	1504	*/
vpcola	0:f1d3878b8dd9	1505
vpcola	0:f1d3878b8dd9	1506
vpcola	0:f1d3878b8dd9	1507
vpcola	0:f1d3878b8dd9	1508	/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers
vpcola	0:f1d3878b8dd9	1509	* @{
vpcola	0:f1d3878b8dd9	1510	*/
vpcola	0:f1d3878b8dd9	1511
vpcola	0:f1d3878b8dd9	1512	/**
vpcola	0:f1d3878b8dd9	1513	* \brief PCKT_FLT_GOALS_CONTROLx_MASK registers
vpcola	0:f1d3878b8dd9	1514	* \code
vpcola	0:f1d3878b8dd9	1515	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1516	* Read Write
vpcola	0:f1d3878b8dd9	1517	* 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering
vpcola	0:f1d3878b8dd9	1518	*
vpcola	0:f1d3878b8dd9	1519	* \endcode
vpcola	0:f1d3878b8dd9	1520	*/
vpcola	0:f1d3878b8dd9	1521	#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /!< Packet control field #3 mask, all 0s -> no filtering /
vpcola	0:f1d3878b8dd9	1522
vpcola	0:f1d3878b8dd9	1523	#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /!< Packet control field #2 mask, all 0s -> no filtering /
vpcola	0:f1d3878b8dd9	1524
vpcola	0:f1d3878b8dd9	1525	#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /!< Packet control field #1 mask, all 0s -> no filtering /
vpcola	0:f1d3878b8dd9	1526
vpcola	0:f1d3878b8dd9	1527	#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /!< Packet control field #0 mask, all 0s -> no filtering /
vpcola	0:f1d3878b8dd9	1528
vpcola	0:f1d3878b8dd9	1529	/**
vpcola	0:f1d3878b8dd9	1530	* @}
vpcola	0:f1d3878b8dd9	1531	*/
vpcola	0:f1d3878b8dd9	1532
vpcola	0:f1d3878b8dd9	1533	/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers
vpcola	0:f1d3878b8dd9	1534	* @{
vpcola	0:f1d3878b8dd9	1535	*/
vpcola	0:f1d3878b8dd9	1536
vpcola	0:f1d3878b8dd9	1537	/**
vpcola	0:f1d3878b8dd9	1538	* \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers
vpcola	0:f1d3878b8dd9	1539	* \code
vpcola	0:f1d3878b8dd9	1540	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1541	* Read Write
vpcola	0:f1d3878b8dd9	1542	* 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference
vpcola	0:f1d3878b8dd9	1543	*
vpcola	0:f1d3878b8dd9	1544	* \endcode
vpcola	0:f1d3878b8dd9	1545	*/
vpcola	0:f1d3878b8dd9	1546	#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /!< Control field (byte #3) /
vpcola	0:f1d3878b8dd9	1547
vpcola	0:f1d3878b8dd9	1548	#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /!< Control field (byte #2) /
vpcola	0:f1d3878b8dd9	1549
vpcola	0:f1d3878b8dd9	1550	#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /!< Control field (byte #1) /
vpcola	0:f1d3878b8dd9	1551
vpcola	0:f1d3878b8dd9	1552	#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /!< Control field (byte #0) /
vpcola	0:f1d3878b8dd9	1553
vpcola	0:f1d3878b8dd9	1554	/**
vpcola	0:f1d3878b8dd9	1555	* @}
vpcola	0:f1d3878b8dd9	1556	*/
vpcola	0:f1d3878b8dd9	1557
vpcola	0:f1d3878b8dd9	1558	/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register
vpcola	0:f1d3878b8dd9	1559	* @{
vpcola	0:f1d3878b8dd9	1560	*/
vpcola	0:f1d3878b8dd9	1561
vpcola	0:f1d3878b8dd9	1562	/**
vpcola	0:f1d3878b8dd9	1563	* \brief PCKT_FLT_GOALS_SOURCE_MASK register
vpcola	0:f1d3878b8dd9	1564	* \code
vpcola	0:f1d3878b8dd9	1565	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1566	* Read Write
vpcola	0:f1d3878b8dd9	1567	* 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering
vpcola	0:f1d3878b8dd9	1568	*
vpcola	0:f1d3878b8dd9	1569	* \endcode
vpcola	0:f1d3878b8dd9	1570	*/
vpcola	0:f1d3878b8dd9	1571	#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /!< Source address mask, valid in RX mode /
vpcola	0:f1d3878b8dd9	1572
vpcola	0:f1d3878b8dd9	1573	/**
vpcola	0:f1d3878b8dd9	1574	* @}
vpcola	0:f1d3878b8dd9	1575	*/
vpcola	0:f1d3878b8dd9	1576
vpcola	0:f1d3878b8dd9	1577	/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register
vpcola	0:f1d3878b8dd9	1578	* @{
vpcola	0:f1d3878b8dd9	1579	*/
vpcola	0:f1d3878b8dd9	1580	/**
vpcola	0:f1d3878b8dd9	1581	* \brief PCKT_FLT_GOALS_SOURCE_ADDR register
vpcola	0:f1d3878b8dd9	1582	* \code
vpcola	0:f1d3878b8dd9	1583	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1584	* Read Write
vpcola	0:f1d3878b8dd9	1585	* 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields
vpcola	0:f1d3878b8dd9	1586	*
vpcola	0:f1d3878b8dd9	1587	* \endcode
vpcola	0:f1d3878b8dd9	1588	*/
vpcola	0:f1d3878b8dd9	1589	#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /!< Source address /
vpcola	0:f1d3878b8dd9	1590
vpcola	0:f1d3878b8dd9	1591	/**
vpcola	0:f1d3878b8dd9	1592	* @}
vpcola	0:f1d3878b8dd9	1593	*/
vpcola	0:f1d3878b8dd9	1594
vpcola	0:f1d3878b8dd9	1595	/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register
vpcola	0:f1d3878b8dd9	1596	* @{
vpcola	0:f1d3878b8dd9	1597	*/
vpcola	0:f1d3878b8dd9	1598
vpcola	0:f1d3878b8dd9	1599	/**
vpcola	0:f1d3878b8dd9	1600	* \brief PCKT_FLT_GOALS_BROADCAST register
vpcola	0:f1d3878b8dd9	1601	* \code
vpcola	0:f1d3878b8dd9	1602	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1603	* Read Write
vpcola	0:f1d3878b8dd9	1604	* 7:0 BROADCAST[7:0]: Address shared for broadcast communication link
vpcola	0:f1d3878b8dd9	1605	*
vpcola	0:f1d3878b8dd9	1606	* \endcode
vpcola	0:f1d3878b8dd9	1607	*/
vpcola	0:f1d3878b8dd9	1608	#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /!< Address shared for broadcast communication links /
vpcola	0:f1d3878b8dd9	1609
vpcola	0:f1d3878b8dd9	1610	/**
vpcola	0:f1d3878b8dd9	1611	* @}
vpcola	0:f1d3878b8dd9	1612	*/
vpcola	0:f1d3878b8dd9	1613
vpcola	0:f1d3878b8dd9	1614	/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register
vpcola	0:f1d3878b8dd9	1615	* @{
vpcola	0:f1d3878b8dd9	1616	*/
vpcola	0:f1d3878b8dd9	1617
vpcola	0:f1d3878b8dd9	1618	/**
vpcola	0:f1d3878b8dd9	1619	* \brief PCKT_FLT_GOALS_MULTICAST register
vpcola	0:f1d3878b8dd9	1620	* \code
vpcola	0:f1d3878b8dd9	1621	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1622	* Read Write
vpcola	0:f1d3878b8dd9	1623	* 7:0 MULTICAST[7:0]: Address shared for multicast communication links
vpcola	0:f1d3878b8dd9	1624	*
vpcola	0:f1d3878b8dd9	1625	* \endcode
vpcola	0:f1d3878b8dd9	1626	*/
vpcola	0:f1d3878b8dd9	1627	#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /!< Address shared for multicast communication links /
vpcola	0:f1d3878b8dd9	1628
vpcola	0:f1d3878b8dd9	1629	/**
vpcola	0:f1d3878b8dd9	1630	* @}
vpcola	0:f1d3878b8dd9	1631	*/
vpcola	0:f1d3878b8dd9	1632
vpcola	0:f1d3878b8dd9	1633	/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register
vpcola	0:f1d3878b8dd9	1634	* @{
vpcola	0:f1d3878b8dd9	1635	*/
vpcola	0:f1d3878b8dd9	1636
vpcola	0:f1d3878b8dd9	1637	/**
vpcola	0:f1d3878b8dd9	1638	* \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register
vpcola	0:f1d3878b8dd9	1639	* \code
vpcola	0:f1d3878b8dd9	1640	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1641	* Read Write
vpcola	0:f1d3878b8dd9	1642	* 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields
vpcola	0:f1d3878b8dd9	1643	*
vpcola	0:f1d3878b8dd9	1644	* \endcode
vpcola	0:f1d3878b8dd9	1645	*/
vpcola	0:f1d3878b8dd9	1646	#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /!< Address of the destination (also device own address) /
vpcola	0:f1d3878b8dd9	1647
vpcola	0:f1d3878b8dd9	1648	/**
vpcola	0:f1d3878b8dd9	1649	* @}
vpcola	0:f1d3878b8dd9	1650	*/
vpcola	0:f1d3878b8dd9	1651
vpcola	0:f1d3878b8dd9	1652	/** @defgroup PCKT_FLT_OPTIONS_Register
vpcola	0:f1d3878b8dd9	1653	* @{
vpcola	0:f1d3878b8dd9	1654	*/
vpcola	0:f1d3878b8dd9	1655
vpcola	0:f1d3878b8dd9	1656	/**
vpcola	0:f1d3878b8dd9	1657	* \brief PCKT_FLT_OPTIONS register
vpcola	0:f1d3878b8dd9	1658	* \code
vpcola	0:f1d3878b8dd9	1659	* Default value: 0x70
vpcola	0:f1d3878b8dd9	1660	* Read Write
vpcola	0:f1d3878b8dd9	1661	* 7 Reserved.
vpcola	0:f1d3878b8dd9	1662	*
vpcola	0:f1d3878b8dd9	1663	* 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - OR logical function applied to CS/SQI/PQI
vpcola	0:f1d3878b8dd9	1664	* values (masked by 7:5 bits in PROTOCOL register)
vpcola	0:f1d3878b8dd9	1665	* 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches
vpcola	0:f1d3878b8dd9	1666	* with masked CONTROLx_FIELD registers.
vpcola	0:f1d3878b8dd9	1667	* 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field
vpcola	0:f1d3878b8dd9	1668	* matches w/ masked RX_SOURCE_ADDR register.
vpcola	0:f1d3878b8dd9	1669	* 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination
vpcola	0:f1d3878b8dd9	1670	* address matches with TX_SOURCE_ADDR reg.
vpcola	0:f1d3878b8dd9	1671	* 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination
vpcola	0:f1d3878b8dd9	1672	* address matches with MULTICAST register
vpcola	0:f1d3878b8dd9	1673	* 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination
vpcola	0:f1d3878b8dd9	1674	* address matches with BROADCAST register.
vpcola	0:f1d3878b8dd9	1675	* 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid.
vpcola	0:f1d3878b8dd9	1676	*
vpcola	0:f1d3878b8dd9	1677	* \endcode
vpcola	0:f1d3878b8dd9	1678	*/
vpcola	0:f1d3878b8dd9	1679	#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /!< Options relative to packet filtering /
vpcola	0:f1d3878b8dd9	1680
vpcola	0:f1d3878b8dd9	1681	#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] /
vpcola	0:f1d3878b8dd9	1682	#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /!< Packet discarded if destination address differs from BROADCAST register [RX] /
vpcola	0:f1d3878b8dd9	1683	#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /!< Packet discarded if destination address differs from MULTICAST register [RX] /
vpcola	0:f1d3878b8dd9	1684	#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /!< Packet discarded if destination address differs from TX_ADDR register [RX] /
vpcola	0:f1d3878b8dd9	1685	#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register)
vpcola	0:f1d3878b8dd9	1686	differs from SOURCE_ADDR register [RX] */
vpcola	0:f1d3878b8dd9	1687	#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register)
vpcola	0:f1d3878b8dd9	1688	differs from CONTROLx_FIELD register [RX] */
vpcola	0:f1d3878b8dd9	1689	#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2]
vpcola	0:f1d3878b8dd9	1690	register) */
vpcola	0:f1d3878b8dd9	1691
vpcola	0:f1d3878b8dd9	1692	/**
vpcola	0:f1d3878b8dd9	1693	* @}
vpcola	0:f1d3878b8dd9	1694	*/
vpcola	0:f1d3878b8dd9	1695
vpcola	0:f1d3878b8dd9	1696	/** @defgroup TX_CTRL_FIELD_Registers
vpcola	0:f1d3878b8dd9	1697	* @{
vpcola	0:f1d3878b8dd9	1698	*/
vpcola	0:f1d3878b8dd9	1699
vpcola	0:f1d3878b8dd9	1700	/**
vpcola	0:f1d3878b8dd9	1701	* \brief TX_CTRL_FIELDx registers
vpcola	0:f1d3878b8dd9	1702	* \code
vpcola	0:f1d3878b8dd9	1703	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1704	* Read Write
vpcola	0:f1d3878b8dd9	1705	* 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x
vpcola	0:f1d3878b8dd9	1706	* \endcode
vpcola	0:f1d3878b8dd9	1707	*/
vpcola	0:f1d3878b8dd9	1708	#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /!< Control field value to be used in TX packet as byte n.3 /
vpcola	0:f1d3878b8dd9	1709
vpcola	0:f1d3878b8dd9	1710	#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /!< Control field value to be used in TX packet as byte n.2 /
vpcola	0:f1d3878b8dd9	1711
vpcola	0:f1d3878b8dd9	1712	#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /!< Control field value to be used in TX packet as byte n.1 /
vpcola	0:f1d3878b8dd9	1713
vpcola	0:f1d3878b8dd9	1714	#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /!< Control field value to be used in TX packet as byte n.0 /
vpcola	0:f1d3878b8dd9	1715
vpcola	0:f1d3878b8dd9	1716	/**
vpcola	0:f1d3878b8dd9	1717	* @}
vpcola	0:f1d3878b8dd9	1718	*/
vpcola	0:f1d3878b8dd9	1719
vpcola	0:f1d3878b8dd9	1720
vpcola	0:f1d3878b8dd9	1721	/** @defgroup TX_PCKT_INFO_Register
vpcola	0:f1d3878b8dd9	1722	* @{
vpcola	0:f1d3878b8dd9	1723	*/
vpcola	0:f1d3878b8dd9	1724
vpcola	0:f1d3878b8dd9	1725	/**
vpcola	0:f1d3878b8dd9	1726	* \brief TX_PCKT_INFO registers
vpcola	0:f1d3878b8dd9	1727	* \code
vpcola	0:f1d3878b8dd9	1728	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1729	* Read
vpcola	0:f1d3878b8dd9	1730	*
vpcola	0:f1d3878b8dd9	1731	* 7:6 Not used.
vpcola	0:f1d3878b8dd9	1732	*
vpcola	0:f1d3878b8dd9	1733	* 5:4 TX_SEQ_NUM: Current TX packet sequence number
vpcola	0:f1d3878b8dd9	1734	*
vpcola	0:f1d3878b8dd9	1735	* 0 N_RETX[3:0]: Number of retransmissions done on the
vpcola	0:f1d3878b8dd9	1736	* last TX packet
vpcola	0:f1d3878b8dd9	1737	* \endcode
vpcola	0:f1d3878b8dd9	1738	*/
vpcola	0:f1d3878b8dd9	1739	#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4];
vpcola	0:f1d3878b8dd9	1740	Number of retransmissions done on the last TX packet [3:0]*/
vpcola	0:f1d3878b8dd9	1741	/**
vpcola	0:f1d3878b8dd9	1742	* @}
vpcola	0:f1d3878b8dd9	1743	*/
vpcola	0:f1d3878b8dd9	1744
vpcola	0:f1d3878b8dd9	1745	/** @defgroup RX_PCKT_INFO_Register
vpcola	0:f1d3878b8dd9	1746	* @{
vpcola	0:f1d3878b8dd9	1747	*/
vpcola	0:f1d3878b8dd9	1748
vpcola	0:f1d3878b8dd9	1749	/**
vpcola	0:f1d3878b8dd9	1750	* \brief RX_PCKT_INFO registers
vpcola	0:f1d3878b8dd9	1751	* \code
vpcola	0:f1d3878b8dd9	1752	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1753	* Read
vpcola	0:f1d3878b8dd9	1754	*
vpcola	0:f1d3878b8dd9	1755	* 7:3 Not used.
vpcola	0:f1d3878b8dd9	1756	*
vpcola	0:f1d3878b8dd9	1757	* 2 NACK_RX: NACK field of the received packet
vpcola	0:f1d3878b8dd9	1758	*
vpcola	0:f1d3878b8dd9	1759	* 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet
vpcola	0:f1d3878b8dd9	1760	* \endcode
vpcola	0:f1d3878b8dd9	1761	*/
vpcola	0:f1d3878b8dd9	1762	#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2];
vpcola	0:f1d3878b8dd9	1763	sequence number of the received packet [1:0]*/
vpcola	0:f1d3878b8dd9	1764
vpcola	0:f1d3878b8dd9	1765	#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /!< NACK field of the received packet /
vpcola	0:f1d3878b8dd9	1766
vpcola	0:f1d3878b8dd9	1767	/**
vpcola	0:f1d3878b8dd9	1768	* @}
vpcola	0:f1d3878b8dd9	1769	*/
vpcola	0:f1d3878b8dd9	1770
vpcola	0:f1d3878b8dd9	1771	/** @defgroup RX_PCKT_LEN1
vpcola	0:f1d3878b8dd9	1772	* @{
vpcola	0:f1d3878b8dd9	1773	*/
vpcola	0:f1d3878b8dd9	1774
vpcola	0:f1d3878b8dd9	1775	/**
vpcola	0:f1d3878b8dd9	1776	* \brief RX_PCKT_LEN1 registers
vpcola	0:f1d3878b8dd9	1777	* \code
vpcola	0:f1d3878b8dd9	1778	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1779	* Read
vpcola	0:f1d3878b8dd9	1780	*
vpcola	0:f1d3878b8dd9	1781	* 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
vpcola	0:f1d3878b8dd9	1782	* This value is packet_length/256
vpcola	0:f1d3878b8dd9	1783	* \endcode
vpcola	0:f1d3878b8dd9	1784	*/
vpcola	0:f1d3878b8dd9	1785	#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /!< Length (number of bytes) of the received packet: /
vpcola	0:f1d3878b8dd9	1786
vpcola	0:f1d3878b8dd9	1787	/**
vpcola	0:f1d3878b8dd9	1788	* @}
vpcola	0:f1d3878b8dd9	1789	*/
vpcola	0:f1d3878b8dd9	1790
vpcola	0:f1d3878b8dd9	1791	/** @defgroup RX_PCKT_LEN0
vpcola	0:f1d3878b8dd9	1792	* @{
vpcola	0:f1d3878b8dd9	1793	*/
vpcola	0:f1d3878b8dd9	1794
vpcola	0:f1d3878b8dd9	1795	/**
vpcola	0:f1d3878b8dd9	1796	* \brief RX_PCKT_LEN0 registers
vpcola	0:f1d3878b8dd9	1797	* \code
vpcola	0:f1d3878b8dd9	1798	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1799	* Read
vpcola	0:f1d3878b8dd9	1800	*
vpcola	0:f1d3878b8dd9	1801	* 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
vpcola	0:f1d3878b8dd9	1802	* This value is packet_length%256
vpcola	0:f1d3878b8dd9	1803	* \endcode
vpcola	0:f1d3878b8dd9	1804	*/
vpcola	0:f1d3878b8dd9	1805	#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 /
vpcola	0:f1d3878b8dd9	1806
vpcola	0:f1d3878b8dd9	1807	/**
vpcola	0:f1d3878b8dd9	1808	* @}
vpcola	0:f1d3878b8dd9	1809	*/
vpcola	0:f1d3878b8dd9	1810
vpcola	0:f1d3878b8dd9	1811
vpcola	0:f1d3878b8dd9	1812	/** @defgroup CRC_FIELD_Register
vpcola	0:f1d3878b8dd9	1813	* @{
vpcola	0:f1d3878b8dd9	1814	*/
vpcola	0:f1d3878b8dd9	1815
vpcola	0:f1d3878b8dd9	1816	/**
vpcola	0:f1d3878b8dd9	1817	* \brief CRC_FIELD[2:0] registers
vpcola	0:f1d3878b8dd9	1818	* \code
vpcola	0:f1d3878b8dd9	1819	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1820	* Read
vpcola	0:f1d3878b8dd9	1821	*
vpcola	0:f1d3878b8dd9	1822	* 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet
vpcola	0:f1d3878b8dd9	1823	* \endcode
vpcola	0:f1d3878b8dd9	1824	*/
vpcola	0:f1d3878b8dd9	1825	#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /!< CRC2 field of the received packet /
vpcola	0:f1d3878b8dd9	1826
vpcola	0:f1d3878b8dd9	1827	#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /!< CRC1 field of the received packet /
vpcola	0:f1d3878b8dd9	1828
vpcola	0:f1d3878b8dd9	1829	#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /!< CRC0 field of the received packet /
vpcola	0:f1d3878b8dd9	1830
vpcola	0:f1d3878b8dd9	1831	/**
vpcola	0:f1d3878b8dd9	1832	* @}
vpcola	0:f1d3878b8dd9	1833	*/
vpcola	0:f1d3878b8dd9	1834
vpcola	0:f1d3878b8dd9	1835	/** @defgroup RX_CTRL_FIELD_Register
vpcola	0:f1d3878b8dd9	1836	* @{
vpcola	0:f1d3878b8dd9	1837	*/
vpcola	0:f1d3878b8dd9	1838
vpcola	0:f1d3878b8dd9	1839	/**
vpcola	0:f1d3878b8dd9	1840	* \brief RX_CTRL_FIELD[3:0] registers
vpcola	0:f1d3878b8dd9	1841	* \code
vpcola	0:f1d3878b8dd9	1842	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1843	* Read
vpcola	0:f1d3878b8dd9	1844	*
vpcola	0:f1d3878b8dd9	1845	* 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet
vpcola	0:f1d3878b8dd9	1846	* \endcode
vpcola	0:f1d3878b8dd9	1847	*/
vpcola	0:f1d3878b8dd9	1848	#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /!< CRTL3 Control field of the received packet /
vpcola	0:f1d3878b8dd9	1849
vpcola	0:f1d3878b8dd9	1850	#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /!< CRTL2 Control field of the received packet /
vpcola	0:f1d3878b8dd9	1851
vpcola	0:f1d3878b8dd9	1852	#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /!< CRTL1 Control field of the received packet /
vpcola	0:f1d3878b8dd9	1853
vpcola	0:f1d3878b8dd9	1854	#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /!< CRTL0 Control field of the received packet /
vpcola	0:f1d3878b8dd9	1855
vpcola	0:f1d3878b8dd9	1856	/**
vpcola	0:f1d3878b8dd9	1857	* @}
vpcola	0:f1d3878b8dd9	1858	*/
vpcola	0:f1d3878b8dd9	1859
vpcola	0:f1d3878b8dd9	1860	/** @defgroup RX_ADDR_FIELD_Register
vpcola	0:f1d3878b8dd9	1861	* @{
vpcola	0:f1d3878b8dd9	1862	*/
vpcola	0:f1d3878b8dd9	1863
vpcola	0:f1d3878b8dd9	1864	/**
vpcola	0:f1d3878b8dd9	1865	* \brief RX_ADDR_FIELD[1:0] registers
vpcola	0:f1d3878b8dd9	1866	* \code
vpcola	0:f1d3878b8dd9	1867	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1868	* Read
vpcola	0:f1d3878b8dd9	1869	*
vpcola	0:f1d3878b8dd9	1870	* 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet
vpcola	0:f1d3878b8dd9	1871	* \endcode
vpcola	0:f1d3878b8dd9	1872	*/
vpcola	0:f1d3878b8dd9	1873	#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /!< ADDR1 Address field of the received packet /
vpcola	0:f1d3878b8dd9	1874
vpcola	0:f1d3878b8dd9	1875	#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /!< ADDR0 Address field of the received packet /
vpcola	0:f1d3878b8dd9	1876
vpcola	0:f1d3878b8dd9	1877	/**
vpcola	0:f1d3878b8dd9	1878	* @}
vpcola	0:f1d3878b8dd9	1879	*/
vpcola	0:f1d3878b8dd9	1880
vpcola	0:f1d3878b8dd9	1881	/**
vpcola	0:f1d3878b8dd9	1882	* @}
vpcola	0:f1d3878b8dd9	1883	*/
vpcola	0:f1d3878b8dd9	1884
vpcola	0:f1d3878b8dd9	1885
vpcola	0:f1d3878b8dd9	1886	/** @defgroup Protocol_Registers
vpcola	0:f1d3878b8dd9	1887	* @{
vpcola	0:f1d3878b8dd9	1888	*/
vpcola	0:f1d3878b8dd9	1889
vpcola	0:f1d3878b8dd9	1890	/** @defgroup PROTOCOL2_Register
vpcola	0:f1d3878b8dd9	1891	* @{
vpcola	0:f1d3878b8dd9	1892	*/
vpcola	0:f1d3878b8dd9	1893
vpcola	0:f1d3878b8dd9	1894	/**
vpcola	0:f1d3878b8dd9	1895	* \brief PROTOCOL2 register
vpcola	0:f1d3878b8dd9	1896	* \code
vpcola	0:f1d3878b8dd9	1897	* Default value: 0x06
vpcola	0:f1d3878b8dd9	1898	* Read Write
vpcola	0:f1d3878b8dd9	1899	* 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling
vpcola	0:f1d3878b8dd9	1900	*
vpcola	0:f1d3878b8dd9	1901	* 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling
vpcola	0:f1d3878b8dd9	1902	*
vpcola	0:f1d3878b8dd9	1903	* 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling
vpcola	0:f1d3878b8dd9	1904	*
vpcola	0:f1d3878b8dd9	1905	* 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command.
vpcola	0:f1d3878b8dd9	1906	*
vpcola	0:f1d3878b8dd9	1907	* 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration
vpcola	0:f1d3878b8dd9	1908	*
vpcola	0:f1d3878b8dd9	1909	* 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration
vpcola	0:f1d3878b8dd9	1910	*
vpcola	0:f1d3878b8dd9	1911	* 0 LDCR_MODE[0]: 1 - LDCR mode enabled
vpcola	0:f1d3878b8dd9	1912	*
vpcola	0:f1d3878b8dd9	1913	* \endcode
vpcola	0:f1d3878b8dd9	1914	*/
vpcola	0:f1d3878b8dd9	1915	#define PROTOCOL2_BASE ((uint8_t)0x50) /!< Protocol2 regisetr address /
vpcola	0:f1d3878b8dd9	1916
vpcola	0:f1d3878b8dd9	1917	#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /!< Enable/disable Low duty Cycle mode /
vpcola	0:f1d3878b8dd9	1918	#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /!< Enable/disable VCO automatic calibration /
vpcola	0:f1d3878b8dd9	1919	#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /!< Enable/disable RCO automatic calibration /
vpcola	0:f1d3878b8dd9	1920	#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /!< PQI value contributes to timeout disabling /
vpcola	0:f1d3878b8dd9	1921	#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /!< SQI value contributes to timeout disabling /
vpcola	0:f1d3878b8dd9	1922	#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /!< CS value contributes to timeout disabling /
vpcola	0:f1d3878b8dd9	1923
vpcola	0:f1d3878b8dd9	1924	/**
vpcola	0:f1d3878b8dd9	1925	* @}
vpcola	0:f1d3878b8dd9	1926	*/
vpcola	0:f1d3878b8dd9	1927
vpcola	0:f1d3878b8dd9	1928	/** @defgroup PROTOCOL1_Register
vpcola	0:f1d3878b8dd9	1929	* @{
vpcola	0:f1d3878b8dd9	1930	*/
vpcola	0:f1d3878b8dd9	1931
vpcola	0:f1d3878b8dd9	1932	/**
vpcola	0:f1d3878b8dd9	1933	* \brief PROTOCOL1 register
vpcola	0:f1d3878b8dd9	1934	* \code
vpcola	0:f1d3878b8dd9	1935	* Default value: 0x00
vpcola	0:f1d3878b8dd9	1936	* Read Write
vpcola	0:f1d3878b8dd9	1937	* 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers
vpcola	0:f1d3878b8dd9	1938	*
vpcola	0:f1d3878b8dd9	1939	* 6 PIGGYBACKING: 1 - PIGGYBACKING enabled
vpcola	0:f1d3878b8dd9	1940	*
vpcola	0:f1d3878b8dd9	1941	* 5:4 Reserved.
vpcola	0:f1d3878b8dd9	1942	*
vpcola	0:f1d3878b8dd9	1943	* 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator
vpcola	0:f1d3878b8dd9	1944	* seed using the value written in the
vpcola	0:f1d3878b8dd9	1945	* BU_COUNTER_SEED_MSByte / LSByte registers
vpcola	0:f1d3878b8dd9	1946	*
vpcola	0:f1d3878b8dd9	1947	* 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled
vpcola	0:f1d3878b8dd9	1948	*
vpcola	0:f1d3878b8dd9	1949	* 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled
vpcola	0:f1d3878b8dd9	1950	*
vpcola	0:f1d3878b8dd9	1951	* 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled
vpcola	0:f1d3878b8dd9	1952	*
vpcola	0:f1d3878b8dd9	1953	* \endcode
vpcola	0:f1d3878b8dd9	1954	*/
vpcola	0:f1d3878b8dd9	1955	#define PROTOCOL1_BASE ((uint8_t)0x51) /!< Protocol1 regisetr address /
vpcola	0:f1d3878b8dd9	1956
vpcola	0:f1d3878b8dd9	1957	#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /!< Enable/disable automatic packet filtering mode /
vpcola	0:f1d3878b8dd9	1958	#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /!< Enable/disable CSMA persistent (no back-off) /
vpcola	0:f1d3878b8dd9	1959	#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /!< Enable/disable CSMA channel access mode /
vpcola	0:f1d3878b8dd9	1960	#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /!< Reloads the seed of the PN generator for CSMA procedure /
vpcola	0:f1d3878b8dd9	1961	#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /!< Enable/disable Piggybacking /
vpcola	0:f1d3878b8dd9	1962	#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers /
vpcola	0:f1d3878b8dd9	1963
vpcola	0:f1d3878b8dd9	1964	/**
vpcola	0:f1d3878b8dd9	1965	* @}
vpcola	0:f1d3878b8dd9	1966	*/
vpcola	0:f1d3878b8dd9	1967
vpcola	0:f1d3878b8dd9	1968	/** @defgroup PROTOCOL0_Register
vpcola	0:f1d3878b8dd9	1969	* @{
vpcola	0:f1d3878b8dd9	1970	*/
vpcola	0:f1d3878b8dd9	1971
vpcola	0:f1d3878b8dd9	1972	/**
vpcola	0:f1d3878b8dd9	1973	* \brief PROTOCOL0 register
vpcola	0:f1d3878b8dd9	1974	* \code
vpcola	0:f1d3878b8dd9	1975	* Default value: 0x08
vpcola	0:f1d3878b8dd9	1976	* Read Write
vpcola	0:f1d3878b8dd9	1977	* 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed
vpcola	0:f1d3878b8dd9	1978	*
vpcola	0:f1d3878b8dd9	1979	* 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet
vpcola	0:f1d3878b8dd9	1980	*
vpcola	0:f1d3878b8dd9	1981	* 2 AUTO_ACK[0]: 1 - automatic ack after RX
vpcola	0:f1d3878b8dd9	1982	*
vpcola	0:f1d3878b8dd9	1983	* 1 PERS_RX[0]: 1 - persistent reception enabled
vpcola	0:f1d3878b8dd9	1984	*
vpcola	0:f1d3878b8dd9	1985	* 0 PERS_TX[0]: 1 - persistent transmission enabled
vpcola	0:f1d3878b8dd9	1986	*
vpcola	0:f1d3878b8dd9	1987	* \endcode
vpcola	0:f1d3878b8dd9	1988	*/
vpcola	0:f1d3878b8dd9	1989	#define PROTOCOL0_BASE ((uint8_t)0x52) /!< Persistent RX/TX, autoack, Max number of retransmissions /
vpcola	0:f1d3878b8dd9	1990
vpcola	0:f1d3878b8dd9	1991	#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /!< Enables persistent transmission /
vpcola	0:f1d3878b8dd9	1992	#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /!< Enables persistent reception /
vpcola	0:f1d3878b8dd9	1993	#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /!< Enables auto acknowlegment /
vpcola	0:f1d3878b8dd9	1994	#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /!< Writes field NO_ACK=1 on transmitted packet /
vpcola	0:f1d3878b8dd9	1995	#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /!< Retransmission mask /
vpcola	0:f1d3878b8dd9	1996
vpcola	0:f1d3878b8dd9	1997	/**
vpcola	0:f1d3878b8dd9	1998	* @}
vpcola	0:f1d3878b8dd9	1999	*/
vpcola	0:f1d3878b8dd9	2000
vpcola	0:f1d3878b8dd9	2001	/** @defgroup TIMERS5_Register
vpcola	0:f1d3878b8dd9	2002	* @{
vpcola	0:f1d3878b8dd9	2003	*/
vpcola	0:f1d3878b8dd9	2004
vpcola	0:f1d3878b8dd9	2005	/**
vpcola	0:f1d3878b8dd9	2006	* \brief TIMERS5 register
vpcola	0:f1d3878b8dd9	2007	* \code
vpcola	0:f1d3878b8dd9	2008	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2009	* Read Write
vpcola	0:f1d3878b8dd9	2010	* 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value
vpcola	0:f1d3878b8dd9	2011	* \endcode
vpcola	0:f1d3878b8dd9	2012	*/
vpcola	0:f1d3878b8dd9	2013	#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /!< RX operation timeout: prescaler value /
vpcola	0:f1d3878b8dd9	2014
vpcola	0:f1d3878b8dd9	2015	/**
vpcola	0:f1d3878b8dd9	2016	* @}
vpcola	0:f1d3878b8dd9	2017	*/
vpcola	0:f1d3878b8dd9	2018
vpcola	0:f1d3878b8dd9	2019	/** @defgroup TIMERS4_Register
vpcola	0:f1d3878b8dd9	2020	* @{
vpcola	0:f1d3878b8dd9	2021	*/
vpcola	0:f1d3878b8dd9	2022
vpcola	0:f1d3878b8dd9	2023	/**
vpcola	0:f1d3878b8dd9	2024	* \brief TIMERS4 register
vpcola	0:f1d3878b8dd9	2025	* \code
vpcola	0:f1d3878b8dd9	2026	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2027	* Read Write
vpcola	0:f1d3878b8dd9	2028	* 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value
vpcola	0:f1d3878b8dd9	2029	* \endcode
vpcola	0:f1d3878b8dd9	2030	*/
vpcola	0:f1d3878b8dd9	2031	#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /!< RX operation timeout: counter value /
vpcola	0:f1d3878b8dd9	2032
vpcola	0:f1d3878b8dd9	2033	/**
vpcola	0:f1d3878b8dd9	2034	* @}
vpcola	0:f1d3878b8dd9	2035	*/
vpcola	0:f1d3878b8dd9	2036
vpcola	0:f1d3878b8dd9	2037	/** @defgroup TIMERS3_Register
vpcola	0:f1d3878b8dd9	2038	* @{
vpcola	0:f1d3878b8dd9	2039	*/
vpcola	0:f1d3878b8dd9	2040
vpcola	0:f1d3878b8dd9	2041	/**
vpcola	0:f1d3878b8dd9	2042	* \brief TIMERS3 register
vpcola	0:f1d3878b8dd9	2043	* \code
vpcola	0:f1d3878b8dd9	2044	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2045	* Read Write
vpcola	0:f1d3878b8dd9	2046	* 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value
vpcola	0:f1d3878b8dd9	2047	* \endcode
vpcola	0:f1d3878b8dd9	2048	*/
vpcola	0:f1d3878b8dd9	2049	#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /!< LDC Mode: Prescaler of the wake-up timer /
vpcola	0:f1d3878b8dd9	2050
vpcola	0:f1d3878b8dd9	2051	/**
vpcola	0:f1d3878b8dd9	2052	* @}
vpcola	0:f1d3878b8dd9	2053	*/
vpcola	0:f1d3878b8dd9	2054
vpcola	0:f1d3878b8dd9	2055	/** @defgroup TIMERS2_Register
vpcola	0:f1d3878b8dd9	2056	* @{
vpcola	0:f1d3878b8dd9	2057	*/
vpcola	0:f1d3878b8dd9	2058
vpcola	0:f1d3878b8dd9	2059	/**
vpcola	0:f1d3878b8dd9	2060	* \brief TIMERS2 register
vpcola	0:f1d3878b8dd9	2061	* \code
vpcola	0:f1d3878b8dd9	2062	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2063	* Read Write
vpcola	0:f1d3878b8dd9	2064	* 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value
vpcola	0:f1d3878b8dd9	2065	* \endcode
vpcola	0:f1d3878b8dd9	2066	*/
vpcola	0:f1d3878b8dd9	2067	#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /!< LDC Mode: counter of the wake-up timer /
vpcola	0:f1d3878b8dd9	2068
vpcola	0:f1d3878b8dd9	2069	/**
vpcola	0:f1d3878b8dd9	2070	* @}
vpcola	0:f1d3878b8dd9	2071	*/
vpcola	0:f1d3878b8dd9	2072
vpcola	0:f1d3878b8dd9	2073	/** @defgroup TIMERS1_Register
vpcola	0:f1d3878b8dd9	2074	* @{
vpcola	0:f1d3878b8dd9	2075	*/
vpcola	0:f1d3878b8dd9	2076
vpcola	0:f1d3878b8dd9	2077	/**
vpcola	0:f1d3878b8dd9	2078	* \brief TIMERS1 register
vpcola	0:f1d3878b8dd9	2079	* \code
vpcola	0:f1d3878b8dd9	2080	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2081	* Read Write
vpcola	0:f1d3878b8dd9	2082	* 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value
vpcola	0:f1d3878b8dd9	2083	* \endcode
vpcola	0:f1d3878b8dd9	2084	*/
vpcola	0:f1d3878b8dd9	2085	#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /!< LDC Mode: Prescaler part of the reload value /
vpcola	0:f1d3878b8dd9	2086
vpcola	0:f1d3878b8dd9	2087	/**
vpcola	0:f1d3878b8dd9	2088	* @}
vpcola	0:f1d3878b8dd9	2089	*/
vpcola	0:f1d3878b8dd9	2090
vpcola	0:f1d3878b8dd9	2091	/** @defgroup TIMERS0_Register
vpcola	0:f1d3878b8dd9	2092	* @{
vpcola	0:f1d3878b8dd9	2093	*/
vpcola	0:f1d3878b8dd9	2094
vpcola	0:f1d3878b8dd9	2095	/**
vpcola	0:f1d3878b8dd9	2096	* \brief TIMERS0 register
vpcola	0:f1d3878b8dd9	2097	* \code
vpcola	0:f1d3878b8dd9	2098	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2099	* Read Write
vpcola	0:f1d3878b8dd9	2100	* 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value
vpcola	0:f1d3878b8dd9	2101	* \endcode
vpcola	0:f1d3878b8dd9	2102	*/
vpcola	0:f1d3878b8dd9	2103	#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /!< LDC Mode: Counter part of the reload value /
vpcola	0:f1d3878b8dd9	2104
vpcola	0:f1d3878b8dd9	2105	/**
vpcola	0:f1d3878b8dd9	2106	* @}
vpcola	0:f1d3878b8dd9	2107	*/
vpcola	0:f1d3878b8dd9	2108
vpcola	0:f1d3878b8dd9	2109
vpcola	0:f1d3878b8dd9	2110	/** @defgroup CSMA_CONFIG3_Register
vpcola	0:f1d3878b8dd9	2111	* @{
vpcola	0:f1d3878b8dd9	2112	*/
vpcola	0:f1d3878b8dd9	2113
vpcola	0:f1d3878b8dd9	2114	/**
vpcola	0:f1d3878b8dd9	2115	* \brief CSMA_CONFIG3 registers
vpcola	0:f1d3878b8dd9	2116	* \code
vpcola	0:f1d3878b8dd9	2117	* Default value: 0xFF
vpcola	0:f1d3878b8dd9	2118	* Read Write
vpcola	0:f1d3878b8dd9	2119	* 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB)
vpcola	0:f1d3878b8dd9	2120	* \endcode
vpcola	0:f1d3878b8dd9	2121	*/
vpcola	0:f1d3878b8dd9	2122	#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) /
vpcola	0:f1d3878b8dd9	2123
vpcola	0:f1d3878b8dd9	2124	/**
vpcola	0:f1d3878b8dd9	2125	* @}
vpcola	0:f1d3878b8dd9	2126	*/
vpcola	0:f1d3878b8dd9	2127
vpcola	0:f1d3878b8dd9	2128	/** @defgroup CSMA_CONFIG2_Register
vpcola	0:f1d3878b8dd9	2129	* @{
vpcola	0:f1d3878b8dd9	2130	*/
vpcola	0:f1d3878b8dd9	2131
vpcola	0:f1d3878b8dd9	2132	/**
vpcola	0:f1d3878b8dd9	2133	* \brief CSMA_CONFIG2 registers
vpcola	0:f1d3878b8dd9	2134	* \code
vpcola	0:f1d3878b8dd9	2135	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2136	* Read Write
vpcola	0:f1d3878b8dd9	2137	* 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB)
vpcola	0:f1d3878b8dd9	2138	* \endcode
vpcola	0:f1d3878b8dd9	2139	*/
vpcola	0:f1d3878b8dd9	2140	#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) /
vpcola	0:f1d3878b8dd9	2141
vpcola	0:f1d3878b8dd9	2142	/**
vpcola	0:f1d3878b8dd9	2143	* @}
vpcola	0:f1d3878b8dd9	2144	*/
vpcola	0:f1d3878b8dd9	2145
vpcola	0:f1d3878b8dd9	2146	/** @defgroup CSMA_CONFIG1_Register
vpcola	0:f1d3878b8dd9	2147	* @{
vpcola	0:f1d3878b8dd9	2148	*/
vpcola	0:f1d3878b8dd9	2149
vpcola	0:f1d3878b8dd9	2150	/**
vpcola	0:f1d3878b8dd9	2151	* \brief CSMA_CONFIG1 registers
vpcola	0:f1d3878b8dd9	2152	* \code
vpcola	0:f1d3878b8dd9	2153	* Default value: 0x04
vpcola	0:f1d3878b8dd9	2154	* Read Write
vpcola	0:f1d3878b8dd9	2155	* 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
vpcola	0:f1d3878b8dd9	2156	*
vpcola	0:f1d3878b8dd9	2157	* 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit.
vpcola	0:f1d3878b8dd9	2158	* \endcode
vpcola	0:f1d3878b8dd9	2159	*/
vpcola	0:f1d3878b8dd9	2160	#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period /
vpcola	0:f1d3878b8dd9	2161
vpcola	0:f1d3878b8dd9	2162	#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /!< CSMA/CA: Sets CCA period to 64TBIT */
vpcola	0:f1d3878b8dd9	2163	#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /!< CSMA/CA: Sets CCA period to 128TBIT */
vpcola	0:f1d3878b8dd9	2164	#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /!< CSMA/CA: Sets CCA period to 256TBIT */
vpcola	0:f1d3878b8dd9	2165	#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /!< CSMA/CA: Sets CCA period to 512TBIT */
vpcola	0:f1d3878b8dd9	2166
vpcola	0:f1d3878b8dd9	2167	/**
vpcola	0:f1d3878b8dd9	2168	* @}
vpcola	0:f1d3878b8dd9	2169	*/
vpcola	0:f1d3878b8dd9	2170
vpcola	0:f1d3878b8dd9	2171	/** @defgroup CSMA_CONFIG0_Register
vpcola	0:f1d3878b8dd9	2172	* @{
vpcola	0:f1d3878b8dd9	2173	*/
vpcola	0:f1d3878b8dd9	2174
vpcola	0:f1d3878b8dd9	2175	/**
vpcola	0:f1d3878b8dd9	2176	* \brief CSMA_CONFIG0 registers
vpcola	0:f1d3878b8dd9	2177	* \code
vpcola	0:f1d3878b8dd9	2178	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2179	* Read Write
vpcola	0:f1d3878b8dd9	2180	* 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time
vpcola	0:f1d3878b8dd9	2181	*
vpcola	0:f1d3878b8dd9	2182	* 3 Reserved.
vpcola	0:f1d3878b8dd9	2183	*
vpcola	0:f1d3878b8dd9	2184	* 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles.
vpcola	0:f1d3878b8dd9	2185	* \endcode
vpcola	0:f1d3878b8dd9	2186	*/
vpcola	0:f1d3878b8dd9	2187	#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /!< CSMA/CA: CCA lenght; Max number of backoff cycles /
vpcola	0:f1d3878b8dd9	2188
vpcola	0:f1d3878b8dd9	2189	/**
vpcola	0:f1d3878b8dd9	2190	* @}
vpcola	0:f1d3878b8dd9	2191	*/
vpcola	0:f1d3878b8dd9	2192
vpcola	0:f1d3878b8dd9	2193	/**
vpcola	0:f1d3878b8dd9	2194	* @}
vpcola	0:f1d3878b8dd9	2195	*/
vpcola	0:f1d3878b8dd9	2196
vpcola	0:f1d3878b8dd9	2197
vpcola	0:f1d3878b8dd9	2198	/** @defgroup Link_Quality_Registers
vpcola	0:f1d3878b8dd9	2199	* @{
vpcola	0:f1d3878b8dd9	2200	*/
vpcola	0:f1d3878b8dd9	2201
vpcola	0:f1d3878b8dd9	2202	/** @defgroup QI_Register
vpcola	0:f1d3878b8dd9	2203	* @{
vpcola	0:f1d3878b8dd9	2204	*/
vpcola	0:f1d3878b8dd9	2205
vpcola	0:f1d3878b8dd9	2206	/**
vpcola	0:f1d3878b8dd9	2207	* \brief QI register
vpcola	0:f1d3878b8dd9	2208	* \code
vpcola	0:f1d3878b8dd9	2209	* Read Write
vpcola	0:f1d3878b8dd9	2210	* Default value: 0x02
vpcola	0:f1d3878b8dd9	2211	*
vpcola	0:f1d3878b8dd9	2212	* 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8SYNC_LEN - 2SQI_TH
vpcola	0:f1d3878b8dd9	2213	*
vpcola	0:f1d3878b8dd9	2214	* 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR
vpcola	0:f1d3878b8dd9	2215	*
vpcola	0:f1d3878b8dd9	2216	*
vpcola	0:f1d3878b8dd9	2217	* 1 SQI_EN[0]: SQI enable
vpcola	0:f1d3878b8dd9	2218	* 1 - Enable
vpcola	0:f1d3878b8dd9	2219	* 0 - Disable
vpcola	0:f1d3878b8dd9	2220	*
vpcola	0:f1d3878b8dd9	2221	* 0 PQI_EN[0]: PQI enable
vpcola	0:f1d3878b8dd9	2222	* 1 - Enable
vpcola	0:f1d3878b8dd9	2223	* 0 - Disable
vpcola	0:f1d3878b8dd9	2224	* \endcode
vpcola	0:f1d3878b8dd9	2225	*/
vpcola	0:f1d3878b8dd9	2226	#define QI_BASE ((uint8_t)0x3A) /!< QI register /
vpcola	0:f1d3878b8dd9	2227
vpcola	0:f1d3878b8dd9	2228	#define QI_PQI_MASK ((uint8_t)0x01) /!< PQI enable/disable /
vpcola	0:f1d3878b8dd9	2229	#define QI_SQI_MASK ((uint8_t)0x02) /!< SQI enable/disable /
vpcola	0:f1d3878b8dd9	2230
vpcola	0:f1d3878b8dd9	2231	/**
vpcola	0:f1d3878b8dd9	2232	* @}
vpcola	0:f1d3878b8dd9	2233	*/
vpcola	0:f1d3878b8dd9	2234
vpcola	0:f1d3878b8dd9	2235	/** @defgroup LINK_QUALIF2
vpcola	0:f1d3878b8dd9	2236	* @{
vpcola	0:f1d3878b8dd9	2237	*/
vpcola	0:f1d3878b8dd9	2238
vpcola	0:f1d3878b8dd9	2239	/**
vpcola	0:f1d3878b8dd9	2240	* \brief LINK_QUALIF2 registers
vpcola	0:f1d3878b8dd9	2241	* \code
vpcola	0:f1d3878b8dd9	2242	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2243	* Read
vpcola	0:f1d3878b8dd9	2244	*
vpcola	0:f1d3878b8dd9	2245	* 7:0 PQI[7:0]: PQI value of the received packet
vpcola	0:f1d3878b8dd9	2246	* \endcode
vpcola	0:f1d3878b8dd9	2247	*/
vpcola	0:f1d3878b8dd9	2248	#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /!< PQI value of the received packet /
vpcola	0:f1d3878b8dd9	2249
vpcola	0:f1d3878b8dd9	2250	/**
vpcola	0:f1d3878b8dd9	2251	* @}
vpcola	0:f1d3878b8dd9	2252	*/
vpcola	0:f1d3878b8dd9	2253
vpcola	0:f1d3878b8dd9	2254	/** @defgroup LINK_QUALIF1
vpcola	0:f1d3878b8dd9	2255	* @{
vpcola	0:f1d3878b8dd9	2256	*/
vpcola	0:f1d3878b8dd9	2257
vpcola	0:f1d3878b8dd9	2258	/**
vpcola	0:f1d3878b8dd9	2259	* \brief LINK_QUALIF1 registers
vpcola	0:f1d3878b8dd9	2260	* \code
vpcola	0:f1d3878b8dd9	2261	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2262	* Read
vpcola	0:f1d3878b8dd9	2263	*
vpcola	0:f1d3878b8dd9	2264	* 7 CS: Carrier Sense indication
vpcola	0:f1d3878b8dd9	2265	*
vpcola	0:f1d3878b8dd9	2266	* 6:0 SQI[6:0]: SQI value of the received packet
vpcola	0:f1d3878b8dd9	2267	* \endcode
vpcola	0:f1d3878b8dd9	2268	*/
vpcola	0:f1d3878b8dd9	2269	#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /!< Carrier sense indication [7]; SQI value of the received packet /
vpcola	0:f1d3878b8dd9	2270
vpcola	0:f1d3878b8dd9	2271	#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /!< Carrier sense indication [7] /
vpcola	0:f1d3878b8dd9	2272
vpcola	0:f1d3878b8dd9	2273	/**
vpcola	0:f1d3878b8dd9	2274	* @}
vpcola	0:f1d3878b8dd9	2275	*/
vpcola	0:f1d3878b8dd9	2276
vpcola	0:f1d3878b8dd9	2277	/** @defgroup LINK_QUALIF0
vpcola	0:f1d3878b8dd9	2278	* @{
vpcola	0:f1d3878b8dd9	2279	*/
vpcola	0:f1d3878b8dd9	2280
vpcola	0:f1d3878b8dd9	2281	/**
vpcola	0:f1d3878b8dd9	2282	* \brief LINK_QUALIF0 registers
vpcola	0:f1d3878b8dd9	2283	* \code
vpcola	0:f1d3878b8dd9	2284	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2285	* Read
vpcola	0:f1d3878b8dd9	2286	*
vpcola	0:f1d3878b8dd9	2287	* 7:4 LQI [3:0]: LQI value of the received packet
vpcola	0:f1d3878b8dd9	2288	*
vpcola	0:f1d3878b8dd9	2289	* 3:0 AGC_WORD[3:0]: AGC word of the received packet
vpcola	0:f1d3878b8dd9	2290	* \endcode
vpcola	0:f1d3878b8dd9	2291	*/
vpcola	0:f1d3878b8dd9	2292	#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] /
vpcola	0:f1d3878b8dd9	2293
vpcola	0:f1d3878b8dd9	2294	/**
vpcola	0:f1d3878b8dd9	2295	* @}
vpcola	0:f1d3878b8dd9	2296	*/
vpcola	0:f1d3878b8dd9	2297
vpcola	0:f1d3878b8dd9	2298	/** @defgroup RSSI_LEVEL
vpcola	0:f1d3878b8dd9	2299	* @{
vpcola	0:f1d3878b8dd9	2300	*/
vpcola	0:f1d3878b8dd9	2301
vpcola	0:f1d3878b8dd9	2302	/**
vpcola	0:f1d3878b8dd9	2303	* \brief RSSI_LEVEL registers
vpcola	0:f1d3878b8dd9	2304	* \code
vpcola	0:f1d3878b8dd9	2305	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2306	* Read
vpcola	0:f1d3878b8dd9	2307	*
vpcola	0:f1d3878b8dd9	2308	* 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet
vpcola	0:f1d3878b8dd9	2309	* \endcode
vpcola	0:f1d3878b8dd9	2310	*/
vpcola	0:f1d3878b8dd9	2311	#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /!< RSSI level of the received packet /
vpcola	0:f1d3878b8dd9	2312
vpcola	0:f1d3878b8dd9	2313	/**
vpcola	0:f1d3878b8dd9	2314	* @}
vpcola	0:f1d3878b8dd9	2315	*/
vpcola	0:f1d3878b8dd9	2316
vpcola	0:f1d3878b8dd9	2317	/** @defgroup RSSI_FLT_Register
vpcola	0:f1d3878b8dd9	2318	* @{
vpcola	0:f1d3878b8dd9	2319	*/
vpcola	0:f1d3878b8dd9	2320
vpcola	0:f1d3878b8dd9	2321	/**
vpcola	0:f1d3878b8dd9	2322	* \brief RSSI register
vpcola	0:f1d3878b8dd9	2323	* \code
vpcola	0:f1d3878b8dd9	2324	* Read Write
vpcola	0:f1d3878b8dd9	2325	* Default value: 0xF3
vpcola	0:f1d3878b8dd9	2326	* 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter
vpcola	0:f1d3878b8dd9	2327	*
vpcola	0:f1d3878b8dd9	2328	* 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log)
vpcola	0:f1d3878b8dd9	2329	*
vpcola	0:f1d3878b8dd9	2330	* CS_MODE1 \| CS_MODE0 \| CS Mode
vpcola	0:f1d3878b8dd9	2331	* -----------------------------------------------------------------------------------------
vpcola	0:f1d3878b8dd9	2332	* 0 \| 0 \| Static CS
vpcola	0:f1d3878b8dd9	2333	* 0 \| 1 \| Dynamic CS with 6dB dynamic threshold
vpcola	0:f1d3878b8dd9	2334	* 1 \| 0 \| Dynamic CS with 12dB dynamic threshold
vpcola	0:f1d3878b8dd9	2335	* 1 \| 1 \| Dynamic CS with 18dB dynamic threshold
vpcola	0:f1d3878b8dd9	2336	*
vpcola	0:f1d3878b8dd9	2337	* 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay
vpcola	0:f1d3878b8dd9	2338	*
vpcola	0:f1d3878b8dd9	2339	* \endcode
vpcola	0:f1d3878b8dd9	2340	*/
vpcola	0:f1d3878b8dd9	2341	#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate,
vpcola	0:f1d3878b8dd9	2342	higher value is slow and more accurate */
vpcola	0:f1d3878b8dd9	2343	#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /!< Carrier sense mode mask /
vpcola	0:f1d3878b8dd9	2344	#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /!< Carrier sense mode; static carrier sensing /
vpcola	0:f1d3878b8dd9	2345	#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /!< Carrier sense mode; dynamic carrier sensing with 6dB threshold /
vpcola	0:f1d3878b8dd9	2346	#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /!< Carrier sense mode; dynamic carrier sensing with 12dB threshold /
vpcola	0:f1d3878b8dd9	2347	#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /!< Carrier sense mode; dynamic carrier sensing with 18dB threshold /
vpcola	0:f1d3878b8dd9	2348	#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /!< Peak decay control for OOK mask /
vpcola	0:f1d3878b8dd9	2349	#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /!< Peak decay control for OOK: fast decay /
vpcola	0:f1d3878b8dd9	2350	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /!< Peak decay control for OOK: medium_fast decay /
vpcola	0:f1d3878b8dd9	2351	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /!< Peak decay control for OOK: medium_fast decay /
vpcola	0:f1d3878b8dd9	2352	#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /!< Peak decay control for OOK: slow decay /
vpcola	0:f1d3878b8dd9	2353
vpcola	0:f1d3878b8dd9	2354	/**
vpcola	0:f1d3878b8dd9	2355	* @}
vpcola	0:f1d3878b8dd9	2356	*/
vpcola	0:f1d3878b8dd9	2357
vpcola	0:f1d3878b8dd9	2358	/** @defgroup RSSI_TH_Register
vpcola	0:f1d3878b8dd9	2359	* @{
vpcola	0:f1d3878b8dd9	2360	*/
vpcola	0:f1d3878b8dd9	2361
vpcola	0:f1d3878b8dd9	2362	/**
vpcola	0:f1d3878b8dd9	2363	* \brief RSSI_TH register
vpcola	0:f1d3878b8dd9	2364	* \code
vpcola	0:f1d3878b8dd9	2365	* Read Write
vpcola	0:f1d3878b8dd9	2366	* Default value: 0x24
vpcola	0:f1d3878b8dd9	2367	*
vpcola	0:f1d3878b8dd9	2368	* 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20
vpcola	0:f1d3878b8dd9	2369	* \endcode
vpcola	0:f1d3878b8dd9	2370	*/
vpcola	0:f1d3878b8dd9	2371	#define RSSI_TH_BASE ((uint8_t)0x22) /!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm /
vpcola	0:f1d3878b8dd9	2372
vpcola	0:f1d3878b8dd9	2373	/**
vpcola	0:f1d3878b8dd9	2374	* @}
vpcola	0:f1d3878b8dd9	2375	*/
vpcola	0:f1d3878b8dd9	2376
vpcola	0:f1d3878b8dd9	2377	/**
vpcola	0:f1d3878b8dd9	2378	* @}
vpcola	0:f1d3878b8dd9	2379	*/
vpcola	0:f1d3878b8dd9	2380
vpcola	0:f1d3878b8dd9	2381
vpcola	0:f1d3878b8dd9	2382	/** @defgroup FIFO_Registers
vpcola	0:f1d3878b8dd9	2383	* @{
vpcola	0:f1d3878b8dd9	2384	*/
vpcola	0:f1d3878b8dd9	2385
vpcola	0:f1d3878b8dd9	2386	/** @defgroup FIFO_CONFIG3_Register
vpcola	0:f1d3878b8dd9	2387	* @{
vpcola	0:f1d3878b8dd9	2388	*/
vpcola	0:f1d3878b8dd9	2389
vpcola	0:f1d3878b8dd9	2390	/**
vpcola	0:f1d3878b8dd9	2391	* \brief FIFO_CONFIG3 registers
vpcola	0:f1d3878b8dd9	2392	* \code
vpcola	0:f1d3878b8dd9	2393	* Default value: 0x30
vpcola	0:f1d3878b8dd9	2394	* Read Write
vpcola	0:f1d3878b8dd9	2395	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2396	*
vpcola	0:f1d3878b8dd9	2397	* 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo.
vpcola	0:f1d3878b8dd9	2398	*
vpcola	0:f1d3878b8dd9	2399	* \endcode
vpcola	0:f1d3878b8dd9	2400	*/
vpcola	0:f1d3878b8dd9	2401	#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /!< FIFO Almost Full threshold for rx fifo [6:0] /
vpcola	0:f1d3878b8dd9	2402
vpcola	0:f1d3878b8dd9	2403	/**
vpcola	0:f1d3878b8dd9	2404	* @}
vpcola	0:f1d3878b8dd9	2405	*/
vpcola	0:f1d3878b8dd9	2406
vpcola	0:f1d3878b8dd9	2407	/** @defgroup FIFO_CONFIG2_Register
vpcola	0:f1d3878b8dd9	2408	* @{
vpcola	0:f1d3878b8dd9	2409	*/
vpcola	0:f1d3878b8dd9	2410
vpcola	0:f1d3878b8dd9	2411	/**
vpcola	0:f1d3878b8dd9	2412	* \brief FIFO_CONFIG2 registers
vpcola	0:f1d3878b8dd9	2413	* \code
vpcola	0:f1d3878b8dd9	2414	* Default value: 0x30
vpcola	0:f1d3878b8dd9	2415	* Read Write
vpcola	0:f1d3878b8dd9	2416	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2417	*
vpcola	0:f1d3878b8dd9	2418	* 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo.
vpcola	0:f1d3878b8dd9	2419	*
vpcola	0:f1d3878b8dd9	2420	* \endcode
vpcola	0:f1d3878b8dd9	2421	*/
vpcola	0:f1d3878b8dd9	2422	#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /!< FIFO Almost Empty threshold for rx fifo [6:0] /
vpcola	0:f1d3878b8dd9	2423
vpcola	0:f1d3878b8dd9	2424	/**
vpcola	0:f1d3878b8dd9	2425	* @}
vpcola	0:f1d3878b8dd9	2426	*/
vpcola	0:f1d3878b8dd9	2427
vpcola	0:f1d3878b8dd9	2428	/** @defgroup FIFO_CONFIG1_Register
vpcola	0:f1d3878b8dd9	2429	* @{
vpcola	0:f1d3878b8dd9	2430	*/
vpcola	0:f1d3878b8dd9	2431
vpcola	0:f1d3878b8dd9	2432	/**
vpcola	0:f1d3878b8dd9	2433	* \brief FIFO_CONFIG1 registers
vpcola	0:f1d3878b8dd9	2434	* \code
vpcola	0:f1d3878b8dd9	2435	* Default value: 0x30
vpcola	0:f1d3878b8dd9	2436	* Read Write
vpcola	0:f1d3878b8dd9	2437	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2438	*
vpcola	0:f1d3878b8dd9	2439	* 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo.
vpcola	0:f1d3878b8dd9	2440	*
vpcola	0:f1d3878b8dd9	2441	* \endcode
vpcola	0:f1d3878b8dd9	2442	*/
vpcola	0:f1d3878b8dd9	2443	#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /!< FIFO Almost Full threshold for tx fifo [6:0] /
vpcola	0:f1d3878b8dd9	2444
vpcola	0:f1d3878b8dd9	2445	/**
vpcola	0:f1d3878b8dd9	2446	* @}
vpcola	0:f1d3878b8dd9	2447	*/
vpcola	0:f1d3878b8dd9	2448
vpcola	0:f1d3878b8dd9	2449	/** @defgroup FIFO_CONFIG0_Register
vpcola	0:f1d3878b8dd9	2450	* @{
vpcola	0:f1d3878b8dd9	2451	*/
vpcola	0:f1d3878b8dd9	2452
vpcola	0:f1d3878b8dd9	2453	/**
vpcola	0:f1d3878b8dd9	2454	* \brief FIFO_CONFIG0 registers
vpcola	0:f1d3878b8dd9	2455	* \code
vpcola	0:f1d3878b8dd9	2456	* Default value: 0x30
vpcola	0:f1d3878b8dd9	2457	* Read Write
vpcola	0:f1d3878b8dd9	2458	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2459	*
vpcola	0:f1d3878b8dd9	2460	* 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo.
vpcola	0:f1d3878b8dd9	2461	*
vpcola	0:f1d3878b8dd9	2462	* \endcode
vpcola	0:f1d3878b8dd9	2463	*/
vpcola	0:f1d3878b8dd9	2464	#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /!< FIFO Almost Empty threshold for tx fifo [6:0] /
vpcola	0:f1d3878b8dd9	2465
vpcola	0:f1d3878b8dd9	2466	/**
vpcola	0:f1d3878b8dd9	2467	* @}
vpcola	0:f1d3878b8dd9	2468	*/
vpcola	0:f1d3878b8dd9	2469
vpcola	0:f1d3878b8dd9	2470	/** @defgroup LINEAR_FIFO_STATUS1_Register
vpcola	0:f1d3878b8dd9	2471	* @{
vpcola	0:f1d3878b8dd9	2472	*/
vpcola	0:f1d3878b8dd9	2473
vpcola	0:f1d3878b8dd9	2474	/**
vpcola	0:f1d3878b8dd9	2475	* \brief LINEAR_FIFO_STATUS1 registers
vpcola	0:f1d3878b8dd9	2476	* \code
vpcola	0:f1d3878b8dd9	2477	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2478	* Read
vpcola	0:f1d3878b8dd9	2479	*
vpcola	0:f1d3878b8dd9	2480	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2481	*
vpcola	0:f1d3878b8dd9	2482	* 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96)
vpcola	0:f1d3878b8dd9	2483	* \endcode
vpcola	0:f1d3878b8dd9	2484	*/
vpcola	0:f1d3878b8dd9	2485	#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /!< Number of elements in the linear TX FIFO [6:0] (<=96) /
vpcola	0:f1d3878b8dd9	2486
vpcola	0:f1d3878b8dd9	2487	/**
vpcola	0:f1d3878b8dd9	2488	* @}
vpcola	0:f1d3878b8dd9	2489	*/
vpcola	0:f1d3878b8dd9	2490
vpcola	0:f1d3878b8dd9	2491	/** @defgroup LINEAR_FIFO_STATUS0_Register
vpcola	0:f1d3878b8dd9	2492	* @{
vpcola	0:f1d3878b8dd9	2493	*/
vpcola	0:f1d3878b8dd9	2494
vpcola	0:f1d3878b8dd9	2495	/**
vpcola	0:f1d3878b8dd9	2496	* \brief LINEAR_FIFO_STATUS0 registers
vpcola	0:f1d3878b8dd9	2497	* \code
vpcola	0:f1d3878b8dd9	2498	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2499	* Read
vpcola	0:f1d3878b8dd9	2500	*
vpcola	0:f1d3878b8dd9	2501	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2502	*
vpcola	0:f1d3878b8dd9	2503	* 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96)
vpcola	0:f1d3878b8dd9	2504	* \endcode
vpcola	0:f1d3878b8dd9	2505	*/
vpcola	0:f1d3878b8dd9	2506	#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /!< Number of elements in the linear RX FIFO [6:0] (<=96) /
vpcola	0:f1d3878b8dd9	2507
vpcola	0:f1d3878b8dd9	2508	/**
vpcola	0:f1d3878b8dd9	2509	* @}
vpcola	0:f1d3878b8dd9	2510	*/
vpcola	0:f1d3878b8dd9	2511
vpcola	0:f1d3878b8dd9	2512
vpcola	0:f1d3878b8dd9	2513	/**
vpcola	0:f1d3878b8dd9	2514	* @}
vpcola	0:f1d3878b8dd9	2515	*/
vpcola	0:f1d3878b8dd9	2516
vpcola	0:f1d3878b8dd9	2517
vpcola	0:f1d3878b8dd9	2518	/** @defgroup Calibration_Registers
vpcola	0:f1d3878b8dd9	2519	* @{
vpcola	0:f1d3878b8dd9	2520	*/
vpcola	0:f1d3878b8dd9	2521
vpcola	0:f1d3878b8dd9	2522	/** @defgroup RCO_VCO_CALIBR_IN2_Register
vpcola	0:f1d3878b8dd9	2523	* @{
vpcola	0:f1d3878b8dd9	2524	*/
vpcola	0:f1d3878b8dd9	2525
vpcola	0:f1d3878b8dd9	2526	/**
vpcola	0:f1d3878b8dd9	2527	* \brief RCO_VCO_CALIBR_IN2 registers
vpcola	0:f1d3878b8dd9	2528	* \code
vpcola	0:f1d3878b8dd9	2529	* Default value: 0x70
vpcola	0:f1d3878b8dd9	2530	* Read Write
vpcola	0:f1d3878b8dd9	2531	* 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4]
vpcola	0:f1d3878b8dd9	2532	*
vpcola	0:f1d3878b8dd9	2533	* 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits)
vpcola	0:f1d3878b8dd9	2534	* \endcode
vpcola	0:f1d3878b8dd9	2535	*/
vpcola	0:f1d3878b8dd9	2536	#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] /
vpcola	0:f1d3878b8dd9	2537
vpcola	0:f1d3878b8dd9	2538	/**
vpcola	0:f1d3878b8dd9	2539	* @}
vpcola	0:f1d3878b8dd9	2540	*/
vpcola	0:f1d3878b8dd9	2541
vpcola	0:f1d3878b8dd9	2542	/** @defgroup RCO_VCO_CALIBR_IN1_Register
vpcola	0:f1d3878b8dd9	2543	* @{
vpcola	0:f1d3878b8dd9	2544	*/
vpcola	0:f1d3878b8dd9	2545
vpcola	0:f1d3878b8dd9	2546	/**
vpcola	0:f1d3878b8dd9	2547	* \brief RCO_VCO_CALIBR_IN1 registers
vpcola	0:f1d3878b8dd9	2548	* \code
vpcola	0:f1d3878b8dd9	2549	* Default value: 0x48
vpcola	0:f1d3878b8dd9	2550	* Read Write
vpcola	0:f1d3878b8dd9	2551	*
vpcola	0:f1d3878b8dd9	2552	* 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb)
vpcola	0:f1d3878b8dd9	2553	*
vpcola	0:f1d3878b8dd9	2554	* 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode
vpcola	0:f1d3878b8dd9	2555	* \endcode
vpcola	0:f1d3878b8dd9	2556	*/
vpcola	0:f1d3878b8dd9	2557	#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]/
vpcola	0:f1d3878b8dd9	2558
vpcola	0:f1d3878b8dd9	2559	/**
vpcola	0:f1d3878b8dd9	2560	* @}
vpcola	0:f1d3878b8dd9	2561	*/
vpcola	0:f1d3878b8dd9	2562
vpcola	0:f1d3878b8dd9	2563	/** @defgroup RCO_VCO_CALIBR_IN0_Register
vpcola	0:f1d3878b8dd9	2564	* @{
vpcola	0:f1d3878b8dd9	2565	*/
vpcola	0:f1d3878b8dd9	2566
vpcola	0:f1d3878b8dd9	2567	/**
vpcola	0:f1d3878b8dd9	2568	* \brief RCO_VCO_CALIBR_IN0 registers
vpcola	0:f1d3878b8dd9	2569	* \code
vpcola	0:f1d3878b8dd9	2570	* Default value: 0x48
vpcola	0:f1d3878b8dd9	2571	* Read Write
vpcola	0:f1d3878b8dd9	2572	*
vpcola	0:f1d3878b8dd9	2573	* 7 Reserved.
vpcola	0:f1d3878b8dd9	2574	*
vpcola	0:f1d3878b8dd9	2575	* 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode
vpcola	0:f1d3878b8dd9	2576	* \endcode
vpcola	0:f1d3878b8dd9	2577	*/
vpcola	0:f1d3878b8dd9	2578	#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /!< Word value for the VCO to be used in RX mode [6:0] /
vpcola	0:f1d3878b8dd9	2579
vpcola	0:f1d3878b8dd9	2580	/**
vpcola	0:f1d3878b8dd9	2581	* @}
vpcola	0:f1d3878b8dd9	2582	*/
vpcola	0:f1d3878b8dd9	2583
vpcola	0:f1d3878b8dd9	2584	/** @defgroup RCO_VCO_CALIBR_OUT1_Register
vpcola	0:f1d3878b8dd9	2585	* @{
vpcola	0:f1d3878b8dd9	2586	*/
vpcola	0:f1d3878b8dd9	2587
vpcola	0:f1d3878b8dd9	2588	/**
vpcola	0:f1d3878b8dd9	2589	* \brief RCO_VCO_CALIBR_OUT1 registers
vpcola	0:f1d3878b8dd9	2590	* \code
vpcola	0:f1d3878b8dd9	2591	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2592	* Read
vpcola	0:f1d3878b8dd9	2593	*
vpcola	0:f1d3878b8dd9	2594	* 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator
vpcola	0:f1d3878b8dd9	2595	*
vpcola	0:f1d3878b8dd9	2596	* 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part)
vpcola	0:f1d3878b8dd9	2597	* \endcode
vpcola	0:f1d3878b8dd9	2598	*/
vpcola	0:f1d3878b8dd9	2599	#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7];
vpcola	0:f1d3878b8dd9	2600	ResistorFineBit RFB word from internal RCO oscillator [6:0] */
vpcola	0:f1d3878b8dd9	2601	/**
vpcola	0:f1d3878b8dd9	2602	* @}
vpcola	0:f1d3878b8dd9	2603	*/
vpcola	0:f1d3878b8dd9	2604
vpcola	0:f1d3878b8dd9	2605	/** @defgroup RCO_VCO_CALIBR_OUT0_Register
vpcola	0:f1d3878b8dd9	2606	* @{
vpcola	0:f1d3878b8dd9	2607	*/
vpcola	0:f1d3878b8dd9	2608
vpcola	0:f1d3878b8dd9	2609	/**
vpcola	0:f1d3878b8dd9	2610	* \brief RCO_VCO_CALIBR_OUT0 registers
vpcola	0:f1d3878b8dd9	2611	* \code
vpcola	0:f1d3878b8dd9	2612	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2613	* Read
vpcola	0:f1d3878b8dd9	2614	*
vpcola	0:f1d3878b8dd9	2615	* 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB)
vpcola	0:f1d3878b8dd9	2616	*
vpcola	0:f1d3878b8dd9	2617	* 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator
vpcola	0:f1d3878b8dd9	2618	* \endcode
vpcola	0:f1d3878b8dd9	2619	*/
vpcola	0:f1d3878b8dd9	2620	#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0];
vpcola	0:f1d3878b8dd9	2621	Output word from internal calibrator [6:0]; */
vpcola	0:f1d3878b8dd9	2622	/**
vpcola	0:f1d3878b8dd9	2623	* @}
vpcola	0:f1d3878b8dd9	2624	*/
vpcola	0:f1d3878b8dd9	2625
vpcola	0:f1d3878b8dd9	2626	/**
vpcola	0:f1d3878b8dd9	2627	* @}
vpcola	0:f1d3878b8dd9	2628	*/
vpcola	0:f1d3878b8dd9	2629
vpcola	0:f1d3878b8dd9	2630
vpcola	0:f1d3878b8dd9	2631	/** @defgroup AES_Registers
vpcola	0:f1d3878b8dd9	2632	* @{
vpcola	0:f1d3878b8dd9	2633	*/
vpcola	0:f1d3878b8dd9	2634
vpcola	0:f1d3878b8dd9	2635	/** @defgroup AES_KEY_IN_Register
vpcola	0:f1d3878b8dd9	2636	* @{
vpcola	0:f1d3878b8dd9	2637	*/
vpcola	0:f1d3878b8dd9	2638
vpcola	0:f1d3878b8dd9	2639	/**
vpcola	0:f1d3878b8dd9	2640	* \brief AES_KEY_INx registers
vpcola	0:f1d3878b8dd9	2641	* \code
vpcola	0:f1d3878b8dd9	2642	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2643	* Read Write
vpcola	0:f1d3878b8dd9	2644	*
vpcola	0:f1d3878b8dd9	2645	* 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits)
vpcola	0:f1d3878b8dd9	2646	* \endcode
vpcola	0:f1d3878b8dd9	2647	*/
vpcola	0:f1d3878b8dd9	2648	#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /!< AES engine key input 15 /
vpcola	0:f1d3878b8dd9	2649
vpcola	0:f1d3878b8dd9	2650	#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /!< AES engine key input 14 /
vpcola	0:f1d3878b8dd9	2651
vpcola	0:f1d3878b8dd9	2652	#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /!< AES engine key input 13 /
vpcola	0:f1d3878b8dd9	2653
vpcola	0:f1d3878b8dd9	2654	#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /!< AES engine key input 12 /
vpcola	0:f1d3878b8dd9	2655
vpcola	0:f1d3878b8dd9	2656	#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /!< AES engine key input 11 /
vpcola	0:f1d3878b8dd9	2657
vpcola	0:f1d3878b8dd9	2658	#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /!< AES engine key input 10 /
vpcola	0:f1d3878b8dd9	2659
vpcola	0:f1d3878b8dd9	2660	#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /!< AES engine key input 9 /
vpcola	0:f1d3878b8dd9	2661
vpcola	0:f1d3878b8dd9	2662	#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /!< AES engine key input 8 /
vpcola	0:f1d3878b8dd9	2663
vpcola	0:f1d3878b8dd9	2664	#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /!< AES engine key input 7 /
vpcola	0:f1d3878b8dd9	2665
vpcola	0:f1d3878b8dd9	2666	#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /!< AES engine key input 6 /
vpcola	0:f1d3878b8dd9	2667
vpcola	0:f1d3878b8dd9	2668	#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /!< AES engine key input 5 /
vpcola	0:f1d3878b8dd9	2669
vpcola	0:f1d3878b8dd9	2670	#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /!< AES engine key input 4 /
vpcola	0:f1d3878b8dd9	2671
vpcola	0:f1d3878b8dd9	2672	#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /!< AES engine key input 3 /
vpcola	0:f1d3878b8dd9	2673
vpcola	0:f1d3878b8dd9	2674	#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /!< AES engine key input 2 /
vpcola	0:f1d3878b8dd9	2675
vpcola	0:f1d3878b8dd9	2676	#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /!< AES engine key input 1 /
vpcola	0:f1d3878b8dd9	2677
vpcola	0:f1d3878b8dd9	2678	#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /!< AES engine key input 0 /
vpcola	0:f1d3878b8dd9	2679
vpcola	0:f1d3878b8dd9	2680	/**
vpcola	0:f1d3878b8dd9	2681	* @}
vpcola	0:f1d3878b8dd9	2682	*/
vpcola	0:f1d3878b8dd9	2683
vpcola	0:f1d3878b8dd9	2684	/** @defgroup AES_DATA_IN_Register
vpcola	0:f1d3878b8dd9	2685	* @{
vpcola	0:f1d3878b8dd9	2686	*/
vpcola	0:f1d3878b8dd9	2687
vpcola	0:f1d3878b8dd9	2688	/**
vpcola	0:f1d3878b8dd9	2689	* \brief AES_DATA_INx registers
vpcola	0:f1d3878b8dd9	2690	* \code
vpcola	0:f1d3878b8dd9	2691	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2692	* Read Write
vpcola	0:f1d3878b8dd9	2693	*
vpcola	0:f1d3878b8dd9	2694	* 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits)
vpcola	0:f1d3878b8dd9	2695	* \endcode
vpcola	0:f1d3878b8dd9	2696	*/
vpcola	0:f1d3878b8dd9	2697	#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15
vpcola	0:f1d3878b8dd9	2698	Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */
vpcola	0:f1d3878b8dd9	2699	#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /!< AES engine data input 14 /
vpcola	0:f1d3878b8dd9	2700
vpcola	0:f1d3878b8dd9	2701	#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /!< AES engine data input 13 /
vpcola	0:f1d3878b8dd9	2702
vpcola	0:f1d3878b8dd9	2703	#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /!< AES engine data input 12 /
vpcola	0:f1d3878b8dd9	2704
vpcola	0:f1d3878b8dd9	2705	#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /!< AES engine data input 11 /
vpcola	0:f1d3878b8dd9	2706
vpcola	0:f1d3878b8dd9	2707	#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /!< AES engine data input 10 /
vpcola	0:f1d3878b8dd9	2708
vpcola	0:f1d3878b8dd9	2709	#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /!< AES engine data input 9 /
vpcola	0:f1d3878b8dd9	2710
vpcola	0:f1d3878b8dd9	2711	#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /!< AES engine data input 8 /
vpcola	0:f1d3878b8dd9	2712
vpcola	0:f1d3878b8dd9	2713	#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /!< AES engine data input 7 /
vpcola	0:f1d3878b8dd9	2714
vpcola	0:f1d3878b8dd9	2715	#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /!< AES engine data input 6 /
vpcola	0:f1d3878b8dd9	2716
vpcola	0:f1d3878b8dd9	2717	#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /!< AES engine data input 5 /
vpcola	0:f1d3878b8dd9	2718
vpcola	0:f1d3878b8dd9	2719	#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /!< AES engine data input 4 /
vpcola	0:f1d3878b8dd9	2720
vpcola	0:f1d3878b8dd9	2721	#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /!< AES engine data input 3 /
vpcola	0:f1d3878b8dd9	2722
vpcola	0:f1d3878b8dd9	2723	#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /!< AES engine data input 2 /
vpcola	0:f1d3878b8dd9	2724
vpcola	0:f1d3878b8dd9	2725	#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /!< AES engine data input 1 /
vpcola	0:f1d3878b8dd9	2726
vpcola	0:f1d3878b8dd9	2727	#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /!< AES engine data input 0 /
vpcola	0:f1d3878b8dd9	2728
vpcola	0:f1d3878b8dd9	2729	/**
vpcola	0:f1d3878b8dd9	2730	* @}
vpcola	0:f1d3878b8dd9	2731	*/
vpcola	0:f1d3878b8dd9	2732
vpcola	0:f1d3878b8dd9	2733	/** @defgroup AES_DATA_OUT_Register
vpcola	0:f1d3878b8dd9	2734	* @{
vpcola	0:f1d3878b8dd9	2735	*/
vpcola	0:f1d3878b8dd9	2736
vpcola	0:f1d3878b8dd9	2737	/**
vpcola	0:f1d3878b8dd9	2738	* \brief AES_DATA_OUT[15:0] registers
vpcola	0:f1d3878b8dd9	2739	* \code
vpcola	0:f1d3878b8dd9	2740	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2741	* Read
vpcola	0:f1d3878b8dd9	2742	*
vpcola	0:f1d3878b8dd9	2743	* 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits)
vpcola	0:f1d3878b8dd9	2744	* \endcode
vpcola	0:f1d3878b8dd9	2745	*/
vpcola	0:f1d3878b8dd9	2746	#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /!< AES engine data output 15 /
vpcola	0:f1d3878b8dd9	2747
vpcola	0:f1d3878b8dd9	2748	#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /!< AES engine data output 14 /
vpcola	0:f1d3878b8dd9	2749
vpcola	0:f1d3878b8dd9	2750	#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /!< AES engine data output 13 /
vpcola	0:f1d3878b8dd9	2751
vpcola	0:f1d3878b8dd9	2752	#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /!< AES engine data output 12 /
vpcola	0:f1d3878b8dd9	2753
vpcola	0:f1d3878b8dd9	2754	#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /!< AES engine data output 11 /
vpcola	0:f1d3878b8dd9	2755
vpcola	0:f1d3878b8dd9	2756	#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /!< AES engine data output 10 /
vpcola	0:f1d3878b8dd9	2757
vpcola	0:f1d3878b8dd9	2758	#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /!< AES engine data output 9 /
vpcola	0:f1d3878b8dd9	2759
vpcola	0:f1d3878b8dd9	2760	#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /!< AES engine data output 8 /
vpcola	0:f1d3878b8dd9	2761
vpcola	0:f1d3878b8dd9	2762	#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /!< AES engine data output 7 /
vpcola	0:f1d3878b8dd9	2763
vpcola	0:f1d3878b8dd9	2764	#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /!< AES engine data output 6 /
vpcola	0:f1d3878b8dd9	2765
vpcola	0:f1d3878b8dd9	2766	#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /!< AES engine data output 5 /
vpcola	0:f1d3878b8dd9	2767
vpcola	0:f1d3878b8dd9	2768	#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /!< AES engine data output 4 /
vpcola	0:f1d3878b8dd9	2769
vpcola	0:f1d3878b8dd9	2770	#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /!< AES engine data output 3 /
vpcola	0:f1d3878b8dd9	2771
vpcola	0:f1d3878b8dd9	2772	#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /!< AES engine data output 2 /
vpcola	0:f1d3878b8dd9	2773
vpcola	0:f1d3878b8dd9	2774	#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /!< AES engine data output 1 /
vpcola	0:f1d3878b8dd9	2775
vpcola	0:f1d3878b8dd9	2776	#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /!< AES engine data output 0 /
vpcola	0:f1d3878b8dd9	2777
vpcola	0:f1d3878b8dd9	2778	/**
vpcola	0:f1d3878b8dd9	2779	* @}
vpcola	0:f1d3878b8dd9	2780	*/
vpcola	0:f1d3878b8dd9	2781
vpcola	0:f1d3878b8dd9	2782	/**
vpcola	0:f1d3878b8dd9	2783	* @}
vpcola	0:f1d3878b8dd9	2784	*/
vpcola	0:f1d3878b8dd9	2785
vpcola	0:f1d3878b8dd9	2786	/** @defgroup IRQ_Registers
vpcola	0:f1d3878b8dd9	2787	* @{
vpcola	0:f1d3878b8dd9	2788	*/
vpcola	0:f1d3878b8dd9	2789
vpcola	0:f1d3878b8dd9	2790	/** @defgroup IRQ_MASK0_Register
vpcola	0:f1d3878b8dd9	2791	* @{
vpcola	0:f1d3878b8dd9	2792	*/
vpcola	0:f1d3878b8dd9	2793
vpcola	0:f1d3878b8dd9	2794	/**
vpcola	0:f1d3878b8dd9	2795	* \brief IRQ_MASK0 registers
vpcola	0:f1d3878b8dd9	2796	* \code
vpcola	0:f1d3878b8dd9	2797	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2798	* Read Write
vpcola	0:f1d3878b8dd9	2799	*
vpcola	0:f1d3878b8dd9	2800	* 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
vpcola	0:f1d3878b8dd9	2801	*
vpcola	0:f1d3878b8dd9	2802	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	2803	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	2804	* 0 \| RX data ready
vpcola	0:f1d3878b8dd9	2805	* 1 \| RX data discarded (upon filtering)
vpcola	0:f1d3878b8dd9	2806	* 2 \| TX data sent
vpcola	0:f1d3878b8dd9	2807	* 3 \| Max re-TX reached
vpcola	0:f1d3878b8dd9	2808	* 4 \| CRC error
vpcola	0:f1d3878b8dd9	2809	* 5 \| TX FIFO underflow/overflow error
vpcola	0:f1d3878b8dd9	2810	* 6 \| RX FIFO underflow/overflow error
vpcola	0:f1d3878b8dd9	2811	* 7 \| TX FIFO almost full
vpcola	0:f1d3878b8dd9	2812	* \endcode
vpcola	0:f1d3878b8dd9	2813	*/
vpcola	0:f1d3878b8dd9	2814
vpcola	0:f1d3878b8dd9	2815
vpcola	0:f1d3878b8dd9	2816	#define IRQ_MASK0_BASE ((uint8_t)0x93) /!< IRQ_MASK is split into 4 registers/
vpcola	0:f1d3878b8dd9	2817
vpcola	0:f1d3878b8dd9	2818	#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
vpcola	0:f1d3878b8dd9	2819	#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
vpcola	0:f1d3878b8dd9	2820	#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
vpcola	0:f1d3878b8dd9	2821	#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
vpcola	0:f1d3878b8dd9	2822	#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
vpcola	0:f1d3878b8dd9	2823	#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
vpcola	0:f1d3878b8dd9	2824	#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
vpcola	0:f1d3878b8dd9	2825	#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
vpcola	0:f1d3878b8dd9	2826
vpcola	0:f1d3878b8dd9	2827	/**
vpcola	0:f1d3878b8dd9	2828	* @}
vpcola	0:f1d3878b8dd9	2829	*/
vpcola	0:f1d3878b8dd9	2830
vpcola	0:f1d3878b8dd9	2831	/** @defgroup IRQ_MASK1_Register
vpcola	0:f1d3878b8dd9	2832	* @{
vpcola	0:f1d3878b8dd9	2833	*/
vpcola	0:f1d3878b8dd9	2834
vpcola	0:f1d3878b8dd9	2835	/**
vpcola	0:f1d3878b8dd9	2836	* \brief IRQ_MASK1 registers
vpcola	0:f1d3878b8dd9	2837	* \code
vpcola	0:f1d3878b8dd9	2838	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2839	* Read Write
vpcola	0:f1d3878b8dd9	2840	*
vpcola	0:f1d3878b8dd9	2841	* 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
vpcola	0:f1d3878b8dd9	2842	*
vpcola	0:f1d3878b8dd9	2843	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	2844	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	2845	* 8 \| TX FIFO almost empty
vpcola	0:f1d3878b8dd9	2846	* 9 \| RX FIFO almost full
vpcola	0:f1d3878b8dd9	2847	* 10 \| RX FIFO almost empty
vpcola	0:f1d3878b8dd9	2848	* 11 \| Max number of back-off during CCA
vpcola	0:f1d3878b8dd9	2849	* 12 \| Valid preamble detected
vpcola	0:f1d3878b8dd9	2850	* 13 \| Sync word detected
vpcola	0:f1d3878b8dd9	2851	* 14 \| RSSI above threshold (Carrier Sense)
vpcola	0:f1d3878b8dd9	2852	* 15 \| Wake-up timeout in LDCR mode13
vpcola	0:f1d3878b8dd9	2853	* \endcode
vpcola	0:f1d3878b8dd9	2854	*/
vpcola	0:f1d3878b8dd9	2855
vpcola	0:f1d3878b8dd9	2856	#define IRQ_MASK1_BASE ((uint8_t)0x92) /!< IRQ_MASK is split into 4 registers/
vpcola	0:f1d3878b8dd9	2857
vpcola	0:f1d3878b8dd9	2858	#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
vpcola	0:f1d3878b8dd9	2859	#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
vpcola	0:f1d3878b8dd9	2860	#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
vpcola	0:f1d3878b8dd9	2861	#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
vpcola	0:f1d3878b8dd9	2862	#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
vpcola	0:f1d3878b8dd9	2863	#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
vpcola	0:f1d3878b8dd9	2864	#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /!< IRQ: RSSI above threshold /
vpcola	0:f1d3878b8dd9	2865	#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /!< IRQ: Wake-up timeout in LDC mode /
vpcola	0:f1d3878b8dd9	2866
vpcola	0:f1d3878b8dd9	2867	/**
vpcola	0:f1d3878b8dd9	2868	* @}
vpcola	0:f1d3878b8dd9	2869	*/
vpcola	0:f1d3878b8dd9	2870
vpcola	0:f1d3878b8dd9	2871	/** @defgroup IRQ_MASK2_Register
vpcola	0:f1d3878b8dd9	2872	* @{
vpcola	0:f1d3878b8dd9	2873	*/
vpcola	0:f1d3878b8dd9	2874
vpcola	0:f1d3878b8dd9	2875	/**
vpcola	0:f1d3878b8dd9	2876	* \brief IRQ_MASK2 registers
vpcola	0:f1d3878b8dd9	2877	* \code
vpcola	0:f1d3878b8dd9	2878	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2879	* Read Write
vpcola	0:f1d3878b8dd9	2880	*
vpcola	0:f1d3878b8dd9	2881	* 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
vpcola	0:f1d3878b8dd9	2882	*
vpcola	0:f1d3878b8dd9	2883	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	2884	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	2885	* 16 \| READY state in steady condition14
vpcola	0:f1d3878b8dd9	2886	* 17 \| STANDBY state switching in progress
vpcola	0:f1d3878b8dd9	2887	* 18 \| Low battery level
vpcola	0:f1d3878b8dd9	2888	* 19 \| Power-On reset
vpcola	0:f1d3878b8dd9	2889	* 20 \| Brown-Out event
vpcola	0:f1d3878b8dd9	2890	* 21 \| LOCK state in steady condition
vpcola	0:f1d3878b8dd9	2891	* 22 \| PM start-up timer expiration
vpcola	0:f1d3878b8dd9	2892	* 23 \| XO settling timeout
vpcola	0:f1d3878b8dd9	2893	* \endcode
vpcola	0:f1d3878b8dd9	2894	*/
vpcola	0:f1d3878b8dd9	2895	#define IRQ_MASK2_BASE ((uint8_t)0x91) /!< IRQ_MASK is split into 4 registers/
vpcola	0:f1d3878b8dd9	2896
vpcola	0:f1d3878b8dd9	2897	#define IRQ_MASK2_READY ((uint8_t)0x01) /!< IRQ: READY state /
vpcola	0:f1d3878b8dd9	2898	#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
vpcola	0:f1d3878b8dd9	2899	#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /!< IRQ: Battery level below threshold/
vpcola	0:f1d3878b8dd9	2900	#define IRQ_MASK2_POR ((uint8_t)0x08) /!< IRQ: Power On Reset /
vpcola	0:f1d3878b8dd9	2901	#define IRQ_MASK2_BOR ((uint8_t)0x10) /!< IRQ: Brown out event (both accurate and inaccurate)/
vpcola	0:f1d3878b8dd9	2902	#define IRQ_MASK2_LOCK ((uint8_t)0x20) /!< IRQ: LOCK state /
vpcola	0:f1d3878b8dd9	2903	#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
vpcola	0:f1d3878b8dd9	2904	#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /!< IRQ: only for debug; Crystal oscillator settling time counter expired /
vpcola	0:f1d3878b8dd9	2905
vpcola	0:f1d3878b8dd9	2906	/**
vpcola	0:f1d3878b8dd9	2907	* @}
vpcola	0:f1d3878b8dd9	2908	*/
vpcola	0:f1d3878b8dd9	2909
vpcola	0:f1d3878b8dd9	2910	/** @defgroup IRQ_MASK3_Register
vpcola	0:f1d3878b8dd9	2911	* @{
vpcola	0:f1d3878b8dd9	2912	*/
vpcola	0:f1d3878b8dd9	2913
vpcola	0:f1d3878b8dd9	2914	/**
vpcola	0:f1d3878b8dd9	2915	* \brief IRQ_MASK3 registers
vpcola	0:f1d3878b8dd9	2916	* \code
vpcola	0:f1d3878b8dd9	2917	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2918	* Read Write
vpcola	0:f1d3878b8dd9	2919	*
vpcola	0:f1d3878b8dd9	2920	* 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
vpcola	0:f1d3878b8dd9	2921	*
vpcola	0:f1d3878b8dd9	2922	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	2923	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	2924	* 24 \| SYNTH locking timeout
vpcola	0:f1d3878b8dd9	2925	* 25 \| SYNTH calibration start-up time
vpcola	0:f1d3878b8dd9	2926	* 26 \| SYNTH calibration timeout
vpcola	0:f1d3878b8dd9	2927	* 27 \| TX circuitry start-up time
vpcola	0:f1d3878b8dd9	2928	* 28 \| RX circuitry start-up time
vpcola	0:f1d3878b8dd9	2929	* 29 \| RX operation timeout
vpcola	0:f1d3878b8dd9	2930	* 30 \| Others AES Endof Operation
vpcola	0:f1d3878b8dd9	2931	* 31 \| Reserved
vpcola	0:f1d3878b8dd9	2932	* \endcode
vpcola	0:f1d3878b8dd9	2933	*/
vpcola	0:f1d3878b8dd9	2934	#define IRQ_MASK3_BASE ((uint8_t)0x90) /!< IRQ_MASK is split into 4 registers/
vpcola	0:f1d3878b8dd9	2935
vpcola	0:f1d3878b8dd9	2936	#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /!< IRQ: only for debug; LOCK state timeout /
vpcola	0:f1d3878b8dd9	2937	#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
vpcola	0:f1d3878b8dd9	2938	#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /!< IRQ: only for debug; SYNTH calibration timeout /
vpcola	0:f1d3878b8dd9	2939	#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
vpcola	0:f1d3878b8dd9	2940	#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
vpcola	0:f1d3878b8dd9	2941	#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /!< IRQ: RX operation timeout /
vpcola	0:f1d3878b8dd9	2942	#define IRQ_MASK3_AES_END ((uint8_t)0x40) /!< IRQ: AES End of operation /
vpcola	0:f1d3878b8dd9	2943
vpcola	0:f1d3878b8dd9	2944	/**
vpcola	0:f1d3878b8dd9	2945	* @}
vpcola	0:f1d3878b8dd9	2946	*/
vpcola	0:f1d3878b8dd9	2947
vpcola	0:f1d3878b8dd9	2948
vpcola	0:f1d3878b8dd9	2949	/** @defgroup IRQ_STATUS0_Register
vpcola	0:f1d3878b8dd9	2950	* @{
vpcola	0:f1d3878b8dd9	2951	*/
vpcola	0:f1d3878b8dd9	2952
vpcola	0:f1d3878b8dd9	2953	/**
vpcola	0:f1d3878b8dd9	2954	* \brief IRQ_STATUS0 registers
vpcola	0:f1d3878b8dd9	2955	* \code
vpcola	0:f1d3878b8dd9	2956	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2957	* Read Write
vpcola	0:f1d3878b8dd9	2958	*
vpcola	0:f1d3878b8dd9	2959	* 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
vpcola	0:f1d3878b8dd9	2960	*
vpcola	0:f1d3878b8dd9	2961	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	2962	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	2963	* 0 \| RX data ready
vpcola	0:f1d3878b8dd9	2964	* 1 \| RX data discarded (upon filtering)
vpcola	0:f1d3878b8dd9	2965	* 2 \| TX data sent
vpcola	0:f1d3878b8dd9	2966	* 3 \| Max re-TX reached
vpcola	0:f1d3878b8dd9	2967	* 4 \| CRC error
vpcola	0:f1d3878b8dd9	2968	* 5 \| TX FIFO underflow/overflow error
vpcola	0:f1d3878b8dd9	2969	* 6 \| RX FIFO underflow/overflow error
vpcola	0:f1d3878b8dd9	2970	* 7 \| TX FIFO almost full
vpcola	0:f1d3878b8dd9	2971	* \endcode
vpcola	0:f1d3878b8dd9	2972	*/
vpcola	0:f1d3878b8dd9	2973
vpcola	0:f1d3878b8dd9	2974	#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /!< IRQ Events(RR, split into 4 registers) /
vpcola	0:f1d3878b8dd9	2975
vpcola	0:f1d3878b8dd9	2976	#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /!< IRQ: LOCK state timeout /
vpcola	0:f1d3878b8dd9	2977	#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
vpcola	0:f1d3878b8dd9	2978	#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /!< IRQ: SYNTH locking timeout /
vpcola	0:f1d3878b8dd9	2979	#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
vpcola	0:f1d3878b8dd9	2980	#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
vpcola	0:f1d3878b8dd9	2981	#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /!< IRQ: RX operation timeout expiration /
vpcola	0:f1d3878b8dd9	2982	#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /!< IRQ: AES End of operation /
vpcola	0:f1d3878b8dd9	2983
vpcola	0:f1d3878b8dd9	2984	/**
vpcola	0:f1d3878b8dd9	2985	* @}
vpcola	0:f1d3878b8dd9	2986	*/
vpcola	0:f1d3878b8dd9	2987
vpcola	0:f1d3878b8dd9	2988	/** @defgroup IRQ_STATUS1_Register
vpcola	0:f1d3878b8dd9	2989	* @{
vpcola	0:f1d3878b8dd9	2990	*/
vpcola	0:f1d3878b8dd9	2991
vpcola	0:f1d3878b8dd9	2992	/**
vpcola	0:f1d3878b8dd9	2993	* \brief IRQ_STATUS1 registers
vpcola	0:f1d3878b8dd9	2994	* \code
vpcola	0:f1d3878b8dd9	2995	* Default value: 0x00
vpcola	0:f1d3878b8dd9	2996	* Read Write
vpcola	0:f1d3878b8dd9	2997	*
vpcola	0:f1d3878b8dd9	2998	* 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
vpcola	0:f1d3878b8dd9	2999	*
vpcola	0:f1d3878b8dd9	3000	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	3001	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	3002	* 8 \| TX FIFO almost empty
vpcola	0:f1d3878b8dd9	3003	* 9 \| RX FIFO almost full
vpcola	0:f1d3878b8dd9	3004	* 10 \| RX FIFO almost empty
vpcola	0:f1d3878b8dd9	3005	* 11 \| Max number of back-off during CCA
vpcola	0:f1d3878b8dd9	3006	* 12 \| Valid preamble detected
vpcola	0:f1d3878b8dd9	3007	* 13 \| Sync word detected
vpcola	0:f1d3878b8dd9	3008	* 14 \| RSSI above threshold (Carrier Sense)
vpcola	0:f1d3878b8dd9	3009	* 15 \| Wake-up timeout in LDCR mode13
vpcola	0:f1d3878b8dd9	3010	* \endcode
vpcola	0:f1d3878b8dd9	3011	*/
vpcola	0:f1d3878b8dd9	3012
vpcola	0:f1d3878b8dd9	3013	#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /!< IRQ Events(RR, split into 4 registers) /
vpcola	0:f1d3878b8dd9	3014
vpcola	0:f1d3878b8dd9	3015	#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /!< IRQ: READY state in steady condition/
vpcola	0:f1d3878b8dd9	3016	#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
vpcola	0:f1d3878b8dd9	3017	#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /!< IRQ: Battery level below threshold/
vpcola	0:f1d3878b8dd9	3018	#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /!< IRQ: Power On Reset /
vpcola	0:f1d3878b8dd9	3019	#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /!< IRQ: Brown out event (both accurate and inaccurate)/
vpcola	0:f1d3878b8dd9	3020	#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /!< IRQ: LOCK state in steady condition /
vpcola	0:f1d3878b8dd9	3021	#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
vpcola	0:f1d3878b8dd9	3022	#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /!< IRQ: Crystal oscillator settling time counter expired /
vpcola	0:f1d3878b8dd9	3023
vpcola	0:f1d3878b8dd9	3024	/**
vpcola	0:f1d3878b8dd9	3025	* @}
vpcola	0:f1d3878b8dd9	3026	*/
vpcola	0:f1d3878b8dd9	3027
vpcola	0:f1d3878b8dd9	3028	/** @defgroup IRQ_STATUS2_Register
vpcola	0:f1d3878b8dd9	3029	* @{
vpcola	0:f1d3878b8dd9	3030	*/
vpcola	0:f1d3878b8dd9	3031
vpcola	0:f1d3878b8dd9	3032	/**
vpcola	0:f1d3878b8dd9	3033	* \brief IRQ_STATUS2 registers
vpcola	0:f1d3878b8dd9	3034	* \code
vpcola	0:f1d3878b8dd9	3035	* Default value: 0x00
vpcola	0:f1d3878b8dd9	3036	* Read Write
vpcola	0:f1d3878b8dd9	3037	*
vpcola	0:f1d3878b8dd9	3038	* 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
vpcola	0:f1d3878b8dd9	3039	*
vpcola	0:f1d3878b8dd9	3040	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	3041	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	3042	* 16 \| READY state in steady condition14
vpcola	0:f1d3878b8dd9	3043	* 17 \| STANDBY state switching in progress
vpcola	0:f1d3878b8dd9	3044	* 18 \| Low battery level
vpcola	0:f1d3878b8dd9	3045	* 19 \| Power-On reset
vpcola	0:f1d3878b8dd9	3046	* 20 \| Brown-Out event
vpcola	0:f1d3878b8dd9	3047	* 21 \| LOCK state in steady condition
vpcola	0:f1d3878b8dd9	3048	* 22 \| PM start-up timer expiration
vpcola	0:f1d3878b8dd9	3049	* 23 \| XO settling timeout
vpcola	0:f1d3878b8dd9	3050	* \endcode
vpcola	0:f1d3878b8dd9	3051	*/
vpcola	0:f1d3878b8dd9	3052
vpcola	0:f1d3878b8dd9	3053	#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /!< IRQ Events(RR, split into 4 registers) /
vpcola	0:f1d3878b8dd9	3054
vpcola	0:f1d3878b8dd9	3055	#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
vpcola	0:f1d3878b8dd9	3056	#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
vpcola	0:f1d3878b8dd9	3057	#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
vpcola	0:f1d3878b8dd9	3058	#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
vpcola	0:f1d3878b8dd9	3059	#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
vpcola	0:f1d3878b8dd9	3060	#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
vpcola	0:f1d3878b8dd9	3061	#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /!< IRQ: RSSI above threshold /
vpcola	0:f1d3878b8dd9	3062	#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /!< IRQ: Wake-up timeout in LDC mode /
vpcola	0:f1d3878b8dd9	3063
vpcola	0:f1d3878b8dd9	3064	/**
vpcola	0:f1d3878b8dd9	3065	* @}
vpcola	0:f1d3878b8dd9	3066	*/
vpcola	0:f1d3878b8dd9	3067
vpcola	0:f1d3878b8dd9	3068	/** @defgroup IRQ_STATUS3_Register
vpcola	0:f1d3878b8dd9	3069	* @{
vpcola	0:f1d3878b8dd9	3070	*/
vpcola	0:f1d3878b8dd9	3071
vpcola	0:f1d3878b8dd9	3072	/**
vpcola	0:f1d3878b8dd9	3073	* \brief IRQ_STATUS3 registers
vpcola	0:f1d3878b8dd9	3074	* \code
vpcola	0:f1d3878b8dd9	3075	* Default value: 0x00
vpcola	0:f1d3878b8dd9	3076	* Read Write
vpcola	0:f1d3878b8dd9	3077	*
vpcola	0:f1d3878b8dd9	3078	* 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
vpcola	0:f1d3878b8dd9	3079	*
vpcola	0:f1d3878b8dd9	3080	* Bit \| Events Group Interrupt Event
vpcola	0:f1d3878b8dd9	3081	* -------------------------------------------------------
vpcola	0:f1d3878b8dd9	3082	* 24 \| SYNTH locking timeout
vpcola	0:f1d3878b8dd9	3083	* 25 \| SYNTH calibration start-up time
vpcola	0:f1d3878b8dd9	3084	* 26 \| SYNTH calibration timeout
vpcola	0:f1d3878b8dd9	3085	* 27 \| TX circuitry start-up time
vpcola	0:f1d3878b8dd9	3086	* 28 \| RX circuitry start-up time
vpcola	0:f1d3878b8dd9	3087	* 29 \| RX operation timeout
vpcola	0:f1d3878b8dd9	3088	* 30 \| Others AES Endof Operation
vpcola	0:f1d3878b8dd9	3089	* 31 \| Reserved
vpcola	0:f1d3878b8dd9	3090	* \endcode
vpcola	0:f1d3878b8dd9	3091	*/
vpcola	0:f1d3878b8dd9	3092	#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /!< IRQ Events(RR, split into 4 registers) /
vpcola	0:f1d3878b8dd9	3093
vpcola	0:f1d3878b8dd9	3094	#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
vpcola	0:f1d3878b8dd9	3095	#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
vpcola	0:f1d3878b8dd9	3096	#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
vpcola	0:f1d3878b8dd9	3097	#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
vpcola	0:f1d3878b8dd9	3098	#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
vpcola	0:f1d3878b8dd9	3099	#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
vpcola	0:f1d3878b8dd9	3100	#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
vpcola	0:f1d3878b8dd9	3101	#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
vpcola	0:f1d3878b8dd9	3102
vpcola	0:f1d3878b8dd9	3103	/**
vpcola	0:f1d3878b8dd9	3104	* @}
vpcola	0:f1d3878b8dd9	3105	*/
vpcola	0:f1d3878b8dd9	3106
vpcola	0:f1d3878b8dd9	3107	/**
vpcola	0:f1d3878b8dd9	3108	* @}
vpcola	0:f1d3878b8dd9	3109	*/
vpcola	0:f1d3878b8dd9	3110
vpcola	0:f1d3878b8dd9	3111
vpcola	0:f1d3878b8dd9	3112	/** @defgroup MC_STATE_Registers
vpcola	0:f1d3878b8dd9	3113	* @{
vpcola	0:f1d3878b8dd9	3114	*/
vpcola	0:f1d3878b8dd9	3115
vpcola	0:f1d3878b8dd9	3116	/** @defgroup MC_STATE1_Register
vpcola	0:f1d3878b8dd9	3117	* @{
vpcola	0:f1d3878b8dd9	3118	*/
vpcola	0:f1d3878b8dd9	3119
vpcola	0:f1d3878b8dd9	3120	/**
vpcola	0:f1d3878b8dd9	3121	* \brief MC_STATE1 registers
vpcola	0:f1d3878b8dd9	3122	* \code
vpcola	0:f1d3878b8dd9	3123	* Default value: 0x50
vpcola	0:f1d3878b8dd9	3124	* Read
vpcola	0:f1d3878b8dd9	3125	*
vpcola	0:f1d3878b8dd9	3126	* 7:4 Reserved.
vpcola	0:f1d3878b8dd9	3127	*
vpcola	0:f1d3878b8dd9	3128	* 3 ANT_SELECT: Currently selected antenna
vpcola	0:f1d3878b8dd9	3129	*
vpcola	0:f1d3878b8dd9	3130	* 2 TX_FIFO_Full: 1 - TX FIFO is full
vpcola	0:f1d3878b8dd9	3131	*
vpcola	0:f1d3878b8dd9	3132	* 1 RX_FIFO_Empty: 1 - RX FIFO is empty
vpcola	0:f1d3878b8dd9	3133	*
vpcola	0:f1d3878b8dd9	3134	* 0 ERROR_LOCK: 1 - RCO calibrator error
vpcola	0:f1d3878b8dd9	3135	* \endcode
vpcola	0:f1d3878b8dd9	3136	*/
vpcola	0:f1d3878b8dd9	3137	#define MC_STATE1_BASE ((uint8_t)(0xC0)) /!< MC_STATE1 register address (see the SpiritStatus struct /
vpcola	0:f1d3878b8dd9	3138
vpcola	0:f1d3878b8dd9	3139
vpcola	0:f1d3878b8dd9	3140	/**
vpcola	0:f1d3878b8dd9	3141	* @}
vpcola	0:f1d3878b8dd9	3142	*/
vpcola	0:f1d3878b8dd9	3143
vpcola	0:f1d3878b8dd9	3144
vpcola	0:f1d3878b8dd9	3145	/** @defgroup MC_STATE0_Register
vpcola	0:f1d3878b8dd9	3146	* @{
vpcola	0:f1d3878b8dd9	3147	*/
vpcola	0:f1d3878b8dd9	3148
vpcola	0:f1d3878b8dd9	3149	/**
vpcola	0:f1d3878b8dd9	3150	* \brief MC_STATE0 registers
vpcola	0:f1d3878b8dd9	3151	* \code
vpcola	0:f1d3878b8dd9	3152	* Default value: 0x00
vpcola	0:f1d3878b8dd9	3153	* Read
vpcola	0:f1d3878b8dd9	3154	*
vpcola	0:f1d3878b8dd9	3155	* 7:1 STATE[6:0]: Current MC state.
vpcola	0:f1d3878b8dd9	3156	*
vpcola	0:f1d3878b8dd9	3157	* REGISTER VALUE \| STATE
vpcola	0:f1d3878b8dd9	3158	* --------------------------------------------
vpcola	0:f1d3878b8dd9	3159	* 0x40 \| STANDBY
vpcola	0:f1d3878b8dd9	3160	* 0x36 \| SLEEP
vpcola	0:f1d3878b8dd9	3161	* 0x03 \| READY
vpcola	0:f1d3878b8dd9	3162	* 0x3B \| PM setup
vpcola	0:f1d3878b8dd9	3163	* 0x23 \| XO settling
vpcola	0:f1d3878b8dd9	3164	* 0x53 \| SYNTH setup
vpcola	0:f1d3878b8dd9	3165	* 0x1F \| PROTOCOL
vpcola	0:f1d3878b8dd9	3166	* 0x4F \| SYNTH calibration
vpcola	0:f1d3878b8dd9	3167	* 0x0F \| LOCK
vpcola	0:f1d3878b8dd9	3168	* 0x33 \| RX
vpcola	0:f1d3878b8dd9	3169	* 0x5F \| TX
vpcola	0:f1d3878b8dd9	3170	*
vpcola	0:f1d3878b8dd9	3171	* 0 XO_ON: 1 - XO is operating
vpcola	0:f1d3878b8dd9	3172	* \endcode
vpcola	0:f1d3878b8dd9	3173	*/
vpcola	0:f1d3878b8dd9	3174	#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted
vpcola	0:f1d3878b8dd9	3175	and are still to be verified */
vpcola	0:f1d3878b8dd9	3176	/**
vpcola	0:f1d3878b8dd9	3177	* @}
vpcola	0:f1d3878b8dd9	3178	*/
vpcola	0:f1d3878b8dd9	3179
vpcola	0:f1d3878b8dd9	3180	/**
vpcola	0:f1d3878b8dd9	3181	* @}
vpcola	0:f1d3878b8dd9	3182	*/
vpcola	0:f1d3878b8dd9	3183
vpcola	0:f1d3878b8dd9	3184	/** @defgroup Engineering-Test_Registers
vpcola	0:f1d3878b8dd9	3185	* @{
vpcola	0:f1d3878b8dd9	3186	*/
vpcola	0:f1d3878b8dd9	3187
vpcola	0:f1d3878b8dd9	3188	#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4],
vpcola	0:f1d3878b8dd9	3189	Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/
vpcola	0:f1d3878b8dd9	3190	#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector/
vpcola	0:f1d3878b8dd9	3191	#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0]
vpcola	0:f1d3878b8dd9	3192	VCOth frequency=2fXO(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/
vpcola	0:f1d3878b8dd9	3193	#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /!< Enables high current buffer on Temperature sensor, sets SMPS options /
vpcola	0:f1d3878b8dd9	3194	#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /!< Set SMPS options /
vpcola	0:f1d3878b8dd9	3195	#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /!< Set SMPS options /
vpcola	0:f1d3878b8dd9	3196	#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /!< Set VCO current [5:2]part and [1:0] part /
vpcola	0:f1d3878b8dd9	3197	#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /!< Clock management options from XO to digital part /
vpcola	0:f1d3878b8dd9	3198
vpcola	0:f1d3878b8dd9	3199	#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /!< Test of XO and RCO /
vpcola	0:f1d3878b8dd9	3200
vpcola	0:f1d3878b8dd9	3201	/**
vpcola	0:f1d3878b8dd9	3202	* @}
vpcola	0:f1d3878b8dd9	3203	*/
vpcola	0:f1d3878b8dd9	3204
vpcola	0:f1d3878b8dd9	3205
vpcola	0:f1d3878b8dd9	3206	/** @addtogroup Commands
vpcola	0:f1d3878b8dd9	3207	* @{
vpcola	0:f1d3878b8dd9	3208	*/
vpcola	0:f1d3878b8dd9	3209
vpcola	0:f1d3878b8dd9	3210	#define COMMAND_TX ((uint8_t)(0x60)) /!< Start to transmit; valid only from READY /
vpcola	0:f1d3878b8dd9	3211	#define COMMAND_RX ((uint8_t)(0x61)) /!< Start to receive; valid only from READY /
vpcola	0:f1d3878b8dd9	3212	#define COMMAND_READY ((uint8_t)(0x62)) /!< Go to READY; valid only from STANDBY or SLEEP or LOCK /
vpcola	0:f1d3878b8dd9	3213	#define COMMAND_STANDBY ((uint8_t)(0x63)) /!< Go to STANDBY; valid only from READY /
vpcola	0:f1d3878b8dd9	3214	#define COMMAND_SLEEP ((uint8_t)(0x64)) /!< Go to SLEEP; valid only from READY /
vpcola	0:f1d3878b8dd9	3215	#define COMMAND_LOCKRX ((uint8_t)(0x65)) /!< Go to LOCK state by using the RX configuration of the synth; valid only from READY /
vpcola	0:f1d3878b8dd9	3216	#define COMMAND_LOCKTX ((uint8_t)(0x66)) /!< Go to LOCK state by using the TX configuration of the synth; valid only from READY /
vpcola	0:f1d3878b8dd9	3217	#define COMMAND_SABORT ((uint8_t)(0x67)) /!< Force exit form TX or RX states and go to READY state; valid only from TX or RX /
vpcola	0:f1d3878b8dd9	3218	#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER
vpcola	0:f1d3878b8dd9	3219	registers; valid from all states */
vpcola	0:f1d3878b8dd9	3220	#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register
vpcola	0:f1d3878b8dd9	3221	valid from all states */
vpcola	0:f1d3878b8dd9	3222	#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /!< AES: Start the encryption routine; valid from all states; valid from all states /
vpcola	0:f1d3878b8dd9	3223	#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /!< AES: Start the procedure to compute the key for the decryption; valid from all states /
vpcola	0:f1d3878b8dd9	3224	#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /!< AES: Start the decryption routine using the current key; valid from all states /
vpcola	0:f1d3878b8dd9	3225	#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /!< AES: Compute the key and start the decryption; valid from all states /
vpcola	0:f1d3878b8dd9	3226	#define COMMAND_SRES ((uint8_t)(0x70)) /!< Reset of all digital part, except SPI registers /
vpcola	0:f1d3878b8dd9	3227	#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /!< Clean the RX FIFO; valid from all states /
vpcola	0:f1d3878b8dd9	3228	#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /!< Clean the TX FIFO; valid from all states /
vpcola	0:f1d3878b8dd9	3229
vpcola	0:f1d3878b8dd9	3230	/**
vpcola	0:f1d3878b8dd9	3231	* @}
vpcola	0:f1d3878b8dd9	3232	*/
vpcola	0:f1d3878b8dd9	3233
vpcola	0:f1d3878b8dd9	3234	/**
vpcola	0:f1d3878b8dd9	3235	* @}
vpcola	0:f1d3878b8dd9	3236	*/
vpcola	0:f1d3878b8dd9	3237
vpcola	0:f1d3878b8dd9	3238	#ifdef __cplusplus
vpcola	0:f1d3878b8dd9	3239	}
vpcola	0:f1d3878b8dd9	3240	#endif
vpcola	0:f1d3878b8dd9	3241
vpcola	0:f1d3878b8dd9	3242	#endif
vpcola	0:f1d3878b8dd9	3243
vpcola	0:f1d3878b8dd9	3244	/***************** (C) COPYRIGHT 2015 STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Mbed OS support:	Mbed OS
Created:	08 Apr 2017
Imports:	9
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

The code in this repository is Apache licensed.

easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning