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easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Irq.h@0:f1d3878b8dd9, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:45:51 2017 +0000
Revision:
0:f1d3878b8dd9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:f1d3878b8dd9 1 /**
vpcola 0:f1d3878b8dd9 2 ******************************************************************************
vpcola 0:f1d3878b8dd9 3 * @file SPIRIT_Irq.h
vpcola 0:f1d3878b8dd9 4 * @author VMA division - AMS
vpcola 0:f1d3878b8dd9 5 * @version 3.2.2
vpcola 0:f1d3878b8dd9 6 * @date 08-July-2015
vpcola 0:f1d3878b8dd9 7 * @brief Configuration and management of SPIRIT IRQs.
vpcola 0:f1d3878b8dd9 8 *
vpcola 0:f1d3878b8dd9 9 * @details
vpcola 0:f1d3878b8dd9 10 *
vpcola 0:f1d3878b8dd9 11 * On the Spirit side specific IRQs can be enabled by setting a specific bitmask.
vpcola 0:f1d3878b8dd9 12 * The Spirit libraries allow the user to do this in two different ways:
vpcola 0:f1d3878b8dd9 13 * <ul>
vpcola 0:f1d3878b8dd9 14 *
vpcola 0:f1d3878b8dd9 15 * <li>The first enables the IRQs one by one, i.e. using an SPI transaction for each
vpcola 0:f1d3878b8dd9 16 * IRQ to enable.
vpcola 0:f1d3878b8dd9 17 *
vpcola 0:f1d3878b8dd9 18 * <b>Example:</b>
vpcola 0:f1d3878b8dd9 19 * @code
vpcola 0:f1d3878b8dd9 20 *
vpcola 0:f1d3878b8dd9 21 * SpiritIrqDeInit(NULL); // this call is used to reset the IRQ mask registers
vpcola 0:f1d3878b8dd9 22 * SpiritIrq(RX_DATA_READY , S_ENABLE);
vpcola 0:f1d3878b8dd9 23 * SpiritIrq(VALID_SYNC , S_ENABLE);
vpcola 0:f1d3878b8dd9 24 * SpiritIrq(RX_TIMEOUT , S_ENABLE);
vpcola 0:f1d3878b8dd9 25 *
vpcola 0:f1d3878b8dd9 26 * @endcode
vpcola 0:f1d3878b8dd9 27 *
vpcola 0:f1d3878b8dd9 28 * </li>
vpcola 0:f1d3878b8dd9 29 *
vpcola 0:f1d3878b8dd9 30 * <li>The second strategy is to set the IRQ bitfields structure. So, during the initialization the user
vpcola 0:f1d3878b8dd9 31 * has to fill the @ref SpiritIrqs structure setting to one the single field related to the IRQ he
vpcola 0:f1d3878b8dd9 32 * wants to enable, and to zero the single field related to all the IRQs he wants to disable.
vpcola 0:f1d3878b8dd9 33 *
vpcola 0:f1d3878b8dd9 34 * <b>Example:</b>
vpcola 0:f1d3878b8dd9 35 * @code
vpcola 0:f1d3878b8dd9 36 *
vpcola 0:f1d3878b8dd9 37 * SpiritIrqs irqMask;
vpcola 0:f1d3878b8dd9 38 *
vpcola 0:f1d3878b8dd9 39 * ...
vpcola 0:f1d3878b8dd9 40 *
vpcola 0:f1d3878b8dd9 41 * SpiritIrqDeInit(&irqMask); // this call is used to reset the IRQ mask registers
vpcola 0:f1d3878b8dd9 42 * // and to set to 0x00000000 the irq mask in order to disable
vpcola 0:f1d3878b8dd9 43 * // all IRQs (disabled by default on startup)
vpcola 0:f1d3878b8dd9 44 * irqMask.IRQ_RX_DATA_READY = 1;
vpcola 0:f1d3878b8dd9 45 * irqMask.IRQ_VALID_SYNC = 1;
vpcola 0:f1d3878b8dd9 46 * irqMask.IRQ_RX_TIMEOUT = 1;
vpcola 0:f1d3878b8dd9 47 *
vpcola 0:f1d3878b8dd9 48 * ...
vpcola 0:f1d3878b8dd9 49 * @endcode
vpcola 0:f1d3878b8dd9 50 * </li>
vpcola 0:f1d3878b8dd9 51 * </ul>
vpcola 0:f1d3878b8dd9 52 *
vpcola 0:f1d3878b8dd9 53 * The most applications will require a Spirit IRQ notification on an microcontroller EXTI line.
vpcola 0:f1d3878b8dd9 54 * Then, the user can check which IRQ has been raised using two different ways.
vpcola 0:f1d3878b8dd9 55 *
vpcola 0:f1d3878b8dd9 56 * On the ISR of the EXTI line phisically linked to the Spirit pin configured for IRQ:
vpcola 0:f1d3878b8dd9 57 *
vpcola 0:f1d3878b8dd9 58 * <ul>
vpcola 0:f1d3878b8dd9 59 * <li> Check <b>only one</b> Spirit IRQ (because the Spirit IRQ status register automatically blanks itself
vpcola 0:f1d3878b8dd9 60 * after an SPI reading) into the ISR.
vpcola 0:f1d3878b8dd9 61 *
vpcola 0:f1d3878b8dd9 62 * <b>Example:</b>
vpcola 0:f1d3878b8dd9 63 * @code
vpcola 0:f1d3878b8dd9 64 *
vpcola 0:f1d3878b8dd9 65 * if(SpiritIrqCheckFlag(RX_DATA_READY))
vpcola 0:f1d3878b8dd9 66 * {
vpcola 0:f1d3878b8dd9 67 * // do something...
vpcola 0:f1d3878b8dd9 68 * }
vpcola 0:f1d3878b8dd9 69 *
vpcola 0:f1d3878b8dd9 70 * @endcode
vpcola 0:f1d3878b8dd9 71 * </li>
vpcola 0:f1d3878b8dd9 72 *
vpcola 0:f1d3878b8dd9 73 * <li> Check more than one Spirit IRQ status by storing the entire IRQ status registers into a bitfields <i>@ref SpiritIrqs</i> structure
vpcola 0:f1d3878b8dd9 74 * and then check the interested bits.
vpcola 0:f1d3878b8dd9 75 *
vpcola 0:f1d3878b8dd9 76 * <b>Example:</b>
vpcola 0:f1d3878b8dd9 77 * @code
vpcola 0:f1d3878b8dd9 78 *
vpcola 0:f1d3878b8dd9 79 * SpiritIrqGetStatus(&irqStatus);
vpcola 0:f1d3878b8dd9 80 *
vpcola 0:f1d3878b8dd9 81 * if(irqStatus.IRQ_RX_DATA_READY)
vpcola 0:f1d3878b8dd9 82 * {
vpcola 0:f1d3878b8dd9 83 * // do something...
vpcola 0:f1d3878b8dd9 84 * }
vpcola 0:f1d3878b8dd9 85 * if(irqStatus.IRQ_VALID_SYNC)
vpcola 0:f1d3878b8dd9 86 * {
vpcola 0:f1d3878b8dd9 87 * // do something...
vpcola 0:f1d3878b8dd9 88 * }
vpcola 0:f1d3878b8dd9 89 * if(irqStatus.RX_TIMEOUT)
vpcola 0:f1d3878b8dd9 90 * {
vpcola 0:f1d3878b8dd9 91 * // do something...
vpcola 0:f1d3878b8dd9 92 * }
vpcola 0:f1d3878b8dd9 93 *
vpcola 0:f1d3878b8dd9 94 * @endcode
vpcola 0:f1d3878b8dd9 95 * </li>
vpcola 0:f1d3878b8dd9 96 * </ul>
vpcola 0:f1d3878b8dd9 97 *
vpcola 0:f1d3878b8dd9 98
vpcola 0:f1d3878b8dd9 99 * @attention
vpcola 0:f1d3878b8dd9 100 *
vpcola 0:f1d3878b8dd9 101 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
vpcola 0:f1d3878b8dd9 102 *
vpcola 0:f1d3878b8dd9 103 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:f1d3878b8dd9 104 * are permitted provided that the following conditions are met:
vpcola 0:f1d3878b8dd9 105 * 1. Redistributions of source code must retain the above copyright notice,
vpcola 0:f1d3878b8dd9 106 * this list of conditions and the following disclaimer.
vpcola 0:f1d3878b8dd9 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
vpcola 0:f1d3878b8dd9 108 * this list of conditions and the following disclaimer in the documentation
vpcola 0:f1d3878b8dd9 109 * and/or other materials provided with the distribution.
vpcola 0:f1d3878b8dd9 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vpcola 0:f1d3878b8dd9 111 * may be used to endorse or promote products derived from this software
vpcola 0:f1d3878b8dd9 112 * without specific prior written permission.
vpcola 0:f1d3878b8dd9 113 *
vpcola 0:f1d3878b8dd9 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vpcola 0:f1d3878b8dd9 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vpcola 0:f1d3878b8dd9 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:f1d3878b8dd9 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vpcola 0:f1d3878b8dd9 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vpcola 0:f1d3878b8dd9 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vpcola 0:f1d3878b8dd9 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vpcola 0:f1d3878b8dd9 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vpcola 0:f1d3878b8dd9 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vpcola 0:f1d3878b8dd9 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:f1d3878b8dd9 124 *
vpcola 0:f1d3878b8dd9 125 ******************************************************************************
vpcola 0:f1d3878b8dd9 126 */
vpcola 0:f1d3878b8dd9 127
vpcola 0:f1d3878b8dd9 128 /* Define to prevent recursive inclusion -------------------------------------*/
vpcola 0:f1d3878b8dd9 129 #ifndef __SPIRIT1_IRQ_H
vpcola 0:f1d3878b8dd9 130 #define __SPIRIT1_IRQ_H
vpcola 0:f1d3878b8dd9 131
vpcola 0:f1d3878b8dd9 132
vpcola 0:f1d3878b8dd9 133 /* Includes ------------------------------------------------------------------*/
vpcola 0:f1d3878b8dd9 134
vpcola 0:f1d3878b8dd9 135 #include "SPIRIT_Regs.h"
vpcola 0:f1d3878b8dd9 136 #include "SPIRIT_Types.h"
vpcola 0:f1d3878b8dd9 137
vpcola 0:f1d3878b8dd9 138
vpcola 0:f1d3878b8dd9 139 #ifdef __cplusplus
vpcola 0:f1d3878b8dd9 140 extern "C" {
vpcola 0:f1d3878b8dd9 141 #endif
vpcola 0:f1d3878b8dd9 142
vpcola 0:f1d3878b8dd9 143
vpcola 0:f1d3878b8dd9 144 /**
vpcola 0:f1d3878b8dd9 145 * @addtogroup SPIRIT_Libraries
vpcola 0:f1d3878b8dd9 146 * @{
vpcola 0:f1d3878b8dd9 147 */
vpcola 0:f1d3878b8dd9 148
vpcola 0:f1d3878b8dd9 149
vpcola 0:f1d3878b8dd9 150 /**
vpcola 0:f1d3878b8dd9 151 * @defgroup SPIRIT_Irq IRQ
vpcola 0:f1d3878b8dd9 152 * @brief Configuration and management of SPIRIT IRQs.
vpcola 0:f1d3878b8dd9 153 * @details See the file <i>@ref SPIRIT_Irq.h</i> for more details.
vpcola 0:f1d3878b8dd9 154 * @{
vpcola 0:f1d3878b8dd9 155 */
vpcola 0:f1d3878b8dd9 156
vpcola 0:f1d3878b8dd9 157 /**
vpcola 0:f1d3878b8dd9 158 * @defgroup Irq_Exported_Types IRQ Exported Types
vpcola 0:f1d3878b8dd9 159 * @{
vpcola 0:f1d3878b8dd9 160 */
vpcola 0:f1d3878b8dd9 161
vpcola 0:f1d3878b8dd9 162
vpcola 0:f1d3878b8dd9 163 /**
vpcola 0:f1d3878b8dd9 164 * @brief IRQ bitfield structure for SPIRIT. This structure is used to read or write the single IRQ bit.
vpcola 0:f1d3878b8dd9 165 * During the initialization the user has to fill this structure setting to one the single field related
vpcola 0:f1d3878b8dd9 166 * to the IRQ he wants to enable, and to zero the single field related to all the IRQs he wants to disable.
vpcola 0:f1d3878b8dd9 167 * The same structure can be used to retrieve all the IRQ events from the IRQ registers IRQ_STATUS[3:0],
vpcola 0:f1d3878b8dd9 168 * and read if one or more specific IRQ raised.
vpcola 0:f1d3878b8dd9 169 * @note The fields order in the structure depends on used endianness (little or big
vpcola 0:f1d3878b8dd9 170 * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to
vpcola 0:f1d3878b8dd9 171 * change opportunely the fields order when use a different endianness.
vpcola 0:f1d3878b8dd9 172 */
vpcola 0:f1d3878b8dd9 173 typedef struct
vpcola 0:f1d3878b8dd9 174 {
vpcola 0:f1d3878b8dd9 175 SpiritFlagStatus IRQ_SYNTH_LOCK_TIMEOUT:1; /*!< IRQ: only for debug; LOCK state timeout */
vpcola 0:f1d3878b8dd9 176 SpiritFlagStatus IRQ_SYNTH_LOCK_STARTUP:1; /*!< IRQ: only for debug; see CALIBR_START_COUNTER */
vpcola 0:f1d3878b8dd9 177 SpiritFlagStatus IRQ_SYNTH_CAL_TIMEOUT:1; /*!< IRQ: only for debug; SYNTH calibration timeout */
vpcola 0:f1d3878b8dd9 178 SpiritFlagStatus IRQ_TX_START_TIME:1; /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */
vpcola 0:f1d3878b8dd9 179 SpiritFlagStatus IRQ_RX_START_TIME:1; /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */
vpcola 0:f1d3878b8dd9 180 SpiritFlagStatus IRQ_RX_TIMEOUT:1; /*!< IRQ: RX operation timeout */
vpcola 0:f1d3878b8dd9 181 SpiritFlagStatus IRQ_AES_END:1; /*!< IRQ: AES End of operation */
vpcola 0:f1d3878b8dd9 182 SpiritFlagStatus reserved:1; /*!< Reserved bit */
vpcola 0:f1d3878b8dd9 183
vpcola 0:f1d3878b8dd9 184 SpiritFlagStatus IRQ_READY:1; /*!< IRQ: READY state */
vpcola 0:f1d3878b8dd9 185 SpiritFlagStatus IRQ_STANDBY_DELAYED:1; /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */
vpcola 0:f1d3878b8dd9 186 SpiritFlagStatus IRQ_LOW_BATT_LVL:1; /*!< IRQ: Battery level below threshold*/
vpcola 0:f1d3878b8dd9 187 SpiritFlagStatus IRQ_POR:1; /*!< IRQ: Power On Reset */
vpcola 0:f1d3878b8dd9 188 SpiritFlagStatus IRQ_BOR:1; /*!< IRQ: Brown out event (both accurate and inaccurate)*/
vpcola 0:f1d3878b8dd9 189 SpiritFlagStatus IRQ_LOCK:1; /*!< IRQ: LOCK state */
vpcola 0:f1d3878b8dd9 190 SpiritFlagStatus IRQ_PM_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */
vpcola 0:f1d3878b8dd9 191 SpiritFlagStatus IRQ_XO_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */
vpcola 0:f1d3878b8dd9 192
vpcola 0:f1d3878b8dd9 193 SpiritFlagStatus IRQ_TX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: TX FIFO almost empty */
vpcola 0:f1d3878b8dd9 194 SpiritFlagStatus IRQ_RX_FIFO_ALMOST_FULL:1; /*!< IRQ: RX FIFO almost full */
vpcola 0:f1d3878b8dd9 195 SpiritFlagStatus IRQ_RX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: RX FIFO almost empty */
vpcola 0:f1d3878b8dd9 196 SpiritFlagStatus IRQ_MAX_BO_CCA_REACH:1; /*!< IRQ: Max number of back-off during CCA */
vpcola 0:f1d3878b8dd9 197 SpiritFlagStatus IRQ_VALID_PREAMBLE:1; /*!< IRQ: Valid preamble detected */
vpcola 0:f1d3878b8dd9 198 SpiritFlagStatus IRQ_VALID_SYNC:1; /*!< IRQ: Sync word detected */
vpcola 0:f1d3878b8dd9 199 SpiritFlagStatus IRQ_RSSI_ABOVE_TH:1; /*!< IRQ: RSSI above threshold */
vpcola 0:f1d3878b8dd9 200 SpiritFlagStatus IRQ_WKUP_TOUT_LDC:1; /*!< IRQ: Wake-up timeout in LDC mode */
vpcola 0:f1d3878b8dd9 201
vpcola 0:f1d3878b8dd9 202 SpiritFlagStatus IRQ_RX_DATA_READY:1; /*!< IRQ: RX data ready */
vpcola 0:f1d3878b8dd9 203 SpiritFlagStatus IRQ_RX_DATA_DISC:1; /*!< IRQ: RX data discarded (upon filtering) */
vpcola 0:f1d3878b8dd9 204 SpiritFlagStatus IRQ_TX_DATA_SENT:1; /*!< IRQ: TX data sent */
vpcola 0:f1d3878b8dd9 205 SpiritFlagStatus IRQ_MAX_RE_TX_REACH:1; /*!< IRQ: Max re-TX reached */
vpcola 0:f1d3878b8dd9 206 SpiritFlagStatus IRQ_CRC_ERROR:1; /*!< IRQ: CRC error */
vpcola 0:f1d3878b8dd9 207 SpiritFlagStatus IRQ_TX_FIFO_ERROR:1; /*!< IRQ: TX FIFO underflow/overflow error */
vpcola 0:f1d3878b8dd9 208 SpiritFlagStatus IRQ_RX_FIFO_ERROR:1; /*!< IRQ: RX FIFO underflow/overflow error */
vpcola 0:f1d3878b8dd9 209 SpiritFlagStatus IRQ_TX_FIFO_ALMOST_FULL:1; /*!< IRQ: TX FIFO almost full */
vpcola 0:f1d3878b8dd9 210 } SpiritIrqs;
vpcola 0:f1d3878b8dd9 211
vpcola 0:f1d3878b8dd9 212 // betzw: uint32_t masks
vpcola 0:f1d3878b8dd9 213 #define IRQ_TX_FIFO_ALMOST_EMPTY_MASK (0x00010000) /* (1<<16) */
vpcola 0:f1d3878b8dd9 214 #define IRQ_RX_FIFO_ALMOST_FULL_MASK (0x00020000) /* (1<<17) */
vpcola 0:f1d3878b8dd9 215 #define IRQ_VALID_SYNC_MASK (0x00200000) /* (1<<21) */
vpcola 0:f1d3878b8dd9 216 #define IRQ_RX_DATA_READY_MASK (0x01000000) /* (1<<24) */
vpcola 0:f1d3878b8dd9 217 #define IRQ_RX_DATA_DISC_MASK (0x02000000) /* (1<<25) */
vpcola 0:f1d3878b8dd9 218 #define IRQ_TX_DATA_SENT_MASK (0x04000000) /* (1<<26) */
vpcola 0:f1d3878b8dd9 219 #define IRQ_TX_FIFO_ERROR_MASK (0x20000000) /* (1<<29) */
vpcola 0:f1d3878b8dd9 220 #define IRQ_RX_FIFO_ERROR_MASK (0x40000000) /* (1<<30) */
vpcola 0:f1d3878b8dd9 221
vpcola 0:f1d3878b8dd9 222 /**
vpcola 0:f1d3878b8dd9 223 * @brief IRQ list enumeration for SPIRIT. This enumeration type can be used to address a
vpcola 0:f1d3878b8dd9 224 * specific IRQ.
vpcola 0:f1d3878b8dd9 225 */
vpcola 0:f1d3878b8dd9 226 typedef enum
vpcola 0:f1d3878b8dd9 227 {
vpcola 0:f1d3878b8dd9 228 RX_DATA_READY = 0x00000001, /*!< IRQ: RX data ready */
vpcola 0:f1d3878b8dd9 229 RX_DATA_DISC = 0x00000002, /*!< IRQ: RX data discarded (upon filtering) */
vpcola 0:f1d3878b8dd9 230 TX_DATA_SENT = 0x00000004, /*!< IRQ: TX data sent */
vpcola 0:f1d3878b8dd9 231 MAX_RE_TX_REACH = 0x00000008, /*!< IRQ: Max re-TX reached */
vpcola 0:f1d3878b8dd9 232 CRC_ERROR = 0x00000010, /*!< IRQ: CRC error */
vpcola 0:f1d3878b8dd9 233 TX_FIFO_ERROR = 0x00000020, /*!< IRQ: TX FIFO underflow/overflow error */
vpcola 0:f1d3878b8dd9 234 RX_FIFO_ERROR = 0x00000040, /*!< IRQ: RX FIFO underflow/overflow error */
vpcola 0:f1d3878b8dd9 235 TX_FIFO_ALMOST_FULL = 0x00000080, /*!< IRQ: TX FIFO almost full */
vpcola 0:f1d3878b8dd9 236 TX_FIFO_ALMOST_EMPTY = 0x00000100, /*!< IRQ: TX FIFO almost empty */
vpcola 0:f1d3878b8dd9 237 RX_FIFO_ALMOST_FULL = 0x00000200, /*!< IRQ: RX FIFO almost full */
vpcola 0:f1d3878b8dd9 238 RX_FIFO_ALMOST_EMPTY = 0x00000400, /*!< IRQ: RX FIFO almost empty */
vpcola 0:f1d3878b8dd9 239 MAX_BO_CCA_REACH = 0x00000800, /*!< IRQ: Max number of back-off during CCA */
vpcola 0:f1d3878b8dd9 240 VALID_PREAMBLE = 0x00001000, /*!< IRQ: Valid preamble detected */
vpcola 0:f1d3878b8dd9 241 VALID_SYNC = 0x00002000, /*!< IRQ: Sync word detected */
vpcola 0:f1d3878b8dd9 242 RSSI_ABOVE_TH = 0x00004000, /*!< IRQ: RSSI above threshold */
vpcola 0:f1d3878b8dd9 243 WKUP_TOUT_LDC = 0x00008000, /*!< IRQ: Wake-up timeout in LDC mode */
vpcola 0:f1d3878b8dd9 244 READY = 0x00010000, /*!< IRQ: READY state */
vpcola 0:f1d3878b8dd9 245 STANDBY_DELAYED = 0x00020000, /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */
vpcola 0:f1d3878b8dd9 246 LOW_BATT_LVL = 0x00040000, /*!< IRQ: Battery level below threshold*/
vpcola 0:f1d3878b8dd9 247 POR = 0x00080000, /*!< IRQ: Power On Reset */
vpcola 0:f1d3878b8dd9 248 BOR = 0x00100000, /*!< IRQ: Brown out event (both accurate and inaccurate)*/
vpcola 0:f1d3878b8dd9 249 LOCK = 0x00200000, /*!< IRQ: LOCK state */
vpcola 0:f1d3878b8dd9 250 PM_COUNT_EXPIRED = 0x00400000, /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */
vpcola 0:f1d3878b8dd9 251 XO_COUNT_EXPIRED = 0x00800000, /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */
vpcola 0:f1d3878b8dd9 252 SYNTH_LOCK_TIMEOUT = 0x01000000, /*!< IRQ: only for debug; LOCK state timeout */
vpcola 0:f1d3878b8dd9 253 SYNTH_LOCK_STARTUP = 0x02000000, /*!< IRQ: only for debug; see CALIBR_START_COUNTER */
vpcola 0:f1d3878b8dd9 254 SYNTH_CAL_TIMEOUT = 0x04000000, /*!< IRQ: only for debug; SYNTH calibration timeout */
vpcola 0:f1d3878b8dd9 255 TX_START_TIME = 0x08000000, /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */
vpcola 0:f1d3878b8dd9 256 RX_START_TIME = 0x10000000, /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */
vpcola 0:f1d3878b8dd9 257 RX_TIMEOUT = 0x20000000, /*!< IRQ: RX operation timeout */
vpcola 0:f1d3878b8dd9 258 AES_END = 0x40000000, /*!< IRQ: AES End of operation */
vpcola 0:f1d3878b8dd9 259 ALL_IRQ = 0x7FFFFFFF /*!< All the above mentioned IRQs */
vpcola 0:f1d3878b8dd9 260
vpcola 0:f1d3878b8dd9 261 } IrqList;
vpcola 0:f1d3878b8dd9 262
vpcola 0:f1d3878b8dd9 263 #define IS_SPIRIT_IRQ_LIST(VALUE) ((VALUE == RX_DATA_READY) || \
vpcola 0:f1d3878b8dd9 264 (VALUE == RX_DATA_DISC) || \
vpcola 0:f1d3878b8dd9 265 (VALUE == TX_DATA_SENT) || \
vpcola 0:f1d3878b8dd9 266 (VALUE == MAX_RE_TX_REACH) || \
vpcola 0:f1d3878b8dd9 267 (VALUE == CRC_ERROR) || \
vpcola 0:f1d3878b8dd9 268 (VALUE == TX_FIFO_ERROR) || \
vpcola 0:f1d3878b8dd9 269 (VALUE == RX_FIFO_ERROR) || \
vpcola 0:f1d3878b8dd9 270 (VALUE == TX_FIFO_ALMOST_FULL) || \
vpcola 0:f1d3878b8dd9 271 (VALUE == TX_FIFO_ALMOST_EMPTY) || \
vpcola 0:f1d3878b8dd9 272 (VALUE == RX_FIFO_ALMOST_FULL) || \
vpcola 0:f1d3878b8dd9 273 (VALUE == RX_FIFO_ALMOST_EMPTY) || \
vpcola 0:f1d3878b8dd9 274 (VALUE == MAX_BO_CCA_REACH) || \
vpcola 0:f1d3878b8dd9 275 (VALUE == VALID_PREAMBLE) || \
vpcola 0:f1d3878b8dd9 276 (VALUE == VALID_SYNC) || \
vpcola 0:f1d3878b8dd9 277 (VALUE == RSSI_ABOVE_TH) || \
vpcola 0:f1d3878b8dd9 278 (VALUE == WKUP_TOUT_LDC) || \
vpcola 0:f1d3878b8dd9 279 (VALUE == READY) || \
vpcola 0:f1d3878b8dd9 280 (VALUE == STANDBY_DELAYED) || \
vpcola 0:f1d3878b8dd9 281 (VALUE == LOW_BATT_LVL) || \
vpcola 0:f1d3878b8dd9 282 (VALUE == POR) || \
vpcola 0:f1d3878b8dd9 283 (VALUE == BOR) || \
vpcola 0:f1d3878b8dd9 284 (VALUE == LOCK) || \
vpcola 0:f1d3878b8dd9 285 (VALUE == PM_COUNT_EXPIRED) || \
vpcola 0:f1d3878b8dd9 286 (VALUE == XO_COUNT_EXPIRED) || \
vpcola 0:f1d3878b8dd9 287 (VALUE == SYNTH_LOCK_TIMEOUT) || \
vpcola 0:f1d3878b8dd9 288 (VALUE == SYNTH_LOCK_STARTUP) || \
vpcola 0:f1d3878b8dd9 289 (VALUE == SYNTH_CAL_TIMEOUT) || \
vpcola 0:f1d3878b8dd9 290 (VALUE == TX_START_TIME) || \
vpcola 0:f1d3878b8dd9 291 (VALUE == RX_START_TIME) || \
vpcola 0:f1d3878b8dd9 292 (VALUE == RX_TIMEOUT) || \
vpcola 0:f1d3878b8dd9 293 (VALUE == AES_END) || \
vpcola 0:f1d3878b8dd9 294 (VALUE == ALL_IRQ ))
vpcola 0:f1d3878b8dd9 295
vpcola 0:f1d3878b8dd9 296
vpcola 0:f1d3878b8dd9 297 /**
vpcola 0:f1d3878b8dd9 298 * @}
vpcola 0:f1d3878b8dd9 299 */
vpcola 0:f1d3878b8dd9 300
vpcola 0:f1d3878b8dd9 301
vpcola 0:f1d3878b8dd9 302 /**
vpcola 0:f1d3878b8dd9 303 * @defgroup Irq_Exported_Constants IRQ Exported Constants
vpcola 0:f1d3878b8dd9 304 * @{
vpcola 0:f1d3878b8dd9 305 */
vpcola 0:f1d3878b8dd9 306
vpcola 0:f1d3878b8dd9 307
vpcola 0:f1d3878b8dd9 308 /**
vpcola 0:f1d3878b8dd9 309 * @}
vpcola 0:f1d3878b8dd9 310 */
vpcola 0:f1d3878b8dd9 311
vpcola 0:f1d3878b8dd9 312
vpcola 0:f1d3878b8dd9 313 /**
vpcola 0:f1d3878b8dd9 314 * @defgroup Irq_Exported_Macros IRQ Exported Macros
vpcola 0:f1d3878b8dd9 315 * @{
vpcola 0:f1d3878b8dd9 316 */
vpcola 0:f1d3878b8dd9 317
vpcola 0:f1d3878b8dd9 318
vpcola 0:f1d3878b8dd9 319 /**
vpcola 0:f1d3878b8dd9 320 * @}
vpcola 0:f1d3878b8dd9 321 */
vpcola 0:f1d3878b8dd9 322
vpcola 0:f1d3878b8dd9 323
vpcola 0:f1d3878b8dd9 324 /**
vpcola 0:f1d3878b8dd9 325 * @defgroup Irq_Exported_Functions IRQ Exported Functions
vpcola 0:f1d3878b8dd9 326 * @{
vpcola 0:f1d3878b8dd9 327 */
vpcola 0:f1d3878b8dd9 328
vpcola 0:f1d3878b8dd9 329 void SpiritIrqDeInit(SpiritIrqs* pxIrqInit);
vpcola 0:f1d3878b8dd9 330 void SpiritIrqInit(SpiritIrqs* pxIrqInit);
vpcola 0:f1d3878b8dd9 331 void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState);
vpcola 0:f1d3878b8dd9 332 void SpiritIrqGetMask(SpiritIrqs* pxIrqMask);
vpcola 0:f1d3878b8dd9 333 void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus);
vpcola 0:f1d3878b8dd9 334 void SpiritIrqClearStatus(void);
vpcola 0:f1d3878b8dd9 335 SpiritBool SpiritIrqCheckFlag(IrqList xFlag);
vpcola 0:f1d3878b8dd9 336
vpcola 0:f1d3878b8dd9 337 /**
vpcola 0:f1d3878b8dd9 338 * @}
vpcola 0:f1d3878b8dd9 339 */
vpcola 0:f1d3878b8dd9 340
vpcola 0:f1d3878b8dd9 341 /**
vpcola 0:f1d3878b8dd9 342 * @}
vpcola 0:f1d3878b8dd9 343 */
vpcola 0:f1d3878b8dd9 344
vpcola 0:f1d3878b8dd9 345
vpcola 0:f1d3878b8dd9 346 /**
vpcola 0:f1d3878b8dd9 347 * @}
vpcola 0:f1d3878b8dd9 348 */
vpcola 0:f1d3878b8dd9 349
vpcola 0:f1d3878b8dd9 350
vpcola 0:f1d3878b8dd9 351 #ifdef __cplusplus
vpcola 0:f1d3878b8dd9 352 }
vpcola 0:f1d3878b8dd9 353 #endif
vpcola 0:f1d3878b8dd9 354
vpcola 0:f1d3878b8dd9 355 #endif
vpcola 0:f1d3878b8dd9 356
vpcola 0:f1d3878b8dd9 357 /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/