MQTTGateway2 - Fork of my original MQTTGateway

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Fork of my original MQTTGateway

easy-connect/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp@0:a1734fe1ec4b, 2017-04-08 (annotated)

Committer:: vpcola
Date:: Sat Apr 08 14:43:14 2017 +0000
Revision:: 0:a1734fe1ec4b

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
vpcola	0:a1734fe1ec4b	1	/*
vpcola	0:a1734fe1ec4b	2	* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
vpcola	0:a1734fe1ec4b	3	* SPDX-License-Identifier: Apache-2.0
vpcola	0:a1734fe1ec4b	4	* Licensed under the Apache License, Version 2.0 (the License); you may
vpcola	0:a1734fe1ec4b	5	* not use this file except in compliance with the License.
vpcola	0:a1734fe1ec4b	6	* You may obtain a copy of the License at
vpcola	0:a1734fe1ec4b	7	*
vpcola	0:a1734fe1ec4b	8	* http://www.apache.org/licenses/LICENSE-2.0
vpcola	0:a1734fe1ec4b	9	*
vpcola	0:a1734fe1ec4b	10	* Unless required by applicable law or agreed to in writing, software
vpcola	0:a1734fe1ec4b	11	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
vpcola	0:a1734fe1ec4b	12	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
vpcola	0:a1734fe1ec4b	13	* See the License for the specific language governing permissions and
vpcola	0:a1734fe1ec4b	14	* limitations under the License.
vpcola	0:a1734fe1ec4b	15	*/
vpcola	0:a1734fe1ec4b	16	#include <string.h>
vpcola	0:a1734fe1ec4b	17	#include "platform/arm_hal_interrupt.h"
vpcola	0:a1734fe1ec4b	18	#include "nanostack/platform/arm_hal_phy.h"
vpcola	0:a1734fe1ec4b	19	#include "ns_types.h"
vpcola	0:a1734fe1ec4b	20	#include "NanostackRfPhyAtmel.h"
vpcola	0:a1734fe1ec4b	21	#include "randLIB.h"
vpcola	0:a1734fe1ec4b	22	#include "AT86RFReg.h"
vpcola	0:a1734fe1ec4b	23	#include "nanostack/platform/arm_hal_phy.h"
vpcola	0:a1734fe1ec4b	24	#include "toolchain.h"
vpcola	0:a1734fe1ec4b	25
vpcola	0:a1734fe1ec4b	26	/Worst case sensitivity/
vpcola	0:a1734fe1ec4b	27	#define RF_DEFAULT_SENSITIVITY -88
vpcola	0:a1734fe1ec4b	28	/Run calibration every 5 minutes/
vpcola	0:a1734fe1ec4b	29	#define RF_CALIBRATION_INTERVAL 6000000
vpcola	0:a1734fe1ec4b	30	/Wait ACK for 2.5ms/
vpcola	0:a1734fe1ec4b	31	#define RF_ACK_WAIT_DEFAULT_TIMEOUT 50
vpcola	0:a1734fe1ec4b	32	/Base CCA backoff (50us units) - substitutes for Inter-Frame Spacing/
vpcola	0:a1734fe1ec4b	33	#define RF_CCA_BASE_BACKOFF 13 /* 650us */
vpcola	0:a1734fe1ec4b	34	/CCA random backoff (50us units)/
vpcola	0:a1734fe1ec4b	35	#define RF_CCA_RANDOM_BACKOFF 51 /* 2550us */
vpcola	0:a1734fe1ec4b	36
vpcola	0:a1734fe1ec4b	37	#define RF_MTU 127
vpcola	0:a1734fe1ec4b	38
vpcola	0:a1734fe1ec4b	39	#define RF_PHY_MODE OQPSK_SIN_250
vpcola	0:a1734fe1ec4b	40
vpcola	0:a1734fe1ec4b	41	/Radio RX and TX state definitions/
vpcola	0:a1734fe1ec4b	42	#define RFF_ON 0x01
vpcola	0:a1734fe1ec4b	43	#define RFF_RX 0x02
vpcola	0:a1734fe1ec4b	44	#define RFF_TX 0x04
vpcola	0:a1734fe1ec4b	45	#define RFF_CCA 0x08
vpcola	0:a1734fe1ec4b	46	#define RFF_PROT 0x10
vpcola	0:a1734fe1ec4b	47
vpcola	0:a1734fe1ec4b	48	typedef enum
vpcola	0:a1734fe1ec4b	49	{
vpcola	0:a1734fe1ec4b	50	RF_MODE_NORMAL = 0,
vpcola	0:a1734fe1ec4b	51	RF_MODE_SNIFFER = 1,
vpcola	0:a1734fe1ec4b	52	RF_MODE_ED = 2
vpcola	0:a1734fe1ec4b	53	}rf_mode_t;
vpcola	0:a1734fe1ec4b	54
vpcola	0:a1734fe1ec4b	55	/Atmel RF Part Type/
vpcola	0:a1734fe1ec4b	56	typedef enum
vpcola	0:a1734fe1ec4b	57	{
vpcola	0:a1734fe1ec4b	58	ATMEL_UNKNOW_DEV = 0,
vpcola	0:a1734fe1ec4b	59	ATMEL_AT86RF212,
vpcola	0:a1734fe1ec4b	60	ATMEL_AT86RF231, // No longer supported (doesn't give ED+status on frame read)
vpcola	0:a1734fe1ec4b	61	ATMEL_AT86RF233
vpcola	0:a1734fe1ec4b	62	}rf_trx_part_e;
vpcola	0:a1734fe1ec4b	63
vpcola	0:a1734fe1ec4b	64	/Atmel RF states/
vpcola	0:a1734fe1ec4b	65	typedef enum
vpcola	0:a1734fe1ec4b	66	{
vpcola	0:a1734fe1ec4b	67	NOP = 0x00,
vpcola	0:a1734fe1ec4b	68	BUSY_RX = 0x01,
vpcola	0:a1734fe1ec4b	69	RF_TX_START = 0x02,
vpcola	0:a1734fe1ec4b	70	FORCE_TRX_OFF = 0x03,
vpcola	0:a1734fe1ec4b	71	FORCE_PLL_ON = 0x04,
vpcola	0:a1734fe1ec4b	72	RX_ON = 0x06,
vpcola	0:a1734fe1ec4b	73	TRX_OFF = 0x08,
vpcola	0:a1734fe1ec4b	74	PLL_ON = 0x09,
vpcola	0:a1734fe1ec4b	75	BUSY_RX_AACK = 0x11,
vpcola	0:a1734fe1ec4b	76	SLEEP = 0x0F,
vpcola	0:a1734fe1ec4b	77	RX_AACK_ON = 0x16,
vpcola	0:a1734fe1ec4b	78	TX_ARET_ON = 0x19
vpcola	0:a1734fe1ec4b	79	}rf_trx_states_t;
vpcola	0:a1734fe1ec4b	80
vpcola	0:a1734fe1ec4b	81	static const uint8_t *rf_tx_data; // Points to Nanostack's buffer
vpcola	0:a1734fe1ec4b	82	static uint8_t rf_tx_length;
vpcola	0:a1734fe1ec4b	83	/ACK wait duration changes depending on data rate/
vpcola	0:a1734fe1ec4b	84	static uint16_t rf_ack_wait_duration = RF_ACK_WAIT_DEFAULT_TIMEOUT;
vpcola	0:a1734fe1ec4b	85
vpcola	0:a1734fe1ec4b	86	static int8_t rf_sensitivity = RF_DEFAULT_SENSITIVITY;
vpcola	0:a1734fe1ec4b	87	static rf_mode_t rf_mode = RF_MODE_NORMAL;
vpcola	0:a1734fe1ec4b	88	static uint8_t radio_tx_power = 0x00; // Default to +4dBm
vpcola	0:a1734fe1ec4b	89	static uint8_t rf_phy_channel = 12;
vpcola	0:a1734fe1ec4b	90	static uint8_t rf_tuned = 1;
vpcola	0:a1734fe1ec4b	91	static uint8_t rf_use_antenna_diversity = 0;
vpcola	0:a1734fe1ec4b	92	static int16_t expected_ack_sequence = -1;
vpcola	0:a1734fe1ec4b	93	static uint8_t rf_rx_mode = 0;
vpcola	0:a1734fe1ec4b	94	static uint8_t rf_flags = 0;
vpcola	0:a1734fe1ec4b	95	static int8_t rf_radio_driver_id = -1;
vpcola	0:a1734fe1ec4b	96	static phy_device_driver_s device_driver;
vpcola	0:a1734fe1ec4b	97	static uint8_t mac_tx_handle = 0;
vpcola	0:a1734fe1ec4b	98
vpcola	0:a1734fe1ec4b	99	/* Channel configurations for 2.4 and sub-GHz */
vpcola	0:a1734fe1ec4b	100	static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
vpcola	0:a1734fe1ec4b	101	static const phy_rf_channel_configuration_s phy_subghz = {868300000U, 2000000U, 250000U, 11U, M_OQPSK};
vpcola	0:a1734fe1ec4b	102
vpcola	0:a1734fe1ec4b	103	static const phy_device_channel_page_s phy_channel_pages[] = {
vpcola	0:a1734fe1ec4b	104	{ CHANNEL_PAGE_0, &phy_24ghz},
vpcola	0:a1734fe1ec4b	105	{ CHANNEL_PAGE_2, &phy_subghz},
vpcola	0:a1734fe1ec4b	106	{ CHANNEL_PAGE_0, NULL}
vpcola	0:a1734fe1ec4b	107	};
vpcola	0:a1734fe1ec4b	108
vpcola	0:a1734fe1ec4b	109	/**
vpcola	0:a1734fe1ec4b	110	* RF output power write
vpcola	0:a1734fe1ec4b	111	*
vpcola	0:a1734fe1ec4b	112	* \brief TX power has to be set before network start.
vpcola	0:a1734fe1ec4b	113	*
vpcola	0:a1734fe1ec4b	114	* \param power
vpcola	0:a1734fe1ec4b	115	* AT86RF233
vpcola	0:a1734fe1ec4b	116	* 0 = 4 dBm
vpcola	0:a1734fe1ec4b	117	* 1 = 3.7 dBm
vpcola	0:a1734fe1ec4b	118	* 2 = 3.4 dBm
vpcola	0:a1734fe1ec4b	119	* 3 = 3 dBm
vpcola	0:a1734fe1ec4b	120	* 4 = 2.5 dBm
vpcola	0:a1734fe1ec4b	121	* 5 = 2 dBm
vpcola	0:a1734fe1ec4b	122	* 6 = 1 dBm
vpcola	0:a1734fe1ec4b	123	* 7 = 0 dBm
vpcola	0:a1734fe1ec4b	124	* 8 = -1 dBm
vpcola	0:a1734fe1ec4b	125	* 9 = -2 dBm
vpcola	0:a1734fe1ec4b	126	* 10 = -3 dBm
vpcola	0:a1734fe1ec4b	127	* 11 = -4 dBm
vpcola	0:a1734fe1ec4b	128	* 12 = -6 dBm
vpcola	0:a1734fe1ec4b	129	* 13 = -8 dBm
vpcola	0:a1734fe1ec4b	130	* 14 = -12 dBm
vpcola	0:a1734fe1ec4b	131	* 15 = -17 dBm
vpcola	0:a1734fe1ec4b	132	*
vpcola	0:a1734fe1ec4b	133	* AT86RF212B
vpcola	0:a1734fe1ec4b	134	* See datasheet for TX power settings
vpcola	0:a1734fe1ec4b	135	*
vpcola	0:a1734fe1ec4b	136	* \return 0, Supported Value
vpcola	0:a1734fe1ec4b	137	* \return -1, Not Supported Value
vpcola	0:a1734fe1ec4b	138	*/
vpcola	0:a1734fe1ec4b	139	static int8_t rf_tx_power_set(uint8_t power);
vpcola	0:a1734fe1ec4b	140	static rf_trx_part_e rf_radio_type_read(void);
vpcola	0:a1734fe1ec4b	141	static void rf_ack_wait_timer_start(uint16_t slots);
vpcola	0:a1734fe1ec4b	142	static void rf_ack_wait_timer_stop(void);
vpcola	0:a1734fe1ec4b	143	static void rf_handle_cca_ed_done(void);
vpcola	0:a1734fe1ec4b	144	static void rf_handle_tx_end(void);
vpcola	0:a1734fe1ec4b	145	static void rf_handle_rx_end(void);
vpcola	0:a1734fe1ec4b	146	static void rf_on(void);
vpcola	0:a1734fe1ec4b	147	static void rf_receive(void);
vpcola	0:a1734fe1ec4b	148	static void rf_poll_trx_state_change(rf_trx_states_t trx_state);
vpcola	0:a1734fe1ec4b	149	static void rf_init(void);
vpcola	0:a1734fe1ec4b	150	static int8_t rf_device_register(const uint8_t *mac_addr);
vpcola	0:a1734fe1ec4b	151	static void rf_device_unregister(void);
vpcola	0:a1734fe1ec4b	152	static void rf_enable_static_frame_buffer_protection(void);
vpcola	0:a1734fe1ec4b	153	static void rf_disable_static_frame_buffer_protection(void);
vpcola	0:a1734fe1ec4b	154	static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
vpcola	0:a1734fe1ec4b	155	static void rf_cca_abort(void);
vpcola	0:a1734fe1ec4b	156	static void rf_calibration_cb(void);
vpcola	0:a1734fe1ec4b	157	static void rf_init_phy_mode(void);
vpcola	0:a1734fe1ec4b	158	static void rf_ack_wait_timer_interrupt(void);
vpcola	0:a1734fe1ec4b	159	static void rf_calibration_timer_interrupt(void);
vpcola	0:a1734fe1ec4b	160	static void rf_calibration_timer_start(uint32_t slots);
vpcola	0:a1734fe1ec4b	161	static void rf_cca_timer_interrupt(void);
vpcola	0:a1734fe1ec4b	162	static void rf_cca_timer_start(uint32_t slots);
vpcola	0:a1734fe1ec4b	163	static uint8_t rf_scale_lqi(int8_t rssi);
vpcola	0:a1734fe1ec4b	164
vpcola	0:a1734fe1ec4b	165	static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
vpcola	0:a1734fe1ec4b	166	static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
vpcola	0:a1734fe1ec4b	167	static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
vpcola	0:a1734fe1ec4b	168
vpcola	0:a1734fe1ec4b	169	static void rf_if_cca_timer_start(uint32_t slots);
vpcola	0:a1734fe1ec4b	170	static void rf_if_enable_promiscuous_mode(void);
vpcola	0:a1734fe1ec4b	171	static void rf_if_lock(void);
vpcola	0:a1734fe1ec4b	172	static void rf_if_unlock(void);
vpcola	0:a1734fe1ec4b	173	static uint8_t rf_if_read_rnd(void);
vpcola	0:a1734fe1ec4b	174	static void rf_if_calibration_timer_start(uint32_t slots);
vpcola	0:a1734fe1ec4b	175	static void rf_if_interrupt_handler(void);
vpcola	0:a1734fe1ec4b	176	static void rf_if_ack_wait_timer_start(uint16_t slots);
vpcola	0:a1734fe1ec4b	177	static void rf_if_ack_wait_timer_stop(void);
vpcola	0:a1734fe1ec4b	178	static void rf_if_ack_pending_ctrl(uint8_t state);
vpcola	0:a1734fe1ec4b	179	static void rf_if_calibration(void);
vpcola	0:a1734fe1ec4b	180	static uint8_t rf_if_read_register(uint8_t addr);
vpcola	0:a1734fe1ec4b	181	static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask);
vpcola	0:a1734fe1ec4b	182	static void rf_if_clear_bit(uint8_t addr, uint8_t bit);
vpcola	0:a1734fe1ec4b	183	static void rf_if_write_register(uint8_t addr, uint8_t data);
vpcola	0:a1734fe1ec4b	184	static void rf_if_reset_radio(void);
vpcola	0:a1734fe1ec4b	185	static void rf_if_enable_ant_div(void);
vpcola	0:a1734fe1ec4b	186	static void rf_if_disable_ant_div(void);
vpcola	0:a1734fe1ec4b	187	static void rf_if_enable_slptr(void);
vpcola	0:a1734fe1ec4b	188	static void rf_if_disable_slptr(void);
vpcola	0:a1734fe1ec4b	189	static void rf_if_write_antenna_diversity_settings(void);
vpcola	0:a1734fe1ec4b	190	static void rf_if_write_set_tx_power_register(uint8_t value);
vpcola	0:a1734fe1ec4b	191	static void rf_if_write_rf_settings(void);
vpcola	0:a1734fe1ec4b	192	static uint8_t rf_if_check_cca(void);
vpcola	0:a1734fe1ec4b	193	static uint8_t rf_if_read_trx_state(void);
vpcola	0:a1734fe1ec4b	194	static uint16_t rf_if_read_packet(uint8_t data[RF_MTU], uint8_t lqi_out, uint8_t ed_out, bool *crc_good);
vpcola	0:a1734fe1ec4b	195	static void rf_if_write_short_addr_registers(uint8_t *short_address);
vpcola	0:a1734fe1ec4b	196	static uint8_t rf_if_last_acked_pending(void);
vpcola	0:a1734fe1ec4b	197	static void rf_if_write_pan_id_registers(uint8_t *pan_id);
vpcola	0:a1734fe1ec4b	198	static void rf_if_write_ieee_addr_registers(uint8_t *address);
vpcola	0:a1734fe1ec4b	199	static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length);
vpcola	0:a1734fe1ec4b	200	static void rf_if_change_trx_state(rf_trx_states_t trx_state);
vpcola	0:a1734fe1ec4b	201	static void rf_if_enable_tx_end_interrupt(void);
vpcola	0:a1734fe1ec4b	202	static void rf_if_enable_rx_end_interrupt(void);
vpcola	0:a1734fe1ec4b	203	static void rf_if_enable_cca_ed_done_interrupt(void);
vpcola	0:a1734fe1ec4b	204	static void rf_if_start_cca_process(void);
vpcola	0:a1734fe1ec4b	205	static int8_t rf_if_scale_rssi(uint8_t ed_level);
vpcola	0:a1734fe1ec4b	206	static void rf_if_set_channel_register(uint8_t channel);
vpcola	0:a1734fe1ec4b	207	static void rf_if_enable_promiscuous_mode(void);
vpcola	0:a1734fe1ec4b	208	static void rf_if_disable_promiscuous_mode(void);
vpcola	0:a1734fe1ec4b	209	static uint8_t rf_if_read_part_num(void);
vpcola	0:a1734fe1ec4b	210	static void rf_if_enable_irq(void);
vpcola	0:a1734fe1ec4b	211	static void rf_if_disable_irq(void);
vpcola	0:a1734fe1ec4b	212
vpcola	0:a1734fe1ec4b	213	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	214	#include "mbed.h"
vpcola	0:a1734fe1ec4b	215	#include "rtos.h"
vpcola	0:a1734fe1ec4b	216
vpcola	0:a1734fe1ec4b	217	static void rf_if_irq_task_process_irq();
vpcola	0:a1734fe1ec4b	218
vpcola	0:a1734fe1ec4b	219	#define SIG_RADIO 1
vpcola	0:a1734fe1ec4b	220	#define SIG_TIMER_ACK 2
vpcola	0:a1734fe1ec4b	221	#define SIG_TIMER_CAL 4
vpcola	0:a1734fe1ec4b	222	#define SIG_TIMER_CCA 8
vpcola	0:a1734fe1ec4b	223
vpcola	0:a1734fe1ec4b	224	#define SIG_TIMERS (SIG_TIMER_ACK\|SIG_TIMER_CAL\|SIG_TIMER_CCA)
vpcola	0:a1734fe1ec4b	225	#define SIG_ALL (SIG_RADIO\|SIG_TIMERS)
vpcola	0:a1734fe1ec4b	226	#endif
vpcola	0:a1734fe1ec4b	227
vpcola	0:a1734fe1ec4b	228	// HW pins to RF chip
vpcola	0:a1734fe1ec4b	229	#define SPI_SPEED 7500000
vpcola	0:a1734fe1ec4b	230
vpcola	0:a1734fe1ec4b	231	class UnlockedSPI : public SPI {
vpcola	0:a1734fe1ec4b	232	public:
vpcola	0:a1734fe1ec4b	233	UnlockedSPI(PinName mosi, PinName miso, PinName sclk) :
vpcola	0:a1734fe1ec4b	234	SPI(mosi, miso, sclk) { }
vpcola	0:a1734fe1ec4b	235	virtual void lock() { }
vpcola	0:a1734fe1ec4b	236	virtual void unlock() { }
vpcola	0:a1734fe1ec4b	237	};
vpcola	0:a1734fe1ec4b	238
vpcola	0:a1734fe1ec4b	239	class RFBits {
vpcola	0:a1734fe1ec4b	240	public:
vpcola	0:a1734fe1ec4b	241	RFBits(PinName spi_mosi, PinName spi_miso,
vpcola	0:a1734fe1ec4b	242	PinName spi_sclk, PinName spi_cs,
vpcola	0:a1734fe1ec4b	243	PinName spi_rst, PinName spi_slp, PinName spi_irq);
vpcola	0:a1734fe1ec4b	244	UnlockedSPI spi;
vpcola	0:a1734fe1ec4b	245	DigitalOut CS;
vpcola	0:a1734fe1ec4b	246	DigitalOut RST;
vpcola	0:a1734fe1ec4b	247	DigitalOut SLP_TR;
vpcola	0:a1734fe1ec4b	248	InterruptIn IRQ;
vpcola	0:a1734fe1ec4b	249	Timeout ack_timer;
vpcola	0:a1734fe1ec4b	250	Timeout cal_timer;
vpcola	0:a1734fe1ec4b	251	Timeout cca_timer;
vpcola	0:a1734fe1ec4b	252	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	253	Thread irq_thread;
vpcola	0:a1734fe1ec4b	254	Mutex mutex;
vpcola	0:a1734fe1ec4b	255	void rf_if_irq_task();
vpcola	0:a1734fe1ec4b	256	#endif
vpcola	0:a1734fe1ec4b	257	};
vpcola	0:a1734fe1ec4b	258
vpcola	0:a1734fe1ec4b	259	RFBits::RFBits(PinName spi_mosi, PinName spi_miso,
vpcola	0:a1734fe1ec4b	260	PinName spi_sclk, PinName spi_cs,
vpcola	0:a1734fe1ec4b	261	PinName spi_rst, PinName spi_slp, PinName spi_irq)
vpcola	0:a1734fe1ec4b	262	: spi(spi_mosi, spi_miso, spi_sclk),
vpcola	0:a1734fe1ec4b	263	CS(spi_cs),
vpcola	0:a1734fe1ec4b	264	RST(spi_rst),
vpcola	0:a1734fe1ec4b	265	SLP_TR(spi_slp),
vpcola	0:a1734fe1ec4b	266	IRQ(spi_irq)
vpcola	0:a1734fe1ec4b	267	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	268	,irq_thread(osPriorityRealtime, 1024)
vpcola	0:a1734fe1ec4b	269	#endif
vpcola	0:a1734fe1ec4b	270	{
vpcola	0:a1734fe1ec4b	271	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	272	irq_thread.start(mbed::callback(this, &RFBits::rf_if_irq_task));
vpcola	0:a1734fe1ec4b	273	#endif
vpcola	0:a1734fe1ec4b	274	}
vpcola	0:a1734fe1ec4b	275
vpcola	0:a1734fe1ec4b	276	static RFBits *rf;
vpcola	0:a1734fe1ec4b	277	static uint8_t rf_part_num = 0;
vpcola	0:a1734fe1ec4b	278	/TODO: RSSI Base value setting/
vpcola	0:a1734fe1ec4b	279	static int8_t rf_rssi_base_val = -91;
vpcola	0:a1734fe1ec4b	280
vpcola	0:a1734fe1ec4b	281	static uint8_t rf_if_spi_exchange(uint8_t out);
vpcola	0:a1734fe1ec4b	282
vpcola	0:a1734fe1ec4b	283	static void rf_if_lock(void)
vpcola	0:a1734fe1ec4b	284	{
vpcola	0:a1734fe1ec4b	285	platform_enter_critical();
vpcola	0:a1734fe1ec4b	286	}
vpcola	0:a1734fe1ec4b	287
vpcola	0:a1734fe1ec4b	288	static void rf_if_unlock(void)
vpcola	0:a1734fe1ec4b	289	{
vpcola	0:a1734fe1ec4b	290	platform_exit_critical();
vpcola	0:a1734fe1ec4b	291	}
vpcola	0:a1734fe1ec4b	292
vpcola	0:a1734fe1ec4b	293	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	294	static void rf_if_cca_timer_signal(void)
vpcola	0:a1734fe1ec4b	295	{
vpcola	0:a1734fe1ec4b	296	rf->irq_thread.signal_set(SIG_TIMER_CCA);
vpcola	0:a1734fe1ec4b	297	}
vpcola	0:a1734fe1ec4b	298
vpcola	0:a1734fe1ec4b	299	static void rf_if_cal_timer_signal(void)
vpcola	0:a1734fe1ec4b	300	{
vpcola	0:a1734fe1ec4b	301	rf->irq_thread.signal_set(SIG_TIMER_CAL);
vpcola	0:a1734fe1ec4b	302	}
vpcola	0:a1734fe1ec4b	303
vpcola	0:a1734fe1ec4b	304	static void rf_if_ack_timer_signal(void)
vpcola	0:a1734fe1ec4b	305	{
vpcola	0:a1734fe1ec4b	306	rf->irq_thread.signal_set(SIG_TIMER_ACK);
vpcola	0:a1734fe1ec4b	307	}
vpcola	0:a1734fe1ec4b	308	#endif
vpcola	0:a1734fe1ec4b	309
vpcola	0:a1734fe1ec4b	310
vpcola	0:a1734fe1ec4b	311	/* Delay functions for RF Chip SPI access */
vpcola	0:a1734fe1ec4b	312	#ifdef __CC_ARM
vpcola	0:a1734fe1ec4b	313	__asm static void delay_loop(uint32_t count)
vpcola	0:a1734fe1ec4b	314	{
vpcola	0:a1734fe1ec4b	315	1
vpcola	0:a1734fe1ec4b	316	SUBS a1, a1, #1
vpcola	0:a1734fe1ec4b	317	BCS %BT1
vpcola	0:a1734fe1ec4b	318	BX lr
vpcola	0:a1734fe1ec4b	319	}
vpcola	0:a1734fe1ec4b	320	#elif defined (__ICCARM__)
vpcola	0:a1734fe1ec4b	321	static void delay_loop(uint32_t count)
vpcola	0:a1734fe1ec4b	322	{
vpcola	0:a1734fe1ec4b	323	__asm volatile(
vpcola	0:a1734fe1ec4b	324	"loop: \n"
vpcola	0:a1734fe1ec4b	325	" SUBS %0, %0, #1 \n"
vpcola	0:a1734fe1ec4b	326	" BCS.n loop\n"
vpcola	0:a1734fe1ec4b	327	: "+r" (count)
vpcola	0:a1734fe1ec4b	328	:
vpcola	0:a1734fe1ec4b	329	: "cc"
vpcola	0:a1734fe1ec4b	330	);
vpcola	0:a1734fe1ec4b	331	}
vpcola	0:a1734fe1ec4b	332	#else // GCC
vpcola	0:a1734fe1ec4b	333	static void delay_loop(uint32_t count)
vpcola	0:a1734fe1ec4b	334	{
vpcola	0:a1734fe1ec4b	335	__asm__ volatile (
vpcola	0:a1734fe1ec4b	336	"%=:\n\t"
vpcola	0:a1734fe1ec4b	337	#if defined(__thumb__) && !defined(__thumb2__)
vpcola	0:a1734fe1ec4b	338	"SUB %0, #1\n\t"
vpcola	0:a1734fe1ec4b	339	#else
vpcola	0:a1734fe1ec4b	340	"SUBS %0, %0, #1\n\t"
vpcola	0:a1734fe1ec4b	341	#endif
vpcola	0:a1734fe1ec4b	342	"BCS %=b\n\t"
vpcola	0:a1734fe1ec4b	343	: "+l" (count)
vpcola	0:a1734fe1ec4b	344	:
vpcola	0:a1734fe1ec4b	345	: "cc"
vpcola	0:a1734fe1ec4b	346	);
vpcola	0:a1734fe1ec4b	347	}
vpcola	0:a1734fe1ec4b	348	#endif
vpcola	0:a1734fe1ec4b	349
vpcola	0:a1734fe1ec4b	350	static void delay_ns(uint32_t ns)
vpcola	0:a1734fe1ec4b	351	{
vpcola	0:a1734fe1ec4b	352	uint32_t cycles_per_us = SystemCoreClock / 1000000;
vpcola	0:a1734fe1ec4b	353	// Cortex-M0 takes 4 cycles per loop (SUB=1, BCS=3)
vpcola	0:a1734fe1ec4b	354	// Cortex-M3 and M4 takes 3 cycles per loop (SUB=1, BCS=2)
vpcola	0:a1734fe1ec4b	355	// Cortex-M7 - who knows?
vpcola	0:a1734fe1ec4b	356	// Cortex M3-M7 have "CYCCNT" - would be better than a software loop, but M0 doesn't
vpcola	0:a1734fe1ec4b	357	// Assume 3 cycles per loop for now - will be 33% slow on M0. No biggie,
vpcola	0:a1734fe1ec4b	358	// as original version of code was 300% slow on M4.
vpcola	0:a1734fe1ec4b	359	// [Note that this very calculation, plus call overhead, will take multiple
vpcola	0:a1734fe1ec4b	360	// cycles. Could well be 100ns on its own... So round down here, startup is
vpcola	0:a1734fe1ec4b	361	// worth at least one loop iteration.]
vpcola	0:a1734fe1ec4b	362	uint32_t count = (cycles_per_us * ns) / 3000;
vpcola	0:a1734fe1ec4b	363
vpcola	0:a1734fe1ec4b	364	delay_loop(count);
vpcola	0:a1734fe1ec4b	365	}
vpcola	0:a1734fe1ec4b	366
vpcola	0:a1734fe1ec4b	367	// t1 = 180ns, SEL falling edge to MISO active [SPI setup assumed slow enough to not need manual delay]
vpcola	0:a1734fe1ec4b	368	#define CS_SELECT() {rf->CS = 0; /* delay_ns(180); */}
vpcola	0:a1734fe1ec4b	369	// t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access
vpcola	0:a1734fe1ec4b	370	#define CS_RELEASE() {delay_ns(250); rf->CS = 1; delay_ns(250);}
vpcola	0:a1734fe1ec4b	371
vpcola	0:a1734fe1ec4b	372	/*
vpcola	0:a1734fe1ec4b	373	* \brief Function sets the TX power variable.
vpcola	0:a1734fe1ec4b	374	*
vpcola	0:a1734fe1ec4b	375	* \param power TX power setting
vpcola	0:a1734fe1ec4b	376	*
vpcola	0:a1734fe1ec4b	377	* \return 0 Success
vpcola	0:a1734fe1ec4b	378	* \return -1 Fail
vpcola	0:a1734fe1ec4b	379	*/
vpcola	0:a1734fe1ec4b	380	MBED_UNUSED static int8_t rf_tx_power_set(uint8_t power)
vpcola	0:a1734fe1ec4b	381	{
vpcola	0:a1734fe1ec4b	382	int8_t ret_val = -1;
vpcola	0:a1734fe1ec4b	383
vpcola	0:a1734fe1ec4b	384	radio_tx_power = power;
vpcola	0:a1734fe1ec4b	385	rf_if_lock();
vpcola	0:a1734fe1ec4b	386	rf_if_write_set_tx_power_register(radio_tx_power);
vpcola	0:a1734fe1ec4b	387	rf_if_unlock();
vpcola	0:a1734fe1ec4b	388	ret_val = 0;
vpcola	0:a1734fe1ec4b	389
vpcola	0:a1734fe1ec4b	390	return ret_val;
vpcola	0:a1734fe1ec4b	391	}
vpcola	0:a1734fe1ec4b	392
vpcola	0:a1734fe1ec4b	393	/*
vpcola	0:a1734fe1ec4b	394	* \brief Read connected radio part.
vpcola	0:a1734fe1ec4b	395	*
vpcola	0:a1734fe1ec4b	396	* This function only return valid information when rf_init() is called
vpcola	0:a1734fe1ec4b	397	*
vpcola	0:a1734fe1ec4b	398	* \return
vpcola	0:a1734fe1ec4b	399	*/
vpcola	0:a1734fe1ec4b	400	static rf_trx_part_e rf_radio_type_read(void)
vpcola	0:a1734fe1ec4b	401	{
vpcola	0:a1734fe1ec4b	402	rf_trx_part_e ret_val = ATMEL_UNKNOW_DEV;
vpcola	0:a1734fe1ec4b	403
vpcola	0:a1734fe1ec4b	404	switch (rf_part_num)
vpcola	0:a1734fe1ec4b	405	{
vpcola	0:a1734fe1ec4b	406	case PART_AT86RF212:
vpcola	0:a1734fe1ec4b	407	ret_val = ATMEL_AT86RF212;
vpcola	0:a1734fe1ec4b	408	break;
vpcola	0:a1734fe1ec4b	409	case PART_AT86RF233:
vpcola	0:a1734fe1ec4b	410	ret_val = ATMEL_AT86RF233;
vpcola	0:a1734fe1ec4b	411	break;
vpcola	0:a1734fe1ec4b	412	default:
vpcola	0:a1734fe1ec4b	413	break;
vpcola	0:a1734fe1ec4b	414	}
vpcola	0:a1734fe1ec4b	415
vpcola	0:a1734fe1ec4b	416	return ret_val;
vpcola	0:a1734fe1ec4b	417	}
vpcola	0:a1734fe1ec4b	418
vpcola	0:a1734fe1ec4b	419
vpcola	0:a1734fe1ec4b	420	/*
vpcola	0:a1734fe1ec4b	421	* \brief Function starts the ACK wait timeout.
vpcola	0:a1734fe1ec4b	422	*
vpcola	0:a1734fe1ec4b	423	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	424	*
vpcola	0:a1734fe1ec4b	425	* \return none
vpcola	0:a1734fe1ec4b	426	*/
vpcola	0:a1734fe1ec4b	427	static void rf_if_ack_wait_timer_start(uint16_t slots)
vpcola	0:a1734fe1ec4b	428	{
vpcola	0:a1734fe1ec4b	429	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	430	rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots*50);
vpcola	0:a1734fe1ec4b	431	#else
vpcola	0:a1734fe1ec4b	432	rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots*50);
vpcola	0:a1734fe1ec4b	433	#endif
vpcola	0:a1734fe1ec4b	434	}
vpcola	0:a1734fe1ec4b	435
vpcola	0:a1734fe1ec4b	436	/*
vpcola	0:a1734fe1ec4b	437	* \brief Function starts the calibration interval.
vpcola	0:a1734fe1ec4b	438	*
vpcola	0:a1734fe1ec4b	439	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	440	*
vpcola	0:a1734fe1ec4b	441	* \return none
vpcola	0:a1734fe1ec4b	442	*/
vpcola	0:a1734fe1ec4b	443	static void rf_if_calibration_timer_start(uint32_t slots)
vpcola	0:a1734fe1ec4b	444	{
vpcola	0:a1734fe1ec4b	445	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	446	rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots*50);
vpcola	0:a1734fe1ec4b	447	#else
vpcola	0:a1734fe1ec4b	448	rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots*50);
vpcola	0:a1734fe1ec4b	449	#endif
vpcola	0:a1734fe1ec4b	450	}
vpcola	0:a1734fe1ec4b	451
vpcola	0:a1734fe1ec4b	452	/*
vpcola	0:a1734fe1ec4b	453	* \brief Function starts the CCA interval.
vpcola	0:a1734fe1ec4b	454	*
vpcola	0:a1734fe1ec4b	455	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	456	*
vpcola	0:a1734fe1ec4b	457	* \return none
vpcola	0:a1734fe1ec4b	458	*/
vpcola	0:a1734fe1ec4b	459	static void rf_if_cca_timer_start(uint32_t slots)
vpcola	0:a1734fe1ec4b	460	{
vpcola	0:a1734fe1ec4b	461	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	462	rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots*50);
vpcola	0:a1734fe1ec4b	463	#else
vpcola	0:a1734fe1ec4b	464	rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots*50);
vpcola	0:a1734fe1ec4b	465	#endif
vpcola	0:a1734fe1ec4b	466	}
vpcola	0:a1734fe1ec4b	467
vpcola	0:a1734fe1ec4b	468	/*
vpcola	0:a1734fe1ec4b	469	* \brief Function stops the CCA interval.
vpcola	0:a1734fe1ec4b	470	*
vpcola	0:a1734fe1ec4b	471	* \return none
vpcola	0:a1734fe1ec4b	472	*/
vpcola	0:a1734fe1ec4b	473	static void rf_if_cca_timer_stop(void)
vpcola	0:a1734fe1ec4b	474	{
vpcola	0:a1734fe1ec4b	475	rf->cca_timer.detach();
vpcola	0:a1734fe1ec4b	476	}
vpcola	0:a1734fe1ec4b	477
vpcola	0:a1734fe1ec4b	478	/*
vpcola	0:a1734fe1ec4b	479	* \brief Function stops the ACK wait timeout.
vpcola	0:a1734fe1ec4b	480	*
vpcola	0:a1734fe1ec4b	481	* \param none
vpcola	0:a1734fe1ec4b	482	*
vpcola	0:a1734fe1ec4b	483	* \return none
vpcola	0:a1734fe1ec4b	484	*/
vpcola	0:a1734fe1ec4b	485	static void rf_if_ack_wait_timer_stop(void)
vpcola	0:a1734fe1ec4b	486	{
vpcola	0:a1734fe1ec4b	487	rf->ack_timer.detach();
vpcola	0:a1734fe1ec4b	488	}
vpcola	0:a1734fe1ec4b	489
vpcola	0:a1734fe1ec4b	490	/*
vpcola	0:a1734fe1ec4b	491	* \brief Function sets bit(s) in given RF register.
vpcola	0:a1734fe1ec4b	492	*
vpcola	0:a1734fe1ec4b	493	* \param addr Address of the register to set
vpcola	0:a1734fe1ec4b	494	* \param bit Bit(s) to set
vpcola	0:a1734fe1ec4b	495	* \param bit_mask Masks the field inside the register
vpcola	0:a1734fe1ec4b	496	*
vpcola	0:a1734fe1ec4b	497	* \return none
vpcola	0:a1734fe1ec4b	498	*/
vpcola	0:a1734fe1ec4b	499	static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask)
vpcola	0:a1734fe1ec4b	500	{
vpcola	0:a1734fe1ec4b	501	uint8_t reg = rf_if_read_register(addr);
vpcola	0:a1734fe1ec4b	502	reg &= ~bit_mask;
vpcola	0:a1734fe1ec4b	503	reg \|= bit;
vpcola	0:a1734fe1ec4b	504	rf_if_write_register(addr, reg);
vpcola	0:a1734fe1ec4b	505	}
vpcola	0:a1734fe1ec4b	506
vpcola	0:a1734fe1ec4b	507	/*
vpcola	0:a1734fe1ec4b	508	* \brief Function clears bit(s) in given RF register.
vpcola	0:a1734fe1ec4b	509	*
vpcola	0:a1734fe1ec4b	510	* \param addr Address of the register to clear
vpcola	0:a1734fe1ec4b	511	* \param bit Bit(s) to clear
vpcola	0:a1734fe1ec4b	512	*
vpcola	0:a1734fe1ec4b	513	* \return none
vpcola	0:a1734fe1ec4b	514	*/
vpcola	0:a1734fe1ec4b	515	static void rf_if_clear_bit(uint8_t addr, uint8_t bit)
vpcola	0:a1734fe1ec4b	516	{
vpcola	0:a1734fe1ec4b	517	rf_if_set_bit(addr, 0, bit);
vpcola	0:a1734fe1ec4b	518	}
vpcola	0:a1734fe1ec4b	519
vpcola	0:a1734fe1ec4b	520	/*
vpcola	0:a1734fe1ec4b	521	* \brief Function writes register in RF.
vpcola	0:a1734fe1ec4b	522	*
vpcola	0:a1734fe1ec4b	523	* \param addr Address on the RF
vpcola	0:a1734fe1ec4b	524	* \param data Written data
vpcola	0:a1734fe1ec4b	525	*
vpcola	0:a1734fe1ec4b	526	* \return none
vpcola	0:a1734fe1ec4b	527	*/
vpcola	0:a1734fe1ec4b	528	static void rf_if_write_register(uint8_t addr, uint8_t data)
vpcola	0:a1734fe1ec4b	529	{
vpcola	0:a1734fe1ec4b	530	uint8_t cmd = 0xC0;
vpcola	0:a1734fe1ec4b	531	CS_SELECT();
vpcola	0:a1734fe1ec4b	532	rf_if_spi_exchange(cmd \| addr);
vpcola	0:a1734fe1ec4b	533	rf_if_spi_exchange(data);
vpcola	0:a1734fe1ec4b	534	CS_RELEASE();
vpcola	0:a1734fe1ec4b	535	}
vpcola	0:a1734fe1ec4b	536
vpcola	0:a1734fe1ec4b	537	/*
vpcola	0:a1734fe1ec4b	538	* \brief Function reads RF register.
vpcola	0:a1734fe1ec4b	539	*
vpcola	0:a1734fe1ec4b	540	* \param addr Address on the RF
vpcola	0:a1734fe1ec4b	541	*
vpcola	0:a1734fe1ec4b	542	* \return Read data
vpcola	0:a1734fe1ec4b	543	*/
vpcola	0:a1734fe1ec4b	544	static uint8_t rf_if_read_register(uint8_t addr)
vpcola	0:a1734fe1ec4b	545	{
vpcola	0:a1734fe1ec4b	546	uint8_t cmd = 0x80;
vpcola	0:a1734fe1ec4b	547	uint8_t data;
vpcola	0:a1734fe1ec4b	548	CS_SELECT();
vpcola	0:a1734fe1ec4b	549	rf_if_spi_exchange(cmd \| addr);
vpcola	0:a1734fe1ec4b	550	data = rf_if_spi_exchange(0);
vpcola	0:a1734fe1ec4b	551	CS_RELEASE();
vpcola	0:a1734fe1ec4b	552	return data;
vpcola	0:a1734fe1ec4b	553	}
vpcola	0:a1734fe1ec4b	554
vpcola	0:a1734fe1ec4b	555	/*
vpcola	0:a1734fe1ec4b	556	* \brief Function resets the RF.
vpcola	0:a1734fe1ec4b	557	*
vpcola	0:a1734fe1ec4b	558	* \param none
vpcola	0:a1734fe1ec4b	559	*
vpcola	0:a1734fe1ec4b	560	* \return none
vpcola	0:a1734fe1ec4b	561	*/
vpcola	0:a1734fe1ec4b	562	static void rf_if_reset_radio(void)
vpcola	0:a1734fe1ec4b	563	{
vpcola	0:a1734fe1ec4b	564	rf->spi.frequency(SPI_SPEED);
vpcola	0:a1734fe1ec4b	565	rf->IRQ.rise(0);
vpcola	0:a1734fe1ec4b	566	rf->RST = 1;
vpcola	0:a1734fe1ec4b	567	wait_ms(1);
vpcola	0:a1734fe1ec4b	568	rf->RST = 0;
vpcola	0:a1734fe1ec4b	569	wait_ms(10);
vpcola	0:a1734fe1ec4b	570	CS_RELEASE();
vpcola	0:a1734fe1ec4b	571	rf->SLP_TR = 0;
vpcola	0:a1734fe1ec4b	572	wait_ms(10);
vpcola	0:a1734fe1ec4b	573	rf->RST = 1;
vpcola	0:a1734fe1ec4b	574	wait_ms(10);
vpcola	0:a1734fe1ec4b	575
vpcola	0:a1734fe1ec4b	576	rf->IRQ.rise(&rf_if_interrupt_handler);
vpcola	0:a1734fe1ec4b	577	}
vpcola	0:a1734fe1ec4b	578
vpcola	0:a1734fe1ec4b	579	/*
vpcola	0:a1734fe1ec4b	580	* \brief Function enables the promiscuous mode.
vpcola	0:a1734fe1ec4b	581	*
vpcola	0:a1734fe1ec4b	582	* \param none
vpcola	0:a1734fe1ec4b	583	*
vpcola	0:a1734fe1ec4b	584	* \return none
vpcola	0:a1734fe1ec4b	585	*/
vpcola	0:a1734fe1ec4b	586	static void rf_if_enable_promiscuous_mode(void)
vpcola	0:a1734fe1ec4b	587	{
vpcola	0:a1734fe1ec4b	588	/Set AACK_PROM_MODE to enable the promiscuous mode/
vpcola	0:a1734fe1ec4b	589	rf_if_set_bit(XAH_CTRL_1, AACK_PROM_MODE, AACK_PROM_MODE);
vpcola	0:a1734fe1ec4b	590	}
vpcola	0:a1734fe1ec4b	591
vpcola	0:a1734fe1ec4b	592	/*
vpcola	0:a1734fe1ec4b	593	* \brief Function enables the promiscuous mode.
vpcola	0:a1734fe1ec4b	594	*
vpcola	0:a1734fe1ec4b	595	* \param none
vpcola	0:a1734fe1ec4b	596	*
vpcola	0:a1734fe1ec4b	597	* \return none
vpcola	0:a1734fe1ec4b	598	*/
vpcola	0:a1734fe1ec4b	599	static void rf_if_disable_promiscuous_mode(void)
vpcola	0:a1734fe1ec4b	600	{
vpcola	0:a1734fe1ec4b	601	/Set AACK_PROM_MODE to enable the promiscuous mode/
vpcola	0:a1734fe1ec4b	602	rf_if_clear_bit(XAH_CTRL_1, AACK_PROM_MODE);
vpcola	0:a1734fe1ec4b	603	}
vpcola	0:a1734fe1ec4b	604
vpcola	0:a1734fe1ec4b	605	/*
vpcola	0:a1734fe1ec4b	606	* \brief Function enables the Antenna diversity usage.
vpcola	0:a1734fe1ec4b	607	*
vpcola	0:a1734fe1ec4b	608	* \param none
vpcola	0:a1734fe1ec4b	609	*
vpcola	0:a1734fe1ec4b	610	* \return none
vpcola	0:a1734fe1ec4b	611	*/
vpcola	0:a1734fe1ec4b	612	static void rf_if_enable_ant_div(void)
vpcola	0:a1734fe1ec4b	613	{
vpcola	0:a1734fe1ec4b	614	/Set ANT_EXT_SW_EN to enable controlling of antenna diversity/
vpcola	0:a1734fe1ec4b	615	rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN);
vpcola	0:a1734fe1ec4b	616	}
vpcola	0:a1734fe1ec4b	617
vpcola	0:a1734fe1ec4b	618	/*
vpcola	0:a1734fe1ec4b	619	* \brief Function disables the Antenna diversity usage.
vpcola	0:a1734fe1ec4b	620	*
vpcola	0:a1734fe1ec4b	621	* \param none
vpcola	0:a1734fe1ec4b	622	*
vpcola	0:a1734fe1ec4b	623	* \return none
vpcola	0:a1734fe1ec4b	624	*/
vpcola	0:a1734fe1ec4b	625	static void rf_if_disable_ant_div(void)
vpcola	0:a1734fe1ec4b	626	{
vpcola	0:a1734fe1ec4b	627	rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN);
vpcola	0:a1734fe1ec4b	628	}
vpcola	0:a1734fe1ec4b	629
vpcola	0:a1734fe1ec4b	630	/*
vpcola	0:a1734fe1ec4b	631	* \brief Function sets the SLP TR pin.
vpcola	0:a1734fe1ec4b	632	*
vpcola	0:a1734fe1ec4b	633	* \param none
vpcola	0:a1734fe1ec4b	634	*
vpcola	0:a1734fe1ec4b	635	* \return none
vpcola	0:a1734fe1ec4b	636	*/
vpcola	0:a1734fe1ec4b	637	static void rf_if_enable_slptr(void)
vpcola	0:a1734fe1ec4b	638	{
vpcola	0:a1734fe1ec4b	639	rf->SLP_TR = 1;
vpcola	0:a1734fe1ec4b	640	}
vpcola	0:a1734fe1ec4b	641
vpcola	0:a1734fe1ec4b	642	/*
vpcola	0:a1734fe1ec4b	643	* \brief Function clears the SLP TR pin.
vpcola	0:a1734fe1ec4b	644	*
vpcola	0:a1734fe1ec4b	645	* \param none
vpcola	0:a1734fe1ec4b	646	*
vpcola	0:a1734fe1ec4b	647	* \return none
vpcola	0:a1734fe1ec4b	648	*/
vpcola	0:a1734fe1ec4b	649	static void rf_if_disable_slptr(void)
vpcola	0:a1734fe1ec4b	650	{
vpcola	0:a1734fe1ec4b	651	rf->SLP_TR = 0;
vpcola	0:a1734fe1ec4b	652	}
vpcola	0:a1734fe1ec4b	653
vpcola	0:a1734fe1ec4b	654	/*
vpcola	0:a1734fe1ec4b	655	* \brief Function writes the antenna diversity settings.
vpcola	0:a1734fe1ec4b	656	*
vpcola	0:a1734fe1ec4b	657	* \param none
vpcola	0:a1734fe1ec4b	658	*
vpcola	0:a1734fe1ec4b	659	* \return none
vpcola	0:a1734fe1ec4b	660	*/
vpcola	0:a1734fe1ec4b	661	static void rf_if_write_antenna_diversity_settings(void)
vpcola	0:a1734fe1ec4b	662	{
vpcola	0:a1734fe1ec4b	663	/Recommended setting of PDT_THRES is 3 when antenna diversity is used/
vpcola	0:a1734fe1ec4b	664	rf_if_set_bit(RX_CTRL, 0x03, 0x0f);
vpcola	0:a1734fe1ec4b	665	rf_if_write_register(ANT_DIV, ANT_DIV_EN \| ANT_EXT_SW_EN \| ANT_CTRL_DEFAULT);
vpcola	0:a1734fe1ec4b	666	}
vpcola	0:a1734fe1ec4b	667
vpcola	0:a1734fe1ec4b	668	/*
vpcola	0:a1734fe1ec4b	669	* \brief Function writes the TX output power register.
vpcola	0:a1734fe1ec4b	670	*
vpcola	0:a1734fe1ec4b	671	* \param value Given register value
vpcola	0:a1734fe1ec4b	672	*
vpcola	0:a1734fe1ec4b	673	* \return none
vpcola	0:a1734fe1ec4b	674	*/
vpcola	0:a1734fe1ec4b	675	static void rf_if_write_set_tx_power_register(uint8_t value)
vpcola	0:a1734fe1ec4b	676	{
vpcola	0:a1734fe1ec4b	677	rf_if_write_register(PHY_TX_PWR, value);
vpcola	0:a1734fe1ec4b	678	}
vpcola	0:a1734fe1ec4b	679
vpcola	0:a1734fe1ec4b	680	/*
vpcola	0:a1734fe1ec4b	681	* \brief Function returns the RF part number.
vpcola	0:a1734fe1ec4b	682	*
vpcola	0:a1734fe1ec4b	683	* \param none
vpcola	0:a1734fe1ec4b	684	*
vpcola	0:a1734fe1ec4b	685	* \return part number
vpcola	0:a1734fe1ec4b	686	*/
vpcola	0:a1734fe1ec4b	687	static uint8_t rf_if_read_part_num(void)
vpcola	0:a1734fe1ec4b	688	{
vpcola	0:a1734fe1ec4b	689	return rf_if_read_register(PART_NUM);
vpcola	0:a1734fe1ec4b	690	}
vpcola	0:a1734fe1ec4b	691
vpcola	0:a1734fe1ec4b	692	/*
vpcola	0:a1734fe1ec4b	693	* \brief Function writes the RF settings and initialises SPI interface.
vpcola	0:a1734fe1ec4b	694	*
vpcola	0:a1734fe1ec4b	695	* \param none
vpcola	0:a1734fe1ec4b	696	*
vpcola	0:a1734fe1ec4b	697	* \return none
vpcola	0:a1734fe1ec4b	698	*/
vpcola	0:a1734fe1ec4b	699	static void rf_if_write_rf_settings(void)
vpcola	0:a1734fe1ec4b	700	{
vpcola	0:a1734fe1ec4b	701	/Reset RF module/
vpcola	0:a1734fe1ec4b	702	rf_if_reset_radio();
vpcola	0:a1734fe1ec4b	703
vpcola	0:a1734fe1ec4b	704	rf_part_num = rf_if_read_part_num();
vpcola	0:a1734fe1ec4b	705
vpcola	0:a1734fe1ec4b	706	rf_if_write_register(XAH_CTRL_0,0);
vpcola	0:a1734fe1ec4b	707	rf_if_write_register(TRX_CTRL_1, 0x20);
vpcola	0:a1734fe1ec4b	708
vpcola	0:a1734fe1ec4b	709	/CCA Mode - Carrier sense OR energy above threshold. Channel list is set separately/
vpcola	0:a1734fe1ec4b	710	rf_if_write_register(PHY_CC_CCA, 0x05);
vpcola	0:a1734fe1ec4b	711
vpcola	0:a1734fe1ec4b	712	/Read transceiver PART_NUM/
vpcola	0:a1734fe1ec4b	713	rf_part_num = rf_if_read_register(PART_NUM);
vpcola	0:a1734fe1ec4b	714
vpcola	0:a1734fe1ec4b	715	/Sub-GHz RF settings/
vpcola	0:a1734fe1ec4b	716	if(rf_part_num == PART_AT86RF212)
vpcola	0:a1734fe1ec4b	717	{
vpcola	0:a1734fe1ec4b	718	/GC_TX_OFFS mode-dependent setting - OQPSK/
vpcola	0:a1734fe1ec4b	719	rf_if_write_register(RF_CTRL_0, 0x32);
vpcola	0:a1734fe1ec4b	720
vpcola	0:a1734fe1ec4b	721	if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B)
vpcola	0:a1734fe1ec4b	722	{
vpcola	0:a1734fe1ec4b	723	/TX Output Power setting - 0 dBm North American Band/
vpcola	0:a1734fe1ec4b	724	rf_if_write_register(PHY_TX_PWR, 0x03);
vpcola	0:a1734fe1ec4b	725	}
vpcola	0:a1734fe1ec4b	726	else
vpcola	0:a1734fe1ec4b	727	{
vpcola	0:a1734fe1ec4b	728	/TX Output Power setting - 0 dBm North American Band/
vpcola	0:a1734fe1ec4b	729	rf_if_write_register(PHY_TX_PWR, 0x24);
vpcola	0:a1734fe1ec4b	730	}
vpcola	0:a1734fe1ec4b	731
vpcola	0:a1734fe1ec4b	732	/PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250/
vpcola	0:a1734fe1ec4b	733	rf_if_write_register(TRX_CTRL_2, RF_PHY_MODE);
vpcola	0:a1734fe1ec4b	734	/Based on receiver Characteristics. See AT86RF212B Datasheet where RSSI BASE VALUE in range -97 - -100 dBm/
vpcola	0:a1734fe1ec4b	735	rf_rssi_base_val = -98;
vpcola	0:a1734fe1ec4b	736	}
vpcola	0:a1734fe1ec4b	737	/2.4GHz RF settings/
vpcola	0:a1734fe1ec4b	738	else
vpcola	0:a1734fe1ec4b	739	{
vpcola	0:a1734fe1ec4b	740	#if 0
vpcola	0:a1734fe1ec4b	741	/* Disable power saving functions for now - can only impact reliability,
vpcola	0:a1734fe1ec4b	742	* and don't have any users demanding it. */
vpcola	0:a1734fe1ec4b	743	/Set RPC register/
vpcola	0:a1734fe1ec4b	744	rf_if_write_register(TRX_RPC, RX_RPC_CTRL\|RX_RPC_EN\|PLL_RPC_EN\|XAH_TX_RPC_EN\|IPAN_RPC_EN\|TRX_RPC_RSVD_1);
vpcola	0:a1734fe1ec4b	745	#endif
vpcola	0:a1734fe1ec4b	746	/PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s/
vpcola	0:a1734fe1ec4b	747	rf_if_write_register(TRX_CTRL_2, 0);
vpcola	0:a1734fe1ec4b	748	rf_rssi_base_val = -91;
vpcola	0:a1734fe1ec4b	749	}
vpcola	0:a1734fe1ec4b	750	}
vpcola	0:a1734fe1ec4b	751
vpcola	0:a1734fe1ec4b	752	/*
vpcola	0:a1734fe1ec4b	753	* \brief Function checks the channel availability
vpcola	0:a1734fe1ec4b	754	*
vpcola	0:a1734fe1ec4b	755	* \param none
vpcola	0:a1734fe1ec4b	756	*
vpcola	0:a1734fe1ec4b	757	* \return 1 Channel clear
vpcola	0:a1734fe1ec4b	758	* \return 0 Channel not clear
vpcola	0:a1734fe1ec4b	759	*/
vpcola	0:a1734fe1ec4b	760	static uint8_t rf_if_check_cca(void)
vpcola	0:a1734fe1ec4b	761	{
vpcola	0:a1734fe1ec4b	762	uint8_t retval = 0;
vpcola	0:a1734fe1ec4b	763	if(rf_if_read_register(TRX_STATUS) & CCA_STATUS)
vpcola	0:a1734fe1ec4b	764	{
vpcola	0:a1734fe1ec4b	765	retval = 1;
vpcola	0:a1734fe1ec4b	766	}
vpcola	0:a1734fe1ec4b	767	return retval;
vpcola	0:a1734fe1ec4b	768	}
vpcola	0:a1734fe1ec4b	769
vpcola	0:a1734fe1ec4b	770	/*
vpcola	0:a1734fe1ec4b	771	* \brief Function returns the RF state
vpcola	0:a1734fe1ec4b	772	*
vpcola	0:a1734fe1ec4b	773	* \param none
vpcola	0:a1734fe1ec4b	774	*
vpcola	0:a1734fe1ec4b	775	* \return RF state
vpcola	0:a1734fe1ec4b	776	*/
vpcola	0:a1734fe1ec4b	777	static uint8_t rf_if_read_trx_state(void)
vpcola	0:a1734fe1ec4b	778	{
vpcola	0:a1734fe1ec4b	779	return rf_if_read_register(TRX_STATUS) & 0x1F;
vpcola	0:a1734fe1ec4b	780	}
vpcola	0:a1734fe1ec4b	781
vpcola	0:a1734fe1ec4b	782	/*
vpcola	0:a1734fe1ec4b	783	* \brief Function reads packet buffer.
vpcola	0:a1734fe1ec4b	784	*
vpcola	0:a1734fe1ec4b	785	* \param data_out Output buffer
vpcola	0:a1734fe1ec4b	786	* \param lqi_out LQI output
vpcola	0:a1734fe1ec4b	787	* \param ed_out ED output
vpcola	0:a1734fe1ec4b	788	* \param crc_good CRC good indication
vpcola	0:a1734fe1ec4b	789	*
vpcola	0:a1734fe1ec4b	790	* \return PSDU length [0..RF_MTU]
vpcola	0:a1734fe1ec4b	791	*/
vpcola	0:a1734fe1ec4b	792	static uint16_t rf_if_read_packet(uint8_t data_out[RF_MTU], uint8_t lqi_out, uint8_t ed_out, bool *crc_good)
vpcola	0:a1734fe1ec4b	793	{
vpcola	0:a1734fe1ec4b	794	CS_SELECT();
vpcola	0:a1734fe1ec4b	795	rf_if_spi_exchange(0x20);
vpcola	0:a1734fe1ec4b	796	uint8_t len = rf_if_spi_exchange(0) & 0x7F;
vpcola	0:a1734fe1ec4b	797	uint8_t *ptr = data_out;
vpcola	0:a1734fe1ec4b	798	for (uint_fast8_t i = 0; i < len; i++) {
vpcola	0:a1734fe1ec4b	799	*ptr++ = rf_if_spi_exchange(0);
vpcola	0:a1734fe1ec4b	800	}
vpcola	0:a1734fe1ec4b	801
vpcola	0:a1734fe1ec4b	802	*lqi_out = rf_if_spi_exchange(0);
vpcola	0:a1734fe1ec4b	803	*ed_out = rf_if_spi_exchange(0);
vpcola	0:a1734fe1ec4b	804	*crc_good = rf_if_spi_exchange(0) & 0x80;
vpcola	0:a1734fe1ec4b	805	CS_RELEASE();
vpcola	0:a1734fe1ec4b	806
vpcola	0:a1734fe1ec4b	807	return len;
vpcola	0:a1734fe1ec4b	808	}
vpcola	0:a1734fe1ec4b	809
vpcola	0:a1734fe1ec4b	810	/*
vpcola	0:a1734fe1ec4b	811	* \brief Function writes RF short address registers
vpcola	0:a1734fe1ec4b	812	*
vpcola	0:a1734fe1ec4b	813	* \param short_address Given short address
vpcola	0:a1734fe1ec4b	814	*
vpcola	0:a1734fe1ec4b	815	* \return none
vpcola	0:a1734fe1ec4b	816	*/
vpcola	0:a1734fe1ec4b	817	static void rf_if_write_short_addr_registers(uint8_t *short_address)
vpcola	0:a1734fe1ec4b	818	{
vpcola	0:a1734fe1ec4b	819	rf_if_write_register(SHORT_ADDR_1, *short_address++);
vpcola	0:a1734fe1ec4b	820	rf_if_write_register(SHORT_ADDR_0, *short_address);
vpcola	0:a1734fe1ec4b	821	}
vpcola	0:a1734fe1ec4b	822
vpcola	0:a1734fe1ec4b	823	/*
vpcola	0:a1734fe1ec4b	824	* \brief Function sets the frame pending in ACK message
vpcola	0:a1734fe1ec4b	825	*
vpcola	0:a1734fe1ec4b	826	* \param state Given frame pending state
vpcola	0:a1734fe1ec4b	827	*
vpcola	0:a1734fe1ec4b	828	* \return none
vpcola	0:a1734fe1ec4b	829	*/
vpcola	0:a1734fe1ec4b	830	static void rf_if_ack_pending_ctrl(uint8_t state)
vpcola	0:a1734fe1ec4b	831	{
vpcola	0:a1734fe1ec4b	832	rf_if_lock();
vpcola	0:a1734fe1ec4b	833	if(state)
vpcola	0:a1734fe1ec4b	834	{
vpcola	0:a1734fe1ec4b	835	rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD));
vpcola	0:a1734fe1ec4b	836	}
vpcola	0:a1734fe1ec4b	837	else
vpcola	0:a1734fe1ec4b	838	{
vpcola	0:a1734fe1ec4b	839	rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD));
vpcola	0:a1734fe1ec4b	840	}
vpcola	0:a1734fe1ec4b	841	rf_if_unlock();
vpcola	0:a1734fe1ec4b	842	}
vpcola	0:a1734fe1ec4b	843
vpcola	0:a1734fe1ec4b	844	/*
vpcola	0:a1734fe1ec4b	845	* \brief Function returns the state of frame pending control
vpcola	0:a1734fe1ec4b	846	*
vpcola	0:a1734fe1ec4b	847	* \param none
vpcola	0:a1734fe1ec4b	848	*
vpcola	0:a1734fe1ec4b	849	* \return Frame pending state
vpcola	0:a1734fe1ec4b	850	*/
vpcola	0:a1734fe1ec4b	851	static uint8_t rf_if_last_acked_pending(void)
vpcola	0:a1734fe1ec4b	852	{
vpcola	0:a1734fe1ec4b	853	uint8_t last_acked_data_pending;
vpcola	0:a1734fe1ec4b	854
vpcola	0:a1734fe1ec4b	855	rf_if_lock();
vpcola	0:a1734fe1ec4b	856	if(rf_if_read_register(CSMA_SEED_1) & 0x20)
vpcola	0:a1734fe1ec4b	857	last_acked_data_pending = 1;
vpcola	0:a1734fe1ec4b	858	else
vpcola	0:a1734fe1ec4b	859	last_acked_data_pending = 0;
vpcola	0:a1734fe1ec4b	860	rf_if_unlock();
vpcola	0:a1734fe1ec4b	861
vpcola	0:a1734fe1ec4b	862	return last_acked_data_pending;
vpcola	0:a1734fe1ec4b	863	}
vpcola	0:a1734fe1ec4b	864
vpcola	0:a1734fe1ec4b	865	/*
vpcola	0:a1734fe1ec4b	866	* \brief Function calibrates the RF part.
vpcola	0:a1734fe1ec4b	867	*
vpcola	0:a1734fe1ec4b	868	* \param none
vpcola	0:a1734fe1ec4b	869	*
vpcola	0:a1734fe1ec4b	870	* \return none
vpcola	0:a1734fe1ec4b	871	*/
vpcola	0:a1734fe1ec4b	872	static void rf_if_calibration(void)
vpcola	0:a1734fe1ec4b	873	{
vpcola	0:a1734fe1ec4b	874	rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START);
vpcola	0:a1734fe1ec4b	875	/Wait while calibration is running/
vpcola	0:a1734fe1ec4b	876	while(rf_if_read_register(FTN_CTRL) & FTN_START);
vpcola	0:a1734fe1ec4b	877	}
vpcola	0:a1734fe1ec4b	878
vpcola	0:a1734fe1ec4b	879	/*
vpcola	0:a1734fe1ec4b	880	* \brief Function writes RF PAN Id registers
vpcola	0:a1734fe1ec4b	881	*
vpcola	0:a1734fe1ec4b	882	* \param pan_id Given PAN Id
vpcola	0:a1734fe1ec4b	883	*
vpcola	0:a1734fe1ec4b	884	* \return none
vpcola	0:a1734fe1ec4b	885	*/
vpcola	0:a1734fe1ec4b	886	static void rf_if_write_pan_id_registers(uint8_t *pan_id)
vpcola	0:a1734fe1ec4b	887	{
vpcola	0:a1734fe1ec4b	888	rf_if_write_register(PAN_ID_1, *pan_id++);
vpcola	0:a1734fe1ec4b	889	rf_if_write_register(PAN_ID_0, *pan_id);
vpcola	0:a1734fe1ec4b	890	}
vpcola	0:a1734fe1ec4b	891
vpcola	0:a1734fe1ec4b	892	/*
vpcola	0:a1734fe1ec4b	893	* \brief Function writes RF IEEE Address registers
vpcola	0:a1734fe1ec4b	894	*
vpcola	0:a1734fe1ec4b	895	* \param address Given IEEE Address
vpcola	0:a1734fe1ec4b	896	*
vpcola	0:a1734fe1ec4b	897	* \return none
vpcola	0:a1734fe1ec4b	898	*/
vpcola	0:a1734fe1ec4b	899	static void rf_if_write_ieee_addr_registers(uint8_t *address)
vpcola	0:a1734fe1ec4b	900	{
vpcola	0:a1734fe1ec4b	901	uint8_t i;
vpcola	0:a1734fe1ec4b	902	uint8_t temp = IEEE_ADDR_0;
vpcola	0:a1734fe1ec4b	903
vpcola	0:a1734fe1ec4b	904	for(i=0; i<8; i++)
vpcola	0:a1734fe1ec4b	905	rf_if_write_register(temp++, address[7-i]);
vpcola	0:a1734fe1ec4b	906	}
vpcola	0:a1734fe1ec4b	907
vpcola	0:a1734fe1ec4b	908	/*
vpcola	0:a1734fe1ec4b	909	* \brief Function writes data in RF frame buffer.
vpcola	0:a1734fe1ec4b	910	*
vpcola	0:a1734fe1ec4b	911	* \param ptr Pointer to data (PSDU, except FCS)
vpcola	0:a1734fe1ec4b	912	* \param length Pointer to length (PSDU length, minus 2 for FCS)
vpcola	0:a1734fe1ec4b	913	*
vpcola	0:a1734fe1ec4b	914	* \return none
vpcola	0:a1734fe1ec4b	915	*/
vpcola	0:a1734fe1ec4b	916	static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length)
vpcola	0:a1734fe1ec4b	917	{
vpcola	0:a1734fe1ec4b	918	uint8_t i;
vpcola	0:a1734fe1ec4b	919	uint8_t cmd = 0x60;
vpcola	0:a1734fe1ec4b	920
vpcola	0:a1734fe1ec4b	921	CS_SELECT();
vpcola	0:a1734fe1ec4b	922	rf_if_spi_exchange(cmd);
vpcola	0:a1734fe1ec4b	923	rf_if_spi_exchange(length + 2);
vpcola	0:a1734fe1ec4b	924	for(i=0; i<length; i++)
vpcola	0:a1734fe1ec4b	925	rf_if_spi_exchange(*ptr++);
vpcola	0:a1734fe1ec4b	926
vpcola	0:a1734fe1ec4b	927	CS_RELEASE();
vpcola	0:a1734fe1ec4b	928	}
vpcola	0:a1734fe1ec4b	929
vpcola	0:a1734fe1ec4b	930	/*
vpcola	0:a1734fe1ec4b	931	* \brief Function returns 8-bit random value.
vpcola	0:a1734fe1ec4b	932	*
vpcola	0:a1734fe1ec4b	933	* \param none
vpcola	0:a1734fe1ec4b	934	*
vpcola	0:a1734fe1ec4b	935	* \return random value
vpcola	0:a1734fe1ec4b	936	*/
vpcola	0:a1734fe1ec4b	937	static uint8_t rf_if_read_rnd(void)
vpcola	0:a1734fe1ec4b	938	{
vpcola	0:a1734fe1ec4b	939	uint8_t temp;
vpcola	0:a1734fe1ec4b	940	uint8_t tmp_rpc_val = 0;
vpcola	0:a1734fe1ec4b	941	/RPC must be disabled while reading the random number/
vpcola	0:a1734fe1ec4b	942	if(rf_part_num == PART_AT86RF233)
vpcola	0:a1734fe1ec4b	943	{
vpcola	0:a1734fe1ec4b	944	tmp_rpc_val = rf_if_read_register(TRX_RPC);
vpcola	0:a1734fe1ec4b	945	rf_if_write_register(TRX_RPC, RX_RPC_CTRL\|TRX_RPC_RSVD_1);
vpcola	0:a1734fe1ec4b	946	}
vpcola	0:a1734fe1ec4b	947
vpcola	0:a1734fe1ec4b	948	wait_ms(1);
vpcola	0:a1734fe1ec4b	949	temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6);
vpcola	0:a1734fe1ec4b	950	wait_ms(1);
vpcola	0:a1734fe1ec4b	951	temp \|= ((rf_if_read_register(PHY_RSSI)>>5) << 4);
vpcola	0:a1734fe1ec4b	952	wait_ms(1);
vpcola	0:a1734fe1ec4b	953	temp \|= ((rf_if_read_register(PHY_RSSI)>>5) << 2);
vpcola	0:a1734fe1ec4b	954	wait_ms(1);
vpcola	0:a1734fe1ec4b	955	temp \|= ((rf_if_read_register(PHY_RSSI)>>5));
vpcola	0:a1734fe1ec4b	956	wait_ms(1);
vpcola	0:a1734fe1ec4b	957	if(rf_part_num == PART_AT86RF233)
vpcola	0:a1734fe1ec4b	958	rf_if_write_register(TRX_RPC, tmp_rpc_val);
vpcola	0:a1734fe1ec4b	959	return temp;
vpcola	0:a1734fe1ec4b	960	}
vpcola	0:a1734fe1ec4b	961
vpcola	0:a1734fe1ec4b	962	/*
vpcola	0:a1734fe1ec4b	963	* \brief Function changes the state of the RF.
vpcola	0:a1734fe1ec4b	964	*
vpcola	0:a1734fe1ec4b	965	* \param trx_state Given RF state
vpcola	0:a1734fe1ec4b	966	*
vpcola	0:a1734fe1ec4b	967	* \return none
vpcola	0:a1734fe1ec4b	968	*/
vpcola	0:a1734fe1ec4b	969	static void rf_if_change_trx_state(rf_trx_states_t trx_state)
vpcola	0:a1734fe1ec4b	970	{
vpcola	0:a1734fe1ec4b	971	// XXX Lock claim apparently not required
vpcola	0:a1734fe1ec4b	972	rf_if_lock();
vpcola	0:a1734fe1ec4b	973	rf_if_write_register(TRX_STATE, trx_state);
vpcola	0:a1734fe1ec4b	974	/Wait while not in desired state/
vpcola	0:a1734fe1ec4b	975	rf_poll_trx_state_change(trx_state);
vpcola	0:a1734fe1ec4b	976	rf_if_unlock();
vpcola	0:a1734fe1ec4b	977	}
vpcola	0:a1734fe1ec4b	978
vpcola	0:a1734fe1ec4b	979	/*
vpcola	0:a1734fe1ec4b	980	* \brief Function enables the TX END interrupt
vpcola	0:a1734fe1ec4b	981	*
vpcola	0:a1734fe1ec4b	982	* \param none
vpcola	0:a1734fe1ec4b	983	*
vpcola	0:a1734fe1ec4b	984	* \return none
vpcola	0:a1734fe1ec4b	985	*/
vpcola	0:a1734fe1ec4b	986	static void rf_if_enable_tx_end_interrupt(void)
vpcola	0:a1734fe1ec4b	987	{
vpcola	0:a1734fe1ec4b	988	rf_if_set_bit(IRQ_MASK, TRX_END, TRX_END);
vpcola	0:a1734fe1ec4b	989	}
vpcola	0:a1734fe1ec4b	990
vpcola	0:a1734fe1ec4b	991	/*
vpcola	0:a1734fe1ec4b	992	* \brief Function enables the RX END interrupt
vpcola	0:a1734fe1ec4b	993	*
vpcola	0:a1734fe1ec4b	994	* \param none
vpcola	0:a1734fe1ec4b	995	*
vpcola	0:a1734fe1ec4b	996	* \return none
vpcola	0:a1734fe1ec4b	997	*/
vpcola	0:a1734fe1ec4b	998	static void rf_if_enable_rx_end_interrupt(void)
vpcola	0:a1734fe1ec4b	999	{
vpcola	0:a1734fe1ec4b	1000	rf_if_set_bit(IRQ_MASK, TRX_END, TRX_END);
vpcola	0:a1734fe1ec4b	1001	}
vpcola	0:a1734fe1ec4b	1002
vpcola	0:a1734fe1ec4b	1003	/*
vpcola	0:a1734fe1ec4b	1004	* \brief Function enables the CCA ED interrupt
vpcola	0:a1734fe1ec4b	1005	*
vpcola	0:a1734fe1ec4b	1006	* \param none
vpcola	0:a1734fe1ec4b	1007	*
vpcola	0:a1734fe1ec4b	1008	* \return none
vpcola	0:a1734fe1ec4b	1009	*/
vpcola	0:a1734fe1ec4b	1010	static void rf_if_enable_cca_ed_done_interrupt(void)
vpcola	0:a1734fe1ec4b	1011	{
vpcola	0:a1734fe1ec4b	1012	rf_if_set_bit(IRQ_MASK, CCA_ED_DONE, CCA_ED_DONE);
vpcola	0:a1734fe1ec4b	1013	}
vpcola	0:a1734fe1ec4b	1014
vpcola	0:a1734fe1ec4b	1015	/*
vpcola	0:a1734fe1ec4b	1016	* \brief Function starts the CCA process
vpcola	0:a1734fe1ec4b	1017	*
vpcola	0:a1734fe1ec4b	1018	* \param none
vpcola	0:a1734fe1ec4b	1019	*
vpcola	0:a1734fe1ec4b	1020	* \return none
vpcola	0:a1734fe1ec4b	1021	*/
vpcola	0:a1734fe1ec4b	1022	static void rf_if_start_cca_process(void)
vpcola	0:a1734fe1ec4b	1023	{
vpcola	0:a1734fe1ec4b	1024	rf_if_set_bit(PHY_CC_CCA, CCA_REQUEST, CCA_REQUEST);
vpcola	0:a1734fe1ec4b	1025	}
vpcola	0:a1734fe1ec4b	1026
vpcola	0:a1734fe1ec4b	1027	/*
vpcola	0:a1734fe1ec4b	1028	* \brief Function scales RSSI
vpcola	0:a1734fe1ec4b	1029	*
vpcola	0:a1734fe1ec4b	1030	* \param ed_level ED level read from chip
vpcola	0:a1734fe1ec4b	1031	*
vpcola	0:a1734fe1ec4b	1032	* \return appropriately scaled RSSI dBm
vpcola	0:a1734fe1ec4b	1033	*/
vpcola	0:a1734fe1ec4b	1034	static int8_t rf_if_scale_rssi(uint8_t ed_level)
vpcola	0:a1734fe1ec4b	1035	{
vpcola	0:a1734fe1ec4b	1036	if (rf_part_num == PART_AT86RF212) {
vpcola	0:a1734fe1ec4b	1037	/* Data sheet says to multiply by 1.03 - this is 1.03125, rounding down */
vpcola	0:a1734fe1ec4b	1038	ed_level += ed_level >> 5;
vpcola	0:a1734fe1ec4b	1039	}
vpcola	0:a1734fe1ec4b	1040	return rf_rssi_base_val + ed_level;
vpcola	0:a1734fe1ec4b	1041	}
vpcola	0:a1734fe1ec4b	1042
vpcola	0:a1734fe1ec4b	1043	/*
vpcola	0:a1734fe1ec4b	1044	* \brief Function sets the RF channel field
vpcola	0:a1734fe1ec4b	1045	*
vpcola	0:a1734fe1ec4b	1046	* \param Given channel
vpcola	0:a1734fe1ec4b	1047	*
vpcola	0:a1734fe1ec4b	1048	* \return none
vpcola	0:a1734fe1ec4b	1049	*/
vpcola	0:a1734fe1ec4b	1050	static void rf_if_set_channel_register(uint8_t channel)
vpcola	0:a1734fe1ec4b	1051	{
vpcola	0:a1734fe1ec4b	1052	rf_if_set_bit(PHY_CC_CCA, channel, 0x1f);
vpcola	0:a1734fe1ec4b	1053	}
vpcola	0:a1734fe1ec4b	1054
vpcola	0:a1734fe1ec4b	1055	/*
vpcola	0:a1734fe1ec4b	1056	* \brief Function enables RF irq pin interrupts in RF interface.
vpcola	0:a1734fe1ec4b	1057	*
vpcola	0:a1734fe1ec4b	1058	* \param none
vpcola	0:a1734fe1ec4b	1059	*
vpcola	0:a1734fe1ec4b	1060	* \return none
vpcola	0:a1734fe1ec4b	1061	*/
vpcola	0:a1734fe1ec4b	1062	static void rf_if_enable_irq(void)
vpcola	0:a1734fe1ec4b	1063	{
vpcola	0:a1734fe1ec4b	1064	rf->IRQ.enable_irq();
vpcola	0:a1734fe1ec4b	1065	}
vpcola	0:a1734fe1ec4b	1066
vpcola	0:a1734fe1ec4b	1067	/*
vpcola	0:a1734fe1ec4b	1068	* \brief Function disables RF irq pin interrupts in RF interface.
vpcola	0:a1734fe1ec4b	1069	*
vpcola	0:a1734fe1ec4b	1070	* \param none
vpcola	0:a1734fe1ec4b	1071	*
vpcola	0:a1734fe1ec4b	1072	* \return none
vpcola	0:a1734fe1ec4b	1073	*/
vpcola	0:a1734fe1ec4b	1074	static void rf_if_disable_irq(void)
vpcola	0:a1734fe1ec4b	1075	{
vpcola	0:a1734fe1ec4b	1076	rf->IRQ.disable_irq();
vpcola	0:a1734fe1ec4b	1077	}
vpcola	0:a1734fe1ec4b	1078
vpcola	0:a1734fe1ec4b	1079	#ifdef MBED_CONF_RTOS_PRESENT
vpcola	0:a1734fe1ec4b	1080	static void rf_if_interrupt_handler(void)
vpcola	0:a1734fe1ec4b	1081	{
vpcola	0:a1734fe1ec4b	1082	rf->irq_thread.signal_set(SIG_RADIO);
vpcola	0:a1734fe1ec4b	1083	}
vpcola	0:a1734fe1ec4b	1084
vpcola	0:a1734fe1ec4b	1085	// Started during construction of rf, so variable
vpcola	0:a1734fe1ec4b	1086	// rf isn't set at the start. Uses 'this' instead.
vpcola	0:a1734fe1ec4b	1087	void RFBits::rf_if_irq_task(void)
vpcola	0:a1734fe1ec4b	1088	{
vpcola	0:a1734fe1ec4b	1089	for (;;) {
vpcola	0:a1734fe1ec4b	1090	osEvent event = irq_thread.signal_wait(0);
vpcola	0:a1734fe1ec4b	1091	if (event.status != osEventSignal) {
vpcola	0:a1734fe1ec4b	1092	continue;
vpcola	0:a1734fe1ec4b	1093	}
vpcola	0:a1734fe1ec4b	1094	rf_if_lock();
vpcola	0:a1734fe1ec4b	1095	if (event.value.signals & SIG_RADIO) {
vpcola	0:a1734fe1ec4b	1096	rf_if_irq_task_process_irq();
vpcola	0:a1734fe1ec4b	1097	}
vpcola	0:a1734fe1ec4b	1098	if (event.value.signals & SIG_TIMER_ACK) {
vpcola	0:a1734fe1ec4b	1099	rf_ack_wait_timer_interrupt();
vpcola	0:a1734fe1ec4b	1100	}
vpcola	0:a1734fe1ec4b	1101	if (event.value.signals & SIG_TIMER_CCA) {
vpcola	0:a1734fe1ec4b	1102	rf_cca_timer_interrupt();
vpcola	0:a1734fe1ec4b	1103	}
vpcola	0:a1734fe1ec4b	1104	if (event.value.signals & SIG_TIMER_CAL) {
vpcola	0:a1734fe1ec4b	1105	rf_calibration_timer_interrupt();
vpcola	0:a1734fe1ec4b	1106	}
vpcola	0:a1734fe1ec4b	1107	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1108	}
vpcola	0:a1734fe1ec4b	1109	}
vpcola	0:a1734fe1ec4b	1110
vpcola	0:a1734fe1ec4b	1111	static void rf_if_irq_task_process_irq(void)
vpcola	0:a1734fe1ec4b	1112	#else
vpcola	0:a1734fe1ec4b	1113	/*
vpcola	0:a1734fe1ec4b	1114	* \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
vpcola	0:a1734fe1ec4b	1115	*
vpcola	0:a1734fe1ec4b	1116	* \param none
vpcola	0:a1734fe1ec4b	1117	*
vpcola	0:a1734fe1ec4b	1118	* \return none
vpcola	0:a1734fe1ec4b	1119	*/
vpcola	0:a1734fe1ec4b	1120	static void rf_if_interrupt_handler(void)
vpcola	0:a1734fe1ec4b	1121	#endif
vpcola	0:a1734fe1ec4b	1122	{
vpcola	0:a1734fe1ec4b	1123	uint8_t irq_status;
vpcola	0:a1734fe1ec4b	1124
vpcola	0:a1734fe1ec4b	1125	/Read interrupt flag/
vpcola	0:a1734fe1ec4b	1126	irq_status = rf_if_read_register(IRQ_STATUS);
vpcola	0:a1734fe1ec4b	1127
vpcola	0:a1734fe1ec4b	1128	/Disable interrupt on RF/
vpcola	0:a1734fe1ec4b	1129	rf_if_clear_bit(IRQ_MASK, irq_status);
vpcola	0:a1734fe1ec4b	1130	/RX start interrupt/
vpcola	0:a1734fe1ec4b	1131	if(irq_status & RX_START)
vpcola	0:a1734fe1ec4b	1132	{
vpcola	0:a1734fe1ec4b	1133	}
vpcola	0:a1734fe1ec4b	1134	/Address matching interrupt/
vpcola	0:a1734fe1ec4b	1135	if(irq_status & AMI)
vpcola	0:a1734fe1ec4b	1136	{
vpcola	0:a1734fe1ec4b	1137	}
vpcola	0:a1734fe1ec4b	1138	if(irq_status & TRX_UR)
vpcola	0:a1734fe1ec4b	1139	{
vpcola	0:a1734fe1ec4b	1140	}
vpcola	0:a1734fe1ec4b	1141	/Frame end interrupt (RX and TX)/
vpcola	0:a1734fe1ec4b	1142	if(irq_status & TRX_END)
vpcola	0:a1734fe1ec4b	1143	{
vpcola	0:a1734fe1ec4b	1144	/TX done interrupt/
vpcola	0:a1734fe1ec4b	1145	if(rf_if_read_trx_state() == PLL_ON \|\| rf_if_read_trx_state() == TX_ARET_ON)
vpcola	0:a1734fe1ec4b	1146	{
vpcola	0:a1734fe1ec4b	1147	rf_handle_tx_end();
vpcola	0:a1734fe1ec4b	1148	}
vpcola	0:a1734fe1ec4b	1149	/Frame received interrupt/
vpcola	0:a1734fe1ec4b	1150	else
vpcola	0:a1734fe1ec4b	1151	{
vpcola	0:a1734fe1ec4b	1152	rf_handle_rx_end();
vpcola	0:a1734fe1ec4b	1153	}
vpcola	0:a1734fe1ec4b	1154	}
vpcola	0:a1734fe1ec4b	1155	if(irq_status & CCA_ED_DONE)
vpcola	0:a1734fe1ec4b	1156	{
vpcola	0:a1734fe1ec4b	1157	rf_handle_cca_ed_done();
vpcola	0:a1734fe1ec4b	1158	}
vpcola	0:a1734fe1ec4b	1159	}
vpcola	0:a1734fe1ec4b	1160
vpcola	0:a1734fe1ec4b	1161	/*
vpcola	0:a1734fe1ec4b	1162	* \brief Function writes/read data in SPI interface
vpcola	0:a1734fe1ec4b	1163	*
vpcola	0:a1734fe1ec4b	1164	* \param out Output data
vpcola	0:a1734fe1ec4b	1165	*
vpcola	0:a1734fe1ec4b	1166	* \return Input data
vpcola	0:a1734fe1ec4b	1167	*/
vpcola	0:a1734fe1ec4b	1168	static uint8_t rf_if_spi_exchange(uint8_t out)
vpcola	0:a1734fe1ec4b	1169	{
vpcola	0:a1734fe1ec4b	1170	uint8_t v;
vpcola	0:a1734fe1ec4b	1171	v = rf->spi.write(out);
vpcola	0:a1734fe1ec4b	1172	// t9 = t5 = 250ns, delay between LSB of last byte to next MSB or delay between LSB & SEL rising
vpcola	0:a1734fe1ec4b	1173	// [SPI setup assumed slow enough to not need manual delay]
vpcola	0:a1734fe1ec4b	1174	// delay_ns(250);
vpcola	0:a1734fe1ec4b	1175	return v;
vpcola	0:a1734fe1ec4b	1176	}
vpcola	0:a1734fe1ec4b	1177
vpcola	0:a1734fe1ec4b	1178	/*
vpcola	0:a1734fe1ec4b	1179	* \brief Function sets given RF flag on.
vpcola	0:a1734fe1ec4b	1180	*
vpcola	0:a1734fe1ec4b	1181	* \param x Given RF flag
vpcola	0:a1734fe1ec4b	1182	*
vpcola	0:a1734fe1ec4b	1183	* \return none
vpcola	0:a1734fe1ec4b	1184	*/
vpcola	0:a1734fe1ec4b	1185	static void rf_flags_set(uint8_t x)
vpcola	0:a1734fe1ec4b	1186	{
vpcola	0:a1734fe1ec4b	1187	rf_flags \|= x;
vpcola	0:a1734fe1ec4b	1188	}
vpcola	0:a1734fe1ec4b	1189
vpcola	0:a1734fe1ec4b	1190	/*
vpcola	0:a1734fe1ec4b	1191	* \brief Function clears given RF flag on.
vpcola	0:a1734fe1ec4b	1192	*
vpcola	0:a1734fe1ec4b	1193	* \param x Given RF flag
vpcola	0:a1734fe1ec4b	1194	*
vpcola	0:a1734fe1ec4b	1195	* \return none
vpcola	0:a1734fe1ec4b	1196	*/
vpcola	0:a1734fe1ec4b	1197	static void rf_flags_clear(uint8_t x)
vpcola	0:a1734fe1ec4b	1198	{
vpcola	0:a1734fe1ec4b	1199	rf_flags &= ~x;
vpcola	0:a1734fe1ec4b	1200	}
vpcola	0:a1734fe1ec4b	1201
vpcola	0:a1734fe1ec4b	1202	/*
vpcola	0:a1734fe1ec4b	1203	* \brief Function checks if given RF flag is on.
vpcola	0:a1734fe1ec4b	1204	*
vpcola	0:a1734fe1ec4b	1205	* \param x Given RF flag
vpcola	0:a1734fe1ec4b	1206	*
vpcola	0:a1734fe1ec4b	1207	* \return states of the given flags
vpcola	0:a1734fe1ec4b	1208	*/
vpcola	0:a1734fe1ec4b	1209	static uint8_t rf_flags_check(uint8_t x)
vpcola	0:a1734fe1ec4b	1210	{
vpcola	0:a1734fe1ec4b	1211	return (rf_flags & x);
vpcola	0:a1734fe1ec4b	1212	}
vpcola	0:a1734fe1ec4b	1213
vpcola	0:a1734fe1ec4b	1214	/*
vpcola	0:a1734fe1ec4b	1215	* \brief Function clears all RF flags.
vpcola	0:a1734fe1ec4b	1216	*
vpcola	0:a1734fe1ec4b	1217	* \param none
vpcola	0:a1734fe1ec4b	1218	*
vpcola	0:a1734fe1ec4b	1219	* \return none
vpcola	0:a1734fe1ec4b	1220	*/
vpcola	0:a1734fe1ec4b	1221	static void rf_flags_reset(void)
vpcola	0:a1734fe1ec4b	1222	{
vpcola	0:a1734fe1ec4b	1223	rf_flags = 0;
vpcola	0:a1734fe1ec4b	1224	}
vpcola	0:a1734fe1ec4b	1225
vpcola	0:a1734fe1ec4b	1226	/*
vpcola	0:a1734fe1ec4b	1227	* \brief Function initialises and registers the RF driver.
vpcola	0:a1734fe1ec4b	1228	*
vpcola	0:a1734fe1ec4b	1229	* \param none
vpcola	0:a1734fe1ec4b	1230	*
vpcola	0:a1734fe1ec4b	1231	* \return rf_radio_driver_id Driver ID given by NET library
vpcola	0:a1734fe1ec4b	1232	*/
vpcola	0:a1734fe1ec4b	1233	static int8_t rf_device_register(const uint8_t *mac_addr)
vpcola	0:a1734fe1ec4b	1234	{
vpcola	0:a1734fe1ec4b	1235	rf_trx_part_e radio_type;
vpcola	0:a1734fe1ec4b	1236
vpcola	0:a1734fe1ec4b	1237	rf_init();
vpcola	0:a1734fe1ec4b	1238
vpcola	0:a1734fe1ec4b	1239	radio_type = rf_radio_type_read();
vpcola	0:a1734fe1ec4b	1240	if(radio_type != ATMEL_UNKNOW_DEV)
vpcola	0:a1734fe1ec4b	1241	{
vpcola	0:a1734fe1ec4b	1242	/Set pointer to MAC address/
vpcola	0:a1734fe1ec4b	1243	device_driver.PHY_MAC = (uint8_t *)mac_addr;
vpcola	0:a1734fe1ec4b	1244	device_driver.driver_description = (char*)"ATMEL_MAC";
vpcola	0:a1734fe1ec4b	1245	//Create setup Used Radio chips
vpcola	0:a1734fe1ec4b	1246	if(radio_type == ATMEL_AT86RF212)
vpcola	0:a1734fe1ec4b	1247	{
vpcola	0:a1734fe1ec4b	1248	device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
vpcola	0:a1734fe1ec4b	1249	}
vpcola	0:a1734fe1ec4b	1250	else
vpcola	0:a1734fe1ec4b	1251	{
vpcola	0:a1734fe1ec4b	1252	device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
vpcola	0:a1734fe1ec4b	1253	}
vpcola	0:a1734fe1ec4b	1254	device_driver.phy_channel_pages = phy_channel_pages;
vpcola	0:a1734fe1ec4b	1255	/Maximum size of payload is 127/
vpcola	0:a1734fe1ec4b	1256	device_driver.phy_MTU = 127;
vpcola	0:a1734fe1ec4b	1257	/No header in PHY/
vpcola	0:a1734fe1ec4b	1258	device_driver.phy_header_length = 0;
vpcola	0:a1734fe1ec4b	1259	/No tail in PHY/
vpcola	0:a1734fe1ec4b	1260	device_driver.phy_tail_length = 0;
vpcola	0:a1734fe1ec4b	1261	/Set address write function/
vpcola	0:a1734fe1ec4b	1262	device_driver.address_write = &rf_address_write;
vpcola	0:a1734fe1ec4b	1263	/Set RF extension function/
vpcola	0:a1734fe1ec4b	1264	device_driver.extension = &rf_extension;
vpcola	0:a1734fe1ec4b	1265	/Set RF state control function/
vpcola	0:a1734fe1ec4b	1266	device_driver.state_control = &rf_interface_state_control;
vpcola	0:a1734fe1ec4b	1267	/Set transmit function/
vpcola	0:a1734fe1ec4b	1268	device_driver.tx = &rf_start_cca;
vpcola	0:a1734fe1ec4b	1269	/NULLIFY rx and tx_done callbacks/
vpcola	0:a1734fe1ec4b	1270	device_driver.phy_rx_cb = NULL;
vpcola	0:a1734fe1ec4b	1271	device_driver.phy_tx_done_cb = NULL;
vpcola	0:a1734fe1ec4b	1272	/Register device driver/
vpcola	0:a1734fe1ec4b	1273	rf_radio_driver_id = arm_net_phy_register(&device_driver);
vpcola	0:a1734fe1ec4b	1274	}
vpcola	0:a1734fe1ec4b	1275	return rf_radio_driver_id;
vpcola	0:a1734fe1ec4b	1276	}
vpcola	0:a1734fe1ec4b	1277
vpcola	0:a1734fe1ec4b	1278	/*
vpcola	0:a1734fe1ec4b	1279	* \brief Function unregisters the RF driver.
vpcola	0:a1734fe1ec4b	1280	*
vpcola	0:a1734fe1ec4b	1281	* \param none
vpcola	0:a1734fe1ec4b	1282	*
vpcola	0:a1734fe1ec4b	1283	* \return none
vpcola	0:a1734fe1ec4b	1284	*/
vpcola	0:a1734fe1ec4b	1285	static void rf_device_unregister()
vpcola	0:a1734fe1ec4b	1286	{
vpcola	0:a1734fe1ec4b	1287	if (rf_radio_driver_id >= 0) {
vpcola	0:a1734fe1ec4b	1288	arm_net_phy_unregister(rf_radio_driver_id);
vpcola	0:a1734fe1ec4b	1289	rf_radio_driver_id = -1;
vpcola	0:a1734fe1ec4b	1290	}
vpcola	0:a1734fe1ec4b	1291	}
vpcola	0:a1734fe1ec4b	1292
vpcola	0:a1734fe1ec4b	1293	/*
vpcola	0:a1734fe1ec4b	1294	* \brief Enable frame buffer protection
vpcola	0:a1734fe1ec4b	1295	*
vpcola	0:a1734fe1ec4b	1296	* If protection is enabled, reception cannot start - the radio will
vpcola	0:a1734fe1ec4b	1297	* not go into RX_BUSY or write into the frame buffer if in receive mode.
vpcola	0:a1734fe1ec4b	1298	* Setting this won't abort an already-started reception.
vpcola	0:a1734fe1ec4b	1299	* We can still write the frame buffer ourselves.
vpcola	0:a1734fe1ec4b	1300	*/
vpcola	0:a1734fe1ec4b	1301	static void rf_enable_static_frame_buffer_protection(void)
vpcola	0:a1734fe1ec4b	1302	{
vpcola	0:a1734fe1ec4b	1303	if (!rf_flags_check(RFF_PROT)) {
vpcola	0:a1734fe1ec4b	1304	/* This also writes RX_PDT_LEVEL to 0 - maximum RX sensitivity */
vpcola	0:a1734fe1ec4b	1305	/* Would need to modify this function if messing with that */
vpcola	0:a1734fe1ec4b	1306	rf_if_write_register(RX_SYN, RX_PDT_DIS);
vpcola	0:a1734fe1ec4b	1307	rf_flags_set(RFF_PROT);
vpcola	0:a1734fe1ec4b	1308	}
vpcola	0:a1734fe1ec4b	1309	}
vpcola	0:a1734fe1ec4b	1310
vpcola	0:a1734fe1ec4b	1311	/*
vpcola	0:a1734fe1ec4b	1312	* \brief Disable frame buffer protection
vpcola	0:a1734fe1ec4b	1313	*/
vpcola	0:a1734fe1ec4b	1314	static void rf_disable_static_frame_buffer_protection(void)
vpcola	0:a1734fe1ec4b	1315	{
vpcola	0:a1734fe1ec4b	1316	if (rf_flags_check(RFF_PROT)) {
vpcola	0:a1734fe1ec4b	1317	/* This also writes RX_PDT_LEVEL to 0 - maximum RX sensitivity */
vpcola	0:a1734fe1ec4b	1318	/* Would need to modify this function if messing with that */
vpcola	0:a1734fe1ec4b	1319	rf_if_write_register(RX_SYN, 0);
vpcola	0:a1734fe1ec4b	1320	rf_flags_clear(RFF_PROT);
vpcola	0:a1734fe1ec4b	1321	}
vpcola	0:a1734fe1ec4b	1322	}
vpcola	0:a1734fe1ec4b	1323
vpcola	0:a1734fe1ec4b	1324
vpcola	0:a1734fe1ec4b	1325	/*
vpcola	0:a1734fe1ec4b	1326	* \brief Function is a call back for ACK wait timeout.
vpcola	0:a1734fe1ec4b	1327	*
vpcola	0:a1734fe1ec4b	1328	* \param none
vpcola	0:a1734fe1ec4b	1329	*
vpcola	0:a1734fe1ec4b	1330	* \return none
vpcola	0:a1734fe1ec4b	1331	*/
vpcola	0:a1734fe1ec4b	1332	static void rf_ack_wait_timer_interrupt(void)
vpcola	0:a1734fe1ec4b	1333	{
vpcola	0:a1734fe1ec4b	1334	rf_if_lock();
vpcola	0:a1734fe1ec4b	1335	expected_ack_sequence = -1;
vpcola	0:a1734fe1ec4b	1336	/Force PLL state/
vpcola	0:a1734fe1ec4b	1337	rf_if_change_trx_state(FORCE_PLL_ON);
vpcola	0:a1734fe1ec4b	1338	rf_poll_trx_state_change(PLL_ON);
vpcola	0:a1734fe1ec4b	1339	/Start receiver in RX_AACK_ON state/
vpcola	0:a1734fe1ec4b	1340	rf_rx_mode = 0;
vpcola	0:a1734fe1ec4b	1341	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	1342	rf_receive();
vpcola	0:a1734fe1ec4b	1343	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1344	}
vpcola	0:a1734fe1ec4b	1345
vpcola	0:a1734fe1ec4b	1346	/*
vpcola	0:a1734fe1ec4b	1347	* \brief Function is a call back for calibration interval timer.
vpcola	0:a1734fe1ec4b	1348	*
vpcola	0:a1734fe1ec4b	1349	* \param none
vpcola	0:a1734fe1ec4b	1350	*
vpcola	0:a1734fe1ec4b	1351	* \return none
vpcola	0:a1734fe1ec4b	1352	*/
vpcola	0:a1734fe1ec4b	1353	static void rf_calibration_timer_interrupt(void)
vpcola	0:a1734fe1ec4b	1354	{
vpcola	0:a1734fe1ec4b	1355	/Calibrate RF/
vpcola	0:a1734fe1ec4b	1356	rf_calibration_cb();
vpcola	0:a1734fe1ec4b	1357	/Start new calibration timeout/
vpcola	0:a1734fe1ec4b	1358	rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
vpcola	0:a1734fe1ec4b	1359	}
vpcola	0:a1734fe1ec4b	1360
vpcola	0:a1734fe1ec4b	1361	/*
vpcola	0:a1734fe1ec4b	1362	* \brief Function is a call back for cca interval timer.
vpcola	0:a1734fe1ec4b	1363	*
vpcola	0:a1734fe1ec4b	1364	* \param none
vpcola	0:a1734fe1ec4b	1365	*
vpcola	0:a1734fe1ec4b	1366	* \return none
vpcola	0:a1734fe1ec4b	1367	*/
vpcola	0:a1734fe1ec4b	1368	static void rf_cca_timer_interrupt(void)
vpcola	0:a1734fe1ec4b	1369	{
vpcola	0:a1734fe1ec4b	1370	/Disable reception - locks against entering BUSY_RX and overwriting frame buffer/
vpcola	0:a1734fe1ec4b	1371	rf_enable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	1372
vpcola	0:a1734fe1ec4b	1373	if(rf_if_read_trx_state() == BUSY_RX_AACK)
vpcola	0:a1734fe1ec4b	1374	{
vpcola	0:a1734fe1ec4b	1375	/Reception already started - re-enable reception and say CCA fail/
vpcola	0:a1734fe1ec4b	1376	rf_disable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	1377	if(device_driver.phy_tx_done_cb){
vpcola	0:a1734fe1ec4b	1378	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
vpcola	0:a1734fe1ec4b	1379	}
vpcola	0:a1734fe1ec4b	1380	}
vpcola	0:a1734fe1ec4b	1381	else
vpcola	0:a1734fe1ec4b	1382	{
vpcola	0:a1734fe1ec4b	1383	/Load the frame buffer with frame to transmit /
vpcola	0:a1734fe1ec4b	1384	rf_if_write_frame_buffer(rf_tx_data, rf_tx_length);
vpcola	0:a1734fe1ec4b	1385	/Make sure we're in RX state to read channel (any way we could not be?)/
vpcola	0:a1734fe1ec4b	1386	rf_receive();
vpcola	0:a1734fe1ec4b	1387	rf_flags_set(RFF_CCA);
vpcola	0:a1734fe1ec4b	1388	/Start CCA process/
vpcola	0:a1734fe1ec4b	1389	rf_if_enable_cca_ed_done_interrupt();
vpcola	0:a1734fe1ec4b	1390	rf_if_start_cca_process();
vpcola	0:a1734fe1ec4b	1391	}
vpcola	0:a1734fe1ec4b	1392	}
vpcola	0:a1734fe1ec4b	1393
vpcola	0:a1734fe1ec4b	1394	/*
vpcola	0:a1734fe1ec4b	1395	* \brief Function starts the ACK wait timeout.
vpcola	0:a1734fe1ec4b	1396	*
vpcola	0:a1734fe1ec4b	1397	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	1398	*
vpcola	0:a1734fe1ec4b	1399	* \return none
vpcola	0:a1734fe1ec4b	1400	*/
vpcola	0:a1734fe1ec4b	1401	static void rf_ack_wait_timer_start(uint16_t slots)
vpcola	0:a1734fe1ec4b	1402	{
vpcola	0:a1734fe1ec4b	1403	rf_if_ack_wait_timer_start(slots);
vpcola	0:a1734fe1ec4b	1404	}
vpcola	0:a1734fe1ec4b	1405
vpcola	0:a1734fe1ec4b	1406	/*
vpcola	0:a1734fe1ec4b	1407	* \brief Function starts the calibration interval.
vpcola	0:a1734fe1ec4b	1408	*
vpcola	0:a1734fe1ec4b	1409	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	1410	*
vpcola	0:a1734fe1ec4b	1411	* \return none
vpcola	0:a1734fe1ec4b	1412	*/
vpcola	0:a1734fe1ec4b	1413	static void rf_calibration_timer_start(uint32_t slots)
vpcola	0:a1734fe1ec4b	1414	{
vpcola	0:a1734fe1ec4b	1415	rf_if_calibration_timer_start(slots);
vpcola	0:a1734fe1ec4b	1416	}
vpcola	0:a1734fe1ec4b	1417
vpcola	0:a1734fe1ec4b	1418	/*
vpcola	0:a1734fe1ec4b	1419	* \brief Function starts the CCA backoff.
vpcola	0:a1734fe1ec4b	1420	*
vpcola	0:a1734fe1ec4b	1421	* \param slots Given slots, resolution 50us
vpcola	0:a1734fe1ec4b	1422	*
vpcola	0:a1734fe1ec4b	1423	* \return none
vpcola	0:a1734fe1ec4b	1424	*/
vpcola	0:a1734fe1ec4b	1425	static void rf_cca_timer_start(uint32_t slots)
vpcola	0:a1734fe1ec4b	1426	{
vpcola	0:a1734fe1ec4b	1427	rf_if_cca_timer_start(slots);
vpcola	0:a1734fe1ec4b	1428	}
vpcola	0:a1734fe1ec4b	1429
vpcola	0:a1734fe1ec4b	1430	/*
vpcola	0:a1734fe1ec4b	1431	* \brief Function stops the CCA backoff.
vpcola	0:a1734fe1ec4b	1432	*
vpcola	0:a1734fe1ec4b	1433	* \return none
vpcola	0:a1734fe1ec4b	1434	*/
vpcola	0:a1734fe1ec4b	1435	static void rf_cca_timer_stop(void)
vpcola	0:a1734fe1ec4b	1436	{
vpcola	0:a1734fe1ec4b	1437	rf_if_cca_timer_stop();
vpcola	0:a1734fe1ec4b	1438	}
vpcola	0:a1734fe1ec4b	1439
vpcola	0:a1734fe1ec4b	1440	/*
vpcola	0:a1734fe1ec4b	1441	* \brief Function stops the ACK wait timeout.
vpcola	0:a1734fe1ec4b	1442	*
vpcola	0:a1734fe1ec4b	1443	* \param none
vpcola	0:a1734fe1ec4b	1444	*
vpcola	0:a1734fe1ec4b	1445	* \return none
vpcola	0:a1734fe1ec4b	1446	*/
vpcola	0:a1734fe1ec4b	1447	static void rf_ack_wait_timer_stop(void)
vpcola	0:a1734fe1ec4b	1448	{
vpcola	0:a1734fe1ec4b	1449	rf_if_ack_wait_timer_stop();
vpcola	0:a1734fe1ec4b	1450	}
vpcola	0:a1734fe1ec4b	1451
vpcola	0:a1734fe1ec4b	1452	/*
vpcola	0:a1734fe1ec4b	1453	* \brief Function writes various RF settings in startup.
vpcola	0:a1734fe1ec4b	1454	*
vpcola	0:a1734fe1ec4b	1455	* \param none
vpcola	0:a1734fe1ec4b	1456	*
vpcola	0:a1734fe1ec4b	1457	* \return none
vpcola	0:a1734fe1ec4b	1458	*/
vpcola	0:a1734fe1ec4b	1459	static void rf_write_settings(void)
vpcola	0:a1734fe1ec4b	1460	{
vpcola	0:a1734fe1ec4b	1461	rf_if_lock();
vpcola	0:a1734fe1ec4b	1462	rf_if_write_rf_settings();
vpcola	0:a1734fe1ec4b	1463	/Set output power/
vpcola	0:a1734fe1ec4b	1464	rf_if_write_set_tx_power_register(radio_tx_power);
vpcola	0:a1734fe1ec4b	1465	/Initialise Antenna Diversity/
vpcola	0:a1734fe1ec4b	1466	if(rf_use_antenna_diversity)
vpcola	0:a1734fe1ec4b	1467	rf_if_write_antenna_diversity_settings();
vpcola	0:a1734fe1ec4b	1468	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1469	}
vpcola	0:a1734fe1ec4b	1470
vpcola	0:a1734fe1ec4b	1471	/*
vpcola	0:a1734fe1ec4b	1472	* \brief Function writes 16-bit address in RF address filter.
vpcola	0:a1734fe1ec4b	1473	*
vpcola	0:a1734fe1ec4b	1474	* \param short_address Given short address
vpcola	0:a1734fe1ec4b	1475	*
vpcola	0:a1734fe1ec4b	1476	* \return none
vpcola	0:a1734fe1ec4b	1477	*/
vpcola	0:a1734fe1ec4b	1478	static void rf_set_short_adr(uint8_t * short_address)
vpcola	0:a1734fe1ec4b	1479	{
vpcola	0:a1734fe1ec4b	1480	rf_if_lock();
vpcola	0:a1734fe1ec4b	1481	/Wake up RF if sleeping/
vpcola	0:a1734fe1ec4b	1482	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1483	{
vpcola	0:a1734fe1ec4b	1484	rf_if_disable_slptr();
vpcola	0:a1734fe1ec4b	1485	rf_poll_trx_state_change(TRX_OFF);
vpcola	0:a1734fe1ec4b	1486	}
vpcola	0:a1734fe1ec4b	1487	/Write address filter registers/
vpcola	0:a1734fe1ec4b	1488	rf_if_write_short_addr_registers(short_address);
vpcola	0:a1734fe1ec4b	1489	/RF back to sleep/
vpcola	0:a1734fe1ec4b	1490	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1491	{
vpcola	0:a1734fe1ec4b	1492	rf_if_enable_slptr();
vpcola	0:a1734fe1ec4b	1493	}
vpcola	0:a1734fe1ec4b	1494	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1495	}
vpcola	0:a1734fe1ec4b	1496
vpcola	0:a1734fe1ec4b	1497	/*
vpcola	0:a1734fe1ec4b	1498	* \brief Function writes PAN Id in RF PAN Id filter.
vpcola	0:a1734fe1ec4b	1499	*
vpcola	0:a1734fe1ec4b	1500	* \param pan_id Given PAN Id
vpcola	0:a1734fe1ec4b	1501	*
vpcola	0:a1734fe1ec4b	1502	* \return none
vpcola	0:a1734fe1ec4b	1503	*/
vpcola	0:a1734fe1ec4b	1504	static void rf_set_pan_id(uint8_t *pan_id)
vpcola	0:a1734fe1ec4b	1505	{
vpcola	0:a1734fe1ec4b	1506	rf_if_lock();
vpcola	0:a1734fe1ec4b	1507	/Wake up RF if sleeping/
vpcola	0:a1734fe1ec4b	1508	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1509	{
vpcola	0:a1734fe1ec4b	1510	rf_if_disable_slptr();
vpcola	0:a1734fe1ec4b	1511	rf_poll_trx_state_change(TRX_OFF);
vpcola	0:a1734fe1ec4b	1512	}
vpcola	0:a1734fe1ec4b	1513	/Write address filter registers/
vpcola	0:a1734fe1ec4b	1514	rf_if_write_pan_id_registers(pan_id);
vpcola	0:a1734fe1ec4b	1515	/RF back to sleep/
vpcola	0:a1734fe1ec4b	1516	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1517	{
vpcola	0:a1734fe1ec4b	1518	rf_if_enable_slptr();
vpcola	0:a1734fe1ec4b	1519	}
vpcola	0:a1734fe1ec4b	1520	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1521	}
vpcola	0:a1734fe1ec4b	1522
vpcola	0:a1734fe1ec4b	1523	/*
vpcola	0:a1734fe1ec4b	1524	* \brief Function writes 64-bit address in RF address filter.
vpcola	0:a1734fe1ec4b	1525	*
vpcola	0:a1734fe1ec4b	1526	* \param address Given 64-bit address
vpcola	0:a1734fe1ec4b	1527	*
vpcola	0:a1734fe1ec4b	1528	* \return none
vpcola	0:a1734fe1ec4b	1529	*/
vpcola	0:a1734fe1ec4b	1530	static void rf_set_address(uint8_t *address)
vpcola	0:a1734fe1ec4b	1531	{
vpcola	0:a1734fe1ec4b	1532	rf_if_lock();
vpcola	0:a1734fe1ec4b	1533	/Wake up RF if sleeping/
vpcola	0:a1734fe1ec4b	1534	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1535	{
vpcola	0:a1734fe1ec4b	1536	rf_if_disable_slptr();
vpcola	0:a1734fe1ec4b	1537	rf_poll_trx_state_change(TRX_OFF);
vpcola	0:a1734fe1ec4b	1538	}
vpcola	0:a1734fe1ec4b	1539	/Write address filter registers/
vpcola	0:a1734fe1ec4b	1540	rf_if_write_ieee_addr_registers(address);
vpcola	0:a1734fe1ec4b	1541	/RF back to sleep/
vpcola	0:a1734fe1ec4b	1542	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1543	{
vpcola	0:a1734fe1ec4b	1544	rf_if_enable_slptr();
vpcola	0:a1734fe1ec4b	1545	}
vpcola	0:a1734fe1ec4b	1546	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1547	}
vpcola	0:a1734fe1ec4b	1548
vpcola	0:a1734fe1ec4b	1549	/*
vpcola	0:a1734fe1ec4b	1550	* \brief Function sets the RF channel.
vpcola	0:a1734fe1ec4b	1551	*
vpcola	0:a1734fe1ec4b	1552	* \param ch New channel
vpcola	0:a1734fe1ec4b	1553	*
vpcola	0:a1734fe1ec4b	1554	* \return none
vpcola	0:a1734fe1ec4b	1555	*/
vpcola	0:a1734fe1ec4b	1556	static void rf_channel_set(uint8_t ch)
vpcola	0:a1734fe1ec4b	1557	{
vpcola	0:a1734fe1ec4b	1558	rf_if_lock();
vpcola	0:a1734fe1ec4b	1559	rf_phy_channel = ch;
vpcola	0:a1734fe1ec4b	1560	if(ch < 0x1f)
vpcola	0:a1734fe1ec4b	1561	rf_if_set_channel_register(ch);
vpcola	0:a1734fe1ec4b	1562	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1563	}
vpcola	0:a1734fe1ec4b	1564
vpcola	0:a1734fe1ec4b	1565
vpcola	0:a1734fe1ec4b	1566	/*
vpcola	0:a1734fe1ec4b	1567	* \brief Function initialises the radio driver and resets the radio.
vpcola	0:a1734fe1ec4b	1568	*
vpcola	0:a1734fe1ec4b	1569	* \param none
vpcola	0:a1734fe1ec4b	1570	*
vpcola	0:a1734fe1ec4b	1571	* \return none
vpcola	0:a1734fe1ec4b	1572	*/
vpcola	0:a1734fe1ec4b	1573	static void rf_init(void)
vpcola	0:a1734fe1ec4b	1574	{
vpcola	0:a1734fe1ec4b	1575	/Reset RF module/
vpcola	0:a1734fe1ec4b	1576	rf_if_reset_radio();
vpcola	0:a1734fe1ec4b	1577
vpcola	0:a1734fe1ec4b	1578	rf_if_lock();
vpcola	0:a1734fe1ec4b	1579
vpcola	0:a1734fe1ec4b	1580	/Write RF settings/
vpcola	0:a1734fe1ec4b	1581	rf_write_settings();
vpcola	0:a1734fe1ec4b	1582	/Initialise PHY mode/
vpcola	0:a1734fe1ec4b	1583	rf_init_phy_mode();
vpcola	0:a1734fe1ec4b	1584	/Clear RF flags/
vpcola	0:a1734fe1ec4b	1585	rf_flags_reset();
vpcola	0:a1734fe1ec4b	1586	/Set RF in TRX OFF state/
vpcola	0:a1734fe1ec4b	1587	rf_if_change_trx_state(TRX_OFF);
vpcola	0:a1734fe1ec4b	1588	/Set RF in PLL_ON state/
vpcola	0:a1734fe1ec4b	1589	rf_if_change_trx_state(PLL_ON);
vpcola	0:a1734fe1ec4b	1590	/Start receiver/
vpcola	0:a1734fe1ec4b	1591	rf_receive();
vpcola	0:a1734fe1ec4b	1592	/Read randomness, and add to seed/
vpcola	0:a1734fe1ec4b	1593	randLIB_add_seed(rf_if_read_rnd());
vpcola	0:a1734fe1ec4b	1594	/Start RF calibration timer/
vpcola	0:a1734fe1ec4b	1595	rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
vpcola	0:a1734fe1ec4b	1596
vpcola	0:a1734fe1ec4b	1597	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1598	}
vpcola	0:a1734fe1ec4b	1599
vpcola	0:a1734fe1ec4b	1600	/**
vpcola	0:a1734fe1ec4b	1601	* \brief Function gets called when MAC is setting radio off.
vpcola	0:a1734fe1ec4b	1602	*
vpcola	0:a1734fe1ec4b	1603	* \param none
vpcola	0:a1734fe1ec4b	1604	*
vpcola	0:a1734fe1ec4b	1605	* \return none
vpcola	0:a1734fe1ec4b	1606	*/
vpcola	0:a1734fe1ec4b	1607	static void rf_off(void)
vpcola	0:a1734fe1ec4b	1608	{
vpcola	0:a1734fe1ec4b	1609	if(rf_flags_check(RFF_ON))
vpcola	0:a1734fe1ec4b	1610	{
vpcola	0:a1734fe1ec4b	1611	rf_if_lock();
vpcola	0:a1734fe1ec4b	1612	rf_cca_abort();
vpcola	0:a1734fe1ec4b	1613	uint16_t while_counter = 0;
vpcola	0:a1734fe1ec4b	1614	/Wait while receiving/
vpcola	0:a1734fe1ec4b	1615	while(rf_if_read_trx_state() == BUSY_RX_AACK)
vpcola	0:a1734fe1ec4b	1616	{
vpcola	0:a1734fe1ec4b	1617	while_counter++;
vpcola	0:a1734fe1ec4b	1618	if(while_counter == 0xffff)
vpcola	0:a1734fe1ec4b	1619	break;
vpcola	0:a1734fe1ec4b	1620	}
vpcola	0:a1734fe1ec4b	1621	/RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP/
vpcola	0:a1734fe1ec4b	1622	if(rf_if_read_trx_state() == RX_AACK_ON)
vpcola	0:a1734fe1ec4b	1623	{
vpcola	0:a1734fe1ec4b	1624	rf_if_change_trx_state(PLL_ON);
vpcola	0:a1734fe1ec4b	1625	}
vpcola	0:a1734fe1ec4b	1626	rf_if_change_trx_state(TRX_OFF);
vpcola	0:a1734fe1ec4b	1627	rf_if_enable_slptr();
vpcola	0:a1734fe1ec4b	1628
vpcola	0:a1734fe1ec4b	1629	/Disable Antenna Diversity/
vpcola	0:a1734fe1ec4b	1630	if(rf_use_antenna_diversity)
vpcola	0:a1734fe1ec4b	1631	rf_if_disable_ant_div();
vpcola	0:a1734fe1ec4b	1632	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1633	}
vpcola	0:a1734fe1ec4b	1634
vpcola	0:a1734fe1ec4b	1635	/Clears all flags/
vpcola	0:a1734fe1ec4b	1636	rf_flags_reset();
vpcola	0:a1734fe1ec4b	1637	}
vpcola	0:a1734fe1ec4b	1638
vpcola	0:a1734fe1ec4b	1639	/*
vpcola	0:a1734fe1ec4b	1640	* \brief Function polls the RF state until it has changed to desired state.
vpcola	0:a1734fe1ec4b	1641	*
vpcola	0:a1734fe1ec4b	1642	* \param trx_state RF state
vpcola	0:a1734fe1ec4b	1643	*
vpcola	0:a1734fe1ec4b	1644	* \return none
vpcola	0:a1734fe1ec4b	1645	*/
vpcola	0:a1734fe1ec4b	1646	static void rf_poll_trx_state_change(rf_trx_states_t trx_state)
vpcola	0:a1734fe1ec4b	1647	{
vpcola	0:a1734fe1ec4b	1648	uint16_t while_counter = 0;
vpcola	0:a1734fe1ec4b	1649	// XXX lock apparently not needed
vpcola	0:a1734fe1ec4b	1650	rf_if_lock();
vpcola	0:a1734fe1ec4b	1651
vpcola	0:a1734fe1ec4b	1652	if(trx_state != RF_TX_START)
vpcola	0:a1734fe1ec4b	1653	{
vpcola	0:a1734fe1ec4b	1654	if(trx_state == FORCE_PLL_ON)
vpcola	0:a1734fe1ec4b	1655	trx_state = PLL_ON;
vpcola	0:a1734fe1ec4b	1656	else if(trx_state == FORCE_TRX_OFF)
vpcola	0:a1734fe1ec4b	1657	trx_state = TRX_OFF;
vpcola	0:a1734fe1ec4b	1658
vpcola	0:a1734fe1ec4b	1659	while(rf_if_read_trx_state() != trx_state)
vpcola	0:a1734fe1ec4b	1660	{
vpcola	0:a1734fe1ec4b	1661	while_counter++;
vpcola	0:a1734fe1ec4b	1662	if(while_counter == 0x1ff)
vpcola	0:a1734fe1ec4b	1663	break;
vpcola	0:a1734fe1ec4b	1664	}
vpcola	0:a1734fe1ec4b	1665	}
vpcola	0:a1734fe1ec4b	1666	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1667	}
vpcola	0:a1734fe1ec4b	1668
vpcola	0:a1734fe1ec4b	1669	/*
vpcola	0:a1734fe1ec4b	1670	* \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
vpcola	0:a1734fe1ec4b	1671	*
vpcola	0:a1734fe1ec4b	1672	* \param data_ptr Pointer to TX data (excluding FCS)
vpcola	0:a1734fe1ec4b	1673	* \param data_length Length of the TX data (excluding FCS)
vpcola	0:a1734fe1ec4b	1674	* \param tx_handle Handle to transmission
vpcola	0:a1734fe1ec4b	1675	* \return 0 Success
vpcola	0:a1734fe1ec4b	1676	* \return -1 Busy
vpcola	0:a1734fe1ec4b	1677	*/
vpcola	0:a1734fe1ec4b	1678	static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
vpcola	0:a1734fe1ec4b	1679	{
vpcola	0:a1734fe1ec4b	1680	(void)data_protocol;
vpcola	0:a1734fe1ec4b	1681	rf_if_lock();
vpcola	0:a1734fe1ec4b	1682	/Check if transmitter is busy/
vpcola	0:a1734fe1ec4b	1683	if(rf_if_read_trx_state() == BUSY_RX_AACK \|\| data_length > RF_MTU - 2)
vpcola	0:a1734fe1ec4b	1684	{
vpcola	0:a1734fe1ec4b	1685	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1686	/Return busy/
vpcola	0:a1734fe1ec4b	1687	return -1;
vpcola	0:a1734fe1ec4b	1688	}
vpcola	0:a1734fe1ec4b	1689	else
vpcola	0:a1734fe1ec4b	1690	{
vpcola	0:a1734fe1ec4b	1691	expected_ack_sequence = -1;
vpcola	0:a1734fe1ec4b	1692
vpcola	0:a1734fe1ec4b	1693	/Nanostack has a static TX buffer, which will remain valid until we/
vpcola	0:a1734fe1ec4b	1694	/generate a callback, so we just note the pointer for reading later./
vpcola	0:a1734fe1ec4b	1695	rf_tx_data = data_ptr;
vpcola	0:a1734fe1ec4b	1696	rf_tx_length = data_length;
vpcola	0:a1734fe1ec4b	1697	/Start CCA timeout/
vpcola	0:a1734fe1ec4b	1698	rf_cca_timer_start(RF_CCA_BASE_BACKOFF + randLIB_get_random_in_range(0, RF_CCA_RANDOM_BACKOFF));
vpcola	0:a1734fe1ec4b	1699	/Store TX handle/
vpcola	0:a1734fe1ec4b	1700	mac_tx_handle = tx_handle;
vpcola	0:a1734fe1ec4b	1701	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1702	}
vpcola	0:a1734fe1ec4b	1703
vpcola	0:a1734fe1ec4b	1704	/Return success/
vpcola	0:a1734fe1ec4b	1705	return 0;
vpcola	0:a1734fe1ec4b	1706	}
vpcola	0:a1734fe1ec4b	1707
vpcola	0:a1734fe1ec4b	1708	/*
vpcola	0:a1734fe1ec4b	1709	* \brief Function aborts CCA process.
vpcola	0:a1734fe1ec4b	1710	*
vpcola	0:a1734fe1ec4b	1711	* \param none
vpcola	0:a1734fe1ec4b	1712	*
vpcola	0:a1734fe1ec4b	1713	* \return none
vpcola	0:a1734fe1ec4b	1714	*/
vpcola	0:a1734fe1ec4b	1715	static void rf_cca_abort(void)
vpcola	0:a1734fe1ec4b	1716	{
vpcola	0:a1734fe1ec4b	1717	rf_cca_timer_stop();
vpcola	0:a1734fe1ec4b	1718	rf_flags_clear(RFF_CCA);
vpcola	0:a1734fe1ec4b	1719	rf_disable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	1720	}
vpcola	0:a1734fe1ec4b	1721
vpcola	0:a1734fe1ec4b	1722	/*
vpcola	0:a1734fe1ec4b	1723	* \brief Function starts the transmission of the frame.
vpcola	0:a1734fe1ec4b	1724	*
vpcola	0:a1734fe1ec4b	1725	* \param none
vpcola	0:a1734fe1ec4b	1726	*
vpcola	0:a1734fe1ec4b	1727	* \return none
vpcola	0:a1734fe1ec4b	1728	*/
vpcola	0:a1734fe1ec4b	1729	static void rf_start_tx(void)
vpcola	0:a1734fe1ec4b	1730	{
vpcola	0:a1734fe1ec4b	1731	/Only start transmitting from RX state/
vpcola	0:a1734fe1ec4b	1732	uint8_t trx_state = rf_if_read_trx_state();
vpcola	0:a1734fe1ec4b	1733	if(trx_state != RX_AACK_ON)
vpcola	0:a1734fe1ec4b	1734	{
vpcola	0:a1734fe1ec4b	1735	rf_disable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	1736	if(device_driver.phy_tx_done_cb){
vpcola	0:a1734fe1ec4b	1737	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
vpcola	0:a1734fe1ec4b	1738	}
vpcola	0:a1734fe1ec4b	1739	}
vpcola	0:a1734fe1ec4b	1740	else
vpcola	0:a1734fe1ec4b	1741	{
vpcola	0:a1734fe1ec4b	1742	/RF state change: ->PLL_ON->RF_TX_START/
vpcola	0:a1734fe1ec4b	1743	rf_if_change_trx_state(FORCE_PLL_ON);
vpcola	0:a1734fe1ec4b	1744	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	1745	/Now we're out of receive mode, can release protection/
vpcola	0:a1734fe1ec4b	1746	rf_disable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	1747	rf_if_enable_tx_end_interrupt();
vpcola	0:a1734fe1ec4b	1748	rf_flags_set(RFF_TX);
vpcola	0:a1734fe1ec4b	1749	rf_if_change_trx_state(RF_TX_START);
vpcola	0:a1734fe1ec4b	1750	}
vpcola	0:a1734fe1ec4b	1751	}
vpcola	0:a1734fe1ec4b	1752
vpcola	0:a1734fe1ec4b	1753	/*
vpcola	0:a1734fe1ec4b	1754	* \brief Function sets the RF in RX state.
vpcola	0:a1734fe1ec4b	1755	*
vpcola	0:a1734fe1ec4b	1756	* \param none
vpcola	0:a1734fe1ec4b	1757	*
vpcola	0:a1734fe1ec4b	1758	* \return none
vpcola	0:a1734fe1ec4b	1759	*/
vpcola	0:a1734fe1ec4b	1760	static void rf_receive(void)
vpcola	0:a1734fe1ec4b	1761	{
vpcola	0:a1734fe1ec4b	1762	uint16_t while_counter = 0;
vpcola	0:a1734fe1ec4b	1763	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1764	{
vpcola	0:a1734fe1ec4b	1765	rf_on();
vpcola	0:a1734fe1ec4b	1766	}
vpcola	0:a1734fe1ec4b	1767	/If not yet in RX state set it/
vpcola	0:a1734fe1ec4b	1768	if(rf_flags_check(RFF_RX) == 0)
vpcola	0:a1734fe1ec4b	1769	{
vpcola	0:a1734fe1ec4b	1770	rf_if_lock();
vpcola	0:a1734fe1ec4b	1771	/Wait while receiving data/
vpcola	0:a1734fe1ec4b	1772	while(rf_if_read_trx_state() == BUSY_RX_AACK)
vpcola	0:a1734fe1ec4b	1773	{
vpcola	0:a1734fe1ec4b	1774	while_counter++;
vpcola	0:a1734fe1ec4b	1775	if(while_counter == 0xffff)
vpcola	0:a1734fe1ec4b	1776	{
vpcola	0:a1734fe1ec4b	1777	break;
vpcola	0:a1734fe1ec4b	1778	}
vpcola	0:a1734fe1ec4b	1779	}
vpcola	0:a1734fe1ec4b	1780
vpcola	0:a1734fe1ec4b	1781	rf_if_change_trx_state(PLL_ON);
vpcola	0:a1734fe1ec4b	1782
vpcola	0:a1734fe1ec4b	1783	if((rf_mode == RF_MODE_SNIFFER) \|\| (rf_mode == RF_MODE_ED))
vpcola	0:a1734fe1ec4b	1784	{
vpcola	0:a1734fe1ec4b	1785	rf_if_change_trx_state(RX_ON);
vpcola	0:a1734fe1ec4b	1786	}
vpcola	0:a1734fe1ec4b	1787	else
vpcola	0:a1734fe1ec4b	1788	{
vpcola	0:a1734fe1ec4b	1789	/ACK is always received in promiscuous mode to bypass address filters/
vpcola	0:a1734fe1ec4b	1790	if(rf_rx_mode)
vpcola	0:a1734fe1ec4b	1791	{
vpcola	0:a1734fe1ec4b	1792	rf_rx_mode = 0;
vpcola	0:a1734fe1ec4b	1793	rf_if_enable_promiscuous_mode();
vpcola	0:a1734fe1ec4b	1794	}
vpcola	0:a1734fe1ec4b	1795	else
vpcola	0:a1734fe1ec4b	1796	{
vpcola	0:a1734fe1ec4b	1797	rf_if_disable_promiscuous_mode();
vpcola	0:a1734fe1ec4b	1798	}
vpcola	0:a1734fe1ec4b	1799	rf_if_change_trx_state(RX_AACK_ON);
vpcola	0:a1734fe1ec4b	1800	}
vpcola	0:a1734fe1ec4b	1801	/If calibration timer was unable to calibrate the RF, run calibration now/
vpcola	0:a1734fe1ec4b	1802	if(!rf_tuned)
vpcola	0:a1734fe1ec4b	1803	{
vpcola	0:a1734fe1ec4b	1804	/Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state/
vpcola	0:a1734fe1ec4b	1805	rf_if_calibration();
vpcola	0:a1734fe1ec4b	1806	/RF is tuned now/
vpcola	0:a1734fe1ec4b	1807	rf_tuned = 1;
vpcola	0:a1734fe1ec4b	1808	}
vpcola	0:a1734fe1ec4b	1809
vpcola	0:a1734fe1ec4b	1810	rf_channel_set(rf_phy_channel);
vpcola	0:a1734fe1ec4b	1811	rf_flags_set(RFF_RX);
vpcola	0:a1734fe1ec4b	1812	// Don't receive packets when ED mode enabled
vpcola	0:a1734fe1ec4b	1813	if (rf_mode != RF_MODE_ED)
vpcola	0:a1734fe1ec4b	1814	{
vpcola	0:a1734fe1ec4b	1815	rf_if_enable_rx_end_interrupt();
vpcola	0:a1734fe1ec4b	1816	}
vpcola	0:a1734fe1ec4b	1817	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1818	}
vpcola	0:a1734fe1ec4b	1819	}
vpcola	0:a1734fe1ec4b	1820
vpcola	0:a1734fe1ec4b	1821	/*
vpcola	0:a1734fe1ec4b	1822	* \brief Function calibrates the radio.
vpcola	0:a1734fe1ec4b	1823	*
vpcola	0:a1734fe1ec4b	1824	* \param none
vpcola	0:a1734fe1ec4b	1825	*
vpcola	0:a1734fe1ec4b	1826	* \return none
vpcola	0:a1734fe1ec4b	1827	*/
vpcola	0:a1734fe1ec4b	1828	static void rf_calibration_cb(void)
vpcola	0:a1734fe1ec4b	1829	{
vpcola	0:a1734fe1ec4b	1830	/clear tuned flag to start tuning in rf_receive/
vpcola	0:a1734fe1ec4b	1831	rf_tuned = 0;
vpcola	0:a1734fe1ec4b	1832	/If RF is in default receive state, start calibration/
vpcola	0:a1734fe1ec4b	1833	if(rf_if_read_trx_state() == RX_AACK_ON)
vpcola	0:a1734fe1ec4b	1834	{
vpcola	0:a1734fe1ec4b	1835	rf_if_lock();
vpcola	0:a1734fe1ec4b	1836	/Set RF in PLL_ON state/
vpcola	0:a1734fe1ec4b	1837	rf_if_change_trx_state(PLL_ON);
vpcola	0:a1734fe1ec4b	1838	/Set RF in TRX_OFF state to start PLL tuning/
vpcola	0:a1734fe1ec4b	1839	rf_if_change_trx_state(TRX_OFF);
vpcola	0:a1734fe1ec4b	1840	/Set RF in RX_ON state to calibrate/
vpcola	0:a1734fe1ec4b	1841	rf_if_change_trx_state(RX_ON);
vpcola	0:a1734fe1ec4b	1842	/Calibrate FTN/
vpcola	0:a1734fe1ec4b	1843	rf_if_calibration();
vpcola	0:a1734fe1ec4b	1844	/RF is tuned now/
vpcola	0:a1734fe1ec4b	1845	rf_tuned = 1;
vpcola	0:a1734fe1ec4b	1846	/Back to default receive state/
vpcola	0:a1734fe1ec4b	1847	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	1848	rf_receive();
vpcola	0:a1734fe1ec4b	1849	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1850	}
vpcola	0:a1734fe1ec4b	1851	}
vpcola	0:a1734fe1ec4b	1852
vpcola	0:a1734fe1ec4b	1853	/*
vpcola	0:a1734fe1ec4b	1854	* \brief Function sets RF_ON flag when radio is powered.
vpcola	0:a1734fe1ec4b	1855	*
vpcola	0:a1734fe1ec4b	1856	* \param none
vpcola	0:a1734fe1ec4b	1857	*
vpcola	0:a1734fe1ec4b	1858	* \return none
vpcola	0:a1734fe1ec4b	1859	*/
vpcola	0:a1734fe1ec4b	1860	static void rf_on(void)
vpcola	0:a1734fe1ec4b	1861	{
vpcola	0:a1734fe1ec4b	1862	/Set RFF_ON flag/
vpcola	0:a1734fe1ec4b	1863	if(rf_flags_check(RFF_ON) == 0)
vpcola	0:a1734fe1ec4b	1864	{
vpcola	0:a1734fe1ec4b	1865	rf_if_lock();
vpcola	0:a1734fe1ec4b	1866	rf_flags_set(RFF_ON);
vpcola	0:a1734fe1ec4b	1867	/Enable Antenna diversity/
vpcola	0:a1734fe1ec4b	1868	if(rf_use_antenna_diversity)
vpcola	0:a1734fe1ec4b	1869	/Set ANT_EXT_SW_EN to enable controlling of antenna diversity/
vpcola	0:a1734fe1ec4b	1870	rf_if_enable_ant_div();
vpcola	0:a1734fe1ec4b	1871
vpcola	0:a1734fe1ec4b	1872	/Wake up from sleep state/
vpcola	0:a1734fe1ec4b	1873	rf_if_disable_slptr();
vpcola	0:a1734fe1ec4b	1874	rf_poll_trx_state_change(TRX_OFF);
vpcola	0:a1734fe1ec4b	1875	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1876	}
vpcola	0:a1734fe1ec4b	1877	}
vpcola	0:a1734fe1ec4b	1878
vpcola	0:a1734fe1ec4b	1879	/*
vpcola	0:a1734fe1ec4b	1880	* \brief Function handles the received ACK frame.
vpcola	0:a1734fe1ec4b	1881	*
vpcola	0:a1734fe1ec4b	1882	* \param seq_number Sequence number of received ACK
vpcola	0:a1734fe1ec4b	1883	* \param data_pending Pending bit state in received ACK
vpcola	0:a1734fe1ec4b	1884	*
vpcola	0:a1734fe1ec4b	1885	* \return none
vpcola	0:a1734fe1ec4b	1886	*/
vpcola	0:a1734fe1ec4b	1887	static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
vpcola	0:a1734fe1ec4b	1888	{
vpcola	0:a1734fe1ec4b	1889	phy_link_tx_status_e phy_status;
vpcola	0:a1734fe1ec4b	1890	rf_if_lock();
vpcola	0:a1734fe1ec4b	1891	/Received ACK sequence must be equal with transmitted packet sequence/
vpcola	0:a1734fe1ec4b	1892	if(expected_ack_sequence == seq_number)
vpcola	0:a1734fe1ec4b	1893	{
vpcola	0:a1734fe1ec4b	1894	rf_ack_wait_timer_stop();
vpcola	0:a1734fe1ec4b	1895	expected_ack_sequence = -1;
vpcola	0:a1734fe1ec4b	1896	/When data pending bit in ACK frame is set, inform NET library/
vpcola	0:a1734fe1ec4b	1897	if(data_pending)
vpcola	0:a1734fe1ec4b	1898	phy_status = PHY_LINK_TX_DONE_PENDING;
vpcola	0:a1734fe1ec4b	1899	else
vpcola	0:a1734fe1ec4b	1900	phy_status = PHY_LINK_TX_DONE;
vpcola	0:a1734fe1ec4b	1901	/Call PHY TX Done API/
vpcola	0:a1734fe1ec4b	1902	if(device_driver.phy_tx_done_cb){
vpcola	0:a1734fe1ec4b	1903	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle,phy_status, 0, 0);
vpcola	0:a1734fe1ec4b	1904	}
vpcola	0:a1734fe1ec4b	1905	}
vpcola	0:a1734fe1ec4b	1906	rf_if_unlock();
vpcola	0:a1734fe1ec4b	1907	}
vpcola	0:a1734fe1ec4b	1908
vpcola	0:a1734fe1ec4b	1909	/*
vpcola	0:a1734fe1ec4b	1910	* \brief Function is a call back for RX end interrupt.
vpcola	0:a1734fe1ec4b	1911	*
vpcola	0:a1734fe1ec4b	1912	* \param none
vpcola	0:a1734fe1ec4b	1913	*
vpcola	0:a1734fe1ec4b	1914	* \return none
vpcola	0:a1734fe1ec4b	1915	*/
vpcola	0:a1734fe1ec4b	1916	static void rf_handle_rx_end(void)
vpcola	0:a1734fe1ec4b	1917	{
vpcola	0:a1734fe1ec4b	1918	/Start receiver/
vpcola	0:a1734fe1ec4b	1919	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	1920	rf_receive();
vpcola	0:a1734fe1ec4b	1921
vpcola	0:a1734fe1ec4b	1922	/Frame received interrupt/
vpcola	0:a1734fe1ec4b	1923	if(!rf_flags_check(RFF_RX)) {
vpcola	0:a1734fe1ec4b	1924	return;
vpcola	0:a1734fe1ec4b	1925	}
vpcola	0:a1734fe1ec4b	1926
vpcola	0:a1734fe1ec4b	1927	static uint8_t rf_buffer[RF_MTU];
vpcola	0:a1734fe1ec4b	1928	uint8_t rf_lqi, rf_ed;
vpcola	0:a1734fe1ec4b	1929	int8_t rf_rssi;
vpcola	0:a1734fe1ec4b	1930	bool crc_good;
vpcola	0:a1734fe1ec4b	1931
vpcola	0:a1734fe1ec4b	1932	/Read received packet/
vpcola	0:a1734fe1ec4b	1933	uint8_t len = rf_if_read_packet(rf_buffer, &rf_lqi, &rf_ed, &crc_good);
vpcola	0:a1734fe1ec4b	1934	if (len < 5 \|\| !crc_good) {
vpcola	0:a1734fe1ec4b	1935	return;
vpcola	0:a1734fe1ec4b	1936	}
vpcola	0:a1734fe1ec4b	1937
vpcola	0:a1734fe1ec4b	1938	/* Convert raw ED to dBm value (chip-dependent) */
vpcola	0:a1734fe1ec4b	1939	rf_rssi = rf_if_scale_rssi(rf_ed);
vpcola	0:a1734fe1ec4b	1940
vpcola	0:a1734fe1ec4b	1941	/* Create a virtual LQI using received RSSI, forgetting actual HW LQI */
vpcola	0:a1734fe1ec4b	1942	/* (should be done through PHY_EXTENSION_CONVERT_SIGNAL_INFO) */
vpcola	0:a1734fe1ec4b	1943	rf_lqi = rf_scale_lqi(rf_rssi);
vpcola	0:a1734fe1ec4b	1944
vpcola	0:a1734fe1ec4b	1945	/Handle received ACK/
vpcola	0:a1734fe1ec4b	1946	if((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER)
vpcola	0:a1734fe1ec4b	1947	{
vpcola	0:a1734fe1ec4b	1948	/Check if data is pending/
vpcola	0:a1734fe1ec4b	1949	bool pending = (rf_buffer[0] & 0x10);
vpcola	0:a1734fe1ec4b	1950
vpcola	0:a1734fe1ec4b	1951	/Send sequence number in ACK handler/
vpcola	0:a1734fe1ec4b	1952	rf_handle_ack(rf_buffer[2], pending);
vpcola	0:a1734fe1ec4b	1953	} else {
vpcola	0:a1734fe1ec4b	1954	if( device_driver.phy_rx_cb ){
vpcola	0:a1734fe1ec4b	1955	device_driver.phy_rx_cb(rf_buffer, len - 2, rf_lqi, rf_rssi, rf_radio_driver_id);
vpcola	0:a1734fe1ec4b	1956	}
vpcola	0:a1734fe1ec4b	1957	}
vpcola	0:a1734fe1ec4b	1958	}
vpcola	0:a1734fe1ec4b	1959
vpcola	0:a1734fe1ec4b	1960	/*
vpcola	0:a1734fe1ec4b	1961	* \brief Function is called when MAC is shutting down the radio.
vpcola	0:a1734fe1ec4b	1962	*
vpcola	0:a1734fe1ec4b	1963	* \param none
vpcola	0:a1734fe1ec4b	1964	*
vpcola	0:a1734fe1ec4b	1965	* \return none
vpcola	0:a1734fe1ec4b	1966	*/
vpcola	0:a1734fe1ec4b	1967	static void rf_shutdown(void)
vpcola	0:a1734fe1ec4b	1968	{
vpcola	0:a1734fe1ec4b	1969	/Call RF OFF/
vpcola	0:a1734fe1ec4b	1970	rf_off();
vpcola	0:a1734fe1ec4b	1971	}
vpcola	0:a1734fe1ec4b	1972
vpcola	0:a1734fe1ec4b	1973	/*
vpcola	0:a1734fe1ec4b	1974	* \brief Function is a call back for TX end interrupt.
vpcola	0:a1734fe1ec4b	1975	*
vpcola	0:a1734fe1ec4b	1976	* \param none
vpcola	0:a1734fe1ec4b	1977	*
vpcola	0:a1734fe1ec4b	1978	* \return none
vpcola	0:a1734fe1ec4b	1979	*/
vpcola	0:a1734fe1ec4b	1980	static void rf_handle_tx_end(void)
vpcola	0:a1734fe1ec4b	1981	{
vpcola	0:a1734fe1ec4b	1982	rf_rx_mode = 0;
vpcola	0:a1734fe1ec4b	1983	/If ACK is needed for this transmission/
vpcola	0:a1734fe1ec4b	1984	if((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX))
vpcola	0:a1734fe1ec4b	1985	{
vpcola	0:a1734fe1ec4b	1986	expected_ack_sequence = rf_tx_data[2];
vpcola	0:a1734fe1ec4b	1987	rf_ack_wait_timer_start(rf_ack_wait_duration);
vpcola	0:a1734fe1ec4b	1988	rf_rx_mode = 1;
vpcola	0:a1734fe1ec4b	1989	}
vpcola	0:a1734fe1ec4b	1990	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	1991	/Start receiver/
vpcola	0:a1734fe1ec4b	1992	rf_receive();
vpcola	0:a1734fe1ec4b	1993
vpcola	0:a1734fe1ec4b	1994	/Call PHY TX Done API/
vpcola	0:a1734fe1ec4b	1995	if(device_driver.phy_tx_done_cb){
vpcola	0:a1734fe1ec4b	1996	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0);
vpcola	0:a1734fe1ec4b	1997	}
vpcola	0:a1734fe1ec4b	1998	}
vpcola	0:a1734fe1ec4b	1999
vpcola	0:a1734fe1ec4b	2000	/*
vpcola	0:a1734fe1ec4b	2001	* \brief Function is a call back for CCA ED done interrupt.
vpcola	0:a1734fe1ec4b	2002	*
vpcola	0:a1734fe1ec4b	2003	* \param none
vpcola	0:a1734fe1ec4b	2004	*
vpcola	0:a1734fe1ec4b	2005	* \return none
vpcola	0:a1734fe1ec4b	2006	*/
vpcola	0:a1734fe1ec4b	2007	static void rf_handle_cca_ed_done(void)
vpcola	0:a1734fe1ec4b	2008	{
vpcola	0:a1734fe1ec4b	2009	if (!rf_flags_check(RFF_CCA)) {
vpcola	0:a1734fe1ec4b	2010	return;
vpcola	0:a1734fe1ec4b	2011	}
vpcola	0:a1734fe1ec4b	2012	rf_flags_clear(RFF_CCA);
vpcola	0:a1734fe1ec4b	2013	/Check the result of CCA process/
vpcola	0:a1734fe1ec4b	2014	if(rf_if_check_cca())
vpcola	0:a1734fe1ec4b	2015	{
vpcola	0:a1734fe1ec4b	2016	rf_start_tx();
vpcola	0:a1734fe1ec4b	2017	}
vpcola	0:a1734fe1ec4b	2018	else
vpcola	0:a1734fe1ec4b	2019	{
vpcola	0:a1734fe1ec4b	2020	/Re-enable reception/
vpcola	0:a1734fe1ec4b	2021	rf_disable_static_frame_buffer_protection();
vpcola	0:a1734fe1ec4b	2022	/Send CCA fail notification/
vpcola	0:a1734fe1ec4b	2023	if(device_driver.phy_tx_done_cb){
vpcola	0:a1734fe1ec4b	2024	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
vpcola	0:a1734fe1ec4b	2025	}
vpcola	0:a1734fe1ec4b	2026	}
vpcola	0:a1734fe1ec4b	2027	}
vpcola	0:a1734fe1ec4b	2028
vpcola	0:a1734fe1ec4b	2029	/*
vpcola	0:a1734fe1ec4b	2030	* \brief Function returns the TX power variable.
vpcola	0:a1734fe1ec4b	2031	*
vpcola	0:a1734fe1ec4b	2032	* \param none
vpcola	0:a1734fe1ec4b	2033	*
vpcola	0:a1734fe1ec4b	2034	* \return radio_tx_power TX power variable
vpcola	0:a1734fe1ec4b	2035	*/
vpcola	0:a1734fe1ec4b	2036	MBED_UNUSED static uint8_t rf_tx_power_get(void)
vpcola	0:a1734fe1ec4b	2037	{
vpcola	0:a1734fe1ec4b	2038	return radio_tx_power;
vpcola	0:a1734fe1ec4b	2039	}
vpcola	0:a1734fe1ec4b	2040
vpcola	0:a1734fe1ec4b	2041	/*
vpcola	0:a1734fe1ec4b	2042	* \brief Function enables the usage of Antenna diversity.
vpcola	0:a1734fe1ec4b	2043	*
vpcola	0:a1734fe1ec4b	2044	* \param none
vpcola	0:a1734fe1ec4b	2045	*
vpcola	0:a1734fe1ec4b	2046	* \return 0 Success
vpcola	0:a1734fe1ec4b	2047	*/
vpcola	0:a1734fe1ec4b	2048	MBED_UNUSED static int8_t rf_enable_antenna_diversity(void)
vpcola	0:a1734fe1ec4b	2049	{
vpcola	0:a1734fe1ec4b	2050	int8_t ret_val = 0;
vpcola	0:a1734fe1ec4b	2051	rf_use_antenna_diversity = 1;
vpcola	0:a1734fe1ec4b	2052	return ret_val;
vpcola	0:a1734fe1ec4b	2053	}
vpcola	0:a1734fe1ec4b	2054
vpcola	0:a1734fe1ec4b	2055	/*
vpcola	0:a1734fe1ec4b	2056	* \brief Function gives the control of RF states to MAC.
vpcola	0:a1734fe1ec4b	2057	*
vpcola	0:a1734fe1ec4b	2058	* \param new_state RF state
vpcola	0:a1734fe1ec4b	2059	* \param rf_channel RF channel
vpcola	0:a1734fe1ec4b	2060	*
vpcola	0:a1734fe1ec4b	2061	* \return 0 Success
vpcola	0:a1734fe1ec4b	2062	*/
vpcola	0:a1734fe1ec4b	2063	static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
vpcola	0:a1734fe1ec4b	2064	{
vpcola	0:a1734fe1ec4b	2065	int8_t ret_val = 0;
vpcola	0:a1734fe1ec4b	2066	switch (new_state)
vpcola	0:a1734fe1ec4b	2067	{
vpcola	0:a1734fe1ec4b	2068	/Reset PHY driver and set to idle/
vpcola	0:a1734fe1ec4b	2069	case PHY_INTERFACE_RESET:
vpcola	0:a1734fe1ec4b	2070	break;
vpcola	0:a1734fe1ec4b	2071	/Disable PHY Interface driver/
vpcola	0:a1734fe1ec4b	2072	case PHY_INTERFACE_DOWN:
vpcola	0:a1734fe1ec4b	2073	rf_shutdown();
vpcola	0:a1734fe1ec4b	2074	break;
vpcola	0:a1734fe1ec4b	2075	/Enable PHY Interface driver/
vpcola	0:a1734fe1ec4b	2076	case PHY_INTERFACE_UP:
vpcola	0:a1734fe1ec4b	2077	rf_mode = RF_MODE_NORMAL;
vpcola	0:a1734fe1ec4b	2078	rf_channel_set(rf_channel);
vpcola	0:a1734fe1ec4b	2079	rf_receive();
vpcola	0:a1734fe1ec4b	2080	rf_if_enable_irq();
vpcola	0:a1734fe1ec4b	2081	break;
vpcola	0:a1734fe1ec4b	2082	/Enable wireless interface ED scan mode/
vpcola	0:a1734fe1ec4b	2083	case PHY_INTERFACE_RX_ENERGY_STATE:
vpcola	0:a1734fe1ec4b	2084	rf_mode = RF_MODE_ED;
vpcola	0:a1734fe1ec4b	2085	rf_channel_set(rf_channel);
vpcola	0:a1734fe1ec4b	2086	rf_receive();
vpcola	0:a1734fe1ec4b	2087	rf_if_disable_irq();
vpcola	0:a1734fe1ec4b	2088	// Read status to clear pending flags.
vpcola	0:a1734fe1ec4b	2089	rf_if_read_register(IRQ_STATUS);
vpcola	0:a1734fe1ec4b	2090	// Must set interrupt mask to be able to read IRQ status. GPIO interrupt is disabled.
vpcola	0:a1734fe1ec4b	2091	rf_if_enable_cca_ed_done_interrupt();
vpcola	0:a1734fe1ec4b	2092	// ED can be initiated by writing arbitrary value to PHY_ED_LEVEL
vpcola	0:a1734fe1ec4b	2093	rf_if_write_register(PHY_ED_LEVEL, 0xff);
vpcola	0:a1734fe1ec4b	2094	break;
vpcola	0:a1734fe1ec4b	2095	case PHY_INTERFACE_SNIFFER_STATE: /*< Enable Sniffer state /
vpcola	0:a1734fe1ec4b	2096	rf_mode = RF_MODE_SNIFFER;
vpcola	0:a1734fe1ec4b	2097	rf_channel_set(rf_channel);
vpcola	0:a1734fe1ec4b	2098	rf_flags_clear(RFF_RX);
vpcola	0:a1734fe1ec4b	2099	rf_receive();
vpcola	0:a1734fe1ec4b	2100	rf_if_enable_irq();
vpcola	0:a1734fe1ec4b	2101	break;
vpcola	0:a1734fe1ec4b	2102	}
vpcola	0:a1734fe1ec4b	2103	return ret_val;
vpcola	0:a1734fe1ec4b	2104	}
vpcola	0:a1734fe1ec4b	2105
vpcola	0:a1734fe1ec4b	2106	/*
vpcola	0:a1734fe1ec4b	2107	* \brief Function controls the ACK pending, channel setting and energy detection.
vpcola	0:a1734fe1ec4b	2108	*
vpcola	0:a1734fe1ec4b	2109	* \param extension_type Type of control
vpcola	0:a1734fe1ec4b	2110	* \param data_ptr Data from NET library
vpcola	0:a1734fe1ec4b	2111	*
vpcola	0:a1734fe1ec4b	2112	* \return 0 Success
vpcola	0:a1734fe1ec4b	2113	*/
vpcola	0:a1734fe1ec4b	2114	static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
vpcola	0:a1734fe1ec4b	2115	{
vpcola	0:a1734fe1ec4b	2116	switch (extension_type)
vpcola	0:a1734fe1ec4b	2117	{
vpcola	0:a1734fe1ec4b	2118	/Control MAC pending bit for Indirect data transmission/
vpcola	0:a1734fe1ec4b	2119	case PHY_EXTENSION_CTRL_PENDING_BIT:
vpcola	0:a1734fe1ec4b	2120	if(*data_ptr)
vpcola	0:a1734fe1ec4b	2121	{
vpcola	0:a1734fe1ec4b	2122	rf_if_ack_pending_ctrl(1);
vpcola	0:a1734fe1ec4b	2123	}
vpcola	0:a1734fe1ec4b	2124	else
vpcola	0:a1734fe1ec4b	2125	{
vpcola	0:a1734fe1ec4b	2126	rf_if_ack_pending_ctrl(0);
vpcola	0:a1734fe1ec4b	2127	}
vpcola	0:a1734fe1ec4b	2128	break;
vpcola	0:a1734fe1ec4b	2129	/Return frame pending status/
vpcola	0:a1734fe1ec4b	2130	case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS:
vpcola	0:a1734fe1ec4b	2131	*data_ptr = rf_if_last_acked_pending();
vpcola	0:a1734fe1ec4b	2132	break;
vpcola	0:a1734fe1ec4b	2133	/Set channel/
vpcola	0:a1734fe1ec4b	2134	case PHY_EXTENSION_SET_CHANNEL:
vpcola	0:a1734fe1ec4b	2135	break;
vpcola	0:a1734fe1ec4b	2136	/Read energy on the channel/
vpcola	0:a1734fe1ec4b	2137	case PHY_EXTENSION_READ_CHANNEL_ENERGY:
vpcola	0:a1734fe1ec4b	2138	// End of the ED measurement is indicated by CCA_ED_DONE
vpcola	0:a1734fe1ec4b	2139	while (!(rf_if_read_register(IRQ_STATUS) & CCA_ED_DONE));
vpcola	0:a1734fe1ec4b	2140	// RF input power: RSSI base level + 1[db] * PHY_ED_LEVEL
vpcola	0:a1734fe1ec4b	2141	*data_ptr = rf_sensitivity + rf_if_read_register(PHY_ED_LEVEL);
vpcola	0:a1734fe1ec4b	2142	// Read status to clear pending flags.
vpcola	0:a1734fe1ec4b	2143	rf_if_read_register(IRQ_STATUS);
vpcola	0:a1734fe1ec4b	2144	// Next ED measurement is started, next PHY_EXTENSION_READ_CHANNEL_ENERGY call will return the result.
vpcola	0:a1734fe1ec4b	2145	rf_if_write_register(PHY_ED_LEVEL, 0xff);
vpcola	0:a1734fe1ec4b	2146	break;
vpcola	0:a1734fe1ec4b	2147	/Read status of the link/
vpcola	0:a1734fe1ec4b	2148	case PHY_EXTENSION_READ_LINK_STATUS:
vpcola	0:a1734fe1ec4b	2149	break;
vpcola	0:a1734fe1ec4b	2150	default:
vpcola	0:a1734fe1ec4b	2151	break;
vpcola	0:a1734fe1ec4b	2152	}
vpcola	0:a1734fe1ec4b	2153	return 0;
vpcola	0:a1734fe1ec4b	2154	}
vpcola	0:a1734fe1ec4b	2155
vpcola	0:a1734fe1ec4b	2156	/*
vpcola	0:a1734fe1ec4b	2157	* \brief Function sets the addresses to RF address filters.
vpcola	0:a1734fe1ec4b	2158	*
vpcola	0:a1734fe1ec4b	2159	* \param address_type Type of address
vpcola	0:a1734fe1ec4b	2160	* \param address_ptr Pointer to given address
vpcola	0:a1734fe1ec4b	2161	*
vpcola	0:a1734fe1ec4b	2162	* \return 0 Success
vpcola	0:a1734fe1ec4b	2163	*/
vpcola	0:a1734fe1ec4b	2164	static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
vpcola	0:a1734fe1ec4b	2165	{
vpcola	0:a1734fe1ec4b	2166	int8_t ret_val = 0;
vpcola	0:a1734fe1ec4b	2167	switch (address_type)
vpcola	0:a1734fe1ec4b	2168	{
vpcola	0:a1734fe1ec4b	2169	/Set 48-bit address/
vpcola	0:a1734fe1ec4b	2170	case PHY_MAC_48BIT:
vpcola	0:a1734fe1ec4b	2171	break;
vpcola	0:a1734fe1ec4b	2172	/Set 64-bit address/
vpcola	0:a1734fe1ec4b	2173	case PHY_MAC_64BIT:
vpcola	0:a1734fe1ec4b	2174	rf_set_address(address_ptr);
vpcola	0:a1734fe1ec4b	2175	break;
vpcola	0:a1734fe1ec4b	2176	/Set 16-bit address/
vpcola	0:a1734fe1ec4b	2177	case PHY_MAC_16BIT:
vpcola	0:a1734fe1ec4b	2178	rf_set_short_adr(address_ptr);
vpcola	0:a1734fe1ec4b	2179	break;
vpcola	0:a1734fe1ec4b	2180	/Set PAN Id/
vpcola	0:a1734fe1ec4b	2181	case PHY_MAC_PANID:
vpcola	0:a1734fe1ec4b	2182	rf_set_pan_id(address_ptr);
vpcola	0:a1734fe1ec4b	2183	break;
vpcola	0:a1734fe1ec4b	2184	}
vpcola	0:a1734fe1ec4b	2185	return ret_val;
vpcola	0:a1734fe1ec4b	2186	}
vpcola	0:a1734fe1ec4b	2187
vpcola	0:a1734fe1ec4b	2188	/*
vpcola	0:a1734fe1ec4b	2189	* \brief Function initialises the ACK wait time and returns the used PHY mode.
vpcola	0:a1734fe1ec4b	2190	*
vpcola	0:a1734fe1ec4b	2191	* \param none
vpcola	0:a1734fe1ec4b	2192	*
vpcola	0:a1734fe1ec4b	2193	* \return tmp Used PHY mode
vpcola	0:a1734fe1ec4b	2194	*/
vpcola	0:a1734fe1ec4b	2195	static void rf_init_phy_mode(void)
vpcola	0:a1734fe1ec4b	2196	{
vpcola	0:a1734fe1ec4b	2197	uint8_t tmp = 0;
vpcola	0:a1734fe1ec4b	2198	uint8_t part = rf_if_read_part_num();
vpcola	0:a1734fe1ec4b	2199	/Read used PHY Mode/
vpcola	0:a1734fe1ec4b	2200	tmp = rf_if_read_register(TRX_CTRL_2);
vpcola	0:a1734fe1ec4b	2201	/Set ACK wait time for used data rate/
vpcola	0:a1734fe1ec4b	2202	if(part == PART_AT86RF212)
vpcola	0:a1734fe1ec4b	2203	{
vpcola	0:a1734fe1ec4b	2204	if((tmp & 0x1f) == 0x00)
vpcola	0:a1734fe1ec4b	2205	{
vpcola	0:a1734fe1ec4b	2206	rf_sensitivity = -110;
vpcola	0:a1734fe1ec4b	2207	rf_ack_wait_duration = 938;
vpcola	0:a1734fe1ec4b	2208	tmp = BPSK_20;
vpcola	0:a1734fe1ec4b	2209	}
vpcola	0:a1734fe1ec4b	2210	else if((tmp & 0x1f) == 0x04)
vpcola	0:a1734fe1ec4b	2211	{
vpcola	0:a1734fe1ec4b	2212	rf_sensitivity = -108;
vpcola	0:a1734fe1ec4b	2213	rf_ack_wait_duration = 469;
vpcola	0:a1734fe1ec4b	2214	tmp = BPSK_40;
vpcola	0:a1734fe1ec4b	2215	}
vpcola	0:a1734fe1ec4b	2216	else if((tmp & 0x1f) == 0x14)
vpcola	0:a1734fe1ec4b	2217	{
vpcola	0:a1734fe1ec4b	2218	rf_sensitivity = -108;
vpcola	0:a1734fe1ec4b	2219	rf_ack_wait_duration = 469;
vpcola	0:a1734fe1ec4b	2220	tmp = BPSK_40_ALT;
vpcola	0:a1734fe1ec4b	2221	}
vpcola	0:a1734fe1ec4b	2222	else if((tmp & 0x1f) == 0x08)
vpcola	0:a1734fe1ec4b	2223	{
vpcola	0:a1734fe1ec4b	2224	rf_sensitivity = -101;
vpcola	0:a1734fe1ec4b	2225	rf_ack_wait_duration = 50;
vpcola	0:a1734fe1ec4b	2226	tmp = OQPSK_SIN_RC_100;
vpcola	0:a1734fe1ec4b	2227	}
vpcola	0:a1734fe1ec4b	2228	else if((tmp & 0x1f) == 0x09)
vpcola	0:a1734fe1ec4b	2229	{
vpcola	0:a1734fe1ec4b	2230	rf_sensitivity = -99;
vpcola	0:a1734fe1ec4b	2231	rf_ack_wait_duration = 30;
vpcola	0:a1734fe1ec4b	2232	tmp = OQPSK_SIN_RC_200;
vpcola	0:a1734fe1ec4b	2233	}
vpcola	0:a1734fe1ec4b	2234	else if((tmp & 0x1f) == 0x18)
vpcola	0:a1734fe1ec4b	2235	{
vpcola	0:a1734fe1ec4b	2236	rf_sensitivity = -102;
vpcola	0:a1734fe1ec4b	2237	rf_ack_wait_duration = 50;
vpcola	0:a1734fe1ec4b	2238	tmp = OQPSK_RC_100;
vpcola	0:a1734fe1ec4b	2239	}
vpcola	0:a1734fe1ec4b	2240	else if((tmp & 0x1f) == 0x19)
vpcola	0:a1734fe1ec4b	2241	{
vpcola	0:a1734fe1ec4b	2242	rf_sensitivity = -100;
vpcola	0:a1734fe1ec4b	2243	rf_ack_wait_duration = 30;
vpcola	0:a1734fe1ec4b	2244	tmp = OQPSK_RC_200;
vpcola	0:a1734fe1ec4b	2245	}
vpcola	0:a1734fe1ec4b	2246	else if((tmp & 0x1f) == 0x0c)
vpcola	0:a1734fe1ec4b	2247	{
vpcola	0:a1734fe1ec4b	2248	rf_sensitivity = -100;
vpcola	0:a1734fe1ec4b	2249	rf_ack_wait_duration = 20;
vpcola	0:a1734fe1ec4b	2250	tmp = OQPSK_SIN_250;
vpcola	0:a1734fe1ec4b	2251	}
vpcola	0:a1734fe1ec4b	2252	else if((tmp & 0x1f) == 0x0d)
vpcola	0:a1734fe1ec4b	2253	{
vpcola	0:a1734fe1ec4b	2254	rf_sensitivity = -98;
vpcola	0:a1734fe1ec4b	2255	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2256	tmp = OQPSK_SIN_500;
vpcola	0:a1734fe1ec4b	2257	}
vpcola	0:a1734fe1ec4b	2258	else if((tmp & 0x1f) == 0x0f)
vpcola	0:a1734fe1ec4b	2259	{
vpcola	0:a1734fe1ec4b	2260	rf_sensitivity = -98;
vpcola	0:a1734fe1ec4b	2261	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2262	tmp = OQPSK_SIN_500_ALT;
vpcola	0:a1734fe1ec4b	2263	}
vpcola	0:a1734fe1ec4b	2264	else if((tmp & 0x1f) == 0x1c)
vpcola	0:a1734fe1ec4b	2265	{
vpcola	0:a1734fe1ec4b	2266	rf_sensitivity = -101;
vpcola	0:a1734fe1ec4b	2267	rf_ack_wait_duration = 20;
vpcola	0:a1734fe1ec4b	2268	tmp = OQPSK_RC_250;
vpcola	0:a1734fe1ec4b	2269	}
vpcola	0:a1734fe1ec4b	2270	else if((tmp & 0x1f) == 0x1d)
vpcola	0:a1734fe1ec4b	2271	{
vpcola	0:a1734fe1ec4b	2272	rf_sensitivity = -99;
vpcola	0:a1734fe1ec4b	2273	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2274	tmp = OQPSK_RC_500;
vpcola	0:a1734fe1ec4b	2275	}
vpcola	0:a1734fe1ec4b	2276	else if((tmp & 0x1f) == 0x1f)
vpcola	0:a1734fe1ec4b	2277	{
vpcola	0:a1734fe1ec4b	2278	rf_sensitivity = -99;
vpcola	0:a1734fe1ec4b	2279	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2280	tmp = OQPSK_RC_500_ALT;
vpcola	0:a1734fe1ec4b	2281	}
vpcola	0:a1734fe1ec4b	2282	else if((tmp & 0x3f) == 0x2A)
vpcola	0:a1734fe1ec4b	2283	{
vpcola	0:a1734fe1ec4b	2284	rf_sensitivity = -91;
vpcola	0:a1734fe1ec4b	2285	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2286	tmp = OQPSK_SIN_RC_400_SCR_ON;
vpcola	0:a1734fe1ec4b	2287	}
vpcola	0:a1734fe1ec4b	2288	else if((tmp & 0x3f) == 0x0A)
vpcola	0:a1734fe1ec4b	2289	{
vpcola	0:a1734fe1ec4b	2290	rf_sensitivity = -91;
vpcola	0:a1734fe1ec4b	2291	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2292	tmp = OQPSK_SIN_RC_400_SCR_OFF;
vpcola	0:a1734fe1ec4b	2293	}
vpcola	0:a1734fe1ec4b	2294	else if((tmp & 0x3f) == 0x3A)
vpcola	0:a1734fe1ec4b	2295	{
vpcola	0:a1734fe1ec4b	2296	rf_sensitivity = -97;
vpcola	0:a1734fe1ec4b	2297	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2298	tmp = OQPSK_RC_400_SCR_ON;
vpcola	0:a1734fe1ec4b	2299	}
vpcola	0:a1734fe1ec4b	2300	else if((tmp & 0x3f) == 0x1A)
vpcola	0:a1734fe1ec4b	2301	{
vpcola	0:a1734fe1ec4b	2302	rf_sensitivity = -97;
vpcola	0:a1734fe1ec4b	2303	rf_ack_wait_duration = 25;
vpcola	0:a1734fe1ec4b	2304	tmp = OQPSK_RC_400_SCR_OFF;
vpcola	0:a1734fe1ec4b	2305	}
vpcola	0:a1734fe1ec4b	2306	else if((tmp & 0x3f) == 0x2E)
vpcola	0:a1734fe1ec4b	2307	{
vpcola	0:a1734fe1ec4b	2308	rf_sensitivity = -93;
vpcola	0:a1734fe1ec4b	2309	rf_ack_wait_duration = 13;
vpcola	0:a1734fe1ec4b	2310	tmp = OQPSK_SIN_1000_SCR_ON;
vpcola	0:a1734fe1ec4b	2311	}
vpcola	0:a1734fe1ec4b	2312	else if((tmp & 0x3f) == 0x0E)
vpcola	0:a1734fe1ec4b	2313	{
vpcola	0:a1734fe1ec4b	2314	rf_sensitivity = -93;
vpcola	0:a1734fe1ec4b	2315	rf_ack_wait_duration = 13;
vpcola	0:a1734fe1ec4b	2316	tmp = OQPSK_SIN_1000_SCR_OFF;
vpcola	0:a1734fe1ec4b	2317	}
vpcola	0:a1734fe1ec4b	2318	else if((tmp & 0x3f) == 0x3E)
vpcola	0:a1734fe1ec4b	2319	{
vpcola	0:a1734fe1ec4b	2320	rf_sensitivity = -95;
vpcola	0:a1734fe1ec4b	2321	rf_ack_wait_duration = 13;
vpcola	0:a1734fe1ec4b	2322	tmp = OQPSK_RC_1000_SCR_ON;
vpcola	0:a1734fe1ec4b	2323	}
vpcola	0:a1734fe1ec4b	2324	else if((tmp & 0x3f) == 0x1E)
vpcola	0:a1734fe1ec4b	2325	{
vpcola	0:a1734fe1ec4b	2326	rf_sensitivity = -95;
vpcola	0:a1734fe1ec4b	2327	rf_ack_wait_duration = 13;
vpcola	0:a1734fe1ec4b	2328	tmp = OQPSK_RC_1000_SCR_OFF;
vpcola	0:a1734fe1ec4b	2329	}
vpcola	0:a1734fe1ec4b	2330	}
vpcola	0:a1734fe1ec4b	2331	else
vpcola	0:a1734fe1ec4b	2332	{
vpcola	0:a1734fe1ec4b	2333	rf_sensitivity = -101;
vpcola	0:a1734fe1ec4b	2334	rf_ack_wait_duration = 20;
vpcola	0:a1734fe1ec4b	2335	}
vpcola	0:a1734fe1ec4b	2336	/Board design might reduces the sensitivity/
vpcola	0:a1734fe1ec4b	2337	//rf_sensitivity += RF_SENSITIVITY_CALIBRATION;
vpcola	0:a1734fe1ec4b	2338	}
vpcola	0:a1734fe1ec4b	2339
vpcola	0:a1734fe1ec4b	2340
vpcola	0:a1734fe1ec4b	2341	static uint8_t rf_scale_lqi(int8_t rssi)
vpcola	0:a1734fe1ec4b	2342	{
vpcola	0:a1734fe1ec4b	2343	uint8_t scaled_lqi;
vpcola	0:a1734fe1ec4b	2344
vpcola	0:a1734fe1ec4b	2345	/rssi < RF sensitivity/
vpcola	0:a1734fe1ec4b	2346	if(rssi < rf_sensitivity)
vpcola	0:a1734fe1ec4b	2347	scaled_lqi=0;
vpcola	0:a1734fe1ec4b	2348	/-91 dBm < rssi < -81 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2349	/-90 dBm < rssi < -80 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2350	else if(rssi < (rf_sensitivity + 10))
vpcola	0:a1734fe1ec4b	2351	scaled_lqi=31;
vpcola	0:a1734fe1ec4b	2352	/-81 dBm < rssi < -71 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2353	/-80 dBm < rssi < -70 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2354	else if(rssi < (rf_sensitivity + 20))
vpcola	0:a1734fe1ec4b	2355	scaled_lqi=207;
vpcola	0:a1734fe1ec4b	2356	/-71 dBm < rssi < -61 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2357	/-70 dBm < rssi < -60 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2358	else if(rssi < (rf_sensitivity + 30))
vpcola	0:a1734fe1ec4b	2359	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2360	/-61 dBm < rssi < -51 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2361	/-60 dBm < rssi < -50 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2362	else if(rssi < (rf_sensitivity + 40))
vpcola	0:a1734fe1ec4b	2363	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2364	/-51 dBm < rssi < -41 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2365	/-50 dBm < rssi < -40 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2366	else if(rssi < (rf_sensitivity + 50))
vpcola	0:a1734fe1ec4b	2367	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2368	/-41 dBm < rssi < -31 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2369	/-40 dBm < rssi < -30 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2370	else if(rssi < (rf_sensitivity + 60))
vpcola	0:a1734fe1ec4b	2371	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2372	/-31 dBm < rssi < -21 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2373	/-30 dBm < rssi < -20 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2374	else if(rssi < (rf_sensitivity + 70))
vpcola	0:a1734fe1ec4b	2375	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2376	/rssi > RF saturation/
vpcola	0:a1734fe1ec4b	2377	else if(rssi > (rf_sensitivity + 80))
vpcola	0:a1734fe1ec4b	2378	scaled_lqi=111;
vpcola	0:a1734fe1ec4b	2379	/-21 dBm < rssi < -11 dBm (AT86RF233 XPro)/
vpcola	0:a1734fe1ec4b	2380	/-20 dBm < rssi < -10 dBm (AT86RF212B XPro)/
vpcola	0:a1734fe1ec4b	2381	else
vpcola	0:a1734fe1ec4b	2382	scaled_lqi=255;
vpcola	0:a1734fe1ec4b	2383
vpcola	0:a1734fe1ec4b	2384	return scaled_lqi;
vpcola	0:a1734fe1ec4b	2385	}
vpcola	0:a1734fe1ec4b	2386
vpcola	0:a1734fe1ec4b	2387	NanostackRfPhyAtmel::NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso,
vpcola	0:a1734fe1ec4b	2388	PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq,
vpcola	0:a1734fe1ec4b	2389	PinName i2c_sda, PinName i2c_scl)
vpcola	0:a1734fe1ec4b	2390	: _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _mac_set(false),
vpcola	0:a1734fe1ec4b	2391	_spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk),
vpcola	0:a1734fe1ec4b	2392	_spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq)
vpcola	0:a1734fe1ec4b	2393	{
vpcola	0:a1734fe1ec4b	2394	_rf = new RFBits(_spi_mosi, _spi_miso, _spi_sclk, _spi_cs, _spi_rst, _spi_slp, _spi_irq);
vpcola	0:a1734fe1ec4b	2395	}
vpcola	0:a1734fe1ec4b	2396
vpcola	0:a1734fe1ec4b	2397	NanostackRfPhyAtmel::~NanostackRfPhyAtmel()
vpcola	0:a1734fe1ec4b	2398	{
vpcola	0:a1734fe1ec4b	2399	delete _rf;
vpcola	0:a1734fe1ec4b	2400	}
vpcola	0:a1734fe1ec4b	2401
vpcola	0:a1734fe1ec4b	2402	int8_t NanostackRfPhyAtmel::rf_register()
vpcola	0:a1734fe1ec4b	2403	{
vpcola	0:a1734fe1ec4b	2404	if (NULL == _rf) {
vpcola	0:a1734fe1ec4b	2405	return -1;
vpcola	0:a1734fe1ec4b	2406	}
vpcola	0:a1734fe1ec4b	2407
vpcola	0:a1734fe1ec4b	2408	rf_if_lock();
vpcola	0:a1734fe1ec4b	2409
vpcola	0:a1734fe1ec4b	2410	if (rf != NULL) {
vpcola	0:a1734fe1ec4b	2411	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2412	error("Multiple registrations of NanostackRfPhyAtmel not supported");
vpcola	0:a1734fe1ec4b	2413	return -1;
vpcola	0:a1734fe1ec4b	2414	}
vpcola	0:a1734fe1ec4b	2415
vpcola	0:a1734fe1ec4b	2416	// Read the mac address if it hasn't been set by a user
vpcola	0:a1734fe1ec4b	2417	rf = _rf;
vpcola	0:a1734fe1ec4b	2418	if (!_mac_set) {
vpcola	0:a1734fe1ec4b	2419	int ret = _mac.read_eui64((void*)_mac_addr);
vpcola	0:a1734fe1ec4b	2420	if (ret < 0) {
vpcola	0:a1734fe1ec4b	2421	rf = NULL;
vpcola	0:a1734fe1ec4b	2422	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2423	return -1;
vpcola	0:a1734fe1ec4b	2424	}
vpcola	0:a1734fe1ec4b	2425	}
vpcola	0:a1734fe1ec4b	2426
vpcola	0:a1734fe1ec4b	2427	int8_t radio_id = rf_device_register(_mac_addr);
vpcola	0:a1734fe1ec4b	2428	if (radio_id < 0) {
vpcola	0:a1734fe1ec4b	2429	rf = NULL;
vpcola	0:a1734fe1ec4b	2430	}
vpcola	0:a1734fe1ec4b	2431
vpcola	0:a1734fe1ec4b	2432	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2433	return radio_id;
vpcola	0:a1734fe1ec4b	2434	}
vpcola	0:a1734fe1ec4b	2435
vpcola	0:a1734fe1ec4b	2436	void NanostackRfPhyAtmel::rf_unregister()
vpcola	0:a1734fe1ec4b	2437	{
vpcola	0:a1734fe1ec4b	2438	rf_if_lock();
vpcola	0:a1734fe1ec4b	2439
vpcola	0:a1734fe1ec4b	2440	if (NULL == rf) {
vpcola	0:a1734fe1ec4b	2441	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2442	return;
vpcola	0:a1734fe1ec4b	2443	}
vpcola	0:a1734fe1ec4b	2444
vpcola	0:a1734fe1ec4b	2445	rf_device_unregister();
vpcola	0:a1734fe1ec4b	2446	rf = NULL;
vpcola	0:a1734fe1ec4b	2447
vpcola	0:a1734fe1ec4b	2448	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2449	}
vpcola	0:a1734fe1ec4b	2450
vpcola	0:a1734fe1ec4b	2451	void NanostackRfPhyAtmel::get_mac_address(uint8_t *mac)
vpcola	0:a1734fe1ec4b	2452	{
vpcola	0:a1734fe1ec4b	2453	rf_if_lock();
vpcola	0:a1734fe1ec4b	2454
vpcola	0:a1734fe1ec4b	2455	if (NULL == rf) {
vpcola	0:a1734fe1ec4b	2456	error("NanostackRfPhyAtmel Must be registered to read mac address");
vpcola	0:a1734fe1ec4b	2457	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2458	return;
vpcola	0:a1734fe1ec4b	2459	}
vpcola	0:a1734fe1ec4b	2460	memcpy((void)mac, (void)_mac_addr, sizeof(_mac_addr));
vpcola	0:a1734fe1ec4b	2461
vpcola	0:a1734fe1ec4b	2462	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2463	}
vpcola	0:a1734fe1ec4b	2464
vpcola	0:a1734fe1ec4b	2465	void NanostackRfPhyAtmel::set_mac_address(uint8_t *mac)
vpcola	0:a1734fe1ec4b	2466	{
vpcola	0:a1734fe1ec4b	2467	rf_if_lock();
vpcola	0:a1734fe1ec4b	2468
vpcola	0:a1734fe1ec4b	2469	if (NULL != rf) {
vpcola	0:a1734fe1ec4b	2470	error("NanostackRfPhyAtmel cannot change mac address when running");
vpcola	0:a1734fe1ec4b	2471	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2472	return;
vpcola	0:a1734fe1ec4b	2473	}
vpcola	0:a1734fe1ec4b	2474	memcpy((void)_mac_addr, (void)mac, sizeof(_mac_addr));
vpcola	0:a1734fe1ec4b	2475	_mac_set = true;
vpcola	0:a1734fe1ec4b	2476
vpcola	0:a1734fe1ec4b	2477	rf_if_unlock();
vpcola	0:a1734fe1ec4b	2478	}
vpcola	0:a1734fe1ec4b	2479

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Type:	Program
Mbed OS support:	Mbed OS
Created:	08 Apr 2017
Imports:	10
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

The code in this repository is Apache licensed.

easy-connect/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp@0:a1734fe1ec4b, 2017-04-08 (annotated)

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