Diff: SparkFun-Si4703.cpp

Revision:

3:9ac35cc4a0b0

Parent:

2:558ef02f39d0

--- a/SparkFun-Si4703.cpp	Sat Aug 08 18:15:36 2015 +0000
+++ b/SparkFun-Si4703.cpp	Sat Jan 16 19:26:55 2016 +0000
@@ -1,5 +1,6 @@
 #include "mbed.h"
 #include "SparkFun-Si4703.h"
+#include "millis.h"
 
 Si4703_Breakout::Si4703_Breakout(PinName sdioPin, PinName sclkPin, PinName resetPin, Serial *pc)
 {
@@ -22,8 +23,8 @@
 readRegisters();
 
 si4703_registers[POWERCFG] &= ~(1<<DMUTE); // 'Enable Mute'
-si4703_registers[POWERCFG] |= (1<<ENABLE); // 'Enable IC'
-si4703_registers[POWERCFG] |= (1<<DISABLE); // & 'Disable IC'
+//si4703_registers[POWERCFG] |= (1<<ENABLE); // 'Enable IC'
+//si4703_registers[POWERCFG] |= (1<<DISABLE); // & 'Disable IC'
 											// To Init. Power-Down Sequence
 
 updateRegisters();
@@ -32,10 +33,9 @@
 
 void Si4703_Breakout::setChannel(int channel)
 {
-  uint8_t ack;
-  //Freq(MHz) = 0.1 (in Europe) * Channel + 87.5MHz
-  //97.3 = 0.1 * Chan + 87.5
-  //9.8 / 0.1 = 98
+  //Freq(MHz) = 0.200(in USA) * Channel + 87.5MHz
+  //97.3 = 0.2 * Chan + 87.5
+  //9.8 / 0.2 = 49
   int newChannel = channel * 10; //973 * 10 = 9730
   newChannel -= 8750; //9730 - 8750 = 980
   newChannel /= 10; //980 / 10 = 98
@@ -47,13 +47,12 @@
   si4703_registers[CHANNEL] |= (1<<TUNE); //Set the TUNE bit to start
   updateRegisters();
 
-  wait_ms(60); //Wait 60ms - you can use or skip this delay
+  //delay(60); //Wait 60ms - you can use or skip this delay
 
   //Poll to see if STC is set
   while(1) {
-    ack = readRegisters();
-    wait_ms(1); // Just In Case...
-    if (( (si4703_registers[STATUSRSSI] & (1<<STC)) != 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
+    readRegisters();
+    if( (si4703_registers[STATUSRSSI] & (1<<STC)) != 0) break; //Tuning complete!
   }
 
   readRegisters();
@@ -62,9 +61,8 @@
 
   //Wait for the si4703 to clear the STC as well
   while(1) {
-    ack = readRegisters();
-    wait_ms(1); // Just In Case...
-    if (( (si4703_registers[STATUSRSSI] & (1<<STC)) == 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
+    readRegisters();
+    if( (si4703_registers[STATUSRSSI] & (1<<STC)) == 0) break; //Tuning complete!
   }
 }
 
@@ -95,15 +93,15 @@
   return (si4703_registers[SYSCONFIG2] & 0x000F);
 }
 
-/*
+
 void Si4703_Breakout::readRDS(char* buffer, long timeout)
 { 
 	long endTime = millis() + timeout;
-  boolean completed[] = {false, false, false, false};
-  int completedCount = 0;
-  while(completedCount < 4 && millis() < endTime) {
-	readRegisters();
-	if(si4703_registers[STATUSRSSI] & (1<<RDSR)){
+    bool completed[] = {false, false, false, false};
+    int completedCount = 0;
+  	while(completedCount < 4 && millis() < endTime) {
+		readRegisters();
+		if(si4703_registers[STATUSRSSI] & (1<<RDSR)){
 		// ls 2 bits of B determine the 4 letter pairs
 		// once we have a full set return
 		// if you get nothing after 20 readings return with empty string
@@ -123,10 +121,12 @@
 		// Serial.write(Dl);
 		// Serial.println();
       }
-      delay(40); //Wait for the RDS bit to clear
+      wait_ms(40);
+      /////delay(40); //Wait for the RDS bit to clear
 	}
 	else {
-	  delay(30); //From AN230, using the polling method 40ms should be sufficient amount of time between checks
+	  /////////delay(30); //From AN230, using the polling method 40ms should be sufficient amount of time between checks
+	  wait_ms(40);
 	}
   }
 	if (millis() >= endTime) {
@@ -136,7 +136,7 @@
 
   buffer[8] = '\0';
 }
-*/
+
 
 
 
@@ -177,9 +177,9 @@
   si4703_registers[SYSCONFIG2] |= 0x0001; //Set volume to lowest
 
   // SI AN230 page 40 - Table 23 ('Good Quality Stations Only' Settings)
-  si4703_registers[SYSCONFIG2] |= (0xC<<SEEKTH);
+/***********  si4703_registers[SYSCONFIG2] |= (0xC<<SEEKTH);
   si4703_registers[SYSCONFIG3] |= (0x7<<SKSNR);
-  si4703_registers[SYSCONFIG3] |= (0xF<<SKCNT);
+  si4703_registers[SYSCONFIG3] |= (0xF<<SKCNT);*************/
   ///
   updateRegisters(); //Update