core_cmFunc.h

00001 /**************************************************************************//**
00002  * @file     core_cmFunc.h
00003  * @brief    CMSIS Cortex-M Core Function Access Header File
00004  * @version  V4.10
00005  * @date     18. March 2015
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2015 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #ifndef __CORE_CMFUNC_H
00039 #define __CORE_CMFUNC_H
00040 
00041 
00042 /* ###########################  Core Function Access  ########################### */
00043 /** \ingroup  CMSIS_Core_FunctionInterface
00044     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
00045   @{
00046  */
00047 
00048 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
00049 /* ARM armcc specific functions */
00050 
00051 #if (__ARMCC_VERSION < 400677)
00052   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
00053 #endif
00054 
00055 /* intrinsic void __enable_irq();     */
00056 /* intrinsic void __disable_irq();    */
00057 
00058 /** \brief  Get Control Register
00059 
00060     This function returns the content of the Control Register.
00061 
00062     \return               Control Register value
00063  */
00064 __STATIC_INLINE uint32_t __get_CONTROL(void)
00065 {
00066   register uint32_t __regControl         __ASM("control");
00067   return(__regControl);
00068 }
00069 
00070 
00071 /** \brief  Set Control Register
00072 
00073     This function writes the given value to the Control Register.
00074 
00075     \param [in]    control  Control Register value to set
00076  */
00077 __STATIC_INLINE void __set_CONTROL(uint32_t control)
00078 {
00079   register uint32_t __regControl         __ASM("control");
00080   __regControl = control;
00081 }
00082 
00083 
00084 /** \brief  Get IPSR Register
00085 
00086     This function returns the content of the IPSR Register.
00087 
00088     \return               IPSR Register value
00089  */
00090 __STATIC_INLINE uint32_t __get_IPSR(void)
00091 {
00092   register uint32_t __regIPSR          __ASM("ipsr");
00093   return(__regIPSR);
00094 }
00095 
00096 
00097 /** \brief  Get APSR Register
00098 
00099     This function returns the content of the APSR Register.
00100 
00101     \return               APSR Register value
00102  */
00103 __STATIC_INLINE uint32_t __get_APSR(void)
00104 {
00105   register uint32_t __regAPSR          __ASM("apsr");
00106   return(__regAPSR);
00107 }
00108 
00109 
00110 /** \brief  Get xPSR Register
00111 
00112     This function returns the content of the xPSR Register.
00113 
00114     \return               xPSR Register value
00115  */
00116 __STATIC_INLINE uint32_t __get_xPSR(void)
00117 {
00118   register uint32_t __regXPSR          __ASM("xpsr");
00119   return(__regXPSR);
00120 }
00121 
00122 
00123 /** \brief  Get Process Stack Pointer
00124 
00125     This function returns the current value of the Process Stack Pointer (PSP).
00126 
00127     \return               PSP Register value
00128  */
00129 __STATIC_INLINE uint32_t __get_PSP(void)
00130 {
00131   register uint32_t __regProcessStackPointer  __ASM("psp");
00132   return(__regProcessStackPointer);
00133 }
00134 
00135 
00136 /** \brief  Set Process Stack Pointer
00137 
00138     This function assigns the given value to the Process Stack Pointer (PSP).
00139 
00140     \param [in]    topOfProcStack  Process Stack Pointer value to set
00141  */
00142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
00143 {
00144   register uint32_t __regProcessStackPointer  __ASM("psp");
00145   __regProcessStackPointer = topOfProcStack;
00146 }
00147 
00148 
00149 /** \brief  Get Main Stack Pointer
00150 
00151     This function returns the current value of the Main Stack Pointer (MSP).
00152 
00153     \return               MSP Register value
00154  */
00155 __STATIC_INLINE uint32_t __get_MSP(void)
00156 {
00157   register uint32_t __regMainStackPointer     __ASM("msp");
00158   return(__regMainStackPointer);
00159 }
00160 
00161 
00162 /** \brief  Set Main Stack Pointer
00163 
00164     This function assigns the given value to the Main Stack Pointer (MSP).
00165 
00166     \param [in]    topOfMainStack  Main Stack Pointer value to set
00167  */
00168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
00169 {
00170   register uint32_t __regMainStackPointer     __ASM("msp");
00171   __regMainStackPointer = topOfMainStack;
00172 }
00173 
00174 
00175 /** \brief  Get Priority Mask
00176 
00177     This function returns the current state of the priority mask bit from the Priority Mask Register.
00178 
00179     \return               Priority Mask value
00180  */
00181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
00182 {
00183   register uint32_t __regPriMask         __ASM("primask");
00184   return(__regPriMask);
00185 }
00186 
00187 
00188 /** \brief  Set Priority Mask
00189 
00190     This function assigns the given value to the Priority Mask Register.
00191 
00192     \param [in]    priMask  Priority Mask
00193  */
00194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
00195 {
00196   register uint32_t __regPriMask         __ASM("primask");
00197   __regPriMask = (priMask);
00198 }
00199 
00200 
00201 #if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
00202 
00203 /** \brief  Enable FIQ
00204 
00205     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
00206     Can only be executed in Privileged modes.
00207  */
00208 #define __enable_fault_irq                __enable_fiq
00209 
00210 
00211 /** \brief  Disable FIQ
00212 
00213     This function disables FIQ interrupts by setting the F-bit in the CPSR.
00214     Can only be executed in Privileged modes.
00215  */
00216 #define __disable_fault_irq               __disable_fiq
00217 
00218 
00219 /** \brief  Get Base Priority
00220 
00221     This function returns the current value of the Base Priority register.
00222 
00223     \return               Base Priority register value
00224  */
00225 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
00226 {
00227   register uint32_t __regBasePri         __ASM("basepri");
00228   return(__regBasePri);
00229 }
00230 
00231 
00232 /** \brief  Set Base Priority
00233 
00234     This function assigns the given value to the Base Priority register.
00235 
00236     \param [in]    basePri  Base Priority value to set
00237  */
00238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
00239 {
00240   register uint32_t __regBasePri         __ASM("basepri");
00241   __regBasePri = (basePri & 0xff);
00242 }
00243 
00244 
00245 /** \brief  Set Base Priority with condition
00246 
00247     This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
00248     or the new value increases the BASEPRI priority level.
00249 
00250     \param [in]    basePri  Base Priority value to set
00251  */
00252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
00253 {
00254   register uint32_t __regBasePriMax      __ASM("basepri_max");
00255   __regBasePriMax = (basePri & 0xff);
00256 }
00257 
00258 
00259 /** \brief  Get Fault Mask
00260 
00261     This function returns the current value of the Fault Mask register.
00262 
00263     \return               Fault Mask register value
00264  */
00265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
00266 {
00267   register uint32_t __regFaultMask       __ASM("faultmask");
00268   return(__regFaultMask);
00269 }
00270 
00271 
00272 /** \brief  Set Fault Mask
00273 
00274     This function assigns the given value to the Fault Mask register.
00275 
00276     \param [in]    faultMask  Fault Mask value to set
00277  */
00278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
00279 {
00280   register uint32_t __regFaultMask       __ASM("faultmask");
00281   __regFaultMask = (faultMask & (uint32_t)1);
00282 }
00283 
00284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
00285 
00286 
00287 #if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
00288 
00289 /** \brief  Get FPSCR
00290 
00291     This function returns the current value of the Floating Point Status/Control register.
00292 
00293     \return               Floating Point Status/Control register value
00294  */
00295 __STATIC_INLINE uint32_t __get_FPSCR(void)
00296 {
00297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00298   register uint32_t __regfpscr         __ASM("fpscr");
00299   return(__regfpscr);
00300 #else
00301    return(0);
00302 #endif
00303 }
00304 
00305 
00306 /** \brief  Set FPSCR
00307 
00308     This function assigns the given value to the Floating Point Status/Control register.
00309 
00310     \param [in]    fpscr  Floating Point Status/Control value to set
00311  */
00312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
00313 {
00314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00315   register uint32_t __regfpscr         __ASM("fpscr");
00316   __regfpscr = (fpscr);
00317 #endif
00318 }
00319 
00320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
00321 
00322 
00323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
00324 /* GNU gcc specific functions */
00325 
00326 /** \brief  Enable IRQ Interrupts
00327 
00328   This function enables IRQ interrupts by clearing the I-bit in the CPSR.
00329   Can only be executed in Privileged modes.
00330  */
00331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
00332 {
00333   __ASM volatile ("cpsie i" : : : "memory");
00334 }
00335 
00336 
00337 /** \brief  Disable IRQ Interrupts
00338 
00339   This function disables IRQ interrupts by setting the I-bit in the CPSR.
00340   Can only be executed in Privileged modes.
00341  */
00342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
00343 {
00344   __ASM volatile ("cpsid i" : : : "memory");
00345 }
00346 
00347 
00348 /** \brief  Get Control Register
00349 
00350     This function returns the content of the Control Register.
00351 
00352     \return               Control Register value
00353  */
00354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
00355 {
00356   uint32_t result;
00357 
00358   __ASM volatile ("MRS %0, control" : "=r" (result) );
00359   return(result);
00360 }
00361 
00362 
00363 /** \brief  Set Control Register
00364 
00365     This function writes the given value to the Control Register.
00366 
00367     \param [in]    control  Control Register value to set
00368  */
00369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
00370 {
00371   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
00372 }
00373 
00374 
00375 /** \brief  Get IPSR Register
00376 
00377     This function returns the content of the IPSR Register.
00378 
00379     \return               IPSR Register value
00380  */
00381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
00382 {
00383   uint32_t result;
00384 
00385   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
00386   return(result);
00387 }
00388 
00389 
00390 /** \brief  Get APSR Register
00391 
00392     This function returns the content of the APSR Register.
00393 
00394     \return               APSR Register value
00395  */
00396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
00397 {
00398   uint32_t result;
00399 
00400   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
00401   return(result);
00402 }
00403 
00404 
00405 /** \brief  Get xPSR Register
00406 
00407     This function returns the content of the xPSR Register.
00408 
00409     \return               xPSR Register value
00410  */
00411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
00412 {
00413   uint32_t result;
00414 
00415   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
00416   return(result);
00417 }
00418 
00419 
00420 /** \brief  Get Process Stack Pointer
00421 
00422     This function returns the current value of the Process Stack Pointer (PSP).
00423 
00424     \return               PSP Register value
00425  */
00426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
00427 {
00428   register uint32_t result;
00429 
00430   __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
00431   return(result);
00432 }
00433 
00434 
00435 /** \brief  Set Process Stack Pointer
00436 
00437     This function assigns the given value to the Process Stack Pointer (PSP).
00438 
00439     \param [in]    topOfProcStack  Process Stack Pointer value to set
00440  */
00441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
00442 {
00443   __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
00444 }
00445 
00446 
00447 /** \brief  Get Main Stack Pointer
00448 
00449     This function returns the current value of the Main Stack Pointer (MSP).
00450 
00451     \return               MSP Register value
00452  */
00453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
00454 {
00455   register uint32_t result;
00456 
00457   __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
00458   return(result);
00459 }
00460 
00461 
00462 /** \brief  Set Main Stack Pointer
00463 
00464     This function assigns the given value to the Main Stack Pointer (MSP).
00465 
00466     \param [in]    topOfMainStack  Main Stack Pointer value to set
00467  */
00468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
00469 {
00470   __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
00471 }
00472 
00473 
00474 /** \brief  Get Priority Mask
00475 
00476     This function returns the current state of the priority mask bit from the Priority Mask Register.
00477 
00478     \return               Priority Mask value
00479  */
00480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
00481 {
00482   uint32_t result;
00483 
00484   __ASM volatile ("MRS %0, primask" : "=r" (result) );
00485   return(result);
00486 }
00487 
00488 
00489 /** \brief  Set Priority Mask
00490 
00491     This function assigns the given value to the Priority Mask Register.
00492 
00493     \param [in]    priMask  Priority Mask
00494  */
00495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
00496 {
00497   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
00498 }
00499 
00500 
00501 #if       (__CORTEX_M >= 0x03)
00502 
00503 /** \brief  Enable FIQ
00504 
00505     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
00506     Can only be executed in Privileged modes.
00507  */
00508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
00509 {
00510   __ASM volatile ("cpsie f" : : : "memory");
00511 }
00512 
00513 
00514 /** \brief  Disable FIQ
00515 
00516     This function disables FIQ interrupts by setting the F-bit in the CPSR.
00517     Can only be executed in Privileged modes.
00518  */
00519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
00520 {
00521   __ASM volatile ("cpsid f" : : : "memory");
00522 }
00523 
00524 
00525 /** \brief  Get Base Priority
00526 
00527     This function returns the current value of the Base Priority register.
00528 
00529     \return               Base Priority register value
00530  */
00531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
00532 {
00533   uint32_t result;
00534 
00535   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
00536   return(result);
00537 }
00538 
00539 
00540 /** \brief  Set Base Priority
00541 
00542     This function assigns the given value to the Base Priority register.
00543 
00544     \param [in]    basePri  Base Priority value to set
00545  */
00546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
00547 {
00548   __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
00549 }
00550 
00551 
00552 /** \brief  Set Base Priority with condition
00553 
00554     This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
00555     or the new value increases the BASEPRI priority level.
00556 
00557     \param [in]    basePri  Base Priority value to set
00558  */
00559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
00560 {
00561   __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
00562 }
00563 
00564 
00565 /** \brief  Get Fault Mask
00566 
00567     This function returns the current value of the Fault Mask register.
00568 
00569     \return               Fault Mask register value
00570  */
00571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
00572 {
00573   uint32_t result;
00574 
00575   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
00576   return(result);
00577 }
00578 
00579 
00580 /** \brief  Set Fault Mask
00581 
00582     This function assigns the given value to the Fault Mask register.
00583 
00584     \param [in]    faultMask  Fault Mask value to set
00585  */
00586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
00587 {
00588   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
00589 }
00590 
00591 #endif /* (__CORTEX_M >= 0x03) */
00592 
00593 
00594 #if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
00595 
00596 /** \brief  Get FPSCR
00597 
00598     This function returns the current value of the Floating Point Status/Control register.
00599 
00600     \return               Floating Point Status/Control register value
00601  */
00602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
00603 {
00604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00605   uint32_t result;
00606 
00607   /* Empty asm statement works as a scheduling barrier */
00608   __ASM volatile ("");
00609   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
00610   __ASM volatile ("");
00611   return(result);
00612 #else
00613    return(0);
00614 #endif
00615 }
00616 
00617 
00618 /** \brief  Set FPSCR
00619 
00620     This function assigns the given value to the Floating Point Status/Control register.
00621 
00622     \param [in]    fpscr  Floating Point Status/Control value to set
00623  */
00624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
00625 {
00626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00627   /* Empty asm statement works as a scheduling barrier */
00628   __ASM volatile ("");
00629   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
00630   __ASM volatile ("");
00631 #endif
00632 }
00633 
00634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
00635 
00636 
00637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
00638 /* IAR iccarm specific functions */
00639 #include <cmsis_iar.h>
00640 
00641 
00642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
00643 /* TI CCS specific functions */
00644 #include <cmsis_ccs.h>
00645 
00646 
00647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
00648 /* TASKING carm specific functions */
00649 /*
00650  * The CMSIS functions have been implemented as intrinsics in the compiler.
00651  * Please use "carm -?i" to get an up to date list of all intrinsics,
00652  * Including the CMSIS ones.
00653  */
00654 
00655 
00656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
00657 /* Cosmic specific functions */
00658 #include <cmsis_csm.h>
00659 
00660 #endif
00661 
00662 /*@} end of CMSIS_Core_RegAccFunctions */
00663 
00664 #endif /* __CORE_CMFUNC_H */