Vipin Ranka
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core_cm7.h
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00001 /**************************************************************************//** 00002 * @file core_cm7.h 00003 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 00004 * @version V4.10 00005 * @date 18. March 2015 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2015 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM7_H_GENERIC 00043 #define __CORE_CM7_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M7 00067 @{ 00068 */ 00069 00070 /* CMSIS CM7 definitions */ 00071 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x07) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00113 */ 00114 #if defined ( __CC_ARM ) 00115 #if defined __TARGET_FPU_VFP 00116 #if (__FPU_PRESENT == 1) 00117 #define __FPU_USED 1 00118 #else 00119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00120 #define __FPU_USED 0 00121 #endif 00122 #else 00123 #define __FPU_USED 0 00124 #endif 00125 00126 #elif defined ( __GNUC__ ) 00127 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00128 #if (__FPU_PRESENT == 1) 00129 #define __FPU_USED 1 00130 #else 00131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00132 #define __FPU_USED 0 00133 #endif 00134 #else 00135 #define __FPU_USED 0 00136 #endif 00137 00138 #elif defined ( __ICCARM__ ) 00139 #if defined __ARMVFP__ 00140 #if (__FPU_PRESENT == 1) 00141 #define __FPU_USED 1 00142 #else 00143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #define __FPU_USED 0 00145 #endif 00146 #else 00147 #define __FPU_USED 0 00148 #endif 00149 00150 #elif defined ( __TMS470__ ) 00151 #if defined __TI_VFP_SUPPORT__ 00152 #if (__FPU_PRESENT == 1) 00153 #define __FPU_USED 1 00154 #else 00155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00156 #define __FPU_USED 0 00157 #endif 00158 #else 00159 #define __FPU_USED 0 00160 #endif 00161 00162 #elif defined ( __TASKING__ ) 00163 #if defined __FPU_VFP__ 00164 #if (__FPU_PRESENT == 1) 00165 #define __FPU_USED 1 00166 #else 00167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00168 #define __FPU_USED 0 00169 #endif 00170 #else 00171 #define __FPU_USED 0 00172 #endif 00173 00174 #elif defined ( __CSMC__ ) /* Cosmic */ 00175 #if ( __CSMC__ & 0x400) // FPU present for parser 00176 #if (__FPU_PRESENT == 1) 00177 #define __FPU_USED 1 00178 #else 00179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00180 #define __FPU_USED 0 00181 #endif 00182 #else 00183 #define __FPU_USED 0 00184 #endif 00185 #endif 00186 00187 #include <stdint.h> /* standard types definitions */ 00188 #include <core_cmInstr.h> /* Core Instruction Access */ 00189 #include <core_cmFunc.h> /* Core Function Access */ 00190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ 00191 00192 #ifdef __cplusplus 00193 } 00194 #endif 00195 00196 #endif /* __CORE_CM7_H_GENERIC */ 00197 00198 #ifndef __CMSIS_GENERIC 00199 00200 #ifndef __CORE_CM7_H_DEPENDANT 00201 #define __CORE_CM7_H_DEPENDANT 00202 00203 #ifdef __cplusplus 00204 extern "C" { 00205 #endif 00206 00207 /* check device defines and use defaults */ 00208 #if defined __CHECK_DEVICE_DEFINES 00209 #ifndef __CM7_REV 00210 #define __CM7_REV 0x0000 00211 #warning "__CM7_REV not defined in device header file; using default!" 00212 #endif 00213 00214 #ifndef __FPU_PRESENT 00215 #define __FPU_PRESENT 0 00216 #warning "__FPU_PRESENT not defined in device header file; using default!" 00217 #endif 00218 00219 #ifndef __MPU_PRESENT 00220 #define __MPU_PRESENT 0 00221 #warning "__MPU_PRESENT not defined in device header file; using default!" 00222 #endif 00223 00224 #ifndef __ICACHE_PRESENT 00225 #define __ICACHE_PRESENT 0 00226 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 00227 #endif 00228 00229 #ifndef __DCACHE_PRESENT 00230 #define __DCACHE_PRESENT 0 00231 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 00232 #endif 00233 00234 #ifndef __DTCM_PRESENT 00235 #define __DTCM_PRESENT 0 00236 #warning "__DTCM_PRESENT not defined in device header file; using default!" 00237 #endif 00238 00239 #ifndef __NVIC_PRIO_BITS 00240 #define __NVIC_PRIO_BITS 3 00241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00242 #endif 00243 00244 #ifndef __Vendor_SysTickConfig 00245 #define __Vendor_SysTickConfig 0 00246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00247 #endif 00248 #endif 00249 00250 /* IO definitions (access restrictions to peripheral registers) */ 00251 /** 00252 \defgroup CMSIS_glob_defs CMSIS Global Defines 00253 00254 <strong>IO Type Qualifiers</strong> are used 00255 \li to specify the access to peripheral variables. 00256 \li for automatic generation of peripheral register debug information. 00257 */ 00258 #ifdef __cplusplus 00259 #define __I volatile /*!< Defines 'read only' permissions */ 00260 #else 00261 #define __I volatile const /*!< Defines 'read only' permissions */ 00262 #endif 00263 #define __O volatile /*!< Defines 'write only' permissions */ 00264 #define __IO volatile /*!< Defines 'read / write' permissions */ 00265 00266 #ifdef __cplusplus 00267 #define __IM volatile /*!< Defines 'read only' permissions */ 00268 #else 00269 #define __IM volatile const /*!< Defines 'read only' permissions */ 00270 #endif 00271 #define __OM volatile /*!< Defines 'write only' permissions */ 00272 #define __IOM volatile /*!< Defines 'read / write' permissions */ 00273 00274 /*@} end of group Cortex_M7 */ 00275 00276 00277 00278 /******************************************************************************* 00279 * Register Abstraction 00280 Core Register contain: 00281 - Core Register 00282 - Core NVIC Register 00283 - Core SCB Register 00284 - Core SysTick Register 00285 - Core Debug Register 00286 - Core MPU Register 00287 - Core FPU Register 00288 ******************************************************************************/ 00289 /** \defgroup CMSIS_core_register Defines and Type Definitions 00290 \brief Type definitions and defines for Cortex-M processor based devices. 00291 */ 00292 00293 /** \ingroup CMSIS_core_register 00294 \defgroup CMSIS_CORE Status and Control Registers 00295 \brief Core Register type definitions. 00296 @{ 00297 */ 00298 00299 /** \brief Union type to access the Application Program Status Register (APSR). 00300 */ 00301 typedef union 00302 { 00303 struct 00304 { 00305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00313 } b; /*!< Structure used for bit access */ 00314 uint32_t w; /*!< Type used for word access */ 00315 } APSR_Type; 00316 00317 /* APSR Register Definitions */ 00318 #define APSR_N_Pos 31 /*!< APSR: N Position */ 00319 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00320 00321 #define APSR_Z_Pos 30 /*!< APSR: Z Position */ 00322 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00323 00324 #define APSR_C_Pos 29 /*!< APSR: C Position */ 00325 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00326 00327 #define APSR_V_Pos 28 /*!< APSR: V Position */ 00328 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00329 00330 #define APSR_Q_Pos 27 /*!< APSR: Q Position */ 00331 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00332 00333 #define APSR_GE_Pos 16 /*!< APSR: GE Position */ 00334 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00335 00336 00337 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00338 */ 00339 typedef union 00340 { 00341 struct 00342 { 00343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00345 } b; /*!< Structure used for bit access */ 00346 uint32_t w; /*!< Type used for word access */ 00347 } IPSR_Type; 00348 00349 /* IPSR Register Definitions */ 00350 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ 00351 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00352 00353 00354 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00355 */ 00356 typedef union 00357 { 00358 struct 00359 { 00360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00371 } b; /*!< Structure used for bit access */ 00372 uint32_t w; /*!< Type used for word access */ 00373 } xPSR_Type; 00374 00375 /* xPSR Register Definitions */ 00376 #define xPSR_N_Pos 31 /*!< xPSR: N Position */ 00377 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00378 00379 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ 00380 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00381 00382 #define xPSR_C_Pos 29 /*!< xPSR: C Position */ 00383 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00384 00385 #define xPSR_V_Pos 28 /*!< xPSR: V Position */ 00386 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00387 00388 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ 00389 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00390 00391 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ 00392 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 00393 00394 #define xPSR_T_Pos 24 /*!< xPSR: T Position */ 00395 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00396 00397 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ 00398 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00399 00400 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ 00401 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00402 00403 00404 /** \brief Union type to access the Control Registers (CONTROL). 00405 */ 00406 typedef union 00407 { 00408 struct 00409 { 00410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00414 } b; /*!< Structure used for bit access */ 00415 uint32_t w; /*!< Type used for word access */ 00416 } CONTROL_Type; 00417 00418 /* CONTROL Register Definitions */ 00419 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ 00420 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00421 00422 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ 00423 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00424 00425 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ 00426 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00427 00428 /*@} end of group CMSIS_CORE */ 00429 00430 00431 /** \ingroup CMSIS_core_register 00432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00433 \brief Type definitions for the NVIC Registers 00434 @{ 00435 */ 00436 00437 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00438 */ 00439 typedef struct 00440 { 00441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00442 uint32_t RESERVED0[24]; 00443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00444 uint32_t RSERVED1[24]; 00445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00446 uint32_t RESERVED2[24]; 00447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00448 uint32_t RESERVED3[24]; 00449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00450 uint32_t RESERVED4[56]; 00451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00452 uint32_t RESERVED5[644]; 00453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00454 } NVIC_Type; 00455 00456 /* Software Triggered Interrupt Register Definitions */ 00457 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 00458 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00459 00460 /*@} end of group CMSIS_NVIC */ 00461 00462 00463 /** \ingroup CMSIS_core_register 00464 \defgroup CMSIS_SCB System Control Block (SCB) 00465 \brief Type definitions for the System Control Block Registers 00466 @{ 00467 */ 00468 00469 /** \brief Structure type to access the System Control Block (SCB). 00470 */ 00471 typedef struct 00472 { 00473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00492 uint32_t RESERVED0[1]; 00493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00498 uint32_t RESERVED3[93]; 00499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00500 uint32_t RESERVED4[15]; 00501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ 00504 uint32_t RESERVED5[1]; 00505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00506 uint32_t RESERVED6[1]; 00507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00515 uint32_t RESERVED7[6]; 00516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 00517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 00518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 00519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 00520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 00521 uint32_t RESERVED8[1]; 00522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 00523 } SCB_Type; 00524 00525 /* SCB CPUID Register Definitions */ 00526 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00527 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00528 00529 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00530 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00531 00532 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00533 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00534 00535 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00536 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00537 00538 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00539 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00540 00541 /* SCB Interrupt Control State Register Definitions */ 00542 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00543 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00544 00545 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00546 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00547 00548 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00549 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00550 00551 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00552 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00553 00554 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00555 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00556 00557 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00558 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00559 00560 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00561 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00562 00563 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00564 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00565 00566 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 00567 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00568 00569 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00570 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00571 00572 /* SCB Vector Table Offset Register Definitions */ 00573 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00574 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00575 00576 /* SCB Application Interrupt and Reset Control Register Definitions */ 00577 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00578 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00579 00580 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00581 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00582 00583 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00584 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00585 00586 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 00587 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00588 00589 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00590 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00591 00592 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00593 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00594 00595 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 00596 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00597 00598 /* SCB System Control Register Definitions */ 00599 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00600 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00601 00602 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00603 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00604 00605 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00606 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00607 00608 /* SCB Configuration Control Register Definitions */ 00609 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ 00610 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 00611 00612 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ 00613 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 00614 00615 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ 00616 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 00617 00618 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00619 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00620 00621 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 00622 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00623 00624 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 00625 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00626 00627 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00628 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00629 00630 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 00631 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00632 00633 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 00634 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00635 00636 /* SCB System Handler Control and State Register Definitions */ 00637 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 00638 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00639 00640 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 00641 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00642 00643 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 00644 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00645 00646 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00647 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00648 00649 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00650 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00651 00652 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00653 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00654 00655 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 00656 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00657 00658 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 00659 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00660 00661 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 00662 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00663 00664 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 00665 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00666 00667 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 00668 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00669 00670 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 00671 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00672 00673 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 00674 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00675 00676 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 00677 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00678 00679 /* SCB Configurable Fault Status Registers Definitions */ 00680 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 00681 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00682 00683 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 00684 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00685 00686 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00687 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00688 00689 /* SCB Hard Fault Status Registers Definitions */ 00690 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 00691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00692 00693 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 00694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00695 00696 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 00697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00698 00699 /* SCB Debug Fault Status Register Definitions */ 00700 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 00701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00702 00703 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 00704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00705 00706 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 00707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00708 00709 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 00710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00711 00712 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 00713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00714 00715 /* Cache Level ID register */ 00716 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ 00717 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00718 00719 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ 00720 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ 00721 00722 /* Cache Type register */ 00723 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ 00724 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00725 00726 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ 00727 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00728 00729 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ 00730 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00731 00732 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ 00733 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00734 00735 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ 00736 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00737 00738 /* Cache Size ID Register */ 00739 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ 00740 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00741 00742 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ 00743 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00744 00745 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ 00746 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00747 00748 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ 00749 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00750 00751 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ 00752 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00753 00754 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ 00755 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00756 00757 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ 00758 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00759 00760 /* Cache Size Selection Register */ 00761 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ 00762 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00763 00764 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ 00765 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00766 00767 /* SCB Software Triggered Interrupt Register */ 00768 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ 00769 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00770 00771 /* Instruction Tightly-Coupled Memory Control Register*/ 00772 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ 00773 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 00774 00775 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ 00776 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 00777 00778 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ 00779 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 00780 00781 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ 00782 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 00783 00784 /* Data Tightly-Coupled Memory Control Registers */ 00785 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ 00786 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 00787 00788 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ 00789 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 00790 00791 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ 00792 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 00793 00794 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ 00795 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 00796 00797 /* AHBP Control Register */ 00798 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ 00799 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 00800 00801 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ 00802 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 00803 00804 /* L1 Cache Control Register */ 00805 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ 00806 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 00807 00808 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ 00809 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 00810 00811 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ 00812 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 00813 00814 /* AHBS control register */ 00815 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ 00816 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 00817 00818 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ 00819 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 00820 00821 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ 00822 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 00823 00824 /* Auxiliary Bus Fault Status Register */ 00825 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ 00826 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 00827 00828 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ 00829 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 00830 00831 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ 00832 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 00833 00834 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ 00835 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 00836 00837 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ 00838 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 00839 00840 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ 00841 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 00842 00843 /*@} end of group CMSIS_SCB */ 00844 00845 00846 /** \ingroup CMSIS_core_register 00847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00848 \brief Type definitions for the System Control and ID Register not in the SCB 00849 @{ 00850 */ 00851 00852 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00853 */ 00854 typedef struct 00855 { 00856 uint32_t RESERVED0[1]; 00857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00859 } SCnSCB_Type; 00860 00861 /* Interrupt Controller Type Register Definitions */ 00862 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 00863 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00864 00865 /* Auxiliary Control Register Definitions */ 00866 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ 00867 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 00868 00869 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ 00870 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 00871 00872 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ 00873 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 00874 00875 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 00876 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00877 00878 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00879 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00880 00881 /*@} end of group CMSIS_SCnotSCB */ 00882 00883 00884 /** \ingroup CMSIS_core_register 00885 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00886 \brief Type definitions for the System Timer Registers. 00887 @{ 00888 */ 00889 00890 /** \brief Structure type to access the System Timer (SysTick). 00891 */ 00892 typedef struct 00893 { 00894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00898 } SysTick_Type; 00899 00900 /* SysTick Control / Status Register Definitions */ 00901 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00902 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00903 00904 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00905 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00906 00907 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00908 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00909 00910 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00911 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00912 00913 /* SysTick Reload Register Definitions */ 00914 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00915 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00916 00917 /* SysTick Current Register Definitions */ 00918 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00919 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00920 00921 /* SysTick Calibration Register Definitions */ 00922 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00923 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00924 00925 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00926 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00927 00928 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00929 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00930 00931 /*@} end of group CMSIS_SysTick */ 00932 00933 00934 /** \ingroup CMSIS_core_register 00935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00937 @{ 00938 */ 00939 00940 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00941 */ 00942 typedef struct 00943 { 00944 __O union 00945 { 00946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00950 uint32_t RESERVED0[864]; 00951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00952 uint32_t RESERVED1[15]; 00953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00954 uint32_t RESERVED2[15]; 00955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00956 uint32_t RESERVED3[29]; 00957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00960 uint32_t RESERVED4[43]; 00961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00963 uint32_t RESERVED5[6]; 00964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00976 } ITM_Type; 00977 00978 /* ITM Trace Privilege Register Definitions */ 00979 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 00980 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00981 00982 /* ITM Trace Control Register Definitions */ 00983 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 00984 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00985 00986 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 00987 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00988 00989 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 00990 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00991 00992 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 00993 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00994 00995 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 00996 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00997 00998 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 00999 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01000 01001 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 01002 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01003 01004 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 01005 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01006 01007 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 01008 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01009 01010 /* ITM Integration Write Register Definitions */ 01011 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 01012 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 01013 01014 /* ITM Integration Read Register Definitions */ 01015 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 01016 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 01017 01018 /* ITM Integration Mode Control Register Definitions */ 01019 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 01020 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 01021 01022 /* ITM Lock Status Register Definitions */ 01023 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 01024 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01025 01026 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 01027 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01028 01029 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 01030 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01031 01032 /*@}*/ /* end of group CMSIS_ITM */ 01033 01034 01035 /** \ingroup CMSIS_core_register 01036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01037 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01038 @{ 01039 */ 01040 01041 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01042 */ 01043 typedef struct 01044 { 01045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 01055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01056 uint32_t RESERVED0[1]; 01057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 01059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01060 uint32_t RESERVED1[1]; 01061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 01063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01064 uint32_t RESERVED2[1]; 01065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 01067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01068 uint32_t RESERVED3[981]; 01069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 01070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01071 } DWT_Type; 01072 01073 /* DWT Control Register Definitions */ 01074 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 01075 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01076 01077 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 01078 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01079 01080 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 01081 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01082 01083 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 01084 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01085 01086 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 01087 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01088 01089 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 01090 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01091 01092 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 01093 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01094 01095 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 01096 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01097 01098 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 01099 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01100 01101 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 01102 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01103 01104 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 01105 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01106 01107 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 01108 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01109 01110 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 01111 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01112 01113 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 01114 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01115 01116 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 01117 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01118 01119 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 01120 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01121 01122 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 01123 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01124 01125 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 01126 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01127 01128 /* DWT CPI Count Register Definitions */ 01129 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 01130 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01131 01132 /* DWT Exception Overhead Count Register Definitions */ 01133 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 01134 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01135 01136 /* DWT Sleep Count Register Definitions */ 01137 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01138 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01139 01140 /* DWT LSU Count Register Definitions */ 01141 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 01142 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01143 01144 /* DWT Folded-instruction Count Register Definitions */ 01145 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 01146 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01147 01148 /* DWT Comparator Mask Register Definitions */ 01149 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 01150 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 01151 01152 /* DWT Comparator Function Register Definitions */ 01153 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 01154 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01155 01156 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 01157 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01158 01159 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 01160 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01161 01162 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 01163 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01164 01165 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 01166 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01167 01168 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 01169 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01170 01171 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 01172 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01173 01174 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 01175 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01176 01177 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 01178 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 01179 01180 /*@}*/ /* end of group CMSIS_DWT */ 01181 01182 01183 /** \ingroup CMSIS_core_register 01184 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01185 \brief Type definitions for the Trace Port Interface (TPI) 01186 @{ 01187 */ 01188 01189 /** \brief Structure type to access the Trace Port Interface Register (TPI). 01190 */ 01191 typedef struct 01192 { 01193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01195 uint32_t RESERVED0[2]; 01196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01197 uint32_t RESERVED1[55]; 01198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01199 uint32_t RESERVED2[131]; 01200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01203 uint32_t RESERVED3[759]; 01204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01207 uint32_t RESERVED4[1]; 01208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01211 uint32_t RESERVED5[39]; 01212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01214 uint32_t RESERVED7[8]; 01215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01217 } TPI_Type; 01218 01219 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01220 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 01221 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01222 01223 /* TPI Selected Pin Protocol Register Definitions */ 01224 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 01225 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01226 01227 /* TPI Formatter and Flush Status Register Definitions */ 01228 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 01229 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01230 01231 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 01232 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01233 01234 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 01235 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01236 01237 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 01238 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01239 01240 /* TPI Formatter and Flush Control Register Definitions */ 01241 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 01242 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01243 01244 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 01245 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01246 01247 /* TPI TRIGGER Register Definitions */ 01248 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 01249 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01250 01251 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01252 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 01253 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01254 01255 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 01256 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01257 01258 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 01259 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01260 01261 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 01262 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01263 01264 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 01265 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01266 01267 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 01268 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01269 01270 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 01271 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01272 01273 /* TPI ITATBCTR2 Register Definitions */ 01274 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 01275 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01276 01277 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01278 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 01279 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01280 01281 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 01282 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01283 01284 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 01285 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01286 01287 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 01288 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01289 01290 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 01291 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01292 01293 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 01294 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01295 01296 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 01297 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01298 01299 /* TPI ITATBCTR0 Register Definitions */ 01300 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 01301 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01302 01303 /* TPI Integration Mode Control Register Definitions */ 01304 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 01305 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01306 01307 /* TPI DEVID Register Definitions */ 01308 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 01309 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01310 01311 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 01312 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01313 01314 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 01315 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01316 01317 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 01318 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01319 01320 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 01321 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01322 01323 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 01324 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01325 01326 /* TPI DEVTYPE Register Definitions */ 01327 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 01328 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01329 01330 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 01331 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01332 01333 /*@}*/ /* end of group CMSIS_TPI */ 01334 01335 01336 #if (__MPU_PRESENT == 1) 01337 /** \ingroup CMSIS_core_register 01338 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01339 \brief Type definitions for the Memory Protection Unit (MPU) 01340 @{ 01341 */ 01342 01343 /** \brief Structure type to access the Memory Protection Unit (MPU). 01344 */ 01345 typedef struct 01346 { 01347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01358 } MPU_Type; 01359 01360 /* MPU Type Register */ 01361 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 01362 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01363 01364 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 01365 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01366 01367 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 01368 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01369 01370 /* MPU Control Register */ 01371 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 01372 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01373 01374 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 01375 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01376 01377 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 01378 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01379 01380 /* MPU Region Number Register */ 01381 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 01382 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01383 01384 /* MPU Region Base Address Register */ 01385 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 01386 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01387 01388 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 01389 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01390 01391 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 01392 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01393 01394 /* MPU Region Attribute and Size Register */ 01395 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 01396 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01397 01398 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 01399 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01400 01401 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 01402 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01403 01404 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 01405 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01406 01407 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 01408 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01409 01410 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 01411 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01412 01413 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 01414 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01415 01416 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 01417 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01418 01419 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 01420 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01421 01422 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 01423 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01424 01425 /*@} end of group CMSIS_MPU */ 01426 #endif 01427 01428 01429 #if (__FPU_PRESENT == 1) 01430 /** \ingroup CMSIS_core_register 01431 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01432 \brief Type definitions for the Floating Point Unit (FPU) 01433 @{ 01434 */ 01435 01436 /** \brief Structure type to access the Floating Point Unit (FPU). 01437 */ 01438 typedef struct 01439 { 01440 uint32_t RESERVED0[1]; 01441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01447 } FPU_Type; 01448 01449 /* Floating-Point Context Control Register */ 01450 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ 01451 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01452 01453 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ 01454 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01455 01456 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ 01457 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01458 01459 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ 01460 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01461 01462 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ 01463 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01464 01465 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ 01466 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01467 01468 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ 01469 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01470 01471 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ 01472 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01473 01474 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ 01475 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01476 01477 /* Floating-Point Context Address Register */ 01478 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ 01479 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01480 01481 /* Floating-Point Default Status Control Register */ 01482 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ 01483 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01484 01485 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ 01486 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01487 01488 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ 01489 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01490 01491 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ 01492 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01493 01494 /* Media and FP Feature Register 0 */ 01495 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ 01496 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01497 01498 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ 01499 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01500 01501 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ 01502 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01503 01504 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ 01505 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01506 01507 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ 01508 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01509 01510 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ 01511 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01512 01513 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ 01514 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01515 01516 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ 01517 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01518 01519 /* Media and FP Feature Register 1 */ 01520 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ 01521 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01522 01523 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ 01524 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01525 01526 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ 01527 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01528 01529 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ 01530 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01531 01532 /* Media and FP Feature Register 2 */ 01533 01534 /*@} end of group CMSIS_FPU */ 01535 #endif 01536 01537 01538 /** \ingroup CMSIS_core_register 01539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01540 \brief Type definitions for the Core Debug Registers 01541 @{ 01542 */ 01543 01544 /** \brief Structure type to access the Core Debug Register (CoreDebug). 01545 */ 01546 typedef struct 01547 { 01548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01552 } CoreDebug_Type; 01553 01554 /* Debug Halting Control and Status Register */ 01555 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 01556 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01557 01558 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01559 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01560 01561 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01562 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01563 01564 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01565 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01566 01567 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 01568 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01569 01570 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 01571 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01572 01573 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 01574 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01575 01576 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01577 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01578 01579 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01580 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01581 01582 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 01583 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01584 01585 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 01586 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01587 01588 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01589 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01590 01591 /* Debug Core Register Selector Register */ 01592 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 01593 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01594 01595 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 01596 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01597 01598 /* Debug Exception and Monitor Control Register */ 01599 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 01600 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01601 01602 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 01603 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01604 01605 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 01606 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01607 01608 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 01609 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01610 01611 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 01612 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01613 01614 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01615 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01616 01617 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 01618 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01619 01620 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01621 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01622 01623 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 01624 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01625 01626 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01627 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01628 01629 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01630 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01631 01632 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 01633 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01634 01635 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01636 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01637 01638 /*@} end of group CMSIS_CoreDebug */ 01639 01640 01641 /** \ingroup CMSIS_core_register 01642 \defgroup CMSIS_core_base Core Definitions 01643 \brief Definitions for base addresses, unions, and structures. 01644 @{ 01645 */ 01646 01647 /* Memory mapping of Cortex-M4 Hardware */ 01648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01649 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01650 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01651 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01652 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01653 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01654 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01655 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01656 01657 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01661 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01662 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01663 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01664 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01665 01666 #if (__MPU_PRESENT == 1) 01667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01669 #endif 01670 01671 #if (__FPU_PRESENT == 1) 01672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01674 #endif 01675 01676 /*@} */ 01677 01678 01679 01680 /******************************************************************************* 01681 * Hardware Abstraction Layer 01682 Core Function Interface contains: 01683 - Core NVIC Functions 01684 - Core SysTick Functions 01685 - Core Debug Functions 01686 - Core Register Access Functions 01687 ******************************************************************************/ 01688 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01689 */ 01690 01691 01692 01693 /* ########################## NVIC functions #################################### */ 01694 /** \ingroup CMSIS_Core_FunctionInterface 01695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01696 \brief Functions that manage interrupts and exceptions via the NVIC. 01697 @{ 01698 */ 01699 01700 /** \brief Set Priority Grouping 01701 01702 The function sets the priority grouping field using the required unlock sequence. 01703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01704 Only values from 0..7 are used. 01705 In case of a conflict between priority grouping and available 01706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01707 01708 \param [in] PriorityGroup Priority grouping field. 01709 */ 01710 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01711 { 01712 uint32_t reg_value; 01713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01714 01715 reg_value = SCB->AIRCR; /* read old register configuration */ 01716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01717 reg_value = (reg_value | 01718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ 01720 SCB->AIRCR = reg_value; 01721 } 01722 01723 01724 /** \brief Get Priority Grouping 01725 01726 The function reads the priority grouping field from the NVIC Interrupt Controller. 01727 01728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01729 */ 01730 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01731 { 01732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01733 } 01734 01735 01736 /** \brief Enable External Interrupt 01737 01738 The function enables a device-specific interrupt in the NVIC interrupt controller. 01739 01740 \param [in] IRQn External interrupt number. Value cannot be negative. 01741 */ 01742 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01743 { 01744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01745 } 01746 01747 01748 /** \brief Disable External Interrupt 01749 01750 The function disables a device-specific interrupt in the NVIC interrupt controller. 01751 01752 \param [in] IRQn External interrupt number. Value cannot be negative. 01753 */ 01754 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01755 { 01756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01757 __DSB(); 01758 __ISB(); 01759 } 01760 01761 01762 /** \brief Get Pending Interrupt 01763 01764 The function reads the pending register in the NVIC and returns the pending bit 01765 for the specified interrupt. 01766 01767 \param [in] IRQn Interrupt number. 01768 01769 \return 0 Interrupt status is not pending. 01770 \return 1 Interrupt status is pending. 01771 */ 01772 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01773 { 01774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01775 } 01776 01777 01778 /** \brief Set Pending Interrupt 01779 01780 The function sets the pending bit of an external interrupt. 01781 01782 \param [in] IRQn Interrupt number. Value cannot be negative. 01783 */ 01784 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01785 { 01786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01787 } 01788 01789 01790 /** \brief Clear Pending Interrupt 01791 01792 The function clears the pending bit of an external interrupt. 01793 01794 \param [in] IRQn External interrupt number. Value cannot be negative. 01795 */ 01796 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01797 { 01798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01799 } 01800 01801 01802 /** \brief Get Active Interrupt 01803 01804 The function reads the active register in NVIC and returns the active bit. 01805 01806 \param [in] IRQn Interrupt number. 01807 01808 \return 0 Interrupt status is not active. 01809 \return 1 Interrupt status is active. 01810 */ 01811 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01812 { 01813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01814 } 01815 01816 01817 /** \brief Set Interrupt Priority 01818 01819 The function sets the priority of an interrupt. 01820 01821 \note The priority cannot be set for every core interrupt. 01822 01823 \param [in] IRQn Interrupt number. 01824 \param [in] priority Priority to set. 01825 */ 01826 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01827 { 01828 if((int32_t)IRQn < 0) { 01829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01830 } 01831 else { 01832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01833 } 01834 } 01835 01836 01837 /** \brief Get Interrupt Priority 01838 01839 The function reads the priority of an interrupt. The interrupt 01840 number can be positive to specify an external (device specific) 01841 interrupt, or negative to specify an internal (core) interrupt. 01842 01843 01844 \param [in] IRQn Interrupt number. 01845 \return Interrupt Priority. Value is aligned automatically to the implemented 01846 priority bits of the microcontroller. 01847 */ 01848 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01849 { 01850 01851 if((int32_t)IRQn < 0) { 01852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); 01853 } 01854 else { 01855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); 01856 } 01857 } 01858 01859 01860 /** \brief Encode Priority 01861 01862 The function encodes the priority for an interrupt with the given priority group, 01863 preemptive priority value, and subpriority value. 01864 In case of a conflict between priority grouping and available 01865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01866 01867 \param [in] PriorityGroup Used priority group. 01868 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01869 \param [in] SubPriority Subpriority value (starting from 0). 01870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01871 */ 01872 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01873 { 01874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01875 uint32_t PreemptPriorityBits; 01876 uint32_t SubPriorityBits; 01877 01878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01880 01881 return ( 01882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01884 ); 01885 } 01886 01887 01888 /** \brief Decode Priority 01889 01890 The function decodes an interrupt priority value with a given priority group to 01891 preemptive priority value and subpriority value. 01892 In case of a conflict between priority grouping and available 01893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01894 01895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01896 \param [in] PriorityGroup Used priority group. 01897 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01898 \param [out] pSubPriority Subpriority value (starting from 0). 01899 */ 01900 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01901 { 01902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01903 uint32_t PreemptPriorityBits; 01904 uint32_t SubPriorityBits; 01905 01906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01908 01909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01911 } 01912 01913 01914 /** \brief System Reset 01915 01916 The function initiates a system reset request to reset the MCU. 01917 */ 01918 __STATIC_INLINE void NVIC_SystemReset(void) 01919 { 01920 __DSB(); /* Ensure all outstanding memory accesses included 01921 buffered write are completed before reset */ 01922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01925 __DSB(); /* Ensure completion of memory access */ 01926 while(1) { __NOP(); } /* wait until reset */ 01927 } 01928 01929 /*@} end of CMSIS_Core_NVICFunctions */ 01930 01931 01932 /* ########################## FPU functions #################################### */ 01933 /** \ingroup CMSIS_Core_FunctionInterface 01934 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01935 \brief Function that provides FPU type. 01936 @{ 01937 */ 01938 01939 /** 01940 \fn uint32_t SCB_GetFPUType(void) 01941 \brief get FPU type 01942 \returns 01943 - \b 0: No FPU 01944 - \b 1: Single precision FPU 01945 - \b 2: Double + Single precision FPU 01946 */ 01947 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01948 { 01949 uint32_t mvfr0; 01950 01951 mvfr0 = SCB->MVFR0; 01952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { 01953 return 2UL; // Double + Single precision FPU 01954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { 01955 return 1UL; // Single precision FPU 01956 } else { 01957 return 0UL; // No FPU 01958 } 01959 } 01960 01961 01962 /*@} end of CMSIS_Core_FpuFunctions */ 01963 01964 01965 01966 /* ########################## Cache functions #################################### */ 01967 /** \ingroup CMSIS_Core_FunctionInterface 01968 \defgroup CMSIS_Core_CacheFunctions Cache Functions 01969 \brief Functions that configure Instruction and Data cache. 01970 @{ 01971 */ 01972 01973 /* Cache Size ID Register Macros */ 01974 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 01975 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 01976 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) 01977 01978 01979 /** \brief Enable I-Cache 01980 01981 The function turns on I-Cache 01982 */ 01983 __STATIC_INLINE void SCB_EnableICache (void) 01984 { 01985 #if (__ICACHE_PRESENT == 1) 01986 __DSB(); 01987 __ISB(); 01988 SCB->ICIALLU = 0UL; // invalidate I-Cache 01989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache 01990 __DSB(); 01991 __ISB(); 01992 #endif 01993 } 01994 01995 01996 /** \brief Disable I-Cache 01997 01998 The function turns off I-Cache 01999 */ 02000 __STATIC_INLINE void SCB_DisableICache (void) 02001 { 02002 #if (__ICACHE_PRESENT == 1) 02003 __DSB(); 02004 __ISB(); 02005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache 02006 SCB->ICIALLU = 0UL; // invalidate I-Cache 02007 __DSB(); 02008 __ISB(); 02009 #endif 02010 } 02011 02012 02013 /** \brief Invalidate I-Cache 02014 02015 The function invalidates I-Cache 02016 */ 02017 __STATIC_INLINE void SCB_InvalidateICache (void) 02018 { 02019 #if (__ICACHE_PRESENT == 1) 02020 __DSB(); 02021 __ISB(); 02022 SCB->ICIALLU = 0UL; 02023 __DSB(); 02024 __ISB(); 02025 #endif 02026 } 02027 02028 02029 /** \brief Enable D-Cache 02030 02031 The function turns on D-Cache 02032 */ 02033 __STATIC_INLINE void SCB_EnableDCache (void) 02034 { 02035 #if (__DCACHE_PRESENT == 1) 02036 uint32_t ccsidr, sshift, wshift, sw; 02037 uint32_t sets, ways; 02038 02039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache 02040 ccsidr = SCB->CCSIDR; 02041 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); 02043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); 02045 02046 __DSB(); 02047 02048 do { // invalidate D-Cache 02049 uint32_t tmpways = ways; 02050 do { 02051 sw = ((tmpways << wshift) | (sets << sshift)); 02052 SCB->DCISW = sw; 02053 } while(tmpways--); 02054 } while(sets--); 02055 __DSB(); 02056 02057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache 02058 02059 __DSB(); 02060 __ISB(); 02061 #endif 02062 } 02063 02064 02065 /** \brief Disable D-Cache 02066 02067 The function turns off D-Cache 02068 */ 02069 __STATIC_INLINE void SCB_DisableDCache (void) 02070 { 02071 #if (__DCACHE_PRESENT == 1) 02072 uint32_t ccsidr, sshift, wshift, sw; 02073 uint32_t sets, ways; 02074 02075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache 02076 ccsidr = SCB->CCSIDR; 02077 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); 02079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); 02081 02082 __DSB(); 02083 02084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache 02085 02086 do { // clean & invalidate D-Cache 02087 uint32_t tmpways = ways; 02088 do { 02089 sw = ((tmpways << wshift) | (sets << sshift)); 02090 SCB->DCCISW = sw; 02091 } while(tmpways--); 02092 } while(sets--); 02093 02094 02095 __DSB(); 02096 __ISB(); 02097 #endif 02098 } 02099 02100 02101 /** \brief Invalidate D-Cache 02102 02103 The function invalidates D-Cache 02104 */ 02105 __STATIC_INLINE void SCB_InvalidateDCache (void) 02106 { 02107 #if (__DCACHE_PRESENT == 1) 02108 uint32_t ccsidr, sshift, wshift, sw; 02109 uint32_t sets, ways; 02110 02111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache 02112 ccsidr = SCB->CCSIDR; 02113 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); 02115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); 02117 02118 __DSB(); 02119 02120 do { // invalidate D-Cache 02121 uint32_t tmpways = ways; 02122 do { 02123 sw = ((tmpways << wshift) | (sets << sshift)); 02124 SCB->DCISW = sw; 02125 } while(tmpways--); 02126 } while(sets--); 02127 02128 __DSB(); 02129 __ISB(); 02130 #endif 02131 } 02132 02133 02134 /** \brief Clean D-Cache 02135 02136 The function cleans D-Cache 02137 */ 02138 __STATIC_INLINE void SCB_CleanDCache (void) 02139 { 02140 #if (__DCACHE_PRESENT == 1) 02141 uint32_t ccsidr, sshift, wshift, sw; 02142 uint32_t sets, ways; 02143 02144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache 02145 ccsidr = SCB->CCSIDR; 02146 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); 02148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); 02150 02151 __DSB(); 02152 02153 do { // clean D-Cache 02154 uint32_t tmpways = ways; 02155 do { 02156 sw = ((tmpways << wshift) | (sets << sshift)); 02157 SCB->DCCSW = sw; 02158 } while(tmpways--); 02159 } while(sets--); 02160 02161 __DSB(); 02162 __ISB(); 02163 #endif 02164 } 02165 02166 02167 /** \brief Clean & Invalidate D-Cache 02168 02169 The function cleans and Invalidates D-Cache 02170 */ 02171 __STATIC_INLINE void SCB_CleanInvalidateDCache (void) 02172 { 02173 #if (__DCACHE_PRESENT == 1) 02174 uint32_t ccsidr, sshift, wshift, sw; 02175 uint32_t sets, ways; 02176 02177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache 02178 ccsidr = SCB->CCSIDR; 02179 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); 02181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); 02183 02184 __DSB(); 02185 02186 do { // clean & invalidate D-Cache 02187 uint32_t tmpways = ways; 02188 do { 02189 sw = ((tmpways << wshift) | (sets << sshift)); 02190 SCB->DCCISW = sw; 02191 } while(tmpways--); 02192 } while(sets--); 02193 02194 __DSB(); 02195 __ISB(); 02196 #endif 02197 } 02198 02199 02200 /** 02201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) 02202 \brief D-Cache Invalidate by address 02203 \param[in] addr address (aligned to 32-byte boundary) 02204 \param[in] dsize size of memory block (in number of bytes) 02205 */ 02206 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) 02207 { 02208 #if (__DCACHE_PRESENT == 1) 02209 int32_t op_size = dsize; 02210 uint32_t op_addr = (uint32_t)addr; 02211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) 02212 02213 __DSB(); 02214 02215 while (op_size > 0) { 02216 SCB->DCIMVAC = op_addr; 02217 op_addr += linesize; 02218 op_size -= (int32_t)linesize; 02219 } 02220 02221 __DSB(); 02222 __ISB(); 02223 #endif 02224 } 02225 02226 02227 /** 02228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) 02229 \brief D-Cache Clean by address 02230 \param[in] addr address (aligned to 32-byte boundary) 02231 \param[in] dsize size of memory block (in number of bytes) 02232 */ 02233 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) 02234 { 02235 #if (__DCACHE_PRESENT == 1) 02236 int32_t op_size = dsize; 02237 uint32_t op_addr = (uint32_t) addr; 02238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) 02239 02240 __DSB(); 02241 02242 while (op_size > 0) { 02243 SCB->DCCMVAC = op_addr; 02244 op_addr += linesize; 02245 op_size -= (int32_t)linesize; 02246 } 02247 02248 __DSB(); 02249 __ISB(); 02250 #endif 02251 } 02252 02253 02254 /** 02255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) 02256 \brief D-Cache Clean and Invalidate by address 02257 \param[in] addr address (aligned to 32-byte boundary) 02258 \param[in] dsize size of memory block (in number of bytes) 02259 */ 02260 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) 02261 { 02262 #if (__DCACHE_PRESENT == 1) 02263 int32_t op_size = dsize; 02264 uint32_t op_addr = (uint32_t) addr; 02265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) 02266 02267 __DSB(); 02268 02269 while (op_size > 0) { 02270 SCB->DCCIMVAC = op_addr; 02271 op_addr += linesize; 02272 op_size -= (int32_t)linesize; 02273 } 02274 02275 __DSB(); 02276 __ISB(); 02277 #endif 02278 } 02279 02280 02281 /*@} end of CMSIS_Core_CacheFunctions */ 02282 02283 02284 02285 /* ################################## SysTick function ############################################ */ 02286 /** \ingroup CMSIS_Core_FunctionInterface 02287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02288 \brief Functions that configure the System. 02289 @{ 02290 */ 02291 02292 #if (__Vendor_SysTickConfig == 0) 02293 02294 /** \brief System Tick Configuration 02295 02296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 02297 Counter is in free running mode to generate periodic interrupts. 02298 02299 \param [in] ticks Number of ticks between two interrupts. 02300 02301 \return 0 Function succeeded. 02302 \return 1 Function failed. 02303 02304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02306 must contain a vendor-specific implementation of this function. 02307 02308 */ 02309 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02310 { 02311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ 02312 02313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02317 SysTick_CTRL_TICKINT_Msk | 02318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02319 return (0UL); /* Function successful */ 02320 } 02321 02322 #endif 02323 02324 /*@} end of CMSIS_Core_SysTickFunctions */ 02325 02326 02327 02328 /* ##################################### Debug In/Output function ########################################### */ 02329 /** \ingroup CMSIS_Core_FunctionInterface 02330 \defgroup CMSIS_core_DebugFunctions ITM Functions 02331 \brief Functions that access the ITM debug interface. 02332 @{ 02333 */ 02334 02335 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02337 02338 02339 /** \brief ITM Send Character 02340 02341 The function transmits a character via the ITM channel 0, and 02342 \li Just returns when no debugger is connected that has booked the output. 02343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02344 02345 \param [in] ch Character to transmit. 02346 02347 \returns Character to transmit. 02348 */ 02349 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02350 { 02351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02353 { 02354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); } 02355 ITM->PORT[0].u8 = (uint8_t)ch; 02356 } 02357 return (ch); 02358 } 02359 02360 02361 /** \brief ITM Receive Character 02362 02363 The function inputs a character via the external variable \ref ITM_RxBuffer. 02364 02365 \return Received character. 02366 \return -1 No character pending. 02367 */ 02368 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 02369 int32_t ch = -1; /* no character available */ 02370 02371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 02372 ch = ITM_RxBuffer; 02373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02374 } 02375 02376 return (ch); 02377 } 02378 02379 02380 /** \brief ITM Check Character 02381 02382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02383 02384 \return 0 No character available. 02385 \return 1 Character available. 02386 */ 02387 __STATIC_INLINE int32_t ITM_CheckChar (void) { 02388 02389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 02390 return (0); /* no character available */ 02391 } else { 02392 return (1); /* character available */ 02393 } 02394 } 02395 02396 /*@} end of CMSIS_core_DebugFunctions */ 02397 02398 02399 02400 02401 #ifdef __cplusplus 02402 } 02403 #endif 02404 02405 #endif /* __CORE_CM7_H_DEPENDANT */ 02406 02407 #endif /* __CMSIS_GENERIC */
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