Vipin Ranka
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core_cm4.h
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00001 /**************************************************************************//** 00002 * @file core_cm4.h 00003 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 00004 * @version V4.10 00005 * @date 18. March 2015 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2015 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM4_H_GENERIC 00043 #define __CORE_CM4_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M4 00067 @{ 00068 */ 00069 00070 /* CMSIS CM4 definitions */ 00071 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x04) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00113 */ 00114 #if defined ( __CC_ARM ) 00115 #if defined __TARGET_FPU_VFP 00116 #if (__FPU_PRESENT == 1) 00117 #define __FPU_USED 1 00118 #else 00119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00120 #define __FPU_USED 0 00121 #endif 00122 #else 00123 #define __FPU_USED 0 00124 #endif 00125 00126 #elif defined ( __GNUC__ ) 00127 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00128 #if (__FPU_PRESENT == 1) 00129 #define __FPU_USED 1 00130 #else 00131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00132 #define __FPU_USED 0 00133 #endif 00134 #else 00135 #define __FPU_USED 0 00136 #endif 00137 00138 #elif defined ( __ICCARM__ ) 00139 #if defined __ARMVFP__ 00140 #if (__FPU_PRESENT == 1) 00141 #define __FPU_USED 1 00142 #else 00143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #define __FPU_USED 0 00145 #endif 00146 #else 00147 #define __FPU_USED 0 00148 #endif 00149 00150 #elif defined ( __TMS470__ ) 00151 #if defined __TI_VFP_SUPPORT__ 00152 #if (__FPU_PRESENT == 1) 00153 #define __FPU_USED 1 00154 #else 00155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00156 #define __FPU_USED 0 00157 #endif 00158 #else 00159 #define __FPU_USED 0 00160 #endif 00161 00162 #elif defined ( __TASKING__ ) 00163 #if defined __FPU_VFP__ 00164 #if (__FPU_PRESENT == 1) 00165 #define __FPU_USED 1 00166 #else 00167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00168 #define __FPU_USED 0 00169 #endif 00170 #else 00171 #define __FPU_USED 0 00172 #endif 00173 00174 #elif defined ( __CSMC__ ) /* Cosmic */ 00175 #if ( __CSMC__ & 0x400) // FPU present for parser 00176 #if (__FPU_PRESENT == 1) 00177 #define __FPU_USED 1 00178 #else 00179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00180 #define __FPU_USED 0 00181 #endif 00182 #else 00183 #define __FPU_USED 0 00184 #endif 00185 #endif 00186 00187 #include <stdint.h> /* standard types definitions */ 00188 #include <core_cmInstr.h> /* Core Instruction Access */ 00189 #include <core_cmFunc.h> /* Core Function Access */ 00190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ 00191 00192 #ifdef __cplusplus 00193 } 00194 #endif 00195 00196 #endif /* __CORE_CM4_H_GENERIC */ 00197 00198 #ifndef __CMSIS_GENERIC 00199 00200 #ifndef __CORE_CM4_H_DEPENDANT 00201 #define __CORE_CM4_H_DEPENDANT 00202 00203 #ifdef __cplusplus 00204 extern "C" { 00205 #endif 00206 00207 /* check device defines and use defaults */ 00208 #if defined __CHECK_DEVICE_DEFINES 00209 #ifndef __CM4_REV 00210 #define __CM4_REV 0x0000 00211 #warning "__CM4_REV not defined in device header file; using default!" 00212 #endif 00213 00214 #ifndef __FPU_PRESENT 00215 #define __FPU_PRESENT 0 00216 #warning "__FPU_PRESENT not defined in device header file; using default!" 00217 #endif 00218 00219 #ifndef __MPU_PRESENT 00220 #define __MPU_PRESENT 0 00221 #warning "__MPU_PRESENT not defined in device header file; using default!" 00222 #endif 00223 00224 #ifndef __NVIC_PRIO_BITS 00225 #define __NVIC_PRIO_BITS 4 00226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00227 #endif 00228 00229 #ifndef __Vendor_SysTickConfig 00230 #define __Vendor_SysTickConfig 0 00231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00232 #endif 00233 #endif 00234 00235 /* IO definitions (access restrictions to peripheral registers) */ 00236 /** 00237 \defgroup CMSIS_glob_defs CMSIS Global Defines 00238 00239 <strong>IO Type Qualifiers</strong> are used 00240 \li to specify the access to peripheral variables. 00241 \li for automatic generation of peripheral register debug information. 00242 */ 00243 #ifdef __cplusplus 00244 #define __I volatile /*!< Defines 'read only' permissions */ 00245 #else 00246 #define __I volatile const /*!< Defines 'read only' permissions */ 00247 #endif 00248 #define __O volatile /*!< Defines 'write only' permissions */ 00249 #define __IO volatile /*!< Defines 'read / write' permissions */ 00250 00251 #ifdef __cplusplus 00252 #define __IM volatile /*!< Defines 'read only' permissions */ 00253 #else 00254 #define __IM volatile const /*!< Defines 'read only' permissions */ 00255 #endif 00256 #define __OM volatile /*!< Defines 'write only' permissions */ 00257 #define __IOM volatile /*!< Defines 'read / write' permissions */ 00258 00259 /*@} end of group Cortex_M4 */ 00260 00261 00262 00263 /******************************************************************************* 00264 * Register Abstraction 00265 Core Register contain: 00266 - Core Register 00267 - Core NVIC Register 00268 - Core SCB Register 00269 - Core SysTick Register 00270 - Core Debug Register 00271 - Core MPU Register 00272 - Core FPU Register 00273 ******************************************************************************/ 00274 /** \defgroup CMSIS_core_register Defines and Type Definitions 00275 \brief Type definitions and defines for Cortex-M processor based devices. 00276 */ 00277 00278 /** \ingroup CMSIS_core_register 00279 \defgroup CMSIS_CORE Status and Control Registers 00280 \brief Core Register type definitions. 00281 @{ 00282 */ 00283 00284 /** \brief Union type to access the Application Program Status Register (APSR). 00285 */ 00286 typedef union 00287 { 00288 struct 00289 { 00290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00298 } b; /*!< Structure used for bit access */ 00299 uint32_t w; /*!< Type used for word access */ 00300 } APSR_Type; 00301 00302 /* APSR Register Definitions */ 00303 #define APSR_N_Pos 31 /*!< APSR: N Position */ 00304 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00305 00306 #define APSR_Z_Pos 30 /*!< APSR: Z Position */ 00307 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00308 00309 #define APSR_C_Pos 29 /*!< APSR: C Position */ 00310 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00311 00312 #define APSR_V_Pos 28 /*!< APSR: V Position */ 00313 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00314 00315 #define APSR_Q_Pos 27 /*!< APSR: Q Position */ 00316 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00317 00318 #define APSR_GE_Pos 16 /*!< APSR: GE Position */ 00319 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00320 00321 00322 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00323 */ 00324 typedef union 00325 { 00326 struct 00327 { 00328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00330 } b; /*!< Structure used for bit access */ 00331 uint32_t w; /*!< Type used for word access */ 00332 } IPSR_Type; 00333 00334 /* IPSR Register Definitions */ 00335 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ 00336 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00337 00338 00339 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00340 */ 00341 typedef union 00342 { 00343 struct 00344 { 00345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00356 } b; /*!< Structure used for bit access */ 00357 uint32_t w; /*!< Type used for word access */ 00358 } xPSR_Type; 00359 00360 /* xPSR Register Definitions */ 00361 #define xPSR_N_Pos 31 /*!< xPSR: N Position */ 00362 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00363 00364 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ 00365 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00366 00367 #define xPSR_C_Pos 29 /*!< xPSR: C Position */ 00368 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00369 00370 #define xPSR_V_Pos 28 /*!< xPSR: V Position */ 00371 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00372 00373 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ 00374 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00375 00376 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ 00377 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 00378 00379 #define xPSR_T_Pos 24 /*!< xPSR: T Position */ 00380 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00381 00382 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ 00383 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00384 00385 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ 00386 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00387 00388 00389 /** \brief Union type to access the Control Registers (CONTROL). 00390 */ 00391 typedef union 00392 { 00393 struct 00394 { 00395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00399 } b; /*!< Structure used for bit access */ 00400 uint32_t w; /*!< Type used for word access */ 00401 } CONTROL_Type; 00402 00403 /* CONTROL Register Definitions */ 00404 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ 00405 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00406 00407 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ 00408 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00409 00410 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ 00411 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00412 00413 /*@} end of group CMSIS_CORE */ 00414 00415 00416 /** \ingroup CMSIS_core_register 00417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00418 \brief Type definitions for the NVIC Registers 00419 @{ 00420 */ 00421 00422 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00423 */ 00424 typedef struct 00425 { 00426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00427 uint32_t RESERVED0[24]; 00428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00429 uint32_t RSERVED1[24]; 00430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00431 uint32_t RESERVED2[24]; 00432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00433 uint32_t RESERVED3[24]; 00434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00435 uint32_t RESERVED4[56]; 00436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00437 uint32_t RESERVED5[644]; 00438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00439 } NVIC_Type; 00440 00441 /* Software Triggered Interrupt Register Definitions */ 00442 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 00443 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00444 00445 /*@} end of group CMSIS_NVIC */ 00446 00447 00448 /** \ingroup CMSIS_core_register 00449 \defgroup CMSIS_SCB System Control Block (SCB) 00450 \brief Type definitions for the System Control Block Registers 00451 @{ 00452 */ 00453 00454 /** \brief Structure type to access the System Control Block (SCB). 00455 */ 00456 typedef struct 00457 { 00458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00477 uint32_t RESERVED0[5]; 00478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00479 } SCB_Type; 00480 00481 /* SCB CPUID Register Definitions */ 00482 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00483 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00484 00485 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00486 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00487 00488 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00489 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00490 00491 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00492 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00493 00494 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00495 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00496 00497 /* SCB Interrupt Control State Register Definitions */ 00498 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00499 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00500 00501 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00503 00504 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00506 00507 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00509 00510 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00512 00513 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00514 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00515 00516 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00517 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00518 00519 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00520 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00521 00522 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 00523 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00524 00525 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00527 00528 /* SCB Vector Table Offset Register Definitions */ 00529 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00530 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00531 00532 /* SCB Application Interrupt and Reset Control Register Definitions */ 00533 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00534 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00535 00536 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00537 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00538 00539 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00540 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00541 00542 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 00543 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00544 00545 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00546 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00547 00548 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00549 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00550 00551 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 00552 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00553 00554 /* SCB System Control Register Definitions */ 00555 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00556 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00557 00558 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00559 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00560 00561 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00562 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00563 00564 /* SCB Configuration Control Register Definitions */ 00565 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00566 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00567 00568 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 00569 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00570 00571 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 00572 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00573 00574 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00575 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00576 00577 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 00578 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00579 00580 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 00581 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00582 00583 /* SCB System Handler Control and State Register Definitions */ 00584 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 00585 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00586 00587 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 00588 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00589 00590 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 00591 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00592 00593 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00594 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00595 00596 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00597 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00598 00599 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00600 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00601 00602 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 00603 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00604 00605 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 00606 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00607 00608 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 00609 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00610 00611 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 00612 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00613 00614 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 00615 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00616 00617 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 00618 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00619 00620 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 00621 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00622 00623 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 00624 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00625 00626 /* SCB Configurable Fault Status Registers Definitions */ 00627 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 00628 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00629 00630 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 00631 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00632 00633 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00634 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00635 00636 /* SCB Hard Fault Status Registers Definitions */ 00637 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 00638 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00639 00640 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 00641 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00642 00643 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 00644 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00645 00646 /* SCB Debug Fault Status Register Definitions */ 00647 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 00648 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00649 00650 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 00651 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00652 00653 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 00654 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00655 00656 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 00657 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00658 00659 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 00660 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00661 00662 /*@} end of group CMSIS_SCB */ 00663 00664 00665 /** \ingroup CMSIS_core_register 00666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00667 \brief Type definitions for the System Control and ID Register not in the SCB 00668 @{ 00669 */ 00670 00671 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00672 */ 00673 typedef struct 00674 { 00675 uint32_t RESERVED0[1]; 00676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00678 } SCnSCB_Type; 00679 00680 /* Interrupt Controller Type Register Definitions */ 00681 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 00682 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00683 00684 /* Auxiliary Control Register Definitions */ 00685 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ 00686 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 00687 00688 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ 00689 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 00690 00691 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 00692 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00693 00694 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ 00695 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00696 00697 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00698 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00699 00700 /*@} end of group CMSIS_SCnotSCB */ 00701 00702 00703 /** \ingroup CMSIS_core_register 00704 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00705 \brief Type definitions for the System Timer Registers. 00706 @{ 00707 */ 00708 00709 /** \brief Structure type to access the System Timer (SysTick). 00710 */ 00711 typedef struct 00712 { 00713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00717 } SysTick_Type; 00718 00719 /* SysTick Control / Status Register Definitions */ 00720 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00721 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00722 00723 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00724 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00725 00726 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00727 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00728 00729 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00730 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00731 00732 /* SysTick Reload Register Definitions */ 00733 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00734 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00735 00736 /* SysTick Current Register Definitions */ 00737 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00738 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00739 00740 /* SysTick Calibration Register Definitions */ 00741 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00742 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00743 00744 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00745 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00746 00747 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00748 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00749 00750 /*@} end of group CMSIS_SysTick */ 00751 00752 00753 /** \ingroup CMSIS_core_register 00754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00756 @{ 00757 */ 00758 00759 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00760 */ 00761 typedef struct 00762 { 00763 __O union 00764 { 00765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00769 uint32_t RESERVED0[864]; 00770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00771 uint32_t RESERVED1[15]; 00772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00773 uint32_t RESERVED2[15]; 00774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00775 uint32_t RESERVED3[29]; 00776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00779 uint32_t RESERVED4[43]; 00780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00782 uint32_t RESERVED5[6]; 00783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00795 } ITM_Type; 00796 00797 /* ITM Trace Privilege Register Definitions */ 00798 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 00799 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00800 00801 /* ITM Trace Control Register Definitions */ 00802 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 00803 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00804 00805 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 00806 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00807 00808 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 00809 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00810 00811 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 00812 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00813 00814 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 00815 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00816 00817 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 00818 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00819 00820 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 00821 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00822 00823 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 00824 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00825 00826 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 00827 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 00828 00829 /* ITM Integration Write Register Definitions */ 00830 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 00831 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 00832 00833 /* ITM Integration Read Register Definitions */ 00834 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 00835 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 00836 00837 /* ITM Integration Mode Control Register Definitions */ 00838 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 00839 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 00840 00841 /* ITM Lock Status Register Definitions */ 00842 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 00843 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00844 00845 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 00846 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00847 00848 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 00849 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 00850 00851 /*@}*/ /* end of group CMSIS_ITM */ 00852 00853 00854 /** \ingroup CMSIS_core_register 00855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00856 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00857 @{ 00858 */ 00859 00860 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00861 */ 00862 typedef struct 00863 { 00864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00875 uint32_t RESERVED0[1]; 00876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00879 uint32_t RESERVED1[1]; 00880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00883 uint32_t RESERVED2[1]; 00884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00887 } DWT_Type; 00888 00889 /* DWT Control Register Definitions */ 00890 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 00891 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00892 00893 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 00894 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00895 00896 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 00897 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00898 00899 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 00900 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00901 00902 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 00903 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00904 00905 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 00906 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00907 00908 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 00909 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00910 00911 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 00912 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00913 00914 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 00915 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00916 00917 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 00918 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00919 00920 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 00921 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00922 00923 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 00924 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00925 00926 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 00927 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00928 00929 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 00930 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00931 00932 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 00933 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00934 00935 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 00936 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00937 00938 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 00939 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00940 00941 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 00942 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 00943 00944 /* DWT CPI Count Register Definitions */ 00945 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 00946 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 00947 00948 /* DWT Exception Overhead Count Register Definitions */ 00949 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 00950 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 00951 00952 /* DWT Sleep Count Register Definitions */ 00953 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00954 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00955 00956 /* DWT LSU Count Register Definitions */ 00957 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 00958 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 00959 00960 /* DWT Folded-instruction Count Register Definitions */ 00961 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 00962 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 00963 00964 /* DWT Comparator Mask Register Definitions */ 00965 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 00966 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 00967 00968 /* DWT Comparator Function Register Definitions */ 00969 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 00970 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00971 00972 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 00973 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 00974 00975 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 00976 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 00977 00978 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 00979 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00980 00981 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 00982 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 00983 00984 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 00985 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 00986 00987 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 00988 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 00989 00990 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 00991 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 00992 00993 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 00994 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 00995 00996 /*@}*/ /* end of group CMSIS_DWT */ 00997 00998 00999 /** \ingroup CMSIS_core_register 01000 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01001 \brief Type definitions for the Trace Port Interface (TPI) 01002 @{ 01003 */ 01004 01005 /** \brief Structure type to access the Trace Port Interface Register (TPI). 01006 */ 01007 typedef struct 01008 { 01009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01011 uint32_t RESERVED0[2]; 01012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01013 uint32_t RESERVED1[55]; 01014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01015 uint32_t RESERVED2[131]; 01016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01019 uint32_t RESERVED3[759]; 01020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01023 uint32_t RESERVED4[1]; 01024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01027 uint32_t RESERVED5[39]; 01028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01030 uint32_t RESERVED7[8]; 01031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01033 } TPI_Type; 01034 01035 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01036 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 01037 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01038 01039 /* TPI Selected Pin Protocol Register Definitions */ 01040 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 01041 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01042 01043 /* TPI Formatter and Flush Status Register Definitions */ 01044 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 01045 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01046 01047 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 01048 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01049 01050 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 01051 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01052 01053 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 01054 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01055 01056 /* TPI Formatter and Flush Control Register Definitions */ 01057 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 01058 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01059 01060 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 01061 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01062 01063 /* TPI TRIGGER Register Definitions */ 01064 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 01065 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01066 01067 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01068 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 01069 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01070 01071 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 01072 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01073 01074 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 01075 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01076 01077 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 01078 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01079 01080 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 01081 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01082 01083 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 01084 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01085 01086 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 01087 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01088 01089 /* TPI ITATBCTR2 Register Definitions */ 01090 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 01091 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01092 01093 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01094 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 01095 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01096 01097 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 01098 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01099 01100 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 01101 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01102 01103 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 01104 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01105 01106 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 01107 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01108 01109 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 01110 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01111 01112 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 01113 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01114 01115 /* TPI ITATBCTR0 Register Definitions */ 01116 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 01117 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01118 01119 /* TPI Integration Mode Control Register Definitions */ 01120 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 01121 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01122 01123 /* TPI DEVID Register Definitions */ 01124 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 01125 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01126 01127 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 01128 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01129 01130 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 01131 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01132 01133 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 01134 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01135 01136 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 01137 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01138 01139 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 01140 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01141 01142 /* TPI DEVTYPE Register Definitions */ 01143 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 01144 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01145 01146 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 01147 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01148 01149 /*@}*/ /* end of group CMSIS_TPI */ 01150 01151 01152 #if (__MPU_PRESENT == 1) 01153 /** \ingroup CMSIS_core_register 01154 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01155 \brief Type definitions for the Memory Protection Unit (MPU) 01156 @{ 01157 */ 01158 01159 /** \brief Structure type to access the Memory Protection Unit (MPU). 01160 */ 01161 typedef struct 01162 { 01163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01174 } MPU_Type; 01175 01176 /* MPU Type Register */ 01177 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 01178 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01179 01180 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 01181 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01182 01183 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 01184 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01185 01186 /* MPU Control Register */ 01187 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 01188 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01189 01190 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 01191 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01192 01193 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 01194 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01195 01196 /* MPU Region Number Register */ 01197 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 01198 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01199 01200 /* MPU Region Base Address Register */ 01201 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 01202 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01203 01204 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 01205 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01206 01207 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 01208 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01209 01210 /* MPU Region Attribute and Size Register */ 01211 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 01212 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01213 01214 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 01215 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01216 01217 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 01218 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01219 01220 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 01221 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01222 01223 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 01224 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01225 01226 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 01227 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01228 01229 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 01230 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01231 01232 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 01233 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01234 01235 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 01236 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01237 01238 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 01239 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01240 01241 /*@} end of group CMSIS_MPU */ 01242 #endif 01243 01244 01245 #if (__FPU_PRESENT == 1) 01246 /** \ingroup CMSIS_core_register 01247 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01248 \brief Type definitions for the Floating Point Unit (FPU) 01249 @{ 01250 */ 01251 01252 /** \brief Structure type to access the Floating Point Unit (FPU). 01253 */ 01254 typedef struct 01255 { 01256 uint32_t RESERVED0[1]; 01257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01262 } FPU_Type; 01263 01264 /* Floating-Point Context Control Register */ 01265 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ 01266 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01267 01268 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ 01269 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01270 01271 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ 01272 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01273 01274 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ 01275 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01276 01277 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ 01278 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01279 01280 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ 01281 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01282 01283 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ 01284 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01285 01286 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ 01287 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01288 01289 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ 01290 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01291 01292 /* Floating-Point Context Address Register */ 01293 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ 01294 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01295 01296 /* Floating-Point Default Status Control Register */ 01297 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ 01298 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01299 01300 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ 01301 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01302 01303 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ 01304 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01305 01306 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ 01307 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01308 01309 /* Media and FP Feature Register 0 */ 01310 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ 01311 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01312 01313 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ 01314 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01315 01316 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ 01317 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01318 01319 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ 01320 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01321 01322 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ 01323 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01324 01325 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ 01326 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01327 01328 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ 01329 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01330 01331 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ 01332 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01333 01334 /* Media and FP Feature Register 1 */ 01335 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ 01336 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01337 01338 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ 01339 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01340 01341 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ 01342 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01343 01344 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ 01345 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01346 01347 /*@} end of group CMSIS_FPU */ 01348 #endif 01349 01350 01351 /** \ingroup CMSIS_core_register 01352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01353 \brief Type definitions for the Core Debug Registers 01354 @{ 01355 */ 01356 01357 /** \brief Structure type to access the Core Debug Register (CoreDebug). 01358 */ 01359 typedef struct 01360 { 01361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01365 } CoreDebug_Type; 01366 01367 /* Debug Halting Control and Status Register */ 01368 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 01369 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01370 01371 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01372 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01373 01374 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01375 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01376 01377 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01378 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01379 01380 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 01381 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01382 01383 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 01384 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01385 01386 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 01387 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01388 01389 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01390 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01391 01392 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01393 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01394 01395 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 01396 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01397 01398 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 01399 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01400 01401 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01402 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01403 01404 /* Debug Core Register Selector Register */ 01405 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 01406 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01407 01408 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 01409 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01410 01411 /* Debug Exception and Monitor Control Register */ 01412 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 01413 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01414 01415 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 01416 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01417 01418 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 01419 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01420 01421 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 01422 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01423 01424 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 01425 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01426 01427 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01428 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01429 01430 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 01431 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01432 01433 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01434 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01435 01436 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 01437 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01438 01439 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01440 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01441 01442 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01443 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01444 01445 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 01446 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01447 01448 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01449 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01450 01451 /*@} end of group CMSIS_CoreDebug */ 01452 01453 01454 /** \ingroup CMSIS_core_register 01455 \defgroup CMSIS_core_base Core Definitions 01456 \brief Definitions for base addresses, unions, and structures. 01457 @{ 01458 */ 01459 01460 /* Memory mapping of Cortex-M4 Hardware */ 01461 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01462 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01463 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01464 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01465 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01466 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01467 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01468 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01469 01470 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01471 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01472 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01473 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01474 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01475 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01476 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01477 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01478 01479 #if (__MPU_PRESENT == 1) 01480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01482 #endif 01483 01484 #if (__FPU_PRESENT == 1) 01485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01487 #endif 01488 01489 /*@} */ 01490 01491 01492 01493 /******************************************************************************* 01494 * Hardware Abstraction Layer 01495 Core Function Interface contains: 01496 - Core NVIC Functions 01497 - Core SysTick Functions 01498 - Core Debug Functions 01499 - Core Register Access Functions 01500 ******************************************************************************/ 01501 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01502 */ 01503 01504 01505 01506 /* ########################## NVIC functions #################################### */ 01507 /** \ingroup CMSIS_Core_FunctionInterface 01508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01509 \brief Functions that manage interrupts and exceptions via the NVIC. 01510 @{ 01511 */ 01512 01513 #ifdef CMSIS_NVIC_VIRTUAL 01514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01516 #endif 01517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01518 #else 01519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01521 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01522 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01526 #define NVIC_GetActive __NVIC_GetActive 01527 #define NVIC_SetPriority __NVIC_SetPriority 01528 #define NVIC_GetPriority __NVIC_GetPriority 01529 #define NVIC_SystemReset __NVIC_SystemReset 01530 #endif /* CMSIS_NVIC_VIRTUAL */ 01531 01532 #ifdef CMSIS_VECTAB_VIRTUAL 01533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01535 #endif 01536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01537 #else 01538 #define NVIC_SetVector __NVIC_SetVector 01539 #define NVIC_GetVector __NVIC_GetVector 01540 #endif /* CMSIS_VECTAB_VIRTUAL */ 01541 01542 01543 /** \brief Set Priority Grouping 01544 01545 The function sets the priority grouping field using the required unlock sequence. 01546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01547 Only values from 0..7 are used. 01548 In case of a conflict between priority grouping and available 01549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01550 01551 \param [in] PriorityGroup Priority grouping field. 01552 */ 01553 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01554 { 01555 uint32_t reg_value; 01556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01557 01558 reg_value = SCB->AIRCR; /* read old register configuration */ 01559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01560 reg_value = (reg_value | 01561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ 01563 SCB->AIRCR = reg_value; 01564 } 01565 01566 01567 /** \brief Get Priority Grouping 01568 01569 The function reads the priority grouping field from the NVIC Interrupt Controller. 01570 01571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01572 */ 01573 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01574 { 01575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01576 } 01577 01578 01579 /** \brief Enable External Interrupt 01580 01581 The function enables a device-specific interrupt in the NVIC interrupt controller. 01582 01583 \param [in] IRQn External interrupt number. Value cannot be negative. 01584 */ 01585 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01586 { 01587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01588 } 01589 01590 01591 /** \brief Disable External Interrupt 01592 01593 The function disables a device-specific interrupt in the NVIC interrupt controller. 01594 01595 \param [in] IRQn External interrupt number. Value cannot be negative. 01596 */ 01597 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01598 { 01599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01600 __DSB(); 01601 __ISB(); 01602 } 01603 01604 01605 /** \brief Get Pending Interrupt 01606 01607 The function reads the pending register in the NVIC and returns the pending bit 01608 for the specified interrupt. 01609 01610 \param [in] IRQn Interrupt number. 01611 01612 \return 0 Interrupt status is not pending. 01613 \return 1 Interrupt status is pending. 01614 */ 01615 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01616 { 01617 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01618 } 01619 01620 01621 /** \brief Set Pending Interrupt 01622 01623 The function sets the pending bit of an external interrupt. 01624 01625 \param [in] IRQn Interrupt number. Value cannot be negative. 01626 */ 01627 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01628 { 01629 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01630 } 01631 01632 01633 /** \brief Clear Pending Interrupt 01634 01635 The function clears the pending bit of an external interrupt. 01636 01637 \param [in] IRQn External interrupt number. Value cannot be negative. 01638 */ 01639 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01640 { 01641 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01642 } 01643 01644 01645 /** \brief Get Active Interrupt 01646 01647 The function reads the active register in NVIC and returns the active bit. 01648 01649 \param [in] IRQn Interrupt number. 01650 01651 \return 0 Interrupt status is not active. 01652 \return 1 Interrupt status is active. 01653 */ 01654 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01655 { 01656 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01657 } 01658 01659 01660 /** \brief Set Interrupt Priority 01661 01662 The function sets the priority of an interrupt. 01663 01664 \note The priority cannot be set for every core interrupt. 01665 01666 \param [in] IRQn Interrupt number. 01667 \param [in] priority Priority to set. 01668 */ 01669 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01670 { 01671 if((int32_t)IRQn < 0) { 01672 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01673 } 01674 else { 01675 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01676 } 01677 } 01678 01679 01680 /** \brief Get Interrupt Priority 01681 01682 The function reads the priority of an interrupt. The interrupt 01683 number can be positive to specify an external (device specific) 01684 interrupt, or negative to specify an internal (core) interrupt. 01685 01686 01687 \param [in] IRQn Interrupt number. 01688 \return Interrupt Priority. Value is aligned automatically to the implemented 01689 priority bits of the microcontroller. 01690 */ 01691 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01692 { 01693 01694 if((int32_t)IRQn < 0) { 01695 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); 01696 } 01697 else { 01698 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); 01699 } 01700 } 01701 01702 01703 /** \brief Encode Priority 01704 01705 The function encodes the priority for an interrupt with the given priority group, 01706 preemptive priority value, and subpriority value. 01707 In case of a conflict between priority grouping and available 01708 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01709 01710 \param [in] PriorityGroup Used priority group. 01711 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01712 \param [in] SubPriority Subpriority value (starting from 0). 01713 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01714 */ 01715 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01716 { 01717 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01718 uint32_t PreemptPriorityBits; 01719 uint32_t SubPriorityBits; 01720 01721 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01722 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01723 01724 return ( 01725 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01726 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01727 ); 01728 } 01729 01730 01731 /** \brief Decode Priority 01732 01733 The function decodes an interrupt priority value with a given priority group to 01734 preemptive priority value and subpriority value. 01735 In case of a conflict between priority grouping and available 01736 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01737 01738 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01739 \param [in] PriorityGroup Used priority group. 01740 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01741 \param [out] pSubPriority Subpriority value (starting from 0). 01742 */ 01743 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01744 { 01745 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01746 uint32_t PreemptPriorityBits; 01747 uint32_t SubPriorityBits; 01748 01749 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01750 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01751 01752 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01753 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01754 } 01755 01756 01757 /** \brief System Reset 01758 01759 The function initiates a system reset request to reset the MCU. 01760 */ 01761 __STATIC_INLINE void __NVIC_SystemReset(void) 01762 { 01763 __DSB(); /* Ensure all outstanding memory accesses included 01764 buffered write are completed before reset */ 01765 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01766 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01767 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01768 __DSB(); /* Ensure completion of memory access */ 01769 while(1) { __NOP(); } /* wait until reset */ 01770 } 01771 01772 /*@} end of CMSIS_Core_NVICFunctions */ 01773 01774 01775 01776 /* ################################## SysTick function ############################################ */ 01777 /** \ingroup CMSIS_Core_FunctionInterface 01778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01779 \brief Functions that configure the System. 01780 @{ 01781 */ 01782 01783 #if (__Vendor_SysTickConfig == 0) 01784 01785 /** \brief System Tick Configuration 01786 01787 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 01788 Counter is in free running mode to generate periodic interrupts. 01789 01790 \param [in] ticks Number of ticks between two interrupts. 01791 01792 \return 0 Function succeeded. 01793 \return 1 Function failed. 01794 01795 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01796 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01797 must contain a vendor-specific implementation of this function. 01798 01799 */ 01800 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01801 { 01802 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ 01803 01804 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01805 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01806 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01807 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01808 SysTick_CTRL_TICKINT_Msk | 01809 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01810 return (0UL); /* Function successful */ 01811 } 01812 01813 #endif 01814 01815 /*@} end of CMSIS_Core_SysTickFunctions */ 01816 01817 01818 01819 /* ##################################### Debug In/Output function ########################################### */ 01820 /** \ingroup CMSIS_Core_FunctionInterface 01821 \defgroup CMSIS_core_DebugFunctions ITM Functions 01822 \brief Functions that access the ITM debug interface. 01823 @{ 01824 */ 01825 01826 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 01827 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 01828 01829 01830 /** \brief ITM Send Character 01831 01832 The function transmits a character via the ITM channel 0, and 01833 \li Just returns when no debugger is connected that has booked the output. 01834 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 01835 01836 \param [in] ch Character to transmit. 01837 01838 \returns Character to transmit. 01839 */ 01840 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01841 { 01842 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 01843 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 01844 { 01845 while (ITM->PORT[0].u32 == 0UL) { __NOP(); } 01846 ITM->PORT[0].u8 = (uint8_t)ch; 01847 } 01848 return (ch); 01849 } 01850 01851 01852 /** \brief ITM Receive Character 01853 01854 The function inputs a character via the external variable \ref ITM_RxBuffer. 01855 01856 \return Received character. 01857 \return -1 No character pending. 01858 */ 01859 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 01860 int32_t ch = -1; /* no character available */ 01861 01862 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 01863 ch = ITM_RxBuffer; 01864 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01865 } 01866 01867 return (ch); 01868 } 01869 01870 01871 /** \brief ITM Check Character 01872 01873 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 01874 01875 \return 0 No character available. 01876 \return 1 Character available. 01877 */ 01878 __STATIC_INLINE int32_t ITM_CheckChar (void) { 01879 01880 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 01881 return (0); /* no character available */ 01882 } else { 01883 return (1); /* character available */ 01884 } 01885 } 01886 01887 /*@} end of CMSIS_core_DebugFunctions */ 01888 01889 01890 01891 01892 #ifdef __cplusplus 01893 } 01894 #endif 01895 01896 #endif /* __CORE_CM4_H_DEPENDANT */ 01897 01898 #endif /* __CMSIS_GENERIC */
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