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core_ca9.h

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00001 /**************************************************************************//**
00002  * @file     core_ca9.h
00003  * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
00004  * @version
00005  * @date     25 March 2013
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2012 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #ifndef __CORE_CA9_H_GENERIC
00047 #define __CORE_CA9_H_GENERIC
00048 
00049 
00050 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00051   CMSIS violates the following MISRA-C:2004 rules:
00052 
00053    \li Required Rule 8.5, object/function definition in header file.<br>
00054      Function definitions in header files are used to allow 'inlining'.
00055 
00056    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00057      Unions are used for effective representation of core registers.
00058 
00059    \li Advisory Rule 19.7, Function-like macro defined.<br>
00060      Function-like macros are used to allow more efficient code.
00061  */
00062 
00063 
00064 /*******************************************************************************
00065  *                 CMSIS definitions
00066  ******************************************************************************/
00067 /** \ingroup Cortex_A9
00068   @{
00069  */
00070 
00071 /*  CMSIS CA9 definitions */
00072 #define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00073 #define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
00074 #define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
00075                                     __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00076 
00077 #define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
00078 
00079 
00080 #if   defined ( __CC_ARM )
00081   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00082   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00083   #define __STATIC_INLINE  static __inline
00084   #define __STATIC_ASM     static __asm
00085 
00086 #elif defined ( __ICCARM__ )
00087   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00088   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00089   #define __STATIC_INLINE  static inline
00090   #define __STATIC_ASM     static __asm
00091 
00092 #include <stdint.h>
00093 inline uint32_t __get_PSR(void) {
00094     __ASM("mrs r0, cpsr");
00095 }
00096 
00097 #elif defined ( __TMS470__ )
00098   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00099   #define __STATIC_INLINE  static inline
00100   #define __STATIC_ASM     static __asm
00101 
00102 #elif defined ( __GNUC__ )
00103   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00104   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00105   #define __STATIC_INLINE  static inline
00106   #define __STATIC_ASM     static __asm
00107 
00108 #elif defined ( __TASKING__ )
00109   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00110   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00111   #define __STATIC_INLINE  static inline
00112   #define __STATIC_ASM     static __asm
00113 
00114 #endif
00115 
00116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
00117 */
00118 #if defined ( __CC_ARM )
00119   #if defined __TARGET_FPU_VFP
00120     #if (__FPU_PRESENT == 1)
00121       #define __FPU_USED       1
00122     #else
00123       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00124       #define __FPU_USED       0
00125     #endif
00126   #else
00127     #define __FPU_USED         0
00128   #endif
00129 
00130 #elif defined ( __ICCARM__ )
00131   #if defined __ARMVFP__
00132     #if (__FPU_PRESENT == 1)
00133       #define __FPU_USED       1
00134     #else
00135       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00136       #define __FPU_USED       0
00137     #endif
00138   #else
00139     #define __FPU_USED         0
00140   #endif
00141 
00142 #elif defined ( __TMS470__ )
00143   #if defined __TI_VFP_SUPPORT__
00144     #if (__FPU_PRESENT == 1)
00145       #define __FPU_USED       1
00146     #else
00147       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00148       #define __FPU_USED       0
00149     #endif
00150   #else
00151     #define __FPU_USED         0
00152   #endif
00153 
00154 #elif defined ( __GNUC__ )
00155   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00156     #if (__FPU_PRESENT == 1)
00157       #define __FPU_USED       1
00158     #else
00159       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00160       #define __FPU_USED       0
00161     #endif
00162   #else
00163     #define __FPU_USED         0
00164   #endif
00165 
00166 #elif defined ( __TASKING__ )
00167   #if defined __FPU_VFP__
00168     #if (__FPU_PRESENT == 1)
00169       #define __FPU_USED       1
00170     #else
00171       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00172       #define __FPU_USED       0
00173     #endif
00174   #else
00175     #define __FPU_USED         0
00176   #endif
00177 #endif
00178 
00179 #include <stdint.h>                      /*!< standard types definitions                      */
00180 #include "core_caInstr.h"                /*!< Core Instruction Access                         */
00181 #include "core_caFunc.h"                 /*!< Core Function Access                            */
00182 #include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
00183 
00184 #endif /* __CORE_CA9_H_GENERIC */
00185 
00186 #ifndef __CMSIS_GENERIC
00187 
00188 #ifndef __CORE_CA9_H_DEPENDANT
00189 #define __CORE_CA9_H_DEPENDANT
00190 
00191 /* check device defines and use defaults */
00192 #if defined __CHECK_DEVICE_DEFINES
00193   #ifndef __CA9_REV
00194     #define __CA9_REV               0x0000
00195     #warning "__CA9_REV not defined in device header file; using default!"
00196   #endif
00197 
00198   #ifndef __FPU_PRESENT
00199     #define __FPU_PRESENT             1
00200     #warning "__FPU_PRESENT not defined in device header file; using default!"
00201   #endif
00202 
00203   #ifndef __Vendor_SysTickConfig
00204     #define __Vendor_SysTickConfig    1
00205   #endif
00206 
00207   #if __Vendor_SysTickConfig == 0
00208     #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
00209   #endif
00210 #endif
00211 
00212 /* IO definitions (access restrictions to peripheral registers) */
00213 /**
00214     \defgroup CMSIS_glob_defs CMSIS Global Defines
00215 
00216     <strong>IO Type Qualifiers</strong> are used
00217     \li to specify the access to peripheral variables.
00218     \li for automatic generation of peripheral register debug information.
00219 */
00220 #ifdef __cplusplus
00221   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00222 #else
00223   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00224 #endif
00225 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00226 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00227 
00228 /*@} end of group Cortex_A9 */
00229 
00230 
00231 /*******************************************************************************
00232  *                 Register Abstraction
00233  ******************************************************************************/
00234 /** \defgroup CMSIS_core_register Defines and Type Definitions
00235     \brief Type definitions and defines for Cortex-A processor based devices.
00236 */
00237 
00238 /** \ingroup    CMSIS_core_register
00239     \defgroup   CMSIS_CORE  Status and Control Registers
00240     \brief  Core Register type definitions.
00241   @{
00242  */
00243 
00244 /** \brief  Union type to access the Application Program Status Register (APSR).
00245  */
00246 typedef union
00247 {
00248   struct
00249   {
00250     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00251     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00252     uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
00253     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00254     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00255     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00256     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00257     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00258   } b;                                   /*!< Structure used for bit  access                  */
00259   uint32_t w ;                            /*!< Type      used for word access                  */ 
00260 } APSR_Type;
00261 
00262 
00263 /*@} end of group CMSIS_CORE */
00264 
00265 /*@} end of CMSIS_Core_FPUFunctions */
00266 
00267 
00268 #endif /* __CORE_CA9_H_GENERIC */
00269 
00270 #endif /* __CMSIS_GENERIC */
00271 
00272 #ifdef __cplusplus
00273 }
00274 
00275 
00276 #endif