Vipin Ranka
This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest
Dependencies: GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem
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mbed-os-examples
RF24/nRF24L01.h@12:9a20164dcc47, 2017-01-11 (annotated)
- Committer:
- vipinranka
- Date:
- Wed Jan 11 11:41:30 2017 +0000
- Revision:
- 12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| vipinranka | 12:9a20164dcc47 | 1 | /* |
| vipinranka | 12:9a20164dcc47 | 2 | Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de> |
| vipinranka | 12:9a20164dcc47 | 3 | Portions Copyright (C) 2011 Greg Copeland |
| vipinranka | 12:9a20164dcc47 | 4 | |
| vipinranka | 12:9a20164dcc47 | 5 | Permission is hereby granted, free of charge, to any person |
| vipinranka | 12:9a20164dcc47 | 6 | obtaining a copy of this software and associated documentation |
| vipinranka | 12:9a20164dcc47 | 7 | files (the "Software"), to deal in the Software without |
| vipinranka | 12:9a20164dcc47 | 8 | restriction, including without limitation the rights to use, copy, |
| vipinranka | 12:9a20164dcc47 | 9 | modify, merge, publish, distribute, sublicense, and/or sell copies |
| vipinranka | 12:9a20164dcc47 | 10 | of the Software, and to permit persons to whom the Software is |
| vipinranka | 12:9a20164dcc47 | 11 | furnished to do so, subject to the following conditions: |
| vipinranka | 12:9a20164dcc47 | 12 | |
| vipinranka | 12:9a20164dcc47 | 13 | The above copyright notice and this permission notice shall be |
| vipinranka | 12:9a20164dcc47 | 14 | included in all copies or substantial portions of the Software. |
| vipinranka | 12:9a20164dcc47 | 15 | |
| vipinranka | 12:9a20164dcc47 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| vipinranka | 12:9a20164dcc47 | 17 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| vipinranka | 12:9a20164dcc47 | 18 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| vipinranka | 12:9a20164dcc47 | 19 | NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| vipinranka | 12:9a20164dcc47 | 20 | HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| vipinranka | 12:9a20164dcc47 | 21 | WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| vipinranka | 12:9a20164dcc47 | 22 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| vipinranka | 12:9a20164dcc47 | 23 | DEALINGS IN THE SOFTWARE. |
| vipinranka | 12:9a20164dcc47 | 24 | */ |
| vipinranka | 12:9a20164dcc47 | 25 | |
| vipinranka | 12:9a20164dcc47 | 26 | /* |
| vipinranka | 12:9a20164dcc47 | 27 | * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com> |
| vipinranka | 12:9a20164dcc47 | 28 | * Porting completed on Nov/05/2015 |
| vipinranka | 12:9a20164dcc47 | 29 | * |
| vipinranka | 12:9a20164dcc47 | 30 | * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20 |
| vipinranka | 12:9a20164dcc47 | 31 | * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20 |
| vipinranka | 12:9a20164dcc47 | 32 | * |
| vipinranka | 12:9a20164dcc47 | 33 | */ |
| vipinranka | 12:9a20164dcc47 | 34 | |
| vipinranka | 12:9a20164dcc47 | 35 | /* Memory Map */ |
| vipinranka | 12:9a20164dcc47 | 36 | #define NRF_CONFIG 0x00 |
| vipinranka | 12:9a20164dcc47 | 37 | #define EN_AA 0x01 |
| vipinranka | 12:9a20164dcc47 | 38 | #define EN_RXADDR 0x02 |
| vipinranka | 12:9a20164dcc47 | 39 | #define SETUP_AW 0x03 |
| vipinranka | 12:9a20164dcc47 | 40 | #define SETUP_RETR 0x04 |
| vipinranka | 12:9a20164dcc47 | 41 | #define RF_CH 0x05 |
| vipinranka | 12:9a20164dcc47 | 42 | #define RF_SETUP 0x06 |
| vipinranka | 12:9a20164dcc47 | 43 | #define NRF_STATUS 0x07 |
| vipinranka | 12:9a20164dcc47 | 44 | #define OBSERVE_TX 0x08 |
| vipinranka | 12:9a20164dcc47 | 45 | #define CD 0x09 |
| vipinranka | 12:9a20164dcc47 | 46 | #define RX_ADDR_P0 0x0A |
| vipinranka | 12:9a20164dcc47 | 47 | #define RX_ADDR_P1 0x0B |
| vipinranka | 12:9a20164dcc47 | 48 | #define RX_ADDR_P2 0x0C |
| vipinranka | 12:9a20164dcc47 | 49 | #define RX_ADDR_P3 0x0D |
| vipinranka | 12:9a20164dcc47 | 50 | #define RX_ADDR_P4 0x0E |
| vipinranka | 12:9a20164dcc47 | 51 | #define RX_ADDR_P5 0x0F |
| vipinranka | 12:9a20164dcc47 | 52 | #define TX_ADDR 0x10 |
| vipinranka | 12:9a20164dcc47 | 53 | #define RX_PW_P0 0x11 |
| vipinranka | 12:9a20164dcc47 | 54 | #define RX_PW_P1 0x12 |
| vipinranka | 12:9a20164dcc47 | 55 | #define RX_PW_P2 0x13 |
| vipinranka | 12:9a20164dcc47 | 56 | #define RX_PW_P3 0x14 |
| vipinranka | 12:9a20164dcc47 | 57 | #define RX_PW_P4 0x15 |
| vipinranka | 12:9a20164dcc47 | 58 | #define RX_PW_P5 0x16 |
| vipinranka | 12:9a20164dcc47 | 59 | #define FIFO_STATUS 0x17 |
| vipinranka | 12:9a20164dcc47 | 60 | #define DYNPD 0x1C |
| vipinranka | 12:9a20164dcc47 | 61 | #define FEATURE 0x1D |
| vipinranka | 12:9a20164dcc47 | 62 | |
| vipinranka | 12:9a20164dcc47 | 63 | /* Bit Mnemonics */ |
| vipinranka | 12:9a20164dcc47 | 64 | #define MASK_RX_DR 6 |
| vipinranka | 12:9a20164dcc47 | 65 | #define MASK_TX_DS 5 |
| vipinranka | 12:9a20164dcc47 | 66 | #define MASK_MAX_RT 4 |
| vipinranka | 12:9a20164dcc47 | 67 | #define EN_CRC 3 |
| vipinranka | 12:9a20164dcc47 | 68 | #define CRCO 2 |
| vipinranka | 12:9a20164dcc47 | 69 | #define PWR_UP 1 |
| vipinranka | 12:9a20164dcc47 | 70 | #define PRIM_RX 0 |
| vipinranka | 12:9a20164dcc47 | 71 | #define ENAA_P5 5 |
| vipinranka | 12:9a20164dcc47 | 72 | #define ENAA_P4 4 |
| vipinranka | 12:9a20164dcc47 | 73 | #define ENAA_P3 3 |
| vipinranka | 12:9a20164dcc47 | 74 | #define ENAA_P2 2 |
| vipinranka | 12:9a20164dcc47 | 75 | #define ENAA_P1 1 |
| vipinranka | 12:9a20164dcc47 | 76 | #define ENAA_P0 0 |
| vipinranka | 12:9a20164dcc47 | 77 | #define ERX_P5 5 |
| vipinranka | 12:9a20164dcc47 | 78 | #define ERX_P4 4 |
| vipinranka | 12:9a20164dcc47 | 79 | #define ERX_P3 3 |
| vipinranka | 12:9a20164dcc47 | 80 | #define ERX_P2 2 |
| vipinranka | 12:9a20164dcc47 | 81 | #define ERX_P1 1 |
| vipinranka | 12:9a20164dcc47 | 82 | #define ERX_P0 0 |
| vipinranka | 12:9a20164dcc47 | 83 | #define AW 0 |
| vipinranka | 12:9a20164dcc47 | 84 | #define ARD 4 |
| vipinranka | 12:9a20164dcc47 | 85 | #define ARC 0 |
| vipinranka | 12:9a20164dcc47 | 86 | #define PLL_LOCK 4 |
| vipinranka | 12:9a20164dcc47 | 87 | #define RF_DR 3 |
| vipinranka | 12:9a20164dcc47 | 88 | #define RF_PWR 6 |
| vipinranka | 12:9a20164dcc47 | 89 | #define RX_DR 6 |
| vipinranka | 12:9a20164dcc47 | 90 | #define TX_DS 5 |
| vipinranka | 12:9a20164dcc47 | 91 | #define MAX_RT 4 |
| vipinranka | 12:9a20164dcc47 | 92 | #define RX_P_NO 1 |
| vipinranka | 12:9a20164dcc47 | 93 | #define TX_FULL 0 |
| vipinranka | 12:9a20164dcc47 | 94 | #define PLOS_CNT 4 |
| vipinranka | 12:9a20164dcc47 | 95 | #define ARC_CNT 0 |
| vipinranka | 12:9a20164dcc47 | 96 | #define TX_REUSE 6 |
| vipinranka | 12:9a20164dcc47 | 97 | #define FIFO_FULL 5 |
| vipinranka | 12:9a20164dcc47 | 98 | #define TX_EMPTY 4 |
| vipinranka | 12:9a20164dcc47 | 99 | #define RX_FULL 1 |
| vipinranka | 12:9a20164dcc47 | 100 | #define RX_EMPTY 0 |
| vipinranka | 12:9a20164dcc47 | 101 | #define DPL_P5 5 |
| vipinranka | 12:9a20164dcc47 | 102 | #define DPL_P4 4 |
| vipinranka | 12:9a20164dcc47 | 103 | #define DPL_P3 3 |
| vipinranka | 12:9a20164dcc47 | 104 | #define DPL_P2 2 |
| vipinranka | 12:9a20164dcc47 | 105 | #define DPL_P1 1 |
| vipinranka | 12:9a20164dcc47 | 106 | #define DPL_P0 0 |
| vipinranka | 12:9a20164dcc47 | 107 | #define EN_DPL 2 |
| vipinranka | 12:9a20164dcc47 | 108 | #define EN_ACK_PAY 1 |
| vipinranka | 12:9a20164dcc47 | 109 | #define EN_DYN_ACK 0 |
| vipinranka | 12:9a20164dcc47 | 110 | |
| vipinranka | 12:9a20164dcc47 | 111 | /* Instruction Mnemonics */ |
| vipinranka | 12:9a20164dcc47 | 112 | #define R_REGISTER 0x00 |
| vipinranka | 12:9a20164dcc47 | 113 | #define W_REGISTER 0x20 |
| vipinranka | 12:9a20164dcc47 | 114 | #define REGISTER_MASK 0x1F |
| vipinranka | 12:9a20164dcc47 | 115 | #define ACTIVATE 0x50 |
| vipinranka | 12:9a20164dcc47 | 116 | #define R_RX_PL_WID 0x60 |
| vipinranka | 12:9a20164dcc47 | 117 | #define R_RX_PAYLOAD 0x61 |
| vipinranka | 12:9a20164dcc47 | 118 | #define W_TX_PAYLOAD 0xA0 |
| vipinranka | 12:9a20164dcc47 | 119 | #define W_ACK_PAYLOAD 0xA8 |
| vipinranka | 12:9a20164dcc47 | 120 | #define FLUSH_TX 0xE1 |
| vipinranka | 12:9a20164dcc47 | 121 | #define FLUSH_RX 0xE2 |
| vipinranka | 12:9a20164dcc47 | 122 | #define REUSE_TX_PL 0xE3 |
| vipinranka | 12:9a20164dcc47 | 123 | #define NOP 0xFF |
| vipinranka | 12:9a20164dcc47 | 124 | |
| vipinranka | 12:9a20164dcc47 | 125 | /* Non-P omissions */ |
| vipinranka | 12:9a20164dcc47 | 126 | #define LNA_HCURR 0 |
| vipinranka | 12:9a20164dcc47 | 127 | |
| vipinranka | 12:9a20164dcc47 | 128 | /* P model memory Map */ |
| vipinranka | 12:9a20164dcc47 | 129 | #define RPD 0x09 |
| vipinranka | 12:9a20164dcc47 | 130 | #define W_TX_PAYLOAD_NO_ACK 0xB0 |
| vipinranka | 12:9a20164dcc47 | 131 | |
| vipinranka | 12:9a20164dcc47 | 132 | /* P model bit Mnemonics */ |
| vipinranka | 12:9a20164dcc47 | 133 | #define RF_DR_LOW 5 |
| vipinranka | 12:9a20164dcc47 | 134 | #define RF_DR_HIGH 3 |
| vipinranka | 12:9a20164dcc47 | 135 | #define RF_PWR_LOW 1 |
| vipinranka | 12:9a20164dcc47 | 136 | #define RF_PWR_HIGH 2 |
| vipinranka | 12:9a20164dcc47 | 137 | |
| vipinranka | 12:9a20164dcc47 | 138 |